xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision a9d85efb) 
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x77>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x77>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x77>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x77>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x77>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x77>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x77>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x77>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x77>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x77>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x77>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x77>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x77>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1401600000 {
209			opp-hz = /bits/ 64 <1401600000>;
210			opp-supported-hw = <0x77>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1478400000 {
214			opp-hz = /bits/ 64 <1478400000>;
215			opp-supported-hw = <0x77>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1593600000 {
219			opp-hz = /bits/ 64 <1593600000>;
220			opp-supported-hw = <0x77>;
221			clock-latency-ns = <200000>;
222		};
223	};
224
225	cluster1_opp: opp_table1 {
226		compatible = "operating-points-v2-kryo-cpu";
227		nvmem-cells = <&speedbin_efuse>;
228		opp-shared;
229
230		/* Nominal fmax for now */
231		opp-307200000 {
232			opp-hz = /bits/ 64 <307200000>;
233			opp-supported-hw = <0x77>;
234			clock-latency-ns = <200000>;
235		};
236		opp-403200000 {
237			opp-hz = /bits/ 64 <403200000>;
238			opp-supported-hw = <0x77>;
239			clock-latency-ns = <200000>;
240		};
241		opp-480000000 {
242			opp-hz = /bits/ 64 <480000000>;
243			opp-supported-hw = <0x77>;
244			clock-latency-ns = <200000>;
245		};
246		opp-556800000 {
247			opp-hz = /bits/ 64 <556800000>;
248			opp-supported-hw = <0x77>;
249			clock-latency-ns = <200000>;
250		};
251		opp-652800000 {
252			opp-hz = /bits/ 64 <652800000>;
253			opp-supported-hw = <0x77>;
254			clock-latency-ns = <200000>;
255		};
256		opp-729600000 {
257			opp-hz = /bits/ 64 <729600000>;
258			opp-supported-hw = <0x77>;
259			clock-latency-ns = <200000>;
260		};
261		opp-806400000 {
262			opp-hz = /bits/ 64 <806400000>;
263			opp-supported-hw = <0x77>;
264			clock-latency-ns = <200000>;
265		};
266		opp-883200000 {
267			opp-hz = /bits/ 64 <883200000>;
268			opp-supported-hw = <0x77>;
269			clock-latency-ns = <200000>;
270		};
271		opp-940800000 {
272			opp-hz = /bits/ 64 <940800000>;
273			opp-supported-hw = <0x77>;
274			clock-latency-ns = <200000>;
275		};
276		opp-1036800000 {
277			opp-hz = /bits/ 64 <1036800000>;
278			opp-supported-hw = <0x77>;
279			clock-latency-ns = <200000>;
280		};
281		opp-1113600000 {
282			opp-hz = /bits/ 64 <1113600000>;
283			opp-supported-hw = <0x77>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1190400000 {
287			opp-hz = /bits/ 64 <1190400000>;
288			opp-supported-hw = <0x77>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1248000000 {
292			opp-hz = /bits/ 64 <1248000000>;
293			opp-supported-hw = <0x77>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1324800000 {
297			opp-hz = /bits/ 64 <1324800000>;
298			opp-supported-hw = <0x77>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1401600000 {
302			opp-hz = /bits/ 64 <1401600000>;
303			opp-supported-hw = <0x77>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1478400000 {
307			opp-hz = /bits/ 64 <1478400000>;
308			opp-supported-hw = <0x77>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1555200000 {
312			opp-hz = /bits/ 64 <1555200000>;
313			opp-supported-hw = <0x77>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1632000000 {
317			opp-hz = /bits/ 64 <1632000000>;
318			opp-supported-hw = <0x77>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1708800000 {
322			opp-hz = /bits/ 64 <1708800000>;
323			opp-supported-hw = <0x77>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1785600000 {
327			opp-hz = /bits/ 64 <1785600000>;
328			opp-supported-hw = <0x77>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1824000000 {
332			opp-hz = /bits/ 64 <1824000000>;
333			opp-supported-hw = <0x77>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1920000000 {
337			opp-hz = /bits/ 64 <1920000000>;
338			opp-supported-hw = <0x77>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1996800000 {
342			opp-hz = /bits/ 64 <1996800000>;
343			opp-supported-hw = <0x77>;
344			clock-latency-ns = <200000>;
345		};
346		opp-2073600000 {
347			opp-hz = /bits/ 64 <2073600000>;
348			opp-supported-hw = <0x77>;
349			clock-latency-ns = <200000>;
350		};
351		opp-2150400000 {
352			opp-hz = /bits/ 64 <2150400000>;
353			opp-supported-hw = <0x77>;
354			clock-latency-ns = <200000>;
355		};
356	};
357
358	firmware {
359		scm {
360			compatible = "qcom,scm-msm8996";
361			qcom,dload-mode = <&tcsr 0x13000>;
362		};
363	};
364
365	tcsr_mutex: hwlock {
366		compatible = "qcom,tcsr-mutex";
367		syscon = <&tcsr_mutex_regs 0 0x1000>;
368		#hwlock-cells = <1>;
369	};
370
371	memory@80000000 {
372		device_type = "memory";
373		/* We expect the bootloader to fill in the reg */
374		reg = <0x0 0x80000000 0x0 0x0>;
375	};
376
377	psci {
378		compatible = "arm,psci-1.0";
379		method = "smc";
380	};
381
382	reserved-memory {
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges;
386
387		mba_region: mba@91500000 {
388			reg = <0x0 0x91500000 0x0 0x200000>;
389			no-map;
390		};
391
392		slpi_region: slpi@90b00000 {
393			reg = <0x0 0x90b00000 0x0 0xa00000>;
394			no-map;
395		};
396
397		venus_region: venus@90400000 {
398			reg = <0x0 0x90400000 0x0 0x700000>;
399			no-map;
400		};
401
402		adsp_region: adsp@8ea00000 {
403			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
404			no-map;
405		};
406
407		mpss_region: mpss@88800000 {
408			reg = <0x0 0x88800000 0x0 0x6200000>;
409			no-map;
410		};
411
412		smem_mem: smem-mem@86000000 {
413			reg = <0x0 0x86000000 0x0 0x200000>;
414			no-map;
415		};
416
417		memory@85800000 {
418			reg = <0x0 0x85800000 0x0 0x800000>;
419			no-map;
420		};
421
422		memory@86200000 {
423			reg = <0x0 0x86200000 0x0 0x2600000>;
424			no-map;
425		};
426
427		rmtfs@86700000 {
428			compatible = "qcom,rmtfs-mem";
429
430			size = <0x0 0x200000>;
431			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432			no-map;
433
434			qcom,client-id = <1>;
435			qcom,vmid = <15>;
436		};
437
438		zap_shader_region: gpu@8f200000 {
439			compatible = "shared-dma-pool";
440			reg = <0x0 0x90b00000 0x0 0xa00000>;
441			no-map;
442		};
443	};
444
445	rpm-glink {
446		compatible = "qcom,glink-rpm";
447
448		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
449
450		qcom,rpm-msg-ram = <&rpm_msg_ram>;
451
452		mboxes = <&apcs_glb 0>;
453
454		rpm_requests: rpm-requests {
455			compatible = "qcom,rpm-msm8996";
456			qcom,glink-channels = "rpm_requests";
457
458			rpmcc: qcom,rpmcc {
459				compatible = "qcom,rpmcc-msm8996";
460				#clock-cells = <1>;
461			};
462
463			rpmpd: power-controller {
464				compatible = "qcom,msm8996-rpmpd";
465				#power-domain-cells = <1>;
466				operating-points-v2 = <&rpmpd_opp_table>;
467
468				rpmpd_opp_table: opp-table {
469					compatible = "operating-points-v2";
470
471					rpmpd_opp1: opp1 {
472						opp-level = <1>;
473					};
474
475					rpmpd_opp2: opp2 {
476						opp-level = <2>;
477					};
478
479					rpmpd_opp3: opp3 {
480						opp-level = <3>;
481					};
482
483					rpmpd_opp4: opp4 {
484						opp-level = <4>;
485					};
486
487					rpmpd_opp5: opp5 {
488						opp-level = <5>;
489					};
490
491					rpmpd_opp6: opp6 {
492						opp-level = <6>;
493					};
494				};
495			};
496		};
497	};
498
499	smem {
500		compatible = "qcom,smem";
501		memory-region = <&smem_mem>;
502		hwlocks = <&tcsr_mutex 3>;
503	};
504
505	smp2p-adsp {
506		compatible = "qcom,smp2p";
507		qcom,smem = <443>, <429>;
508
509		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
510
511		mboxes = <&apcs_glb 10>;
512
513		qcom,local-pid = <0>;
514		qcom,remote-pid = <2>;
515
516		smp2p_adsp_out: master-kernel {
517			qcom,entry-name = "master-kernel";
518			#qcom,smem-state-cells = <1>;
519		};
520
521		smp2p_adsp_in: slave-kernel {
522			qcom,entry-name = "slave-kernel";
523
524			interrupt-controller;
525			#interrupt-cells = <2>;
526		};
527	};
528
529	smp2p-modem {
530		compatible = "qcom,smp2p";
531		qcom,smem = <435>, <428>;
532
533		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
534
535		mboxes = <&apcs_glb 14>;
536
537		qcom,local-pid = <0>;
538		qcom,remote-pid = <1>;
539
540		modem_smp2p_out: master-kernel {
541			qcom,entry-name = "master-kernel";
542			#qcom,smem-state-cells = <1>;
543		};
544
545		modem_smp2p_in: slave-kernel {
546			qcom,entry-name = "slave-kernel";
547
548			interrupt-controller;
549			#interrupt-cells = <2>;
550		};
551	};
552
553	smp2p-slpi {
554		compatible = "qcom,smp2p";
555		qcom,smem = <481>, <430>;
556
557		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
558
559		mboxes = <&apcs_glb 26>;
560
561		qcom,local-pid = <0>;
562		qcom,remote-pid = <3>;
563
564		smp2p_slpi_in: slave-kernel {
565			qcom,entry-name = "slave-kernel";
566			interrupt-controller;
567			#interrupt-cells = <2>;
568		};
569
570		smp2p_slpi_out: master-kernel {
571			qcom,entry-name = "master-kernel";
572			#qcom,smem-state-cells = <1>;
573		};
574	};
575
576	soc: soc {
577		#address-cells = <1>;
578		#size-cells = <1>;
579		ranges = <0 0 0 0xffffffff>;
580		compatible = "simple-bus";
581
582		pcie_phy: phy@34000 {
583			compatible = "qcom,msm8996-qmp-pcie-phy";
584			reg = <0x00034000 0x488>;
585			#clock-cells = <1>;
586			#address-cells = <1>;
587			#size-cells = <1>;
588			ranges;
589
590			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592				<&gcc GCC_PCIE_CLKREF_CLK>;
593			clock-names = "aux", "cfg_ahb", "ref";
594
595			resets = <&gcc GCC_PCIE_PHY_BCR>,
596				<&gcc GCC_PCIE_PHY_COM_BCR>,
597				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
598			reset-names = "phy", "common", "cfg";
599			status = "disabled";
600
601			pciephy_0: lane@35000 {
602				reg = <0x00035000 0x130>,
603				      <0x00035200 0x200>,
604				      <0x00035400 0x1dc>;
605				#phy-cells = <0>;
606
607				clock-output-names = "pcie_0_pipe_clk_src";
608				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609				clock-names = "pipe0";
610				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611				reset-names = "lane0";
612			};
613
614			pciephy_1: lane@36000 {
615				reg = <0x00036000 0x130>,
616				      <0x00036200 0x200>,
617				      <0x00036400 0x1dc>;
618				#phy-cells = <0>;
619
620				clock-output-names = "pcie_1_pipe_clk_src";
621				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622				clock-names = "pipe1";
623				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624				reset-names = "lane1";
625			};
626
627			pciephy_2: lane@37000 {
628				reg = <0x00037000 0x130>,
629				      <0x00037200 0x200>,
630				      <0x00037400 0x1dc>;
631				#phy-cells = <0>;
632
633				clock-output-names = "pcie_2_pipe_clk_src";
634				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635				clock-names = "pipe2";
636				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637				reset-names = "lane2";
638			};
639		};
640
641		rpm_msg_ram: memory@68000 {
642			compatible = "qcom,rpm-msg-ram";
643			reg = <0x00068000 0x6000>;
644		};
645
646		qfprom@74000 {
647			compatible = "qcom,qfprom";
648			reg = <0x00074000 0x8ff>;
649			#address-cells = <1>;
650			#size-cells = <1>;
651
652			qusb2p_hstx_trim: hstx_trim@24e {
653				reg = <0x24e 0x2>;
654				bits = <5 4>;
655			};
656
657			qusb2s_hstx_trim: hstx_trim@24f {
658				reg = <0x24f 0x1>;
659				bits = <1 4>;
660			};
661
662			speedbin_efuse: speedbin@133 {
663				reg = <0x133 0x1>;
664				bits = <5 3>;
665			};
666		};
667
668		rng: rng@83000 {
669			compatible = "qcom,prng-ee";
670			reg = <0x00083000 0x1000>;
671			clocks = <&gcc GCC_PRNG_AHB_CLK>;
672			clock-names = "core";
673		};
674
675		gcc: clock-controller@300000 {
676			compatible = "qcom,gcc-msm8996";
677			#clock-cells = <1>;
678			#reset-cells = <1>;
679			#power-domain-cells = <1>;
680			reg = <0x00300000 0x90000>;
681
682			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683			clock-names = "cxo2";
684		};
685
686		tsens0: thermal-sensor@4a9000 {
687			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688			reg = <0x004a9000 0x1000>, /* TM */
689			      <0x004a8000 0x1000>; /* SROT */
690			#qcom,sensors = <13>;
691			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693			interrupt-names = "uplow", "critical";
694			#thermal-sensor-cells = <1>;
695		};
696
697		tsens1: thermal-sensor@4ad000 {
698			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699			reg = <0x004ad000 0x1000>, /* TM */
700			      <0x004ac000 0x1000>; /* SROT */
701			#qcom,sensors = <8>;
702			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "uplow", "critical";
705			#thermal-sensor-cells = <1>;
706		};
707
708		tcsr_mutex_regs: syscon@740000 {
709			compatible = "syscon";
710			reg = <0x00740000 0x40000>;
711		};
712
713		tcsr: syscon@7a0000 {
714			compatible = "qcom,tcsr-msm8996", "syscon";
715			reg = <0x007a0000 0x18000>;
716		};
717
718		mmcc: clock-controller@8c0000 {
719			compatible = "qcom,mmcc-msm8996";
720			#clock-cells = <1>;
721			#reset-cells = <1>;
722			#power-domain-cells = <1>;
723			reg = <0x008c0000 0x40000>;
724			assigned-clocks = <&mmcc MMPLL9_PLL>,
725					  <&mmcc MMPLL1_PLL>,
726					  <&mmcc MMPLL3_PLL>,
727					  <&mmcc MMPLL4_PLL>,
728					  <&mmcc MMPLL5_PLL>;
729			assigned-clock-rates = <624000000>,
730					       <810000000>,
731					       <980000000>,
732					       <960000000>,
733					       <825000000>;
734		};
735
736		mdss: mdss@900000 {
737			compatible = "qcom,mdss";
738
739			reg = <0x00900000 0x1000>,
740			      <0x009b0000 0x1040>,
741			      <0x009b8000 0x1040>;
742			reg-names = "mdss_phys",
743				    "vbif_phys",
744				    "vbif_nrt_phys";
745
746			power-domains = <&mmcc MDSS_GDSC>;
747			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
748
749			interrupt-controller;
750			#interrupt-cells = <1>;
751
752			clocks = <&mmcc MDSS_AHB_CLK>;
753			clock-names = "iface";
754
755			#address-cells = <1>;
756			#size-cells = <1>;
757			ranges;
758
759			status = "disabled";
760
761			mdp: mdp@901000 {
762				compatible = "qcom,mdp5";
763				reg = <0x00901000 0x90000>;
764				reg-names = "mdp_phys";
765
766				interrupt-parent = <&mdss>;
767				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
768
769				clocks = <&mmcc MDSS_AHB_CLK>,
770					 <&mmcc MDSS_AXI_CLK>,
771					 <&mmcc MDSS_MDP_CLK>,
772					 <&mmcc SMMU_MDP_AXI_CLK>,
773					 <&mmcc MDSS_VSYNC_CLK>;
774				clock-names = "iface",
775					      "bus",
776					      "core",
777					      "iommu",
778					      "vsync";
779
780				iommus = <&mdp_smmu 0>;
781
782				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
783					 <&mmcc MDSS_VSYNC_CLK>;
784				assigned-clock-rates = <300000000>,
785					 <19200000>;
786
787				ports {
788					#address-cells = <1>;
789					#size-cells = <0>;
790
791					port@0 {
792						reg = <0>;
793						mdp5_intf3_out: endpoint {
794							remote-endpoint = <&hdmi_in>;
795						};
796					};
797
798					port@1 {
799						reg = <1>;
800						mdp5_intf1_out: endpoint {
801							remote-endpoint = <&dsi0_in>;
802						};
803					};
804				};
805			};
806
807			dsi0: dsi@994000 {
808				compatible = "qcom,mdss-dsi-ctrl";
809				reg = <0x00994000 0x400>;
810				reg-names = "dsi_ctrl";
811
812				interrupt-parent = <&mdss>;
813				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
814
815				clocks = <&mmcc MDSS_MDP_CLK>,
816					 <&mmcc MDSS_BYTE0_CLK>,
817					 <&mmcc MDSS_AHB_CLK>,
818					 <&mmcc MDSS_AXI_CLK>,
819					 <&mmcc MMSS_MISC_AHB_CLK>,
820					 <&mmcc MDSS_PCLK0_CLK>,
821					 <&mmcc MDSS_ESC0_CLK>;
822				clock-names = "mdp_core",
823					      "byte",
824					      "iface",
825					      "bus",
826					      "core_mmss",
827					      "pixel",
828					      "core";
829
830				phys = <&dsi0_phy>;
831				phy-names = "dsi";
832				status = "disabled";
833
834				#address-cells = <1>;
835				#size-cells = <0>;
836
837				ports {
838					#address-cells = <1>;
839					#size-cells = <0>;
840
841					port@0 {
842						reg = <0>;
843						dsi0_in: endpoint {
844							remote-endpoint = <&mdp5_intf1_out>;
845						};
846					};
847
848					port@1 {
849						reg = <1>;
850						dsi0_out: endpoint {
851						};
852					};
853				};
854			};
855
856			dsi0_phy: dsi-phy@994400 {
857				compatible = "qcom,dsi-phy-14nm";
858				reg = <0x00994400 0x100>,
859				      <0x00994500 0x300>,
860				      <0x00994800 0x188>;
861				reg-names = "dsi_phy",
862					    "dsi_phy_lane",
863					    "dsi_pll";
864
865				#clock-cells = <1>;
866				#phy-cells = <0>;
867
868				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
869				clock-names = "iface", "ref";
870				status = "disabled";
871			};
872
873			hdmi: hdmi-tx@9a0000 {
874				compatible = "qcom,hdmi-tx-8996";
875				reg =	<0x009a0000 0x50c>,
876					<0x00070000 0x6158>,
877					<0x009e0000 0xfff>;
878				reg-names = "core_physical",
879					    "qfprom_physical",
880					    "hdcp_physical";
881
882				interrupt-parent = <&mdss>;
883				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
884
885				clocks = <&mmcc MDSS_MDP_CLK>,
886					 <&mmcc MDSS_AHB_CLK>,
887					 <&mmcc MDSS_HDMI_CLK>,
888					 <&mmcc MDSS_HDMI_AHB_CLK>,
889					 <&mmcc MDSS_EXTPCLK_CLK>;
890				clock-names =
891					"mdp_core",
892					"iface",
893					"core",
894					"alt_iface",
895					"extp";
896
897				phys = <&hdmi_phy>;
898				phy-names = "hdmi_phy";
899				#sound-dai-cells = <1>;
900
901				status = "disabled";
902
903				ports {
904					#address-cells = <1>;
905					#size-cells = <0>;
906
907					port@0 {
908						reg = <0>;
909						hdmi_in: endpoint {
910							remote-endpoint = <&mdp5_intf3_out>;
911						};
912					};
913				};
914			};
915
916			hdmi_phy: hdmi-phy@9a0600 {
917				#phy-cells = <0>;
918				compatible = "qcom,hdmi-phy-8996";
919				reg = <0x009a0600 0x1c4>,
920				      <0x009a0a00 0x124>,
921				      <0x009a0c00 0x124>,
922				      <0x009a0e00 0x124>,
923				      <0x009a1000 0x124>,
924				      <0x009a1200 0x0c8>;
925				reg-names = "hdmi_pll",
926					    "hdmi_tx_l0",
927					    "hdmi_tx_l1",
928					    "hdmi_tx_l2",
929					    "hdmi_tx_l3",
930					    "hdmi_phy";
931
932				clocks = <&mmcc MDSS_AHB_CLK>,
933					 <&gcc GCC_HDMI_CLKREF_CLK>;
934				clock-names = "iface",
935					      "ref";
936
937				status = "disabled";
938			};
939		};
940
941		gpu: gpu@b00000 {
942			compatible = "qcom,adreno-530.2", "qcom,adreno";
943			#stream-id-cells = <16>;
944
945			reg = <0x00b00000 0x3f000>;
946			reg-names = "kgsl_3d0_reg_memory";
947
948			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
949
950			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
951				<&mmcc GPU_AHB_CLK>,
952				<&mmcc GPU_GX_RBBMTIMER_CLK>,
953				<&gcc GCC_BIMC_GFX_CLK>,
954				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
955
956			clock-names = "core",
957				"iface",
958				"rbbmtimer",
959				"mem",
960				"mem_iface";
961
962			power-domains = <&mmcc GPU_GX_GDSC>;
963			iommus = <&adreno_smmu 0>;
964
965			nvmem-cells = <&speedbin_efuse>;
966			nvmem-cell-names = "speed_bin";
967
968			qcom,gpu-quirk-two-pass-use-wfi;
969			qcom,gpu-quirk-fault-detect-mask;
970
971			operating-points-v2 = <&gpu_opp_table>;
972
973			status = "disabled";
974
975			#cooling-cells = <2>;
976
977			gpu_opp_table: opp-table {
978				compatible  ="operating-points-v2";
979
980				/*
981				 * 624Mhz and 560Mhz are only available on speed
982				 * bin (1 << 0). All the rest are available on
983				 * all bins of the hardware
984				 */
985				opp-624000000 {
986					opp-hz = /bits/ 64 <624000000>;
987					opp-supported-hw = <0x01>;
988				};
989				opp-560000000 {
990					opp-hz = /bits/ 64 <560000000>;
991					opp-supported-hw = <0x01>;
992				};
993				opp-510000000 {
994					opp-hz = /bits/ 64 <510000000>;
995					opp-supported-hw = <0xFF>;
996				};
997				opp-401800000 {
998					opp-hz = /bits/ 64 <401800000>;
999					opp-supported-hw = <0xFF>;
1000				};
1001				opp-315000000 {
1002					opp-hz = /bits/ 64 <315000000>;
1003					opp-supported-hw = <0xFF>;
1004				};
1005				opp-214000000 {
1006					opp-hz = /bits/ 64 <214000000>;
1007					opp-supported-hw = <0xFF>;
1008				};
1009				opp-133000000 {
1010					opp-hz = /bits/ 64 <133000000>;
1011					opp-supported-hw = <0xFF>;
1012				};
1013			};
1014
1015			zap-shader {
1016				memory-region = <&zap_shader_region>;
1017			};
1018		};
1019
1020		tlmm: pinctrl@1010000 {
1021			compatible = "qcom,msm8996-pinctrl";
1022			reg = <0x01010000 0x300000>;
1023			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1024			gpio-controller;
1025			gpio-ranges = <&tlmm 0 0 150>;
1026			#gpio-cells = <2>;
1027			interrupt-controller;
1028			#interrupt-cells = <2>;
1029
1030			blsp1_spi1_default: blsp1-spi1-default {
1031				spi {
1032					pins = "gpio0", "gpio1", "gpio3";
1033					function = "blsp_spi1";
1034					drive-strength = <12>;
1035					bias-disable;
1036				};
1037
1038				cs {
1039					pins = "gpio2";
1040					function = "gpio";
1041					drive-strength = <16>;
1042					bias-disable;
1043					output-high;
1044				};
1045			};
1046
1047			blsp1_spi1_sleep: blsp1-spi1-sleep {
1048				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1049				function = "gpio";
1050				drive-strength = <2>;
1051				bias-pull-down;
1052			};
1053
1054			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1055				pins = "gpio4", "gpio5";
1056				function = "blsp_uart8";
1057				drive-strength = <16>;
1058				bias-disable;
1059			};
1060
1061			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1062				pins = "gpio4", "gpio5";
1063				function = "gpio";
1064				drive-strength = <2>;
1065				bias-disable;
1066			};
1067
1068			blsp2_i2c2_default: blsp2-i2c2 {
1069				pins = "gpio6", "gpio7";
1070				function = "blsp_i2c8";
1071				drive-strength = <16>;
1072				bias-disable;
1073			};
1074
1075			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1076				pins = "gpio6", "gpio7";
1077				function = "gpio";
1078				drive-strength = <2>;
1079				bias-disable;
1080			};
1081
1082			cci0_default: cci0-default {
1083				pins = "gpio17", "gpio18";
1084				function = "cci_i2c";
1085				drive-strength = <16>;
1086				bias-disable;
1087			};
1088
1089			camera0_state_on:
1090			camera_rear_default: camera-rear-default {
1091				camera0_mclk: mclk0 {
1092					pins = "gpio13";
1093					function = "cam_mclk";
1094					drive-strength = <16>;
1095					bias-disable;
1096				};
1097
1098				camera0_rst: rst {
1099					pins = "gpio25";
1100					function = "gpio";
1101					drive-strength = <16>;
1102					bias-disable;
1103				};
1104
1105				camera0_pwdn: pwdn {
1106					pins = "gpio26";
1107					function = "gpio";
1108					drive-strength = <16>;
1109					bias-disable;
1110				};
1111			};
1112
1113			cci1_default: cci1-default {
1114				pins = "gpio19", "gpio20";
1115				function = "cci_i2c";
1116				drive-strength = <16>;
1117				bias-disable;
1118			};
1119
1120			camera1_state_on:
1121			camera_board_default: camera-board-default {
1122				mclk1 {
1123					pins = "gpio14";
1124					function = "cam_mclk";
1125					drive-strength = <16>;
1126					bias-disable;
1127				};
1128
1129				pwdn {
1130					pins = "gpio98";
1131					function = "gpio";
1132					drive-strength = <16>;
1133					bias-disable;
1134				};
1135
1136				rst {
1137					pins = "gpio104";
1138					function = "gpio";
1139					drive-strength = <16>;
1140					bias-disable;
1141				};
1142			};
1143
1144			camera2_state_on:
1145			camera_front_default: camera-front-default {
1146				camera2_mclk: mclk2 {
1147					pins = "gpio15";
1148					function = "cam_mclk";
1149					drive-strength = <16>;
1150					bias-disable;
1151				};
1152
1153				camera2_rst: rst {
1154					pins = "gpio23";
1155					function = "gpio";
1156					drive-strength = <16>;
1157					bias-disable;
1158				};
1159
1160				pwdn {
1161					pins = "gpio133";
1162					function = "gpio";
1163					drive-strength = <16>;
1164					bias-disable;
1165				};
1166			};
1167
1168			pcie0_state_on: pcie0-state-on {
1169				perst {
1170					pins = "gpio35";
1171					function = "gpio";
1172					drive-strength = <2>;
1173					bias-pull-down;
1174				};
1175
1176				clkreq {
1177					pins = "gpio36";
1178					function = "pci_e0";
1179					drive-strength = <2>;
1180					bias-pull-up;
1181				};
1182
1183				wake {
1184					pins = "gpio37";
1185					function = "gpio";
1186					drive-strength = <2>;
1187					bias-pull-up;
1188				};
1189			};
1190
1191			pcie0_state_off: pcie0-state-off {
1192				perst {
1193					pins = "gpio35";
1194					function = "gpio";
1195					drive-strength = <2>;
1196					bias-pull-down;
1197				};
1198
1199				clkreq {
1200					pins = "gpio36";
1201					function = "gpio";
1202					drive-strength = <2>;
1203					bias-disable;
1204				};
1205
1206				wake {
1207					pins = "gpio37";
1208					function = "gpio";
1209					drive-strength = <2>;
1210					bias-disable;
1211				};
1212			};
1213
1214			blsp1_i2c3_default: blsp1-i2c2-default {
1215				pins = "gpio47", "gpio48";
1216				function = "blsp_i2c3";
1217				drive-strength = <16>;
1218				bias-disable = <0>;
1219			};
1220
1221			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1222				pins = "gpio47", "gpio48";
1223				function = "gpio";
1224				drive-strength = <2>;
1225				bias-disable = <0>;
1226			};
1227
1228			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1229				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1230				function = "blsp_uart9";
1231				drive-strength = <16>;
1232				bias-disable;
1233			};
1234
1235			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1236				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1237				function = "blsp_uart9";
1238				drive-strength = <2>;
1239				bias-disable;
1240			};
1241
1242			wcd_intr_default: wcd-intr-default{
1243				pins = "gpio54";
1244				function = "gpio";
1245				drive-strength = <2>;
1246				bias-pull-down;
1247				input-enable;
1248			};
1249
1250			blsp2_i2c1_default: blsp2-i2c1 {
1251				pins = "gpio55", "gpio56";
1252				function = "blsp_i2c7";
1253				drive-strength = <16>;
1254				bias-disable;
1255			};
1256
1257			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1258				pins = "gpio55", "gpio56";
1259				function = "gpio";
1260				drive-strength = <2>;
1261				bias-disable;
1262			};
1263
1264			blsp2_i2c5_default: blsp2-i2c5 {
1265				pins = "gpio60", "gpio61";
1266				function = "blsp_i2c11";
1267				drive-strength = <2>;
1268				bias-disable;
1269			};
1270
1271			/* Sleep state for BLSP2_I2C5 is missing.. */
1272
1273			cdc_reset_active: cdc-reset-active {
1274				pins = "gpio64";
1275				function = "gpio";
1276				drive-strength = <16>;
1277				bias-pull-down;
1278				output-high;
1279			};
1280
1281			cdc_reset_sleep: cdc-reset-sleep {
1282				pins = "gpio64";
1283				function = "gpio";
1284				drive-strength = <16>;
1285				bias-disable;
1286				output-low;
1287			};
1288
1289			blsp2_spi6_default: blsp2-spi5-default {
1290				spi {
1291					pins = "gpio85", "gpio86", "gpio88";
1292					function = "blsp_spi12";
1293					drive-strength = <12>;
1294					bias-disable;
1295				};
1296
1297				cs {
1298					pins = "gpio87";
1299					function = "gpio";
1300					drive-strength = <16>;
1301					bias-disable;
1302					output-high;
1303				};
1304			};
1305
1306			blsp2_spi6_sleep: blsp2-spi5-sleep {
1307				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1308				function = "gpio";
1309				drive-strength = <2>;
1310				bias-pull-down;
1311			};
1312
1313			blsp2_i2c6_default: blsp2-i2c6 {
1314				pins = "gpio87", "gpio88";
1315				function = "blsp_i2c12";
1316				drive-strength = <16>;
1317				bias-disable;
1318			};
1319
1320			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1321				pins = "gpio87", "gpio88";
1322				function = "gpio";
1323				drive-strength = <2>;
1324				bias-disable;
1325			};
1326
1327			pcie1_state_on: pcie1-state-on {
1328				perst {
1329					pins = "gpio130";
1330					function = "gpio";
1331					drive-strength = <2>;
1332					bias-pull-down;
1333				};
1334
1335				clkreq {
1336					pins = "gpio131";
1337					function = "pci_e1";
1338					drive-strength = <2>;
1339					bias-pull-up;
1340				};
1341
1342				wake {
1343					pins = "gpio132";
1344					function = "gpio";
1345					drive-strength = <2>;
1346					bias-pull-down;
1347				};
1348			};
1349
1350			pcie1_state_off: pcie1-state-off {
1351				/* Perst is missing? */
1352				clkreq {
1353					pins = "gpio131";
1354					function = "gpio";
1355					drive-strength = <2>;
1356					bias-disable;
1357				};
1358
1359				wake {
1360					pins = "gpio132";
1361					function = "gpio";
1362					drive-strength = <2>;
1363					bias-disable;
1364				};
1365			};
1366
1367			pcie2_state_on: pcie2-state-on {
1368				perst {
1369					pins = "gpio114";
1370					function = "gpio";
1371					drive-strength = <2>;
1372					bias-pull-down;
1373				};
1374
1375				clkreq {
1376					pins = "gpio115";
1377					function = "pci_e2";
1378					drive-strength = <2>;
1379					bias-pull-up;
1380				};
1381
1382				wake {
1383					pins = "gpio116";
1384					function = "gpio";
1385					drive-strength = <2>;
1386					bias-pull-down;
1387				};
1388			};
1389
1390			pcie2_state_off: pcie2-state-off {
1391				/* Perst is missing? */
1392				clkreq {
1393					pins = "gpio115";
1394					function = "gpio";
1395					drive-strength = <2>;
1396					bias-disable;
1397				};
1398
1399				wake {
1400					pins = "gpio116";
1401					function = "gpio";
1402					drive-strength = <2>;
1403					bias-disable;
1404				};
1405			};
1406
1407			sdc1_state_on: sdc1-state-on {
1408				clk {
1409					pins = "sdc1_clk";
1410					bias-disable;
1411					drive-strength = <16>;
1412				};
1413
1414				cmd {
1415					pins = "sdc1_cmd";
1416					bias-pull-up;
1417					drive-strength = <10>;
1418				};
1419
1420				data {
1421					pins = "sdc1_data";
1422					bias-pull-up;
1423					drive-strength = <10>;
1424				};
1425
1426				rclk {
1427					pins = "sdc1_rclk";
1428					bias-pull-down;
1429				};
1430			};
1431
1432			sdc1_state_off: sdc1-state-off {
1433				clk {
1434					pins = "sdc1_clk";
1435					bias-disable;
1436					drive-strength = <2>;
1437				};
1438
1439				cmd {
1440					pins = "sdc1_cmd";
1441					bias-pull-up;
1442					drive-strength = <2>;
1443				};
1444
1445				data {
1446					pins = "sdc1_data";
1447					bias-pull-up;
1448					drive-strength = <2>;
1449				};
1450
1451				rclk {
1452					pins = "sdc1_rclk";
1453					bias-pull-down;
1454				};
1455			};
1456
1457			sdc2_state_on: sdc2-clk-on {
1458				clk {
1459					pins = "sdc2_clk";
1460					bias-disable;
1461					drive-strength = <16>;
1462				};
1463
1464				cmd {
1465					pins = "sdc2_cmd";
1466					bias-pull-up;
1467					drive-strength = <10>;
1468				};
1469
1470				data {
1471					pins = "sdc2_data";
1472					bias-pull-up;
1473					drive-strength = <10>;
1474				};
1475			};
1476
1477			sdc2_state_off: sdc2-clk-off {
1478				clk {
1479					pins = "sdc2_clk";
1480					bias-disable;
1481					drive-strength = <2>;
1482				};
1483
1484				cmd {
1485					pins = "sdc2_cmd";
1486					bias-pull-up;
1487					drive-strength = <2>;
1488				};
1489
1490				data {
1491					pins = "sdc2_data";
1492					bias-pull-up;
1493					drive-strength = <2>;
1494				};
1495			};
1496		};
1497
1498		spmi_bus: qcom,spmi@400f000 {
1499			compatible = "qcom,spmi-pmic-arb";
1500			reg = <0x0400f000 0x1000>,
1501			      <0x04400000 0x800000>,
1502			      <0x04c00000 0x800000>,
1503			      <0x05800000 0x200000>,
1504			      <0x0400a000 0x002100>;
1505			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1506			interrupt-names = "periph_irq";
1507			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1508			qcom,ee = <0>;
1509			qcom,channel = <0>;
1510			#address-cells = <2>;
1511			#size-cells = <0>;
1512			interrupt-controller;
1513			#interrupt-cells = <4>;
1514		};
1515
1516		agnoc@0 {
1517			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1518			compatible = "simple-pm-bus";
1519			#address-cells = <1>;
1520			#size-cells = <1>;
1521			ranges;
1522
1523			pcie0: pcie@600000 {
1524				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1525				status = "disabled";
1526				power-domains = <&gcc PCIE0_GDSC>;
1527				bus-range = <0x00 0xff>;
1528				num-lanes = <1>;
1529
1530				reg = <0x00600000 0x2000>,
1531				      <0x0c000000 0xf1d>,
1532				      <0x0c000f20 0xa8>,
1533				      <0x0c100000 0x100000>;
1534				reg-names = "parf", "dbi", "elbi","config";
1535
1536				phys = <&pciephy_0>;
1537				phy-names = "pciephy";
1538
1539				#address-cells = <3>;
1540				#size-cells = <2>;
1541				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1542					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1543
1544				device_type = "pci";
1545
1546				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1547				interrupt-names = "msi";
1548				#interrupt-cells = <1>;
1549				interrupt-map-mask = <0 0 0 0x7>;
1550				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1551						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1552						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1553						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1554
1555				pinctrl-names = "default", "sleep";
1556				pinctrl-0 = <&pcie0_state_on>;
1557				pinctrl-1 = <&pcie0_state_off>;
1558
1559				linux,pci-domain = <0>;
1560
1561				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1562					<&gcc GCC_PCIE_0_AUX_CLK>,
1563					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1564					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1565					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1566
1567				clock-names =  "pipe",
1568						"aux",
1569						"cfg",
1570						"bus_master",
1571						"bus_slave";
1572
1573			};
1574
1575			pcie1: pcie@608000 {
1576				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1577				power-domains = <&gcc PCIE1_GDSC>;
1578				bus-range = <0x00 0xff>;
1579				num-lanes = <1>;
1580
1581				status  = "disabled";
1582
1583				reg = <0x00608000 0x2000>,
1584				      <0x0d000000 0xf1d>,
1585				      <0x0d000f20 0xa8>,
1586				      <0x0d100000 0x100000>;
1587
1588				reg-names = "parf", "dbi", "elbi","config";
1589
1590				phys = <&pciephy_1>;
1591				phy-names = "pciephy";
1592
1593				#address-cells = <3>;
1594				#size-cells = <2>;
1595				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1596					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1597
1598				device_type = "pci";
1599
1600				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1601				interrupt-names = "msi";
1602				#interrupt-cells = <1>;
1603				interrupt-map-mask = <0 0 0 0x7>;
1604				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1605						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1606						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1607						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1608
1609				pinctrl-names = "default", "sleep";
1610				pinctrl-0 = <&pcie1_state_on>;
1611				pinctrl-1 = <&pcie1_state_off>;
1612
1613				linux,pci-domain = <1>;
1614
1615				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1616					<&gcc GCC_PCIE_1_AUX_CLK>,
1617					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1618					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1619					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1620
1621				clock-names =  "pipe",
1622						"aux",
1623						"cfg",
1624						"bus_master",
1625						"bus_slave";
1626			};
1627
1628			pcie2: pcie@610000 {
1629				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1630				power-domains = <&gcc PCIE2_GDSC>;
1631				bus-range = <0x00 0xff>;
1632				num-lanes = <1>;
1633				status = "disabled";
1634				reg = <0x00610000 0x2000>,
1635				      <0x0e000000 0xf1d>,
1636				      <0x0e000f20 0xa8>,
1637				      <0x0e100000 0x100000>;
1638
1639				reg-names = "parf", "dbi", "elbi","config";
1640
1641				phys = <&pciephy_2>;
1642				phy-names = "pciephy";
1643
1644				#address-cells = <3>;
1645				#size-cells = <2>;
1646				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1647					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1648
1649				device_type = "pci";
1650
1651				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1652				interrupt-names = "msi";
1653				#interrupt-cells = <1>;
1654				interrupt-map-mask = <0 0 0 0x7>;
1655				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1656						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1657						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1658						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1659
1660				pinctrl-names = "default", "sleep";
1661				pinctrl-0 = <&pcie2_state_on>;
1662				pinctrl-1 = <&pcie2_state_off>;
1663
1664				linux,pci-domain = <2>;
1665				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1666					<&gcc GCC_PCIE_2_AUX_CLK>,
1667					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1668					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1669					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1670
1671				clock-names =  "pipe",
1672						"aux",
1673						"cfg",
1674						"bus_master",
1675						"bus_slave";
1676			};
1677		};
1678
1679		ufshc: ufshc@624000 {
1680			compatible = "qcom,ufshc";
1681			reg = <0x00624000 0x2500>;
1682			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1683
1684			phys = <&ufsphy_lane>;
1685			phy-names = "ufsphy";
1686
1687			power-domains = <&gcc UFS_GDSC>;
1688
1689			clock-names =
1690				"core_clk_src",
1691				"core_clk",
1692				"bus_clk",
1693				"bus_aggr_clk",
1694				"iface_clk",
1695				"core_clk_unipro_src",
1696				"core_clk_unipro",
1697				"core_clk_ice",
1698				"ref_clk",
1699				"tx_lane0_sync_clk",
1700				"rx_lane0_sync_clk";
1701			clocks =
1702				<&gcc UFS_AXI_CLK_SRC>,
1703				<&gcc GCC_UFS_AXI_CLK>,
1704				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1705				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1706				<&gcc GCC_UFS_AHB_CLK>,
1707				<&gcc UFS_ICE_CORE_CLK_SRC>,
1708				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1709				<&gcc GCC_UFS_ICE_CORE_CLK>,
1710				<&rpmcc RPM_SMD_LN_BB_CLK>,
1711				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1712				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1713			freq-table-hz =
1714				<100000000 200000000>,
1715				<0 0>,
1716				<0 0>,
1717				<0 0>,
1718				<0 0>,
1719				<150000000 300000000>,
1720				<0 0>,
1721				<0 0>,
1722				<0 0>,
1723				<0 0>,
1724				<0 0>;
1725
1726			lanes-per-direction = <1>;
1727			#reset-cells = <1>;
1728			status = "disabled";
1729
1730			ufs_variant {
1731				compatible = "qcom,ufs_variant";
1732			};
1733		};
1734
1735		ufsphy: phy@627000 {
1736			compatible = "qcom,msm8996-qmp-ufs-phy";
1737			reg = <0x00627000 0x1c4>;
1738			#address-cells = <1>;
1739			#size-cells = <1>;
1740			ranges;
1741
1742			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1743			clock-names = "ref";
1744
1745			resets = <&ufshc 0>;
1746			reset-names = "ufsphy";
1747			status = "disabled";
1748
1749			ufsphy_lane: lanes@627400 {
1750				reg = <0x627400 0x12c>,
1751				      <0x627600 0x200>,
1752				      <0x627c00 0x1b4>;
1753				#phy-cells = <0>;
1754			};
1755		};
1756
1757		camss: camss@a00000 {
1758			compatible = "qcom,msm8996-camss";
1759			reg = <0x00a34000 0x1000>,
1760			      <0x00a00030 0x4>,
1761			      <0x00a35000 0x1000>,
1762			      <0x00a00038 0x4>,
1763			      <0x00a36000 0x1000>,
1764			      <0x00a00040 0x4>,
1765			      <0x00a30000 0x100>,
1766			      <0x00a30400 0x100>,
1767			      <0x00a30800 0x100>,
1768			      <0x00a30c00 0x100>,
1769			      <0x00a31000 0x500>,
1770			      <0x00a00020 0x10>,
1771			      <0x00a10000 0x1000>,
1772			      <0x00a14000 0x1000>;
1773			reg-names = "csiphy0",
1774				"csiphy0_clk_mux",
1775				"csiphy1",
1776				"csiphy1_clk_mux",
1777				"csiphy2",
1778				"csiphy2_clk_mux",
1779				"csid0",
1780				"csid1",
1781				"csid2",
1782				"csid3",
1783				"ispif",
1784				"csi_clk_mux",
1785				"vfe0",
1786				"vfe1";
1787			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1788				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1789				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1790				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1791				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1792				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1793				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1794				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1795				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1796				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1797			interrupt-names = "csiphy0",
1798				"csiphy1",
1799				"csiphy2",
1800				"csid0",
1801				"csid1",
1802				"csid2",
1803				"csid3",
1804				"ispif",
1805				"vfe0",
1806				"vfe1";
1807			power-domains = <&mmcc VFE0_GDSC>,
1808					<&mmcc VFE1_GDSC>;
1809			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1810				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1811				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1812				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1813				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1814				<&mmcc CAMSS_CSI0_AHB_CLK>,
1815				<&mmcc CAMSS_CSI0_CLK>,
1816				<&mmcc CAMSS_CSI0PHY_CLK>,
1817				<&mmcc CAMSS_CSI0PIX_CLK>,
1818				<&mmcc CAMSS_CSI0RDI_CLK>,
1819				<&mmcc CAMSS_CSI1_AHB_CLK>,
1820				<&mmcc CAMSS_CSI1_CLK>,
1821				<&mmcc CAMSS_CSI1PHY_CLK>,
1822				<&mmcc CAMSS_CSI1PIX_CLK>,
1823				<&mmcc CAMSS_CSI1RDI_CLK>,
1824				<&mmcc CAMSS_CSI2_AHB_CLK>,
1825				<&mmcc CAMSS_CSI2_CLK>,
1826				<&mmcc CAMSS_CSI2PHY_CLK>,
1827				<&mmcc CAMSS_CSI2PIX_CLK>,
1828				<&mmcc CAMSS_CSI2RDI_CLK>,
1829				<&mmcc CAMSS_CSI3_AHB_CLK>,
1830				<&mmcc CAMSS_CSI3_CLK>,
1831				<&mmcc CAMSS_CSI3PHY_CLK>,
1832				<&mmcc CAMSS_CSI3PIX_CLK>,
1833				<&mmcc CAMSS_CSI3RDI_CLK>,
1834				<&mmcc CAMSS_AHB_CLK>,
1835				<&mmcc CAMSS_VFE0_CLK>,
1836				<&mmcc CAMSS_CSI_VFE0_CLK>,
1837				<&mmcc CAMSS_VFE0_AHB_CLK>,
1838				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1839				<&mmcc CAMSS_VFE1_CLK>,
1840				<&mmcc CAMSS_CSI_VFE1_CLK>,
1841				<&mmcc CAMSS_VFE1_AHB_CLK>,
1842				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1843				<&mmcc CAMSS_VFE_AHB_CLK>,
1844				<&mmcc CAMSS_VFE_AXI_CLK>;
1845			clock-names = "top_ahb",
1846				"ispif_ahb",
1847				"csiphy0_timer",
1848				"csiphy1_timer",
1849				"csiphy2_timer",
1850				"csi0_ahb",
1851				"csi0",
1852				"csi0_phy",
1853				"csi0_pix",
1854				"csi0_rdi",
1855				"csi1_ahb",
1856				"csi1",
1857				"csi1_phy",
1858				"csi1_pix",
1859				"csi1_rdi",
1860				"csi2_ahb",
1861				"csi2",
1862				"csi2_phy",
1863				"csi2_pix",
1864				"csi2_rdi",
1865				"csi3_ahb",
1866				"csi3",
1867				"csi3_phy",
1868				"csi3_pix",
1869				"csi3_rdi",
1870				"ahb",
1871				"vfe0",
1872				"csi_vfe0",
1873				"vfe0_ahb",
1874				"vfe0_stream",
1875				"vfe1",
1876				"csi_vfe1",
1877				"vfe1_ahb",
1878				"vfe1_stream",
1879				"vfe_ahb",
1880				"vfe_axi";
1881			iommus = <&vfe_smmu 0>,
1882				 <&vfe_smmu 1>,
1883				 <&vfe_smmu 2>,
1884				 <&vfe_smmu 3>;
1885			status = "disabled";
1886			ports {
1887				#address-cells = <1>;
1888				#size-cells = <0>;
1889			};
1890		};
1891
1892		cci: cci@a0c000 {
1893			compatible = "qcom,msm8996-cci";
1894			#address-cells = <1>;
1895			#size-cells = <0>;
1896			reg = <0xa0c000 0x1000>;
1897			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1898			power-domains = <&mmcc CAMSS_GDSC>;
1899			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1900				 <&mmcc CAMSS_CCI_AHB_CLK>,
1901				 <&mmcc CAMSS_CCI_CLK>,
1902				 <&mmcc CAMSS_AHB_CLK>;
1903			clock-names = "camss_top_ahb",
1904				      "cci_ahb",
1905				      "cci",
1906				      "camss_ahb";
1907			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1908					  <&mmcc CAMSS_CCI_CLK>;
1909			assigned-clock-rates = <80000000>, <37500000>;
1910			pinctrl-names = "default";
1911			pinctrl-0 = <&cci0_default &cci1_default>;
1912			status = "disabled";
1913
1914			cci_i2c0: i2c-bus@0 {
1915				reg = <0>;
1916				clock-frequency = <400000>;
1917				#address-cells = <1>;
1918				#size-cells = <0>;
1919			};
1920
1921			cci_i2c1: i2c-bus@1 {
1922				reg = <1>;
1923				clock-frequency = <400000>;
1924				#address-cells = <1>;
1925				#size-cells = <0>;
1926			};
1927		};
1928
1929		adreno_smmu: iommu@b40000 {
1930			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1931			reg = <0x00b40000 0x10000>;
1932
1933			#global-interrupts = <1>;
1934			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1935				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1936				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1937			#iommu-cells = <1>;
1938
1939			clocks = <&mmcc GPU_AHB_CLK>,
1940				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1941			clock-names = "iface", "bus";
1942
1943			power-domains = <&mmcc GPU_GDSC>;
1944		};
1945
1946		venus: video-codec@c00000 {
1947			compatible = "qcom,msm8996-venus";
1948			reg = <0x00c00000 0xff000>;
1949			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1950			power-domains = <&mmcc VENUS_GDSC>;
1951			clocks = <&mmcc VIDEO_CORE_CLK>,
1952				 <&mmcc VIDEO_AHB_CLK>,
1953				 <&mmcc VIDEO_AXI_CLK>,
1954				 <&mmcc VIDEO_MAXI_CLK>;
1955			clock-names = "core", "iface", "bus", "mbus";
1956			iommus = <&venus_smmu 0x00>,
1957				 <&venus_smmu 0x01>,
1958				 <&venus_smmu 0x0a>,
1959				 <&venus_smmu 0x07>,
1960				 <&venus_smmu 0x0e>,
1961				 <&venus_smmu 0x0f>,
1962				 <&venus_smmu 0x08>,
1963				 <&venus_smmu 0x09>,
1964				 <&venus_smmu 0x0b>,
1965				 <&venus_smmu 0x0c>,
1966				 <&venus_smmu 0x0d>,
1967				 <&venus_smmu 0x10>,
1968				 <&venus_smmu 0x11>,
1969				 <&venus_smmu 0x21>,
1970				 <&venus_smmu 0x28>,
1971				 <&venus_smmu 0x29>,
1972				 <&venus_smmu 0x2b>,
1973				 <&venus_smmu 0x2c>,
1974				 <&venus_smmu 0x2d>,
1975				 <&venus_smmu 0x31>;
1976			memory-region = <&venus_region>;
1977			status = "disabled";
1978
1979			video-decoder {
1980				compatible = "venus-decoder";
1981				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1982				clock-names = "core";
1983				power-domains = <&mmcc VENUS_CORE0_GDSC>;
1984			};
1985
1986			video-encoder {
1987				compatible = "venus-encoder";
1988				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1989				clock-names = "core";
1990				power-domains = <&mmcc VENUS_CORE1_GDSC>;
1991			};
1992		};
1993
1994		mdp_smmu: iommu@d00000 {
1995			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1996			reg = <0x00d00000 0x10000>;
1997
1998			#global-interrupts = <1>;
1999			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2000				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2001				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2002			#iommu-cells = <1>;
2003			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2004				 <&mmcc SMMU_MDP_AXI_CLK>;
2005			clock-names = "iface", "bus";
2006
2007			power-domains = <&mmcc MDSS_GDSC>;
2008		};
2009
2010		venus_smmu: iommu@d40000 {
2011			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2012			reg = <0x00d40000 0x20000>;
2013			#global-interrupts = <1>;
2014			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2015				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2016				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2017				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2018				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2019				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2020				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2021				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2022			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2023			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2024				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2025			clock-names = "iface", "bus";
2026			#iommu-cells = <1>;
2027			status = "okay";
2028		};
2029
2030		vfe_smmu: iommu@da0000 {
2031			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2032			reg = <0x00da0000 0x10000>;
2033
2034			#global-interrupts = <1>;
2035			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2036				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2037				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2038			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2039			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2040				 <&mmcc SMMU_VFE_AXI_CLK>;
2041			clock-names = "iface",
2042				      "bus";
2043			#iommu-cells = <1>;
2044		};
2045
2046		lpass_q6_smmu: iommu@1600000 {
2047			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2048			reg = <0x01600000 0x20000>;
2049			#iommu-cells = <1>;
2050			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2051
2052			#global-interrupts = <1>;
2053			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2054		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2055		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2056		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2057		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2058		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2059		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2060		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2061		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2062		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2063		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2064		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2065		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2066
2067			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2068				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2069			clock-names = "iface", "bus";
2070		};
2071
2072		stm@3002000 {
2073			compatible = "arm,coresight-stm", "arm,primecell";
2074			reg = <0x3002000 0x1000>,
2075			      <0x8280000 0x180000>;
2076			reg-names = "stm-base", "stm-stimulus-base";
2077
2078			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2079			clock-names = "apb_pclk", "atclk";
2080
2081			out-ports {
2082				port {
2083					stm_out: endpoint {
2084						remote-endpoint =
2085						  <&funnel0_in>;
2086					};
2087				};
2088			};
2089		};
2090
2091		tpiu@3020000 {
2092			compatible = "arm,coresight-tpiu", "arm,primecell";
2093			reg = <0x3020000 0x1000>;
2094
2095			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2096			clock-names = "apb_pclk", "atclk";
2097
2098			in-ports {
2099				port {
2100					tpiu_in: endpoint {
2101						remote-endpoint =
2102						  <&replicator_out1>;
2103					};
2104				};
2105			};
2106		};
2107
2108		funnel@3021000 {
2109			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2110			reg = <0x3021000 0x1000>;
2111
2112			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2113			clock-names = "apb_pclk", "atclk";
2114
2115			in-ports {
2116				#address-cells = <1>;
2117				#size-cells = <0>;
2118
2119				port@7 {
2120					reg = <7>;
2121					funnel0_in: endpoint {
2122						remote-endpoint =
2123						  <&stm_out>;
2124					};
2125				};
2126			};
2127
2128			out-ports {
2129				port {
2130					funnel0_out: endpoint {
2131						remote-endpoint =
2132						  <&merge_funnel_in0>;
2133					};
2134				};
2135			};
2136		};
2137
2138		funnel@3022000 {
2139			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2140			reg = <0x3022000 0x1000>;
2141
2142			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2143			clock-names = "apb_pclk", "atclk";
2144
2145			in-ports {
2146				#address-cells = <1>;
2147				#size-cells = <0>;
2148
2149				port@6 {
2150					reg = <6>;
2151					funnel1_in: endpoint {
2152						remote-endpoint =
2153						  <&apss_merge_funnel_out>;
2154					};
2155				};
2156			};
2157
2158			out-ports {
2159				port {
2160					funnel1_out: endpoint {
2161						remote-endpoint =
2162						  <&merge_funnel_in1>;
2163					};
2164				};
2165			};
2166		};
2167
2168		funnel@3023000 {
2169			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2170			reg = <0x3023000 0x1000>;
2171
2172			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2173			clock-names = "apb_pclk", "atclk";
2174
2175
2176			out-ports {
2177				port {
2178					funnel2_out: endpoint {
2179						remote-endpoint =
2180						  <&merge_funnel_in2>;
2181					};
2182				};
2183			};
2184		};
2185
2186		funnel@3025000 {
2187			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2188			reg = <0x3025000 0x1000>;
2189
2190			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2191			clock-names = "apb_pclk", "atclk";
2192
2193			in-ports {
2194				#address-cells = <1>;
2195				#size-cells = <0>;
2196
2197				port@0 {
2198					reg = <0>;
2199					merge_funnel_in0: endpoint {
2200						remote-endpoint =
2201						  <&funnel0_out>;
2202					};
2203				};
2204
2205				port@1 {
2206					reg = <1>;
2207					merge_funnel_in1: endpoint {
2208						remote-endpoint =
2209						  <&funnel1_out>;
2210					};
2211				};
2212
2213				port@2 {
2214					reg = <2>;
2215					merge_funnel_in2: endpoint {
2216						remote-endpoint =
2217						  <&funnel2_out>;
2218					};
2219				};
2220			};
2221
2222			out-ports {
2223				port {
2224					merge_funnel_out: endpoint {
2225						remote-endpoint =
2226						  <&etf_in>;
2227					};
2228				};
2229			};
2230		};
2231
2232		replicator@3026000 {
2233			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2234			reg = <0x3026000 0x1000>;
2235
2236			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2237			clock-names = "apb_pclk", "atclk";
2238
2239			in-ports {
2240				port {
2241					replicator_in: endpoint {
2242						remote-endpoint =
2243						  <&etf_out>;
2244					};
2245				};
2246			};
2247
2248			out-ports {
2249				#address-cells = <1>;
2250				#size-cells = <0>;
2251
2252				port@0 {
2253					reg = <0>;
2254					replicator_out0: endpoint {
2255						remote-endpoint =
2256						  <&etr_in>;
2257					};
2258				};
2259
2260				port@1 {
2261					reg = <1>;
2262					replicator_out1: endpoint {
2263						remote-endpoint =
2264						  <&tpiu_in>;
2265					};
2266				};
2267			};
2268		};
2269
2270		etf@3027000 {
2271			compatible = "arm,coresight-tmc", "arm,primecell";
2272			reg = <0x3027000 0x1000>;
2273
2274			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2275			clock-names = "apb_pclk", "atclk";
2276
2277			in-ports {
2278				port {
2279					etf_in: endpoint {
2280						remote-endpoint =
2281						  <&merge_funnel_out>;
2282					};
2283				};
2284			};
2285
2286			out-ports {
2287				port {
2288					etf_out: endpoint {
2289						remote-endpoint =
2290						  <&replicator_in>;
2291					};
2292				};
2293			};
2294		};
2295
2296		etr@3028000 {
2297			compatible = "arm,coresight-tmc", "arm,primecell";
2298			reg = <0x3028000 0x1000>;
2299
2300			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2301			clock-names = "apb_pclk", "atclk";
2302			arm,scatter-gather;
2303
2304			in-ports {
2305				port {
2306					etr_in: endpoint {
2307						remote-endpoint =
2308						  <&replicator_out0>;
2309					};
2310				};
2311			};
2312		};
2313
2314		debug@3810000 {
2315			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2316			reg = <0x3810000 0x1000>;
2317
2318			clocks = <&rpmcc RPM_QDSS_CLK>;
2319			clock-names = "apb_pclk";
2320
2321			cpu = <&CPU0>;
2322		};
2323
2324		etm@3840000 {
2325			compatible = "arm,coresight-etm4x", "arm,primecell";
2326			reg = <0x3840000 0x1000>;
2327
2328			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2329			clock-names = "apb_pclk", "atclk";
2330
2331			cpu = <&CPU0>;
2332
2333			out-ports {
2334				port {
2335					etm0_out: endpoint {
2336						remote-endpoint =
2337						  <&apss_funnel0_in0>;
2338					};
2339				};
2340			};
2341		};
2342
2343		debug@3910000 {
2344			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2345			reg = <0x3910000 0x1000>;
2346
2347			clocks = <&rpmcc RPM_QDSS_CLK>;
2348			clock-names = "apb_pclk";
2349
2350			cpu = <&CPU1>;
2351		};
2352
2353		etm@3940000 {
2354			compatible = "arm,coresight-etm4x", "arm,primecell";
2355			reg = <0x3940000 0x1000>;
2356
2357			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2358			clock-names = "apb_pclk", "atclk";
2359
2360			cpu = <&CPU1>;
2361
2362			out-ports {
2363				port {
2364					etm1_out: endpoint {
2365						remote-endpoint =
2366						  <&apss_funnel0_in1>;
2367					};
2368				};
2369			};
2370		};
2371
2372		funnel@39b0000 { /* APSS Funnel 0 */
2373			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2374			reg = <0x39b0000 0x1000>;
2375
2376			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2377			clock-names = "apb_pclk", "atclk";
2378
2379			in-ports {
2380				#address-cells = <1>;
2381				#size-cells = <0>;
2382
2383				port@0 {
2384					reg = <0>;
2385					apss_funnel0_in0: endpoint {
2386						remote-endpoint = <&etm0_out>;
2387					};
2388				};
2389
2390				port@1 {
2391					reg = <1>;
2392					apss_funnel0_in1: endpoint {
2393						remote-endpoint = <&etm1_out>;
2394					};
2395				};
2396			};
2397
2398			out-ports {
2399				port {
2400					apss_funnel0_out: endpoint {
2401						remote-endpoint =
2402						  <&apss_merge_funnel_in0>;
2403					};
2404				};
2405			};
2406		};
2407
2408		debug@3a10000 {
2409			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2410			reg = <0x3a10000 0x1000>;
2411
2412			clocks = <&rpmcc RPM_QDSS_CLK>;
2413			clock-names = "apb_pclk";
2414
2415			cpu = <&CPU2>;
2416		};
2417
2418		etm@3a40000 {
2419			compatible = "arm,coresight-etm4x", "arm,primecell";
2420			reg = <0x3a40000 0x1000>;
2421
2422			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2423			clock-names = "apb_pclk", "atclk";
2424
2425			cpu = <&CPU2>;
2426
2427			out-ports {
2428				port {
2429					etm2_out: endpoint {
2430						remote-endpoint =
2431						  <&apss_funnel1_in0>;
2432					};
2433				};
2434			};
2435		};
2436
2437		debug@3b10000 {
2438			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2439			reg = <0x3b10000 0x1000>;
2440
2441			clocks = <&rpmcc RPM_QDSS_CLK>;
2442			clock-names = "apb_pclk";
2443
2444			cpu = <&CPU3>;
2445		};
2446
2447		etm@3b40000 {
2448			compatible = "arm,coresight-etm4x", "arm,primecell";
2449			reg = <0x3b40000 0x1000>;
2450
2451			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2452			clock-names = "apb_pclk", "atclk";
2453
2454			cpu = <&CPU3>;
2455
2456			out-ports {
2457				port {
2458					etm3_out: endpoint {
2459						remote-endpoint =
2460						  <&apss_funnel1_in1>;
2461					};
2462				};
2463			};
2464		};
2465
2466		funnel@3bb0000 { /* APSS Funnel 1 */
2467			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2468			reg = <0x3bb0000 0x1000>;
2469
2470			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2471			clock-names = "apb_pclk", "atclk";
2472
2473			in-ports {
2474				#address-cells = <1>;
2475				#size-cells = <0>;
2476
2477				port@0 {
2478					reg = <0>;
2479					apss_funnel1_in0: endpoint {
2480						remote-endpoint = <&etm2_out>;
2481					};
2482				};
2483
2484				port@1 {
2485					reg = <1>;
2486					apss_funnel1_in1: endpoint {
2487						remote-endpoint = <&etm3_out>;
2488					};
2489				};
2490			};
2491
2492			out-ports {
2493				port {
2494					apss_funnel1_out: endpoint {
2495						remote-endpoint =
2496						  <&apss_merge_funnel_in1>;
2497					};
2498				};
2499			};
2500		};
2501
2502		funnel@3bc0000 {
2503			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2504			reg = <0x3bc0000 0x1000>;
2505
2506			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2507			clock-names = "apb_pclk", "atclk";
2508
2509			in-ports {
2510				#address-cells = <1>;
2511				#size-cells = <0>;
2512
2513				port@0 {
2514					reg = <0>;
2515					apss_merge_funnel_in0: endpoint {
2516						remote-endpoint =
2517						  <&apss_funnel0_out>;
2518					};
2519				};
2520
2521				port@1 {
2522					reg = <1>;
2523					apss_merge_funnel_in1: endpoint {
2524						remote-endpoint =
2525						  <&apss_funnel1_out>;
2526					};
2527				};
2528			};
2529
2530			out-ports {
2531				port {
2532					apss_merge_funnel_out: endpoint {
2533						remote-endpoint =
2534						  <&funnel1_in>;
2535					};
2536				};
2537			};
2538		};
2539
2540		kryocc: clock-controller@6400000 {
2541			compatible = "qcom,msm8996-apcc";
2542			reg = <0x06400000 0x90000>;
2543
2544			clock-names = "xo";
2545			clocks = <&xo_board>;
2546
2547			#clock-cells = <1>;
2548		};
2549
2550		usb3: usb@6af8800 {
2551			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2552			reg = <0x06af8800 0x400>;
2553			#address-cells = <1>;
2554			#size-cells = <1>;
2555			ranges;
2556
2557			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2558				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2559			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2560
2561			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2562				<&gcc GCC_USB30_MASTER_CLK>,
2563				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2564				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2565				<&gcc GCC_USB30_SLEEP_CLK>,
2566				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2567
2568			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2569					  <&gcc GCC_USB30_MASTER_CLK>;
2570			assigned-clock-rates = <19200000>, <120000000>;
2571
2572			power-domains = <&gcc USB30_GDSC>;
2573			status = "disabled";
2574
2575			usb3_dwc3: dwc3@6a00000 {
2576				compatible = "snps,dwc3";
2577				reg = <0x06a00000 0xcc00>;
2578				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2579				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2580				phy-names = "usb2-phy", "usb3-phy";
2581				snps,dis_u2_susphy_quirk;
2582				snps,dis_enblslpm_quirk;
2583			};
2584		};
2585
2586		usb3phy: phy@7410000 {
2587			compatible = "qcom,msm8996-qmp-usb3-phy";
2588			reg = <0x07410000 0x1c4>;
2589			#clock-cells = <1>;
2590			#address-cells = <1>;
2591			#size-cells = <1>;
2592			ranges;
2593
2594			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2595				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2596				<&gcc GCC_USB3_CLKREF_CLK>;
2597			clock-names = "aux", "cfg_ahb", "ref";
2598
2599			resets = <&gcc GCC_USB3_PHY_BCR>,
2600				<&gcc GCC_USB3PHY_PHY_BCR>;
2601			reset-names = "phy", "common";
2602			status = "disabled";
2603
2604			ssusb_phy_0: lane@7410200 {
2605				reg = <0x07410200 0x200>,
2606				      <0x07410400 0x130>,
2607				      <0x07410600 0x1a8>;
2608				#phy-cells = <0>;
2609
2610				clock-output-names = "usb3_phy_pipe_clk_src";
2611				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2612				clock-names = "pipe0";
2613			};
2614		};
2615
2616		hsusb_phy1: phy@7411000 {
2617			compatible = "qcom,msm8996-qusb2-phy";
2618			reg = <0x07411000 0x180>;
2619			#phy-cells = <0>;
2620
2621			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2622				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2623			clock-names = "cfg_ahb", "ref";
2624
2625			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2626			nvmem-cells = <&qusb2p_hstx_trim>;
2627			status = "disabled";
2628		};
2629
2630		hsusb_phy2: phy@7412000 {
2631			compatible = "qcom,msm8996-qusb2-phy";
2632			reg = <0x07412000 0x180>;
2633			#phy-cells = <0>;
2634
2635			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2636				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2637			clock-names = "cfg_ahb", "ref";
2638
2639			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2640			nvmem-cells = <&qusb2s_hstx_trim>;
2641			status = "disabled";
2642		};
2643
2644		sdhc1: sdhci@7464900 {
2645			compatible = "qcom,sdhci-msm-v4";
2646			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2647			reg-names = "hc_mem", "core_mem";
2648
2649			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2650					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2651			interrupt-names = "hc_irq", "pwr_irq";
2652
2653			clock-names = "iface", "core", "xo";
2654			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2655				<&gcc GCC_SDCC1_APPS_CLK>,
2656				<&xo_board>;
2657
2658			pinctrl-names = "default", "sleep";
2659			pinctrl-0 = <&sdc1_state_on>;
2660			pinctrl-1 = <&sdc1_state_off>;
2661
2662			bus-width = <8>;
2663			non-removable;
2664			status = "disabled";
2665		};
2666
2667		sdhc2: sdhci@74a4900 {
2668			compatible = "qcom,sdhci-msm-v4";
2669			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2670			reg-names = "hc_mem", "core_mem";
2671
2672			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2673				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2674			interrupt-names = "hc_irq", "pwr_irq";
2675
2676			clock-names = "iface", "core", "xo";
2677			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2678				<&gcc GCC_SDCC2_APPS_CLK>,
2679				<&xo_board>;
2680
2681			pinctrl-names = "default", "sleep";
2682			pinctrl-0 = <&sdc2_state_on>;
2683			pinctrl-1 = <&sdc2_state_off>;
2684
2685			bus-width = <4>;
2686			status = "disabled";
2687		 };
2688
2689		blsp1_dma: dma@7544000 {
2690			compatible = "qcom,bam-v1.7.0";
2691			reg = <0x07544000 0x2b000>;
2692			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2693			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2694			clock-names = "bam_clk";
2695			qcom,controlled-remotely;
2696			#dma-cells = <1>;
2697			qcom,ee = <0>;
2698		};
2699
2700		blsp1_uart2: serial@7570000 {
2701			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2702			reg = <0x07570000 0x1000>;
2703			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2704			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2705				 <&gcc GCC_BLSP1_AHB_CLK>;
2706			clock-names = "core", "iface";
2707			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2708			dma-names = "tx", "rx";
2709			status = "disabled";
2710		};
2711
2712		blsp1_spi1: spi@7575000 {
2713			compatible = "qcom,spi-qup-v2.2.1";
2714			reg = <0x07575000 0x600>;
2715			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2716			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2717				 <&gcc GCC_BLSP1_AHB_CLK>;
2718			clock-names = "core", "iface";
2719			pinctrl-names = "default", "sleep";
2720			pinctrl-0 = <&blsp1_spi1_default>;
2721			pinctrl-1 = <&blsp1_spi1_sleep>;
2722			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2723			dma-names = "tx", "rx";
2724			#address-cells = <1>;
2725			#size-cells = <0>;
2726			status = "disabled";
2727		};
2728
2729		blsp1_i2c3: i2c@7577000 {
2730			compatible = "qcom,i2c-qup-v2.2.1";
2731			reg = <0x07577000 0x1000>;
2732			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2733			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2734				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2735			clock-names = "iface", "core";
2736			pinctrl-names = "default", "sleep";
2737			pinctrl-0 = <&blsp1_i2c3_default>;
2738			pinctrl-1 = <&blsp1_i2c3_sleep>;
2739			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2740			dma-names = "tx", "rx";
2741			#address-cells = <1>;
2742			#size-cells = <0>;
2743			status = "disabled";
2744		};
2745
2746		blsp2_dma: dma@7584000 {
2747			compatible = "qcom,bam-v1.7.0";
2748			reg = <0x07584000 0x2b000>;
2749			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2750			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2751			clock-names = "bam_clk";
2752			qcom,controlled-remotely;
2753			#dma-cells = <1>;
2754			qcom,ee = <0>;
2755		};
2756
2757		blsp2_uart2: serial@75b0000 {
2758			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2759			reg = <0x075b0000 0x1000>;
2760			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2761			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2762				 <&gcc GCC_BLSP2_AHB_CLK>;
2763			clock-names = "core", "iface";
2764			status = "disabled";
2765		};
2766
2767		blsp2_uart3: serial@75b1000 {
2768			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2769			reg = <0x075b1000 0x1000>;
2770			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2771			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2772				 <&gcc GCC_BLSP2_AHB_CLK>;
2773			clock-names = "core", "iface";
2774			status = "disabled";
2775		};
2776
2777		blsp2_i2c1: i2c@75b5000 {
2778			compatible = "qcom,i2c-qup-v2.2.1";
2779			reg = <0x075b5000 0x1000>;
2780			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2781			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2782				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2783			clock-names = "iface", "core";
2784			pinctrl-names = "default", "sleep";
2785			pinctrl-0 = <&blsp2_i2c1_default>;
2786			pinctrl-1 = <&blsp2_i2c1_sleep>;
2787			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2788			dma-names = "tx", "rx";
2789			#address-cells = <1>;
2790			#size-cells = <0>;
2791			status = "disabled";
2792		};
2793
2794		blsp2_i2c2: i2c@75b6000 {
2795			compatible = "qcom,i2c-qup-v2.2.1";
2796			reg = <0x075b6000 0x1000>;
2797			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2798			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2799				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2800			clock-names = "iface", "core";
2801			pinctrl-names = "default", "sleep";
2802			pinctrl-0 = <&blsp2_i2c2_default>;
2803			pinctrl-1 = <&blsp2_i2c2_sleep>;
2804			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2805			dma-names = "tx", "rx";
2806			#address-cells = <1>;
2807			#size-cells = <0>;
2808			status = "disabled";
2809		};
2810
2811		blsp2_i2c5: i2c@75b9000 {
2812			compatible = "qcom,i2c-qup-v2.2.1";
2813			reg = <0x75b9000 0x1000>;
2814			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2815			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2816				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2817			clock-names = "iface", "core";
2818			pinctrl-names = "default";
2819			pinctrl-0 = <&blsp2_i2c5_default>;
2820			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2821			dma-names = "tx", "rx";
2822			#address-cells = <1>;
2823			#size-cells = <0>;
2824			status = "disabled";
2825		};
2826
2827		blsp2_i2c6: i2c@75ba000 {
2828			compatible = "qcom,i2c-qup-v2.2.1";
2829			reg = <0x75ba000 0x1000>;
2830			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2831			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2832				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2833			clock-names = "iface", "core";
2834			pinctrl-names = "default", "sleep";
2835			pinctrl-0 = <&blsp2_i2c6_default>;
2836			pinctrl-1 = <&blsp2_i2c6_sleep>;
2837			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2838			dma-names = "tx", "rx";
2839			#address-cells = <1>;
2840			#size-cells = <0>;
2841			status = "disabled";
2842		};
2843
2844		blsp2_spi6: spi@75ba000{
2845			compatible = "qcom,spi-qup-v2.2.1";
2846			reg = <0x075ba000 0x600>;
2847			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2848			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2849				 <&gcc GCC_BLSP2_AHB_CLK>;
2850			clock-names = "core", "iface";
2851			pinctrl-names = "default", "sleep";
2852			pinctrl-0 = <&blsp2_spi6_default>;
2853			pinctrl-1 = <&blsp2_spi6_sleep>;
2854			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2855			dma-names = "tx", "rx";
2856			#address-cells = <1>;
2857			#size-cells = <0>;
2858			status = "disabled";
2859		};
2860
2861		usb2: usb@76f8800 {
2862			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2863			reg = <0x076f8800 0x400>;
2864			#address-cells = <1>;
2865			#size-cells = <1>;
2866			ranges;
2867
2868			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2869				<&gcc GCC_USB20_MASTER_CLK>,
2870				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2871				<&gcc GCC_USB20_SLEEP_CLK>,
2872				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2873
2874			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2875					  <&gcc GCC_USB20_MASTER_CLK>;
2876			assigned-clock-rates = <19200000>, <60000000>;
2877
2878			power-domains = <&gcc USB30_GDSC>;
2879			qcom,select-utmi-as-pipe-clk;
2880			status = "disabled";
2881
2882			dwc3@7600000 {
2883				compatible = "snps,dwc3";
2884				reg = <0x07600000 0xcc00>;
2885				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2886				phys = <&hsusb_phy2>;
2887				phy-names = "usb2-phy";
2888				maximum-speed = "high-speed";
2889				snps,dis_u2_susphy_quirk;
2890				snps,dis_enblslpm_quirk;
2891			};
2892		};
2893
2894		slimbam: dma-controller@9184000 {
2895			compatible = "qcom,bam-v1.7.0";
2896			qcom,controlled-remotely;
2897			reg = <0x09184000 0x32000>;
2898			num-channels  = <31>;
2899			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2900			#dma-cells = <1>;
2901			qcom,ee = <1>;
2902			qcom,num-ees = <2>;
2903		};
2904
2905		slim_msm: slim@91c0000 {
2906			compatible = "qcom,slim-ngd-v1.5.0";
2907			reg = <0x091c0000 0x2C000>;
2908			reg-names = "ctrl";
2909			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2910			dmas =	<&slimbam 3>, <&slimbam 4>,
2911				<&slimbam 5>, <&slimbam 6>;
2912			dma-names = "rx", "tx", "tx2", "rx2";
2913			#address-cells = <1>;
2914			#size-cells = <0>;
2915			ngd@1 {
2916				reg = <1>;
2917				#address-cells = <1>;
2918				#size-cells = <1>;
2919
2920				tasha_ifd: tas-ifd {
2921					compatible = "slim217,1a0";
2922					reg  = <0 0>;
2923				};
2924
2925				wcd9335: codec@1{
2926					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2927					pinctrl-names = "default";
2928
2929					compatible = "slim217,1a0";
2930					reg  = <1 0>;
2931
2932					interrupt-parent = <&tlmm>;
2933					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2934						     <53 IRQ_TYPE_LEVEL_HIGH>;
2935					interrupt-names  = "intr1", "intr2";
2936					interrupt-controller;
2937					#interrupt-cells = <1>;
2938					reset-gpios = <&tlmm 64 0>;
2939
2940					slim-ifc-dev  = <&tasha_ifd>;
2941
2942					#sound-dai-cells = <1>;
2943				};
2944			};
2945		};
2946
2947		adsp_pil: remoteproc@9300000 {
2948			compatible = "qcom,msm8996-adsp-pil";
2949			reg = <0x09300000 0x80000>;
2950
2951			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2952					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2953					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2954					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2955					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2956			interrupt-names = "wdog", "fatal", "ready",
2957					  "handover", "stop-ack";
2958
2959			clocks = <&xo_board>;
2960			clock-names = "xo";
2961
2962			memory-region = <&adsp_region>;
2963
2964			qcom,smem-states = <&smp2p_adsp_out 0>;
2965			qcom,smem-state-names = "stop";
2966
2967			power-domains = <&rpmpd MSM8996_VDDCX>;
2968			power-domain-names = "cx";
2969
2970			status = "disabled";
2971
2972			smd-edge {
2973				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2974
2975				label = "lpass";
2976				mboxes = <&apcs_glb 8>;
2977				qcom,smd-edge = <1>;
2978				qcom,remote-pid = <2>;
2979				#address-cells = <1>;
2980				#size-cells = <0>;
2981				apr {
2982					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2983					compatible = "qcom,apr-v2";
2984					qcom,smd-channels = "apr_audio_svc";
2985					qcom,apr-domain = <APR_DOMAIN_ADSP>;
2986					#address-cells = <1>;
2987					#size-cells = <0>;
2988
2989					q6core {
2990						reg = <APR_SVC_ADSP_CORE>;
2991						compatible = "qcom,q6core";
2992					};
2993
2994					q6afe: q6afe {
2995						compatible = "qcom,q6afe";
2996						reg = <APR_SVC_AFE>;
2997						q6afedai: dais {
2998							compatible = "qcom,q6afe-dais";
2999							#address-cells = <1>;
3000							#size-cells = <0>;
3001							#sound-dai-cells = <1>;
3002							hdmi@1 {
3003								reg = <1>;
3004							};
3005						};
3006					};
3007
3008					q6asm: q6asm {
3009						compatible = "qcom,q6asm";
3010						reg = <APR_SVC_ASM>;
3011						q6asmdai: dais {
3012							compatible = "qcom,q6asm-dais";
3013							#address-cells = <1>;
3014							#size-cells = <0>;
3015							#sound-dai-cells = <1>;
3016							iommus = <&lpass_q6_smmu 1>;
3017						};
3018					};
3019
3020					q6adm: q6adm {
3021						compatible = "qcom,q6adm";
3022						reg = <APR_SVC_ADM>;
3023						q6routing: routing {
3024							compatible = "qcom,q6adm-routing";
3025							#sound-dai-cells = <0>;
3026						};
3027					};
3028				};
3029
3030			};
3031		};
3032
3033		apcs_glb: mailbox@9820000 {
3034			compatible = "qcom,msm8996-apcs-hmss-global";
3035			reg = <0x09820000 0x1000>;
3036
3037			#mbox-cells = <1>;
3038		};
3039
3040		timer@9840000 {
3041			#address-cells = <1>;
3042			#size-cells = <1>;
3043			ranges;
3044			compatible = "arm,armv7-timer-mem";
3045			reg = <0x09840000 0x1000>;
3046			clock-frequency = <19200000>;
3047
3048			frame@9850000 {
3049				frame-number = <0>;
3050				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3051					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3052				reg = <0x09850000 0x1000>,
3053				      <0x09860000 0x1000>;
3054			};
3055
3056			frame@9870000 {
3057				frame-number = <1>;
3058				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3059				reg = <0x09870000 0x1000>;
3060				status = "disabled";
3061			};
3062
3063			frame@9880000 {
3064				frame-number = <2>;
3065				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3066				reg = <0x09880000 0x1000>;
3067				status = "disabled";
3068			};
3069
3070			frame@9890000 {
3071				frame-number = <3>;
3072				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3073				reg = <0x09890000 0x1000>;
3074				status = "disabled";
3075			};
3076
3077			frame@98a0000 {
3078				frame-number = <4>;
3079				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3080				reg = <0x098a0000 0x1000>;
3081				status = "disabled";
3082			};
3083
3084			frame@98b0000 {
3085				frame-number = <5>;
3086				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3087				reg = <0x098b0000 0x1000>;
3088				status = "disabled";
3089			};
3090
3091			frame@98c0000 {
3092				frame-number = <6>;
3093				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3094				reg = <0x098c0000 0x1000>;
3095				status = "disabled";
3096			};
3097		};
3098
3099		saw3: syscon@9a10000 {
3100			compatible = "syscon";
3101			reg = <0x09a10000 0x1000>;
3102		};
3103
3104		intc: interrupt-controller@9bc0000 {
3105			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3106			#interrupt-cells = <3>;
3107			interrupt-controller;
3108			#redistributor-regions = <1>;
3109			redistributor-stride = <0x0 0x40000>;
3110			reg = <0x09bc0000 0x10000>,
3111			      <0x09c00000 0x100000>;
3112			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3113		};
3114	};
3115
3116	sound: sound {
3117	};
3118
3119	thermal-zones {
3120		cpu0-thermal {
3121			polling-delay-passive = <250>;
3122			polling-delay = <1000>;
3123
3124			thermal-sensors = <&tsens0 3>;
3125
3126			trips {
3127				cpu0_alert0: trip-point0 {
3128					temperature = <75000>;
3129					hysteresis = <2000>;
3130					type = "passive";
3131				};
3132
3133				cpu0_crit: cpu_crit {
3134					temperature = <110000>;
3135					hysteresis = <2000>;
3136					type = "critical";
3137				};
3138			};
3139		};
3140
3141		cpu1-thermal {
3142			polling-delay-passive = <250>;
3143			polling-delay = <1000>;
3144
3145			thermal-sensors = <&tsens0 5>;
3146
3147			trips {
3148				cpu1_alert0: trip-point0 {
3149					temperature = <75000>;
3150					hysteresis = <2000>;
3151					type = "passive";
3152				};
3153
3154				cpu1_crit: cpu_crit {
3155					temperature = <110000>;
3156					hysteresis = <2000>;
3157					type = "critical";
3158				};
3159			};
3160		};
3161
3162		cpu2-thermal {
3163			polling-delay-passive = <250>;
3164			polling-delay = <1000>;
3165
3166			thermal-sensors = <&tsens0 8>;
3167
3168			trips {
3169				cpu2_alert0: trip-point0 {
3170					temperature = <75000>;
3171					hysteresis = <2000>;
3172					type = "passive";
3173				};
3174
3175				cpu2_crit: cpu_crit {
3176					temperature = <110000>;
3177					hysteresis = <2000>;
3178					type = "critical";
3179				};
3180			};
3181		};
3182
3183		cpu3-thermal {
3184			polling-delay-passive = <250>;
3185			polling-delay = <1000>;
3186
3187			thermal-sensors = <&tsens0 10>;
3188
3189			trips {
3190				cpu3_alert0: trip-point0 {
3191					temperature = <75000>;
3192					hysteresis = <2000>;
3193					type = "passive";
3194				};
3195
3196				cpu3_crit: cpu_crit {
3197					temperature = <110000>;
3198					hysteresis = <2000>;
3199					type = "critical";
3200				};
3201			};
3202		};
3203
3204		gpu-thermal-top {
3205			polling-delay-passive = <250>;
3206			polling-delay = <1000>;
3207
3208			thermal-sensors = <&tsens1 6>;
3209
3210			trips {
3211				gpu1_alert0: trip-point0 {
3212					temperature = <90000>;
3213					hysteresis = <2000>;
3214					type = "passive";
3215				};
3216			};
3217
3218			cooling-maps {
3219				map0 {
3220					trip = <&gpu1_alert0>;
3221					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3222				};
3223			};
3224		};
3225
3226		gpu-thermal-bottom {
3227			polling-delay-passive = <250>;
3228			polling-delay = <1000>;
3229
3230			thermal-sensors = <&tsens1 7>;
3231
3232			trips {
3233				gpu2_alert0: trip-point0 {
3234					temperature = <90000>;
3235					hysteresis = <2000>;
3236					type = "passive";
3237				};
3238			};
3239
3240			cooling-maps {
3241				map0 {
3242					trip = <&gpu2_alert0>;
3243					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3244				};
3245			};
3246		};
3247
3248		m4m-thermal {
3249			polling-delay-passive = <250>;
3250			polling-delay = <1000>;
3251
3252			thermal-sensors = <&tsens0 1>;
3253
3254			trips {
3255				m4m_alert0: trip-point0 {
3256					temperature = <90000>;
3257					hysteresis = <2000>;
3258					type = "hot";
3259				};
3260			};
3261		};
3262
3263		l3-or-venus-thermal {
3264			polling-delay-passive = <250>;
3265			polling-delay = <1000>;
3266
3267			thermal-sensors = <&tsens0 2>;
3268
3269			trips {
3270				l3_or_venus_alert0: trip-point0 {
3271					temperature = <90000>;
3272					hysteresis = <2000>;
3273					type = "hot";
3274				};
3275			};
3276		};
3277
3278		cluster0-l2-thermal {
3279			polling-delay-passive = <250>;
3280			polling-delay = <1000>;
3281
3282			thermal-sensors = <&tsens0 7>;
3283
3284			trips {
3285				cluster0_l2_alert0: trip-point0 {
3286					temperature = <90000>;
3287					hysteresis = <2000>;
3288					type = "hot";
3289				};
3290			};
3291		};
3292
3293		cluster1-l2-thermal {
3294			polling-delay-passive = <250>;
3295			polling-delay = <1000>;
3296
3297			thermal-sensors = <&tsens0 12>;
3298
3299			trips {
3300				cluster1_l2_alert0: trip-point0 {
3301					temperature = <90000>;
3302					hysteresis = <2000>;
3303					type = "hot";
3304				};
3305			};
3306		};
3307
3308		camera-thermal {
3309			polling-delay-passive = <250>;
3310			polling-delay = <1000>;
3311
3312			thermal-sensors = <&tsens1 1>;
3313
3314			trips {
3315				camera_alert0: trip-point0 {
3316					temperature = <90000>;
3317					hysteresis = <2000>;
3318					type = "hot";
3319				};
3320			};
3321		};
3322
3323		q6-dsp-thermal {
3324			polling-delay-passive = <250>;
3325			polling-delay = <1000>;
3326
3327			thermal-sensors = <&tsens1 2>;
3328
3329			trips {
3330				q6_dsp_alert0: trip-point0 {
3331					temperature = <90000>;
3332					hysteresis = <2000>;
3333					type = "hot";
3334				};
3335			};
3336		};
3337
3338		mem-thermal {
3339			polling-delay-passive = <250>;
3340			polling-delay = <1000>;
3341
3342			thermal-sensors = <&tsens1 3>;
3343
3344			trips {
3345				mem_alert0: trip-point0 {
3346					temperature = <90000>;
3347					hysteresis = <2000>;
3348					type = "hot";
3349				};
3350			};
3351		};
3352
3353		modemtx-thermal {
3354			polling-delay-passive = <250>;
3355			polling-delay = <1000>;
3356
3357			thermal-sensors = <&tsens1 4>;
3358
3359			trips {
3360				modemtx_alert0: trip-point0 {
3361					temperature = <90000>;
3362					hysteresis = <2000>;
3363					type = "hot";
3364				};
3365			};
3366		};
3367	};
3368
3369	timer {
3370		compatible = "arm,armv8-timer";
3371		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3372			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3373			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3374			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3375	};
3376};
3377