1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16 17/ { 18 model = "Qualcomm Technologies, Inc. MSM8996"; 19 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 memory { 28 device_type = "memory"; 29 /* We expect the bootloader to fill in the reg */ 30 reg = <0 0 0 0>; 31 }; 32 33 reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 mba_region: mba@91500000 { 39 reg = <0x0 0x91500000 0x0 0x200000>; 40 no-map; 41 }; 42 43 slpi_region: slpi@90b00000 { 44 reg = <0x0 0x90b00000 0x0 0xa00000>; 45 no-map; 46 }; 47 48 venus_region: venus@90400000 { 49 reg = <0x0 0x90400000 0x0 0x700000>; 50 no-map; 51 }; 52 53 adsp_region: adsp@8ea00000 { 54 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 55 no-map; 56 }; 57 58 mpss_region: mpss@88800000 { 59 reg = <0x0 0x88800000 0x0 0x6200000>; 60 no-map; 61 }; 62 63 smem_mem: smem-mem@86000000 { 64 reg = <0x0 0x86000000 0x0 0x200000>; 65 no-map; 66 }; 67 68 memory@85800000 { 69 reg = <0x0 0x85800000 0x0 0x800000>; 70 no-map; 71 }; 72 73 memory@86200000 { 74 reg = <0x0 0x86200000 0x0 0x2600000>; 75 no-map; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <2>; 81 #size-cells = <0>; 82 83 CPU0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "qcom,kryo"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_0>; 89 L2_0: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 }; 93 }; 94 95 CPU1: cpu@1 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo"; 98 reg = <0x0 0x1>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 }; 102 103 CPU2: cpu@100 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_1>; 109 L2_1: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 }; 113 }; 114 115 CPU3: cpu@101 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x101>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_1>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&CPU0>; 127 }; 128 129 core1 { 130 cpu = <&CPU1>; 131 }; 132 }; 133 134 cluster1 { 135 core0 { 136 cpu = <&CPU2>; 137 }; 138 139 core1 { 140 cpu = <&CPU3>; 141 }; 142 }; 143 }; 144 }; 145 146 thermal-zones { 147 cpu-thermal0 { 148 polling-delay-passive = <250>; 149 polling-delay = <1000>; 150 151 thermal-sensors = <&tsens0 3>; 152 153 trips { 154 cpu_alert0: trip0 { 155 temperature = <75000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 160 cpu_crit0: trip1 { 161 temperature = <110000>; 162 hysteresis = <2000>; 163 type = "critical"; 164 }; 165 }; 166 }; 167 168 cpu-thermal1 { 169 polling-delay-passive = <250>; 170 polling-delay = <1000>; 171 172 thermal-sensors = <&tsens0 5>; 173 174 trips { 175 cpu_alert1: trip0 { 176 temperature = <75000>; 177 hysteresis = <2000>; 178 type = "passive"; 179 }; 180 181 cpu_crit1: trip1 { 182 temperature = <110000>; 183 hysteresis = <2000>; 184 type = "critical"; 185 }; 186 }; 187 }; 188 189 cpu-thermal2 { 190 polling-delay-passive = <250>; 191 polling-delay = <1000>; 192 193 thermal-sensors = <&tsens0 8>; 194 195 trips { 196 cpu_alert2: trip0 { 197 temperature = <75000>; 198 hysteresis = <2000>; 199 type = "passive"; 200 }; 201 202 cpu_crit2: trip1 { 203 temperature = <110000>; 204 hysteresis = <2000>; 205 type = "critical"; 206 }; 207 }; 208 }; 209 210 cpu-thermal3 { 211 polling-delay-passive = <250>; 212 polling-delay = <1000>; 213 214 thermal-sensors = <&tsens0 10>; 215 216 trips { 217 cpu_alert3: trip0 { 218 temperature = <75000>; 219 hysteresis = <2000>; 220 type = "passive"; 221 }; 222 223 cpu_crit3: trip1 { 224 temperature = <110000>; 225 hysteresis = <2000>; 226 type = "critical"; 227 }; 228 }; 229 }; 230 }; 231 232 timer { 233 compatible = "arm,armv8-timer"; 234 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 238 }; 239 240 clocks { 241 xo_board: xo_board { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <19200000>; 245 clock-output-names = "xo_board"; 246 }; 247 248 sleep_clk: sleep_clk { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <32764>; 252 clock-output-names = "sleep_clk"; 253 }; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 firmware { 262 scm { 263 compatible = "qcom,scm-msm8996"; 264 }; 265 }; 266 267 tcsr_mutex: hwlock { 268 compatible = "qcom,tcsr-mutex"; 269 syscon = <&tcsr_mutex_regs 0 0x1000>; 270 #hwlock-cells = <1>; 271 }; 272 273 smem { 274 compatible = "qcom,smem"; 275 memory-region = <&smem_mem>; 276 hwlocks = <&tcsr_mutex 3>; 277 }; 278 279 soc: soc { 280 #address-cells = <1>; 281 #size-cells = <1>; 282 ranges = <0 0 0 0xffffffff>; 283 compatible = "simple-bus"; 284 285 tcsr_mutex_regs: syscon@740000 { 286 compatible = "syscon"; 287 reg = <0x740000 0x20000>; 288 }; 289 290 intc: interrupt-controller@9bc0000 { 291 compatible = "arm,gic-v3"; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 #redistributor-regions = <1>; 295 redistributor-stride = <0x0 0x40000>; 296 reg = <0x09bc0000 0x10000>, 297 <0x09c00000 0x100000>; 298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 apcs: syscon@9820000 { 302 compatible = "syscon"; 303 reg = <0x9820000 0x1000>; 304 }; 305 306 gcc: clock-controller@300000 { 307 compatible = "qcom,gcc-msm8996"; 308 #clock-cells = <1>; 309 #reset-cells = <1>; 310 #power-domain-cells = <1>; 311 reg = <0x300000 0x90000>; 312 }; 313 314 kryocc: clock-controller@6400000 { 315 compatible = "qcom,apcc-msm8996"; 316 reg = <0x6400000 0x90000>; 317 #clock-cells = <1>; 318 }; 319 320 blsp1_spi0: spi@07575000 { 321 compatible = "qcom,spi-qup-v2.2.1"; 322 reg = <0x07575000 0x600>; 323 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 325 <&gcc GCC_BLSP1_AHB_CLK>; 326 clock-names = "core", "iface"; 327 pinctrl-names = "default", "sleep"; 328 pinctrl-0 = <&blsp1_spi0_default>; 329 pinctrl-1 = <&blsp1_spi0_sleep>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 status = "disabled"; 333 }; 334 335 blsp2_i2c0: i2c@075b5000 { 336 compatible = "qcom,i2c-qup-v2.2.1"; 337 reg = <0x075b5000 0x1000>; 338 interrupts = <GIC_SPI 101 0>; 339 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 340 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 341 clock-names = "iface", "core"; 342 pinctrl-names = "default", "sleep"; 343 pinctrl-0 = <&blsp2_i2c0_default>; 344 pinctrl-1 = <&blsp2_i2c0_sleep>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 }; 349 350 tsens0: thermal-sensor@4a8000 { 351 compatible = "qcom,msm8996-tsens"; 352 reg = <0x4a8000 0x2000>; 353 #thermal-sensor-cells = <1>; 354 }; 355 356 blsp2_uart1: serial@75b0000 { 357 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 358 reg = <0x75b0000 0x1000>; 359 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 361 <&gcc GCC_BLSP2_AHB_CLK>; 362 clock-names = "core", "iface"; 363 status = "disabled"; 364 }; 365 366 blsp2_i2c1: i2c@075b6000 { 367 compatible = "qcom,i2c-qup-v2.2.1"; 368 reg = <0x075b6000 0x1000>; 369 interrupts = <GIC_SPI 102 0>; 370 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 371 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 372 clock-names = "iface", "core"; 373 pinctrl-names = "default", "sleep"; 374 pinctrl-0 = <&blsp2_i2c1_default>; 375 pinctrl-1 = <&blsp2_i2c1_sleep>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 status = "disabled"; 379 }; 380 381 blsp2_uart2: serial@75b1000 { 382 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 383 reg = <0x075b1000 0x1000>; 384 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 386 <&gcc GCC_BLSP2_AHB_CLK>; 387 clock-names = "core", "iface"; 388 status = "disabled"; 389 }; 390 391 blsp1_i2c2: i2c@07577000 { 392 compatible = "qcom,i2c-qup-v2.2.1"; 393 reg = <0x07577000 0x1000>; 394 interrupts = <GIC_SPI 97 0>; 395 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 396 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 397 clock-names = "iface", "core"; 398 pinctrl-names = "default", "sleep"; 399 pinctrl-0 = <&blsp1_i2c2_default>; 400 pinctrl-1 = <&blsp1_i2c2_sleep>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 blsp2_spi5: spi@075ba000{ 407 compatible = "qcom,spi-qup-v2.2.1"; 408 reg = <0x075ba000 0x600>; 409 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 411 <&gcc GCC_BLSP2_AHB_CLK>; 412 clock-names = "core", "iface"; 413 pinctrl-names = "default", "sleep"; 414 pinctrl-0 = <&blsp2_spi5_default>; 415 pinctrl-1 = <&blsp2_spi5_sleep>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 status = "disabled"; 419 }; 420 421 sdhc2: sdhci@74a4900 { 422 status = "disabled"; 423 compatible = "qcom,sdhci-msm-v4"; 424 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 425 reg-names = "hc_mem", "core_mem"; 426 427 interrupts = <0 125 0>, <0 221 0>; 428 interrupt-names = "hc_irq", "pwr_irq"; 429 430 clock-names = "iface", "core", "xo"; 431 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 432 <&gcc GCC_SDCC2_APPS_CLK>, 433 <&xo_board>; 434 bus-width = <4>; 435 }; 436 437 msmgpio: pinctrl@1010000 { 438 compatible = "qcom,msm8996-pinctrl"; 439 reg = <0x01010000 0x300000>; 440 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446 447 timer@09840000 { 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges; 451 compatible = "arm,armv7-timer-mem"; 452 reg = <0x09840000 0x1000>; 453 clock-frequency = <19200000>; 454 455 frame@9850000 { 456 frame-number = <0>; 457 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 459 reg = <0x09850000 0x1000>, 460 <0x09860000 0x1000>; 461 }; 462 463 frame@9870000 { 464 frame-number = <1>; 465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 466 reg = <0x09870000 0x1000>; 467 status = "disabled"; 468 }; 469 470 frame@9880000 { 471 frame-number = <2>; 472 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 473 reg = <0x09880000 0x1000>; 474 status = "disabled"; 475 }; 476 477 frame@9890000 { 478 frame-number = <3>; 479 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 480 reg = <0x09890000 0x1000>; 481 status = "disabled"; 482 }; 483 484 frame@98a0000 { 485 frame-number = <4>; 486 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 487 reg = <0x098a0000 0x1000>; 488 status = "disabled"; 489 }; 490 491 frame@98b0000 { 492 frame-number = <5>; 493 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 494 reg = <0x098b0000 0x1000>; 495 status = "disabled"; 496 }; 497 498 frame@98c0000 { 499 frame-number = <6>; 500 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 501 reg = <0x098c0000 0x1000>; 502 status = "disabled"; 503 }; 504 }; 505 506 spmi_bus: qcom,spmi@400f000 { 507 compatible = "qcom,spmi-pmic-arb"; 508 reg = <0x400f000 0x1000>, 509 <0x4400000 0x800000>, 510 <0x4c00000 0x800000>, 511 <0x5800000 0x200000>, 512 <0x400a000 0x002100>; 513 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 514 interrupt-names = "periph_irq"; 515 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 516 qcom,ee = <0>; 517 qcom,channel = <0>; 518 #address-cells = <2>; 519 #size-cells = <0>; 520 interrupt-controller; 521 #interrupt-cells = <4>; 522 }; 523 524 mmcc: clock-controller@8c0000 { 525 compatible = "qcom,mmcc-msm8996"; 526 #clock-cells = <1>; 527 #reset-cells = <1>; 528 #power-domain-cells = <1>; 529 reg = <0x8c0000 0x40000>; 530 assigned-clocks = <&mmcc MMPLL9_PLL>, 531 <&mmcc MMPLL1_PLL>, 532 <&mmcc MMPLL3_PLL>, 533 <&mmcc MMPLL4_PLL>, 534 <&mmcc MMPLL5_PLL>; 535 assigned-clock-rates = <624000000>, 536 <810000000>, 537 <980000000>, 538 <960000000>, 539 <825000000>; 540 }; 541 }; 542 543 adsp-pil { 544 compatible = "qcom,msm8996-adsp-pil"; 545 546 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 547 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 548 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 549 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 550 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 551 interrupt-names = "wdog", "fatal", "ready", 552 "handover", "stop-ack"; 553 554 clocks = <&xo_board>; 555 clock-names = "xo"; 556 557 memory-region = <&adsp_region>; 558 559 qcom,smem-states = <&adsp_smp2p_out 0>; 560 qcom,smem-state-names = "stop"; 561 }; 562 563 adsp-smp2p { 564 compatible = "qcom,smp2p"; 565 qcom,smem = <443>, <429>; 566 567 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 568 569 qcom,ipc = <&apcs 16 10>; 570 571 qcom,local-pid = <0>; 572 qcom,remote-pid = <2>; 573 574 adsp_smp2p_out: master-kernel { 575 qcom,entry-name = "master-kernel"; 576 #qcom,smem-state-cells = <1>; 577 }; 578 579 adsp_smp2p_in: slave-kernel { 580 qcom,entry-name = "slave-kernel"; 581 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 }; 585 }; 586 587 smp2p-slpi { 588 compatible = "qcom,smp2p"; 589 qcom,smem = <481>, <430>; 590 591 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 592 593 qcom,ipc = <&apcs 16 26>; 594 595 qcom,local-pid = <0>; 596 qcom,remote-pid = <3>; 597 598 slpi_smp2p_in: slave-kernel { 599 qcom,entry-name = "slave-kernel"; 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 }; 603 604 slpi_smp2p_out: master-kernel { 605 qcom,entry-name = "master-kernel"; 606 #qcom,smem-state-cells = <1>; 607 }; 608 }; 609 610}; 611#include "msm8996-pins.dtsi" 612