1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16#include <dt-bindings/clock/qcom,rpmcc.h> 17 18/ { 19 model = "Qualcomm Technologies, Inc. MSM8996"; 20 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 memory { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 mba_region: mba@91500000 { 40 reg = <0x0 0x91500000 0x0 0x200000>; 41 no-map; 42 }; 43 44 slpi_region: slpi@90b00000 { 45 reg = <0x0 0x90b00000 0x0 0xa00000>; 46 no-map; 47 }; 48 49 venus_region: venus@90400000 { 50 reg = <0x0 0x90400000 0x0 0x700000>; 51 no-map; 52 }; 53 54 adsp_region: adsp@8ea00000 { 55 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 56 no-map; 57 }; 58 59 mpss_region: mpss@88800000 { 60 reg = <0x0 0x88800000 0x0 0x6200000>; 61 no-map; 62 }; 63 64 smem_mem: smem-mem@86000000 { 65 reg = <0x0 0x86000000 0x0 0x200000>; 66 no-map; 67 }; 68 69 memory@85800000 { 70 reg = <0x0 0x85800000 0x0 0x800000>; 71 no-map; 72 }; 73 74 memory@86200000 { 75 reg = <0x0 0x86200000 0x0 0x2600000>; 76 no-map; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <2>; 82 #size-cells = <0>; 83 84 CPU0: cpu@0 { 85 device_type = "cpu"; 86 compatible = "qcom,kryo"; 87 reg = <0x0 0x0>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 L2_0: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 }; 94 }; 95 96 CPU1: cpu@1 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_0>; 102 }; 103 104 CPU2: cpu@100 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo"; 107 reg = <0x0 0x100>; 108 enable-method = "psci"; 109 next-level-cache = <&L2_1>; 110 L2_1: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 }; 114 }; 115 116 CPU3: cpu@101 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo"; 119 reg = <0x0 0x101>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_1>; 122 }; 123 124 cpu-map { 125 cluster0 { 126 core0 { 127 cpu = <&CPU0>; 128 }; 129 130 core1 { 131 cpu = <&CPU1>; 132 }; 133 }; 134 135 cluster1 { 136 core0 { 137 cpu = <&CPU2>; 138 }; 139 140 core1 { 141 cpu = <&CPU3>; 142 }; 143 }; 144 }; 145 }; 146 147 thermal-zones { 148 cpu-thermal0 { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens0 3>; 153 154 trips { 155 cpu_alert0: trip0 { 156 temperature = <75000>; 157 hysteresis = <2000>; 158 type = "passive"; 159 }; 160 161 cpu_crit0: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu-thermal1 { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens0 5>; 174 175 trips { 176 cpu_alert1: trip0 { 177 temperature = <75000>; 178 hysteresis = <2000>; 179 type = "passive"; 180 }; 181 182 cpu_crit1: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 190 cpu-thermal2 { 191 polling-delay-passive = <250>; 192 polling-delay = <1000>; 193 194 thermal-sensors = <&tsens0 8>; 195 196 trips { 197 cpu_alert2: trip0 { 198 temperature = <75000>; 199 hysteresis = <2000>; 200 type = "passive"; 201 }; 202 203 cpu_crit2: trip1 { 204 temperature = <110000>; 205 hysteresis = <2000>; 206 type = "critical"; 207 }; 208 }; 209 }; 210 211 cpu-thermal3 { 212 polling-delay-passive = <250>; 213 polling-delay = <1000>; 214 215 thermal-sensors = <&tsens0 10>; 216 217 trips { 218 cpu_alert3: trip0 { 219 temperature = <75000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 224 cpu_crit3: trip1 { 225 temperature = <110000>; 226 hysteresis = <2000>; 227 type = "critical"; 228 }; 229 }; 230 }; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 239 }; 240 241 clocks { 242 xo_board: xo_board { 243 compatible = "fixed-clock"; 244 #clock-cells = <0>; 245 clock-frequency = <19200000>; 246 clock-output-names = "xo_board"; 247 }; 248 249 sleep_clk: sleep_clk { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <32764>; 253 clock-output-names = "sleep_clk"; 254 }; 255 }; 256 257 psci { 258 compatible = "arm,psci-1.0"; 259 method = "smc"; 260 }; 261 262 firmware { 263 scm { 264 compatible = "qcom,scm-msm8996"; 265 266 qcom,dload-mode = <&tcsr 0x13000>; 267 }; 268 }; 269 270 tcsr_mutex: hwlock { 271 compatible = "qcom,tcsr-mutex"; 272 syscon = <&tcsr_mutex_regs 0 0x1000>; 273 #hwlock-cells = <1>; 274 }; 275 276 smem { 277 compatible = "qcom,smem"; 278 memory-region = <&smem_mem>; 279 hwlocks = <&tcsr_mutex 3>; 280 }; 281 282 rpm-glink { 283 compatible = "qcom,glink-rpm"; 284 285 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 286 287 qcom,rpm-msg-ram = <&rpm_msg_ram>; 288 289 mboxes = <&apcs_glb 0>; 290 291 rpm_requests { 292 compatible = "qcom,rpm-msm8996"; 293 qcom,glink-channels = "rpm_requests"; 294 295 rpmcc: qcom,rpmcc { 296 compatible = "qcom,rpmcc-msm8996"; 297 #clock-cells = <1>; 298 }; 299 300 pm8994-regulators { 301 compatible = "qcom,rpm-pm8994-regulators"; 302 303 pm8994_s1: s1 {}; 304 pm8994_s2: s2 {}; 305 pm8994_s3: s3 {}; 306 pm8994_s4: s4 {}; 307 pm8994_s5: s5 {}; 308 pm8994_s6: s6 {}; 309 pm8994_s7: s7 {}; 310 pm8994_s8: s8 {}; 311 pm8994_s9: s9 {}; 312 pm8994_s10: s10 {}; 313 pm8994_s11: s11 {}; 314 pm8994_s12: s12 {}; 315 316 pm8994_l1: l1 {}; 317 pm8994_l2: l2 {}; 318 pm8994_l3: l3 {}; 319 pm8994_l4: l4 {}; 320 pm8994_l5: l5 {}; 321 pm8994_l6: l6 {}; 322 pm8994_l7: l7 {}; 323 pm8994_l8: l8 {}; 324 pm8994_l9: l9 {}; 325 pm8994_l10: l10 {}; 326 pm8994_l11: l11 {}; 327 pm8994_l12: l12 {}; 328 pm8994_l13: l13 {}; 329 pm8994_l14: l14 {}; 330 pm8994_l15: l15 {}; 331 pm8994_l16: l16 {}; 332 pm8994_l17: l17 {}; 333 pm8994_l18: l18 {}; 334 pm8994_l19: l19 {}; 335 pm8994_l20: l20 {}; 336 pm8994_l21: l21 {}; 337 pm8994_l22: l22 {}; 338 pm8994_l23: l23 {}; 339 pm8994_l24: l24 {}; 340 pm8994_l25: l25 {}; 341 pm8994_l26: l26 {}; 342 pm8994_l27: l27 {}; 343 pm8994_l28: l28 {}; 344 pm8994_l29: l29 {}; 345 pm8994_l30: l30 {}; 346 pm8994_l31: l31 {}; 347 pm8994_l32: l32 {}; 348 }; 349 350 }; 351 }; 352 353 soc: soc { 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0 0 0 0xffffffff>; 357 compatible = "simple-bus"; 358 359 rpm_msg_ram: memory@68000 { 360 compatible = "qcom,rpm-msg-ram"; 361 reg = <0x68000 0x6000>; 362 }; 363 364 tcsr_mutex_regs: syscon@740000 { 365 compatible = "syscon"; 366 reg = <0x740000 0x20000>; 367 }; 368 369 tcsr: syscon@7a0000 { 370 compatible = "qcom,tcsr-msm8996", "syscon"; 371 reg = <0x7a0000 0x18000>; 372 }; 373 374 intc: interrupt-controller@9bc0000 { 375 compatible = "arm,gic-v3"; 376 #interrupt-cells = <3>; 377 interrupt-controller; 378 #redistributor-regions = <1>; 379 redistributor-stride = <0x0 0x40000>; 380 reg = <0x09bc0000 0x10000>, 381 <0x09c00000 0x100000>; 382 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 383 }; 384 385 apcs: syscon@9820000 { 386 compatible = "syscon"; 387 reg = <0x9820000 0x1000>; 388 }; 389 390 apcs_glb: mailbox@9820000 { 391 compatible = "qcom,msm8996-apcs-hmss-global"; 392 reg = <0x9820000 0x1000>; 393 394 #mbox-cells = <1>; 395 }; 396 397 gcc: clock-controller@300000 { 398 compatible = "qcom,gcc-msm8996"; 399 #clock-cells = <1>; 400 #reset-cells = <1>; 401 #power-domain-cells = <1>; 402 reg = <0x300000 0x90000>; 403 }; 404 405 kryocc: clock-controller@6400000 { 406 compatible = "qcom,apcc-msm8996"; 407 reg = <0x6400000 0x90000>; 408 #clock-cells = <1>; 409 }; 410 411 blsp1_spi0: spi@7575000 { 412 compatible = "qcom,spi-qup-v2.2.1"; 413 reg = <0x07575000 0x600>; 414 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 416 <&gcc GCC_BLSP1_AHB_CLK>; 417 clock-names = "core", "iface"; 418 pinctrl-names = "default", "sleep"; 419 pinctrl-0 = <&blsp1_spi0_default>; 420 pinctrl-1 = <&blsp1_spi0_sleep>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 blsp2_i2c0: i2c@75b5000 { 427 compatible = "qcom,i2c-qup-v2.2.1"; 428 reg = <0x075b5000 0x1000>; 429 interrupts = <GIC_SPI 101 0>; 430 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 431 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 432 clock-names = "iface", "core"; 433 pinctrl-names = "default", "sleep"; 434 pinctrl-0 = <&blsp2_i2c0_default>; 435 pinctrl-1 = <&blsp2_i2c0_sleep>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 tsens0: thermal-sensor@4a8000 { 442 compatible = "qcom,msm8996-tsens"; 443 reg = <0x4a8000 0x2000>; 444 #thermal-sensor-cells = <1>; 445 }; 446 447 blsp2_uart1: serial@75b0000 { 448 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 449 reg = <0x75b0000 0x1000>; 450 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 452 <&gcc GCC_BLSP2_AHB_CLK>; 453 clock-names = "core", "iface"; 454 status = "disabled"; 455 }; 456 457 blsp2_i2c1: i2c@75b6000 { 458 compatible = "qcom,i2c-qup-v2.2.1"; 459 reg = <0x075b6000 0x1000>; 460 interrupts = <GIC_SPI 102 0>; 461 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 462 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 463 clock-names = "iface", "core"; 464 pinctrl-names = "default", "sleep"; 465 pinctrl-0 = <&blsp2_i2c1_default>; 466 pinctrl-1 = <&blsp2_i2c1_sleep>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 blsp2_uart2: serial@75b1000 { 473 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 474 reg = <0x075b1000 0x1000>; 475 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 477 <&gcc GCC_BLSP2_AHB_CLK>; 478 clock-names = "core", "iface"; 479 status = "disabled"; 480 }; 481 482 blsp1_i2c2: i2c@7577000 { 483 compatible = "qcom,i2c-qup-v2.2.1"; 484 reg = <0x07577000 0x1000>; 485 interrupts = <GIC_SPI 97 0>; 486 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 487 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 488 clock-names = "iface", "core"; 489 pinctrl-names = "default", "sleep"; 490 pinctrl-0 = <&blsp1_i2c2_default>; 491 pinctrl-1 = <&blsp1_i2c2_sleep>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 status = "disabled"; 495 }; 496 497 blsp2_spi5: spi@75ba000{ 498 compatible = "qcom,spi-qup-v2.2.1"; 499 reg = <0x075ba000 0x600>; 500 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 502 <&gcc GCC_BLSP2_AHB_CLK>; 503 clock-names = "core", "iface"; 504 pinctrl-names = "default", "sleep"; 505 pinctrl-0 = <&blsp2_spi5_default>; 506 pinctrl-1 = <&blsp2_spi5_sleep>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 sdhc2: sdhci@74a4900 { 513 status = "disabled"; 514 compatible = "qcom,sdhci-msm-v4"; 515 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 516 reg-names = "hc_mem", "core_mem"; 517 518 interrupts = <0 125 0>, <0 221 0>; 519 interrupt-names = "hc_irq", "pwr_irq"; 520 521 clock-names = "iface", "core", "xo"; 522 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 523 <&gcc GCC_SDCC2_APPS_CLK>, 524 <&xo_board>; 525 bus-width = <4>; 526 }; 527 528 msmgpio: pinctrl@1010000 { 529 compatible = "qcom,msm8996-pinctrl"; 530 reg = <0x01010000 0x300000>; 531 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 532 gpio-controller; 533 #gpio-cells = <2>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 timer@9840000 { 539 #address-cells = <1>; 540 #size-cells = <1>; 541 ranges; 542 compatible = "arm,armv7-timer-mem"; 543 reg = <0x09840000 0x1000>; 544 clock-frequency = <19200000>; 545 546 frame@9850000 { 547 frame-number = <0>; 548 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 550 reg = <0x09850000 0x1000>, 551 <0x09860000 0x1000>; 552 }; 553 554 frame@9870000 { 555 frame-number = <1>; 556 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 557 reg = <0x09870000 0x1000>; 558 status = "disabled"; 559 }; 560 561 frame@9880000 { 562 frame-number = <2>; 563 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 564 reg = <0x09880000 0x1000>; 565 status = "disabled"; 566 }; 567 568 frame@9890000 { 569 frame-number = <3>; 570 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 571 reg = <0x09890000 0x1000>; 572 status = "disabled"; 573 }; 574 575 frame@98a0000 { 576 frame-number = <4>; 577 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 578 reg = <0x098a0000 0x1000>; 579 status = "disabled"; 580 }; 581 582 frame@98b0000 { 583 frame-number = <5>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 reg = <0x098b0000 0x1000>; 586 status = "disabled"; 587 }; 588 589 frame@98c0000 { 590 frame-number = <6>; 591 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 592 reg = <0x098c0000 0x1000>; 593 status = "disabled"; 594 }; 595 }; 596 597 spmi_bus: qcom,spmi@400f000 { 598 compatible = "qcom,spmi-pmic-arb"; 599 reg = <0x400f000 0x1000>, 600 <0x4400000 0x800000>, 601 <0x4c00000 0x800000>, 602 <0x5800000 0x200000>, 603 <0x400a000 0x002100>; 604 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 605 interrupt-names = "periph_irq"; 606 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 607 qcom,ee = <0>; 608 qcom,channel = <0>; 609 #address-cells = <2>; 610 #size-cells = <0>; 611 interrupt-controller; 612 #interrupt-cells = <4>; 613 }; 614 615 mmcc: clock-controller@8c0000 { 616 compatible = "qcom,mmcc-msm8996"; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 #power-domain-cells = <1>; 620 reg = <0x8c0000 0x40000>; 621 assigned-clocks = <&mmcc MMPLL9_PLL>, 622 <&mmcc MMPLL1_PLL>, 623 <&mmcc MMPLL3_PLL>, 624 <&mmcc MMPLL4_PLL>, 625 <&mmcc MMPLL5_PLL>; 626 assigned-clock-rates = <624000000>, 627 <810000000>, 628 <980000000>, 629 <960000000>, 630 <825000000>; 631 }; 632 633 qfprom@74000 { 634 compatible = "qcom,qfprom"; 635 reg = <0x74000 0x8ff>; 636 #address-cells = <1>; 637 #size-cells = <1>; 638 639 qusb2p_hstx_trim: hstx_trim@24e { 640 reg = <0x24e 0x2>; 641 bits = <5 4>; 642 }; 643 644 qusb2s_hstx_trim: hstx_trim@24f { 645 reg = <0x24f 0x1>; 646 bits = <1 4>; 647 }; 648 }; 649 650 phy@34000 { 651 compatible = "qcom,msm8996-qmp-pcie-phy"; 652 reg = <0x34000 0x488>; 653 #clock-cells = <1>; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges; 657 658 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 659 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 660 <&gcc GCC_PCIE_CLKREF_CLK>; 661 clock-names = "aux", "cfg_ahb", "ref"; 662 663 vdda-phy-supply = <&pm8994_l28>; 664 vdda-pll-supply = <&pm8994_l12>; 665 666 resets = <&gcc GCC_PCIE_PHY_BCR>, 667 <&gcc GCC_PCIE_PHY_COM_BCR>, 668 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 669 reset-names = "phy", "common", "cfg"; 670 status = "disabled"; 671 672 pciephy_0: lane@35000 { 673 reg = <0x035000 0x130>, 674 <0x035200 0x200>, 675 <0x035400 0x1dc>; 676 #phy-cells = <0>; 677 678 clock-output-names = "pcie_0_pipe_clk_src"; 679 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 680 clock-names = "pipe0"; 681 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 682 reset-names = "lane0"; 683 }; 684 685 pciephy_1: lane@36000 { 686 reg = <0x036000 0x130>, 687 <0x036200 0x200>, 688 <0x036400 0x1dc>; 689 #phy-cells = <0>; 690 691 clock-output-names = "pcie_1_pipe_clk_src"; 692 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 693 clock-names = "pipe1"; 694 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 695 reset-names = "lane1"; 696 }; 697 698 pciephy_2: lane@37000 { 699 reg = <0x037000 0x130>, 700 <0x037200 0x200>, 701 <0x037400 0x1dc>; 702 #phy-cells = <0>; 703 704 clock-output-names = "pcie_2_pipe_clk_src"; 705 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 706 clock-names = "pipe2"; 707 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 708 reset-names = "lane2"; 709 }; 710 }; 711 712 phy@7410000 { 713 compatible = "qcom,msm8996-qmp-usb3-phy"; 714 reg = <0x7410000 0x1c4>; 715 #clock-cells = <1>; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges; 719 720 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 721 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 722 <&gcc GCC_USB3_CLKREF_CLK>; 723 clock-names = "aux", "cfg_ahb", "ref"; 724 725 vdda-phy-supply = <&pm8994_l28>; 726 vdda-pll-supply = <&pm8994_l12>; 727 728 resets = <&gcc GCC_USB3_PHY_BCR>, 729 <&gcc GCC_USB3PHY_PHY_BCR>; 730 reset-names = "phy", "common"; 731 status = "disabled"; 732 733 ssusb_phy_0: lane@7410200 { 734 reg = <0x7410200 0x200>, 735 <0x7410400 0x130>, 736 <0x7410600 0x1a8>; 737 #phy-cells = <0>; 738 739 clock-output-names = "usb3_phy_pipe_clk_src"; 740 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 741 clock-names = "pipe0"; 742 }; 743 }; 744 745 hsusb_phy1: phy@7411000 { 746 compatible = "qcom,msm8996-qusb2-phy"; 747 reg = <0x7411000 0x180>; 748 #phy-cells = <0>; 749 750 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 751 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 752 clock-names = "cfg_ahb", "ref"; 753 754 vdda-pll-supply = <&pm8994_l12>; 755 vdda-phy-dpdm-supply = <&pm8994_l24>; 756 757 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 758 nvmem-cells = <&qusb2p_hstx_trim>; 759 status = "disabled"; 760 }; 761 762 hsusb_phy2: phy@7412000 { 763 compatible = "qcom,msm8996-qusb2-phy"; 764 reg = <0x7412000 0x180>; 765 #phy-cells = <0>; 766 767 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 768 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 769 clock-names = "cfg_ahb", "ref"; 770 771 vdda-pll-supply = <&pm8994_l12>; 772 vdda-phy-dpdm-supply = <&pm8994_l24>; 773 774 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 775 nvmem-cells = <&qusb2s_hstx_trim>; 776 status = "disabled"; 777 }; 778 779 usb2: usb@7600000 { 780 compatible = "qcom,dwc3"; 781 #address-cells = <1>; 782 #size-cells = <1>; 783 ranges; 784 785 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 786 <&gcc GCC_USB20_MASTER_CLK>, 787 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 788 <&gcc GCC_USB20_SLEEP_CLK>, 789 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 790 791 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 792 <&gcc GCC_USB20_MASTER_CLK>; 793 assigned-clock-rates = <19200000>, <60000000>; 794 795 power-domains = <&gcc USB30_GDSC>; 796 status = "disabled"; 797 798 dwc3@7600000 { 799 compatible = "snps,dwc3"; 800 reg = <0x7600000 0xcc00>; 801 interrupts = <0 138 0>; 802 phys = <&hsusb_phy2>; 803 phy-names = "usb2-phy"; 804 }; 805 }; 806 807 usb3: usb@6a00000 { 808 compatible = "qcom,dwc3"; 809 #address-cells = <1>; 810 #size-cells = <1>; 811 ranges; 812 813 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 814 <&gcc GCC_USB30_MASTER_CLK>, 815 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 816 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 817 <&gcc GCC_USB30_SLEEP_CLK>, 818 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 819 820 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 821 <&gcc GCC_USB30_MASTER_CLK>; 822 assigned-clock-rates = <19200000>, <120000000>; 823 824 power-domains = <&gcc USB30_GDSC>; 825 status = "disabled"; 826 827 dwc3@6a00000 { 828 compatible = "snps,dwc3"; 829 reg = <0x6a00000 0xcc00>; 830 interrupts = <0 131 0>; 831 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 832 phy-names = "usb2-phy", "usb3-phy"; 833 }; 834 }; 835 836 agnoc@0 { 837 power-domains = <&gcc AGGRE0_NOC_GDSC>; 838 compatible = "simple-pm-bus"; 839 #address-cells = <1>; 840 #size-cells = <1>; 841 ranges; 842 843 pcie0: qcom,pcie@600000 { 844 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 845 status = "disabled"; 846 power-domains = <&gcc PCIE0_GDSC>; 847 bus-range = <0x00 0xff>; 848 num-lanes = <1>; 849 850 reg = <0x00600000 0x2000>, 851 <0x0c000000 0xf1d>, 852 <0x0c000f20 0xa8>, 853 <0x0c100000 0x100000>; 854 reg-names = "parf", "dbi", "elbi","config"; 855 856 phys = <&pciephy_0>; 857 phy-names = "pciephy"; 858 859 #address-cells = <3>; 860 #size-cells = <2>; 861 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 862 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 863 864 interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>; 865 interrupt-names = "msi"; 866 #interrupt-cells = <1>; 867 interrupt-map-mask = <0 0 0 0x7>; 868 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 869 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 870 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 871 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 872 873 pinctrl-names = "default", "sleep"; 874 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 875 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 876 877 878 vdda-supply = <&pm8994_l28>; 879 880 linux,pci-domain = <0>; 881 882 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 883 <&gcc GCC_PCIE_0_AUX_CLK>, 884 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 885 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 886 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 887 888 clock-names = "pipe", 889 "aux", 890 "cfg", 891 "bus_master", 892 "bus_slave"; 893 894 }; 895 896 pcie1: qcom,pcie@608000 { 897 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 898 power-domains = <&gcc PCIE1_GDSC>; 899 bus-range = <0x00 0xff>; 900 num-lanes = <1>; 901 902 status = "disabled"; 903 904 reg = <0x00608000 0x2000>, 905 <0x0d000000 0xf1d>, 906 <0x0d000f20 0xa8>, 907 <0x0d100000 0x100000>; 908 909 reg-names = "parf", "dbi", "elbi","config"; 910 911 phys = <&pciephy_1>; 912 phy-names = "pciephy"; 913 914 #address-cells = <3>; 915 #size-cells = <2>; 916 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 917 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 918 919 interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>; 920 interrupt-names = "msi"; 921 #interrupt-cells = <1>; 922 interrupt-map-mask = <0 0 0 0x7>; 923 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 924 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 925 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 926 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 927 928 pinctrl-names = "default", "sleep"; 929 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 930 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 931 932 933 vdda-supply = <&pm8994_l28>; 934 linux,pci-domain = <1>; 935 936 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 937 <&gcc GCC_PCIE_1_AUX_CLK>, 938 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 939 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 940 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 941 942 clock-names = "pipe", 943 "aux", 944 "cfg", 945 "bus_master", 946 "bus_slave"; 947 }; 948 949 pcie2: qcom,pcie@610000 { 950 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 951 power-domains = <&gcc PCIE2_GDSC>; 952 bus-range = <0x00 0xff>; 953 num-lanes = <1>; 954 status = "disabled"; 955 reg = <0x00610000 0x2000>, 956 <0x0e000000 0xf1d>, 957 <0x0e000f20 0xa8>, 958 <0x0e100000 0x100000>; 959 960 reg-names = "parf", "dbi", "elbi","config"; 961 962 phys = <&pciephy_2>; 963 phy-names = "pciephy"; 964 965 #address-cells = <3>; 966 #size-cells = <2>; 967 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 968 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 969 970 device_type = "pci"; 971 972 interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>; 973 interrupt-names = "msi"; 974 #interrupt-cells = <1>; 975 interrupt-map-mask = <0 0 0 0x7>; 976 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 977 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 978 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 979 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 980 981 pinctrl-names = "default", "sleep"; 982 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 983 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 984 985 vdda-supply = <&pm8994_l28>; 986 987 linux,pci-domain = <2>; 988 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 989 <&gcc GCC_PCIE_2_AUX_CLK>, 990 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 991 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 992 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 993 994 clock-names = "pipe", 995 "aux", 996 "cfg", 997 "bus_master", 998 "bus_slave"; 999 }; 1000 }; 1001 }; 1002 1003 adsp-pil { 1004 compatible = "qcom,msm8996-adsp-pil"; 1005 1006 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 1007 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1008 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1009 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1010 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1011 interrupt-names = "wdog", "fatal", "ready", 1012 "handover", "stop-ack"; 1013 1014 clocks = <&xo_board>; 1015 clock-names = "xo"; 1016 1017 memory-region = <&adsp_region>; 1018 1019 qcom,smem-states = <&adsp_smp2p_out 0>; 1020 qcom,smem-state-names = "stop"; 1021 1022 smd-edge { 1023 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1024 1025 label = "lpass"; 1026 qcom,ipc = <&apcs 16 8>; 1027 qcom,smd-edge = <1>; 1028 qcom,remote-pid = <2>; 1029 }; 1030 }; 1031 1032 adsp-smp2p { 1033 compatible = "qcom,smp2p"; 1034 qcom,smem = <443>, <429>; 1035 1036 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 1037 1038 qcom,ipc = <&apcs 16 10>; 1039 1040 qcom,local-pid = <0>; 1041 qcom,remote-pid = <2>; 1042 1043 adsp_smp2p_out: master-kernel { 1044 qcom,entry-name = "master-kernel"; 1045 #qcom,smem-state-cells = <1>; 1046 }; 1047 1048 adsp_smp2p_in: slave-kernel { 1049 qcom,entry-name = "slave-kernel"; 1050 1051 interrupt-controller; 1052 #interrupt-cells = <2>; 1053 }; 1054 }; 1055 1056 modem-smp2p { 1057 compatible = "qcom,smp2p"; 1058 qcom,smem = <435>, <428>; 1059 1060 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1061 1062 qcom,ipc = <&apcs 16 14>; 1063 1064 qcom,local-pid = <0>; 1065 qcom,remote-pid = <1>; 1066 1067 modem_smp2p_out: master-kernel { 1068 qcom,entry-name = "master-kernel"; 1069 #qcom,smem-state-cells = <1>; 1070 }; 1071 1072 modem_smp2p_in: slave-kernel { 1073 qcom,entry-name = "slave-kernel"; 1074 1075 interrupt-controller; 1076 #interrupt-cells = <2>; 1077 }; 1078 }; 1079 1080 smp2p-slpi { 1081 compatible = "qcom,smp2p"; 1082 qcom,smem = <481>, <430>; 1083 1084 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 1085 1086 qcom,ipc = <&apcs 16 26>; 1087 1088 qcom,local-pid = <0>; 1089 qcom,remote-pid = <3>; 1090 1091 slpi_smp2p_in: slave-kernel { 1092 qcom,entry-name = "slave-kernel"; 1093 interrupt-controller; 1094 #interrupt-cells = <2>; 1095 }; 1096 1097 slpi_smp2p_out: master-kernel { 1098 qcom,entry-name = "master-kernel"; 1099 #qcom,smem-state-cells = <1>; 1100 }; 1101 }; 1102 1103}; 1104#include "msm8996-pins.dtsi" 1105