xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision 82003e04) 
1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/qcom,gcc-msm8996.h>
15#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
16
17/ {
18	model = "Qualcomm Technologies, Inc. MSM8996";
19
20	interrupt-parent = <&intc>;
21
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	chosen { };
26
27	memory {
28		device_type = "memory";
29		/* We expect the bootloader to fill in the reg */
30		reg = <0 0 0 0>;
31	};
32
33	cpus {
34		#address-cells = <2>;
35		#size-cells = <0>;
36
37		CPU0: cpu@0 {
38			device_type = "cpu";
39			compatible = "qcom,kryo";
40			reg = <0x0 0x0>;
41			enable-method = "psci";
42			next-level-cache = <&L2_0>;
43			L2_0: l2-cache {
44			      compatible = "cache";
45			      cache-level = <2>;
46			};
47		};
48
49		CPU1: cpu@1 {
50			device_type = "cpu";
51			compatible = "qcom,kryo";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&L2_0>;
55		};
56
57		CPU2: cpu@100 {
58			device_type = "cpu";
59			compatible = "qcom,kryo";
60			reg = <0x0 0x100>;
61			enable-method = "psci";
62			next-level-cache = <&L2_1>;
63			L2_1: l2-cache {
64			      compatible = "cache";
65			      cache-level = <2>;
66			};
67		};
68
69		CPU3: cpu@101 {
70			device_type = "cpu";
71			compatible = "qcom,kryo";
72			reg = <0x0 0x101>;
73			enable-method = "psci";
74			next-level-cache = <&L2_1>;
75		};
76
77		cpu-map {
78			cluster0 {
79				core0 {
80					cpu = <&CPU0>;
81				};
82
83				core1 {
84					cpu = <&CPU1>;
85				};
86			};
87
88			cluster1 {
89				core0 {
90					cpu = <&CPU2>;
91				};
92
93				core1 {
94					cpu = <&CPU3>;
95				};
96			};
97		};
98	};
99
100	thermal-zones {
101		cpu-thermal0 {
102			polling-delay-passive = <250>;
103			polling-delay = <1000>;
104
105			thermal-sensors = <&tsens0 3>;
106
107			trips {
108				cpu_alert0: trip0 {
109					temperature = <75000>;
110					hysteresis = <2000>;
111					type = "passive";
112				};
113
114				cpu_crit0: trip1 {
115					temperature = <110000>;
116					hysteresis = <2000>;
117					type = "critical";
118				};
119			};
120		};
121
122		cpu-thermal1 {
123			polling-delay-passive = <250>;
124			polling-delay = <1000>;
125
126			thermal-sensors = <&tsens0 5>;
127
128			trips {
129				cpu_alert1: trip0 {
130					temperature = <75000>;
131					hysteresis = <2000>;
132					type = "passive";
133				};
134
135				cpu_crit1: trip1 {
136					temperature = <110000>;
137					hysteresis = <2000>;
138					type = "critical";
139				};
140			};
141		};
142
143		cpu-thermal2 {
144			polling-delay-passive = <250>;
145			polling-delay = <1000>;
146
147			thermal-sensors = <&tsens0 8>;
148
149			trips {
150				cpu_alert2: trip0 {
151					temperature = <75000>;
152					hysteresis = <2000>;
153					type = "passive";
154				};
155
156				cpu_crit2: trip1 {
157					temperature = <110000>;
158					hysteresis = <2000>;
159					type = "critical";
160				};
161			};
162		};
163
164		cpu-thermal3 {
165			polling-delay-passive = <250>;
166			polling-delay = <1000>;
167
168			thermal-sensors = <&tsens0 10>;
169
170			trips {
171				cpu_alert3: trip0 {
172					temperature = <75000>;
173					hysteresis = <2000>;
174					type = "passive";
175				};
176
177				cpu_crit3: trip1 {
178					temperature = <110000>;
179					hysteresis = <2000>;
180					type = "critical";
181				};
182			};
183		};
184	};
185
186	timer {
187		compatible = "arm,armv8-timer";
188		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
189			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
190			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
191			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
192	};
193
194	clocks {
195		xo_board {
196			compatible = "fixed-clock";
197			#clock-cells = <0>;
198			clock-frequency = <19200000>;
199			clock-output-names = "xo_board";
200		};
201
202		sleep_clk {
203			compatible = "fixed-clock";
204			#clock-cells = <0>;
205			clock-frequency = <32764>;
206			clock-output-names = "sleep_clk";
207		};
208	};
209
210	psci {
211		compatible = "arm,psci-1.0";
212		method = "smc";
213	};
214
215	soc: soc {
216		#address-cells = <1>;
217		#size-cells = <1>;
218		ranges = <0 0 0 0xffffffff>;
219		compatible = "simple-bus";
220
221		intc: interrupt-controller@9bc0000 {
222			compatible = "arm,gic-v3";
223			#interrupt-cells = <3>;
224			interrupt-controller;
225			#redistributor-regions = <1>;
226			redistributor-stride = <0x0 0x40000>;
227			reg = <0x09bc0000 0x10000>,
228			      <0x09c00000 0x100000>;
229			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
230		};
231
232		gcc: clock-controller@300000 {
233			compatible = "qcom,gcc-msm8996";
234			#clock-cells = <1>;
235			#reset-cells = <1>;
236			#power-domain-cells = <1>;
237			reg = <0x300000 0x90000>;
238		};
239
240		blsp1_spi0: spi@07575000 {
241			compatible = "qcom,spi-qup-v2.2.1";
242			reg = <0x07575000 0x600>;
243			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
244			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
245				 <&gcc GCC_BLSP1_AHB_CLK>;
246			clock-names = "core", "iface";
247			pinctrl-names = "default", "sleep";
248			pinctrl-0 = <&blsp1_spi0_default>;
249			pinctrl-1 = <&blsp1_spi0_sleep>;
250			#address-cells = <1>;
251			#size-cells = <0>;
252			status = "disabled";
253		};
254
255		blsp2_i2c0: i2c@075b5000 {
256			compatible = "qcom,i2c-qup-v2.2.1";
257			reg = <0x075b5000 0x1000>;
258			interrupts = <GIC_SPI 101 0>;
259			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
260				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
261			clock-names = "iface", "core";
262			pinctrl-names = "default", "sleep";
263			pinctrl-0 = <&blsp2_i2c0_default>;
264			pinctrl-1 = <&blsp2_i2c0_sleep>;
265			#address-cells = <1>;
266			#size-cells = <0>;
267			status = "disabled";
268		};
269
270		tsens0: thermal-sensor@4a8000 {
271			compatible = "qcom,msm8996-tsens";
272			reg = <0x4a8000 0x2000>;
273			#thermal-sensor-cells = <1>;
274		};
275
276		blsp2_uart1: serial@75b0000 {
277			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
278			reg = <0x75b0000 0x1000>;
279			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
280			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
281				 <&gcc GCC_BLSP2_AHB_CLK>;
282			clock-names = "core", "iface";
283			status = "disabled";
284		};
285
286		blsp2_i2c1: i2c@075b6000 {
287			compatible = "qcom,i2c-qup-v2.2.1";
288			reg = <0x075b6000 0x1000>;
289			interrupts = <GIC_SPI 102 0>;
290			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
291				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
292			clock-names = "iface", "core";
293			pinctrl-names = "default", "sleep";
294			pinctrl-0 = <&blsp2_i2c1_default>;
295			pinctrl-1 = <&blsp2_i2c1_sleep>;
296			#address-cells = <1>;
297			#size-cells = <0>;
298			status = "disabled";
299		};
300
301		blsp2_uart2: serial@75b1000 {
302			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
303			reg = <0x075b1000 0x1000>;
304			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
305			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
306				 <&gcc GCC_BLSP2_AHB_CLK>;
307			clock-names = "core", "iface";
308			status = "disabled";
309		};
310
311		blsp1_i2c2: i2c@07577000 {
312			compatible = "qcom,i2c-qup-v2.2.1";
313			reg = <0x07577000 0x1000>;
314			interrupts = <GIC_SPI 97 0>;
315			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
316				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
317			clock-names = "iface", "core";
318			pinctrl-names = "default", "sleep";
319			pinctrl-0 = <&blsp1_i2c2_default>;
320			pinctrl-1 = <&blsp1_i2c2_sleep>;
321			#address-cells = <1>;
322			#size-cells = <0>;
323			status = "disabled";
324		};
325
326		blsp2_spi5: spi@075ba000{
327			compatible = "qcom,spi-qup-v2.2.1";
328			reg = <0x075ba000 0x600>;
329			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
330			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
331				 <&gcc GCC_BLSP2_AHB_CLK>;
332			clock-names = "core", "iface";
333			pinctrl-names = "default", "sleep";
334			pinctrl-0 = <&blsp2_spi5_default>;
335			pinctrl-1 = <&blsp2_spi5_sleep>;
336			#address-cells = <1>;
337			#size-cells = <0>;
338			status = "disabled";
339		};
340
341		sdhc2: sdhci@74a4900 {
342			 status = "disabled";
343			 compatible = "qcom,sdhci-msm-v4";
344			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
345			 reg-names = "hc_mem", "core_mem";
346
347			 interrupts = <0 125 0>, <0 221 0>;
348			 interrupt-names = "hc_irq", "pwr_irq";
349
350			 clock-names = "iface", "core";
351			 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
352			 <&gcc GCC_SDCC2_APPS_CLK>;
353			 bus-width = <4>;
354		 };
355
356		msmgpio: pinctrl@1010000 {
357			compatible = "qcom,msm8996-pinctrl";
358			reg = <0x01010000 0x300000>;
359			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
360			gpio-controller;
361			#gpio-cells = <2>;
362			interrupt-controller;
363			#interrupt-cells = <2>;
364		};
365
366		timer@09840000 {
367			#address-cells = <1>;
368			#size-cells = <1>;
369			ranges;
370			compatible = "arm,armv7-timer-mem";
371			reg = <0x09840000 0x1000>;
372			clock-frequency = <19200000>;
373
374			frame@9850000 {
375				frame-number = <0>;
376				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
377					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378				reg = <0x09850000 0x1000>,
379				      <0x09860000 0x1000>;
380			};
381
382			frame@9870000 {
383				frame-number = <1>;
384				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
385				reg = <0x09870000 0x1000>;
386				status = "disabled";
387			};
388
389			frame@9880000 {
390				frame-number = <2>;
391				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
392				reg = <0x09880000 0x1000>;
393				status = "disabled";
394			};
395
396			frame@9890000 {
397				frame-number = <3>;
398				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
399				reg = <0x09890000 0x1000>;
400				status = "disabled";
401			};
402
403			frame@98a0000 {
404				frame-number = <4>;
405				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
406				reg = <0x098a0000 0x1000>;
407				status = "disabled";
408			};
409
410			frame@98b0000 {
411				frame-number = <5>;
412				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413				reg = <0x098b0000 0x1000>;
414				status = "disabled";
415			};
416
417			frame@98c0000 {
418				frame-number = <6>;
419				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
420				reg = <0x098c0000 0x1000>;
421				status = "disabled";
422			};
423		};
424
425		spmi_bus: qcom,spmi@400f000 {
426			compatible = "qcom,spmi-pmic-arb";
427			reg = <0x400f000 0x1000>,
428			      <0x4400000 0x800000>,
429			      <0x4c00000 0x800000>,
430			      <0x5800000 0x200000>,
431			      <0x400a000 0x002100>;
432			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
433			interrupt-names = "periph_irq";
434			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
435			qcom,ee = <0>;
436			qcom,channel = <0>;
437			#address-cells = <2>;
438			#size-cells = <0>;
439			interrupt-controller;
440			#interrupt-cells = <4>;
441		};
442
443		mmcc: clock-controller@8c0000 {
444			compatible = "qcom,mmcc-msm8996";
445			#clock-cells = <1>;
446			#reset-cells = <1>;
447			#power-domain-cells = <1>;
448			reg = <0x8c0000 0x40000>;
449			assigned-clocks = <&mmcc MMPLL9_PLL>,
450					  <&mmcc MMPLL1_PLL>,
451					  <&mmcc MMPLL3_PLL>,
452					  <&mmcc MMPLL4_PLL>,
453					  <&mmcc MMPLL5_PLL>;
454			assigned-clock-rates = <624000000>,
455					       <810000000>,
456					       <980000000>,
457					       <960000000>,
458					       <825000000>;
459		};
460	};
461};
462#include "msm8996-pins.dtsi"
463