1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16#include <dt-bindings/clock/qcom,rpmcc.h> 17 18/ { 19 model = "Qualcomm Technologies, Inc. MSM8996"; 20 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 memory { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 mba_region: mba@91500000 { 40 reg = <0x0 0x91500000 0x0 0x200000>; 41 no-map; 42 }; 43 44 slpi_region: slpi@90b00000 { 45 reg = <0x0 0x90b00000 0x0 0xa00000>; 46 no-map; 47 }; 48 49 venus_region: venus@90400000 { 50 reg = <0x0 0x90400000 0x0 0x700000>; 51 no-map; 52 }; 53 54 adsp_region: adsp@8ea00000 { 55 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 56 no-map; 57 }; 58 59 mpss_region: mpss@88800000 { 60 reg = <0x0 0x88800000 0x0 0x6200000>; 61 no-map; 62 }; 63 64 smem_mem: smem-mem@86000000 { 65 reg = <0x0 0x86000000 0x0 0x200000>; 66 no-map; 67 }; 68 69 memory@85800000 { 70 reg = <0x0 0x85800000 0x0 0x800000>; 71 no-map; 72 }; 73 74 memory@86200000 { 75 reg = <0x0 0x86200000 0x0 0x2600000>; 76 no-map; 77 }; 78 79 rmtfs@86700000 { 80 compatible = "qcom,rmtfs-mem"; 81 82 size = <0x0 0x200000>; 83 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 84 no-map; 85 86 qcom,client-id = <1>; 87 qcom,vmid = <15>; 88 }; 89 }; 90 91 cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 CPU0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo"; 98 reg = <0x0 0x0>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 L2_0: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 }; 105 }; 106 107 CPU1: cpu@1 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo"; 110 reg = <0x0 0x1>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_0>; 113 }; 114 115 CPU2: cpu@100 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x100>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_1>; 121 L2_1: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 }; 125 }; 126 127 CPU3: cpu@101 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo"; 130 reg = <0x0 0x101>; 131 enable-method = "psci"; 132 next-level-cache = <&L2_1>; 133 }; 134 135 cpu-map { 136 cluster0 { 137 core0 { 138 cpu = <&CPU0>; 139 }; 140 141 core1 { 142 cpu = <&CPU1>; 143 }; 144 }; 145 146 cluster1 { 147 core0 { 148 cpu = <&CPU2>; 149 }; 150 151 core1 { 152 cpu = <&CPU3>; 153 }; 154 }; 155 }; 156 }; 157 158 thermal-zones { 159 cpu-thermal0 { 160 polling-delay-passive = <250>; 161 polling-delay = <1000>; 162 163 thermal-sensors = <&tsens0 3>; 164 165 trips { 166 cpu_alert0: trip0 { 167 temperature = <75000>; 168 hysteresis = <2000>; 169 type = "passive"; 170 }; 171 172 cpu_crit0: trip1 { 173 temperature = <110000>; 174 hysteresis = <2000>; 175 type = "critical"; 176 }; 177 }; 178 }; 179 180 cpu-thermal1 { 181 polling-delay-passive = <250>; 182 polling-delay = <1000>; 183 184 thermal-sensors = <&tsens0 5>; 185 186 trips { 187 cpu_alert1: trip0 { 188 temperature = <75000>; 189 hysteresis = <2000>; 190 type = "passive"; 191 }; 192 193 cpu_crit1: trip1 { 194 temperature = <110000>; 195 hysteresis = <2000>; 196 type = "critical"; 197 }; 198 }; 199 }; 200 201 cpu-thermal2 { 202 polling-delay-passive = <250>; 203 polling-delay = <1000>; 204 205 thermal-sensors = <&tsens0 8>; 206 207 trips { 208 cpu_alert2: trip0 { 209 temperature = <75000>; 210 hysteresis = <2000>; 211 type = "passive"; 212 }; 213 214 cpu_crit2: trip1 { 215 temperature = <110000>; 216 hysteresis = <2000>; 217 type = "critical"; 218 }; 219 }; 220 }; 221 222 cpu-thermal3 { 223 polling-delay-passive = <250>; 224 polling-delay = <1000>; 225 226 thermal-sensors = <&tsens0 10>; 227 228 trips { 229 cpu_alert3: trip0 { 230 temperature = <75000>; 231 hysteresis = <2000>; 232 type = "passive"; 233 }; 234 235 cpu_crit3: trip1 { 236 temperature = <110000>; 237 hysteresis = <2000>; 238 type = "critical"; 239 }; 240 }; 241 }; 242 }; 243 244 timer { 245 compatible = "arm,armv8-timer"; 246 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 247 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 248 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 249 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 250 }; 251 252 clocks { 253 xo_board: xo_board { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency = <19200000>; 257 clock-output-names = "xo_board"; 258 }; 259 260 sleep_clk: sleep_clk { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency = <32764>; 264 clock-output-names = "sleep_clk"; 265 }; 266 }; 267 268 psci { 269 compatible = "arm,psci-1.0"; 270 method = "smc"; 271 }; 272 273 firmware { 274 scm { 275 compatible = "qcom,scm-msm8996"; 276 277 qcom,dload-mode = <&tcsr 0x13000>; 278 }; 279 }; 280 281 tcsr_mutex: hwlock { 282 compatible = "qcom,tcsr-mutex"; 283 syscon = <&tcsr_mutex_regs 0 0x1000>; 284 #hwlock-cells = <1>; 285 }; 286 287 smem { 288 compatible = "qcom,smem"; 289 memory-region = <&smem_mem>; 290 hwlocks = <&tcsr_mutex 3>; 291 }; 292 293 rpm-glink { 294 compatible = "qcom,glink-rpm"; 295 296 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 297 298 qcom,rpm-msg-ram = <&rpm_msg_ram>; 299 300 mboxes = <&apcs_glb 0>; 301 302 rpm_requests { 303 compatible = "qcom,rpm-msm8996"; 304 qcom,glink-channels = "rpm_requests"; 305 306 rpmcc: qcom,rpmcc { 307 compatible = "qcom,rpmcc-msm8996"; 308 #clock-cells = <1>; 309 }; 310 311 pm8994-regulators { 312 compatible = "qcom,rpm-pm8994-regulators"; 313 314 pm8994_s1: s1 {}; 315 pm8994_s2: s2 {}; 316 pm8994_s3: s3 {}; 317 pm8994_s4: s4 {}; 318 pm8994_s5: s5 {}; 319 pm8994_s6: s6 {}; 320 pm8994_s7: s7 {}; 321 pm8994_s8: s8 {}; 322 pm8994_s9: s9 {}; 323 pm8994_s10: s10 {}; 324 pm8994_s11: s11 {}; 325 pm8994_s12: s12 {}; 326 327 pm8994_l1: l1 {}; 328 pm8994_l2: l2 {}; 329 pm8994_l3: l3 {}; 330 pm8994_l4: l4 {}; 331 pm8994_l5: l5 {}; 332 pm8994_l6: l6 {}; 333 pm8994_l7: l7 {}; 334 pm8994_l8: l8 {}; 335 pm8994_l9: l9 {}; 336 pm8994_l10: l10 {}; 337 pm8994_l11: l11 {}; 338 pm8994_l12: l12 {}; 339 pm8994_l13: l13 {}; 340 pm8994_l14: l14 {}; 341 pm8994_l15: l15 {}; 342 pm8994_l16: l16 {}; 343 pm8994_l17: l17 {}; 344 pm8994_l18: l18 {}; 345 pm8994_l19: l19 {}; 346 pm8994_l20: l20 {}; 347 pm8994_l21: l21 {}; 348 pm8994_l22: l22 {}; 349 pm8994_l23: l23 {}; 350 pm8994_l24: l24 {}; 351 pm8994_l25: l25 {}; 352 pm8994_l26: l26 {}; 353 pm8994_l27: l27 {}; 354 pm8994_l28: l28 {}; 355 pm8994_l29: l29 {}; 356 pm8994_l30: l30 {}; 357 pm8994_l31: l31 {}; 358 pm8994_l32: l32 {}; 359 }; 360 361 }; 362 }; 363 364 soc: soc { 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0 0 0 0xffffffff>; 368 compatible = "simple-bus"; 369 370 rpm_msg_ram: memory@68000 { 371 compatible = "qcom,rpm-msg-ram"; 372 reg = <0x68000 0x6000>; 373 }; 374 375 tcsr_mutex_regs: syscon@740000 { 376 compatible = "syscon"; 377 reg = <0x740000 0x20000>; 378 }; 379 380 tcsr: syscon@7a0000 { 381 compatible = "qcom,tcsr-msm8996", "syscon"; 382 reg = <0x7a0000 0x18000>; 383 }; 384 385 intc: interrupt-controller@9bc0000 { 386 compatible = "arm,gic-v3"; 387 #interrupt-cells = <3>; 388 interrupt-controller; 389 #redistributor-regions = <1>; 390 redistributor-stride = <0x0 0x40000>; 391 reg = <0x09bc0000 0x10000>, 392 <0x09c00000 0x100000>; 393 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 394 }; 395 396 apcs: syscon@9820000 { 397 compatible = "syscon"; 398 reg = <0x9820000 0x1000>; 399 }; 400 401 apcs_glb: mailbox@9820000 { 402 compatible = "qcom,msm8996-apcs-hmss-global"; 403 reg = <0x9820000 0x1000>; 404 405 #mbox-cells = <1>; 406 }; 407 408 gcc: clock-controller@300000 { 409 compatible = "qcom,gcc-msm8996"; 410 #clock-cells = <1>; 411 #reset-cells = <1>; 412 #power-domain-cells = <1>; 413 reg = <0x300000 0x90000>; 414 }; 415 416 kryocc: clock-controller@6400000 { 417 compatible = "qcom,apcc-msm8996"; 418 reg = <0x6400000 0x90000>; 419 #clock-cells = <1>; 420 }; 421 422 blsp1_uart1: serial@7570000 { 423 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 424 reg = <0x07570000 0x1000>; 425 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 427 <&gcc GCC_BLSP1_AHB_CLK>; 428 clock-names = "core", "iface"; 429 status = "disabled"; 430 }; 431 432 blsp1_spi0: spi@7575000 { 433 compatible = "qcom,spi-qup-v2.2.1"; 434 reg = <0x07575000 0x600>; 435 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 437 <&gcc GCC_BLSP1_AHB_CLK>; 438 clock-names = "core", "iface"; 439 pinctrl-names = "default", "sleep"; 440 pinctrl-0 = <&blsp1_spi0_default>; 441 pinctrl-1 = <&blsp1_spi0_sleep>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 blsp2_i2c0: i2c@75b5000 { 448 compatible = "qcom,i2c-qup-v2.2.1"; 449 reg = <0x075b5000 0x1000>; 450 interrupts = <GIC_SPI 101 0>; 451 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 452 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 453 clock-names = "iface", "core"; 454 pinctrl-names = "default", "sleep"; 455 pinctrl-0 = <&blsp2_i2c0_default>; 456 pinctrl-1 = <&blsp2_i2c0_sleep>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 tsens0: thermal-sensor@4a8000 { 463 compatible = "qcom,msm8996-tsens"; 464 reg = <0x4a8000 0x2000>; 465 #thermal-sensor-cells = <1>; 466 }; 467 468 blsp2_uart1: serial@75b0000 { 469 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 470 reg = <0x75b0000 0x1000>; 471 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 473 <&gcc GCC_BLSP2_AHB_CLK>; 474 clock-names = "core", "iface"; 475 status = "disabled"; 476 }; 477 478 blsp2_i2c1: i2c@75b6000 { 479 compatible = "qcom,i2c-qup-v2.2.1"; 480 reg = <0x075b6000 0x1000>; 481 interrupts = <GIC_SPI 102 0>; 482 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 483 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 484 clock-names = "iface", "core"; 485 pinctrl-names = "default", "sleep"; 486 pinctrl-0 = <&blsp2_i2c1_default>; 487 pinctrl-1 = <&blsp2_i2c1_sleep>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 blsp2_uart2: serial@75b1000 { 494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 495 reg = <0x075b1000 0x1000>; 496 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 498 <&gcc GCC_BLSP2_AHB_CLK>; 499 clock-names = "core", "iface"; 500 status = "disabled"; 501 }; 502 503 blsp1_i2c2: i2c@7577000 { 504 compatible = "qcom,i2c-qup-v2.2.1"; 505 reg = <0x07577000 0x1000>; 506 interrupts = <GIC_SPI 97 0>; 507 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 508 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 509 clock-names = "iface", "core"; 510 pinctrl-names = "default", "sleep"; 511 pinctrl-0 = <&blsp1_i2c2_default>; 512 pinctrl-1 = <&blsp1_i2c2_sleep>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 status = "disabled"; 516 }; 517 518 blsp2_spi5: spi@75ba000{ 519 compatible = "qcom,spi-qup-v2.2.1"; 520 reg = <0x075ba000 0x600>; 521 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 523 <&gcc GCC_BLSP2_AHB_CLK>; 524 clock-names = "core", "iface"; 525 pinctrl-names = "default", "sleep"; 526 pinctrl-0 = <&blsp2_spi5_default>; 527 pinctrl-1 = <&blsp2_spi5_sleep>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 sdhc2: sdhci@74a4900 { 534 status = "disabled"; 535 compatible = "qcom,sdhci-msm-v4"; 536 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 537 reg-names = "hc_mem", "core_mem"; 538 539 interrupts = <0 125 0>, <0 221 0>; 540 interrupt-names = "hc_irq", "pwr_irq"; 541 542 clock-names = "iface", "core", "xo"; 543 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 544 <&gcc GCC_SDCC2_APPS_CLK>, 545 <&xo_board>; 546 bus-width = <4>; 547 }; 548 549 msmgpio: pinctrl@1010000 { 550 compatible = "qcom,msm8996-pinctrl"; 551 reg = <0x01010000 0x300000>; 552 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 }; 558 559 timer@9840000 { 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges; 563 compatible = "arm,armv7-timer-mem"; 564 reg = <0x09840000 0x1000>; 565 clock-frequency = <19200000>; 566 567 frame@9850000 { 568 frame-number = <0>; 569 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 571 reg = <0x09850000 0x1000>, 572 <0x09860000 0x1000>; 573 }; 574 575 frame@9870000 { 576 frame-number = <1>; 577 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 578 reg = <0x09870000 0x1000>; 579 status = "disabled"; 580 }; 581 582 frame@9880000 { 583 frame-number = <2>; 584 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 585 reg = <0x09880000 0x1000>; 586 status = "disabled"; 587 }; 588 589 frame@9890000 { 590 frame-number = <3>; 591 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 592 reg = <0x09890000 0x1000>; 593 status = "disabled"; 594 }; 595 596 frame@98a0000 { 597 frame-number = <4>; 598 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 599 reg = <0x098a0000 0x1000>; 600 status = "disabled"; 601 }; 602 603 frame@98b0000 { 604 frame-number = <5>; 605 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 606 reg = <0x098b0000 0x1000>; 607 status = "disabled"; 608 }; 609 610 frame@98c0000 { 611 frame-number = <6>; 612 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 613 reg = <0x098c0000 0x1000>; 614 status = "disabled"; 615 }; 616 }; 617 618 spmi_bus: qcom,spmi@400f000 { 619 compatible = "qcom,spmi-pmic-arb"; 620 reg = <0x400f000 0x1000>, 621 <0x4400000 0x800000>, 622 <0x4c00000 0x800000>, 623 <0x5800000 0x200000>, 624 <0x400a000 0x002100>; 625 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 626 interrupt-names = "periph_irq"; 627 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 628 qcom,ee = <0>; 629 qcom,channel = <0>; 630 #address-cells = <2>; 631 #size-cells = <0>; 632 interrupt-controller; 633 #interrupt-cells = <4>; 634 }; 635 636 mmcc: clock-controller@8c0000 { 637 compatible = "qcom,mmcc-msm8996"; 638 #clock-cells = <1>; 639 #reset-cells = <1>; 640 #power-domain-cells = <1>; 641 reg = <0x8c0000 0x40000>; 642 assigned-clocks = <&mmcc MMPLL9_PLL>, 643 <&mmcc MMPLL1_PLL>, 644 <&mmcc MMPLL3_PLL>, 645 <&mmcc MMPLL4_PLL>, 646 <&mmcc MMPLL5_PLL>; 647 assigned-clock-rates = <624000000>, 648 <810000000>, 649 <980000000>, 650 <960000000>, 651 <825000000>; 652 }; 653 654 qfprom@74000 { 655 compatible = "qcom,qfprom"; 656 reg = <0x74000 0x8ff>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 660 qusb2p_hstx_trim: hstx_trim@24e { 661 reg = <0x24e 0x2>; 662 bits = <5 4>; 663 }; 664 665 qusb2s_hstx_trim: hstx_trim@24f { 666 reg = <0x24f 0x1>; 667 bits = <1 4>; 668 }; 669 }; 670 671 phy@34000 { 672 compatible = "qcom,msm8996-qmp-pcie-phy"; 673 reg = <0x34000 0x488>; 674 #clock-cells = <1>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges; 678 679 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 680 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 681 <&gcc GCC_PCIE_CLKREF_CLK>; 682 clock-names = "aux", "cfg_ahb", "ref"; 683 684 vdda-phy-supply = <&pm8994_l28>; 685 vdda-pll-supply = <&pm8994_l12>; 686 687 resets = <&gcc GCC_PCIE_PHY_BCR>, 688 <&gcc GCC_PCIE_PHY_COM_BCR>, 689 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 690 reset-names = "phy", "common", "cfg"; 691 status = "disabled"; 692 693 pciephy_0: lane@35000 { 694 reg = <0x035000 0x130>, 695 <0x035200 0x200>, 696 <0x035400 0x1dc>; 697 #phy-cells = <0>; 698 699 clock-output-names = "pcie_0_pipe_clk_src"; 700 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 701 clock-names = "pipe0"; 702 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 703 reset-names = "lane0"; 704 }; 705 706 pciephy_1: lane@36000 { 707 reg = <0x036000 0x130>, 708 <0x036200 0x200>, 709 <0x036400 0x1dc>; 710 #phy-cells = <0>; 711 712 clock-output-names = "pcie_1_pipe_clk_src"; 713 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 714 clock-names = "pipe1"; 715 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 716 reset-names = "lane1"; 717 }; 718 719 pciephy_2: lane@37000 { 720 reg = <0x037000 0x130>, 721 <0x037200 0x200>, 722 <0x037400 0x1dc>; 723 #phy-cells = <0>; 724 725 clock-output-names = "pcie_2_pipe_clk_src"; 726 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 727 clock-names = "pipe2"; 728 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 729 reset-names = "lane2"; 730 }; 731 }; 732 733 phy@7410000 { 734 compatible = "qcom,msm8996-qmp-usb3-phy"; 735 reg = <0x7410000 0x1c4>; 736 #clock-cells = <1>; 737 #address-cells = <1>; 738 #size-cells = <1>; 739 ranges; 740 741 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 742 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 743 <&gcc GCC_USB3_CLKREF_CLK>; 744 clock-names = "aux", "cfg_ahb", "ref"; 745 746 vdda-phy-supply = <&pm8994_l28>; 747 vdda-pll-supply = <&pm8994_l12>; 748 749 resets = <&gcc GCC_USB3_PHY_BCR>, 750 <&gcc GCC_USB3PHY_PHY_BCR>; 751 reset-names = "phy", "common"; 752 status = "disabled"; 753 754 ssusb_phy_0: lane@7410200 { 755 reg = <0x7410200 0x200>, 756 <0x7410400 0x130>, 757 <0x7410600 0x1a8>; 758 #phy-cells = <0>; 759 760 clock-output-names = "usb3_phy_pipe_clk_src"; 761 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 762 clock-names = "pipe0"; 763 }; 764 }; 765 766 hsusb_phy1: phy@7411000 { 767 compatible = "qcom,msm8996-qusb2-phy"; 768 reg = <0x7411000 0x180>; 769 #phy-cells = <0>; 770 771 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 772 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 773 clock-names = "cfg_ahb", "ref"; 774 775 vdda-pll-supply = <&pm8994_l12>; 776 vdda-phy-dpdm-supply = <&pm8994_l24>; 777 778 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 779 nvmem-cells = <&qusb2p_hstx_trim>; 780 status = "disabled"; 781 }; 782 783 hsusb_phy2: phy@7412000 { 784 compatible = "qcom,msm8996-qusb2-phy"; 785 reg = <0x7412000 0x180>; 786 #phy-cells = <0>; 787 788 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 789 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 790 clock-names = "cfg_ahb", "ref"; 791 792 vdda-pll-supply = <&pm8994_l12>; 793 vdda-phy-dpdm-supply = <&pm8994_l24>; 794 795 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 796 nvmem-cells = <&qusb2s_hstx_trim>; 797 status = "disabled"; 798 }; 799 800 usb2: usb@7600000 { 801 compatible = "qcom,dwc3"; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 ranges; 805 806 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 807 <&gcc GCC_USB20_MASTER_CLK>, 808 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 809 <&gcc GCC_USB20_SLEEP_CLK>, 810 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 811 812 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 813 <&gcc GCC_USB20_MASTER_CLK>; 814 assigned-clock-rates = <19200000>, <60000000>; 815 816 power-domains = <&gcc USB30_GDSC>; 817 status = "disabled"; 818 819 dwc3@7600000 { 820 compatible = "snps,dwc3"; 821 reg = <0x7600000 0xcc00>; 822 interrupts = <0 138 0>; 823 phys = <&hsusb_phy2>; 824 phy-names = "usb2-phy"; 825 }; 826 }; 827 828 usb3: usb@6a00000 { 829 compatible = "qcom,dwc3"; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 ranges; 833 834 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 835 <&gcc GCC_USB30_MASTER_CLK>, 836 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 837 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 838 <&gcc GCC_USB30_SLEEP_CLK>, 839 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 840 841 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 842 <&gcc GCC_USB30_MASTER_CLK>; 843 assigned-clock-rates = <19200000>, <120000000>; 844 845 power-domains = <&gcc USB30_GDSC>; 846 status = "disabled"; 847 848 dwc3@6a00000 { 849 compatible = "snps,dwc3"; 850 reg = <0x6a00000 0xcc00>; 851 interrupts = <0 131 0>; 852 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 853 phy-names = "usb2-phy", "usb3-phy"; 854 }; 855 }; 856 857 agnoc@0 { 858 power-domains = <&gcc AGGRE0_NOC_GDSC>; 859 compatible = "simple-pm-bus"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 ranges; 863 864 pcie0: qcom,pcie@600000 { 865 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 866 status = "disabled"; 867 power-domains = <&gcc PCIE0_GDSC>; 868 bus-range = <0x00 0xff>; 869 num-lanes = <1>; 870 871 reg = <0x00600000 0x2000>, 872 <0x0c000000 0xf1d>, 873 <0x0c000f20 0xa8>, 874 <0x0c100000 0x100000>; 875 reg-names = "parf", "dbi", "elbi","config"; 876 877 phys = <&pciephy_0>; 878 phy-names = "pciephy"; 879 880 #address-cells = <3>; 881 #size-cells = <2>; 882 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 883 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 884 885 interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>; 886 interrupt-names = "msi"; 887 #interrupt-cells = <1>; 888 interrupt-map-mask = <0 0 0 0x7>; 889 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 890 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 891 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 892 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 893 894 pinctrl-names = "default", "sleep"; 895 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 896 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 897 898 899 vdda-supply = <&pm8994_l28>; 900 901 linux,pci-domain = <0>; 902 903 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 904 <&gcc GCC_PCIE_0_AUX_CLK>, 905 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 906 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 907 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 908 909 clock-names = "pipe", 910 "aux", 911 "cfg", 912 "bus_master", 913 "bus_slave"; 914 915 }; 916 917 pcie1: qcom,pcie@608000 { 918 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 919 power-domains = <&gcc PCIE1_GDSC>; 920 bus-range = <0x00 0xff>; 921 num-lanes = <1>; 922 923 status = "disabled"; 924 925 reg = <0x00608000 0x2000>, 926 <0x0d000000 0xf1d>, 927 <0x0d000f20 0xa8>, 928 <0x0d100000 0x100000>; 929 930 reg-names = "parf", "dbi", "elbi","config"; 931 932 phys = <&pciephy_1>; 933 phy-names = "pciephy"; 934 935 #address-cells = <3>; 936 #size-cells = <2>; 937 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 938 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 939 940 interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>; 941 interrupt-names = "msi"; 942 #interrupt-cells = <1>; 943 interrupt-map-mask = <0 0 0 0x7>; 944 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 945 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 946 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 947 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 948 949 pinctrl-names = "default", "sleep"; 950 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 951 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 952 953 954 vdda-supply = <&pm8994_l28>; 955 linux,pci-domain = <1>; 956 957 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 958 <&gcc GCC_PCIE_1_AUX_CLK>, 959 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 960 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 961 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 962 963 clock-names = "pipe", 964 "aux", 965 "cfg", 966 "bus_master", 967 "bus_slave"; 968 }; 969 970 pcie2: qcom,pcie@610000 { 971 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 972 power-domains = <&gcc PCIE2_GDSC>; 973 bus-range = <0x00 0xff>; 974 num-lanes = <1>; 975 status = "disabled"; 976 reg = <0x00610000 0x2000>, 977 <0x0e000000 0xf1d>, 978 <0x0e000f20 0xa8>, 979 <0x0e100000 0x100000>; 980 981 reg-names = "parf", "dbi", "elbi","config"; 982 983 phys = <&pciephy_2>; 984 phy-names = "pciephy"; 985 986 #address-cells = <3>; 987 #size-cells = <2>; 988 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 989 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 990 991 device_type = "pci"; 992 993 interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>; 994 interrupt-names = "msi"; 995 #interrupt-cells = <1>; 996 interrupt-map-mask = <0 0 0 0x7>; 997 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 998 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 999 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1000 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1001 1002 pinctrl-names = "default", "sleep"; 1003 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 1004 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 1005 1006 vdda-supply = <&pm8994_l28>; 1007 1008 linux,pci-domain = <2>; 1009 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1010 <&gcc GCC_PCIE_2_AUX_CLK>, 1011 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1012 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1013 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1014 1015 clock-names = "pipe", 1016 "aux", 1017 "cfg", 1018 "bus_master", 1019 "bus_slave"; 1020 }; 1021 }; 1022 }; 1023 1024 adsp-pil { 1025 compatible = "qcom,msm8996-adsp-pil"; 1026 1027 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 1028 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1029 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1030 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1031 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1032 interrupt-names = "wdog", "fatal", "ready", 1033 "handover", "stop-ack"; 1034 1035 clocks = <&xo_board>; 1036 clock-names = "xo"; 1037 1038 memory-region = <&adsp_region>; 1039 1040 qcom,smem-states = <&adsp_smp2p_out 0>; 1041 qcom,smem-state-names = "stop"; 1042 1043 smd-edge { 1044 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1045 1046 label = "lpass"; 1047 qcom,ipc = <&apcs 16 8>; 1048 qcom,smd-edge = <1>; 1049 qcom,remote-pid = <2>; 1050 }; 1051 }; 1052 1053 adsp-smp2p { 1054 compatible = "qcom,smp2p"; 1055 qcom,smem = <443>, <429>; 1056 1057 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 1058 1059 qcom,ipc = <&apcs 16 10>; 1060 1061 qcom,local-pid = <0>; 1062 qcom,remote-pid = <2>; 1063 1064 adsp_smp2p_out: master-kernel { 1065 qcom,entry-name = "master-kernel"; 1066 #qcom,smem-state-cells = <1>; 1067 }; 1068 1069 adsp_smp2p_in: slave-kernel { 1070 qcom,entry-name = "slave-kernel"; 1071 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 }; 1075 }; 1076 1077 modem-smp2p { 1078 compatible = "qcom,smp2p"; 1079 qcom,smem = <435>, <428>; 1080 1081 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1082 1083 qcom,ipc = <&apcs 16 14>; 1084 1085 qcom,local-pid = <0>; 1086 qcom,remote-pid = <1>; 1087 1088 modem_smp2p_out: master-kernel { 1089 qcom,entry-name = "master-kernel"; 1090 #qcom,smem-state-cells = <1>; 1091 }; 1092 1093 modem_smp2p_in: slave-kernel { 1094 qcom,entry-name = "slave-kernel"; 1095 1096 interrupt-controller; 1097 #interrupt-cells = <2>; 1098 }; 1099 }; 1100 1101 smp2p-slpi { 1102 compatible = "qcom,smp2p"; 1103 qcom,smem = <481>, <430>; 1104 1105 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 1106 1107 qcom,ipc = <&apcs 16 26>; 1108 1109 qcom,local-pid = <0>; 1110 qcom,remote-pid = <3>; 1111 1112 slpi_smp2p_in: slave-kernel { 1113 qcom,entry-name = "slave-kernel"; 1114 interrupt-controller; 1115 #interrupt-cells = <2>; 1116 }; 1117 1118 slpi_smp2p_out: master-kernel { 1119 qcom,entry-name = "master-kernel"; 1120 #qcom,smem-state-cells = <1>; 1121 }; 1122 }; 1123 1124}; 1125#include "msm8996-pins.dtsi" 1126