1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 capacity-dmips-mhz = <1024>; 51 clocks = <&kryocc 0>; 52 operating-points-v2 = <&cluster0_opp>; 53 #cooling-cells = <2>; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 }; 59 }; 60 61 CPU1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo"; 64 reg = <0x0 0x1>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 capacity-dmips-mhz = <1024>; 68 clocks = <&kryocc 0>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU2: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 capacity-dmips-mhz = <1024>; 81 clocks = <&kryocc 1>; 82 operating-points-v2 = <&cluster1_opp>; 83 #cooling-cells = <2>; 84 next-level-cache = <&L2_1>; 85 L2_1: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 }; 89 }; 90 91 CPU3: cpu@101 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CPU_SLEEP_0>; 97 capacity-dmips-mhz = <1024>; 98 clocks = <&kryocc 1>; 99 operating-points-v2 = <&cluster1_opp>; 100 #cooling-cells = <2>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 cpu-map { 105 cluster0 { 106 core0 { 107 cpu = <&CPU0>; 108 }; 109 110 core1 { 111 cpu = <&CPU1>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&CPU2>; 118 }; 119 120 core1 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 }; 125 126 idle-states { 127 entry-method = "psci"; 128 129 CPU_SLEEP_0: cpu-sleep-0 { 130 compatible = "arm,idle-state"; 131 idle-state-name = "standalone-power-collapse"; 132 arm,psci-suspend-param = <0x00000004>; 133 entry-latency-us = <130>; 134 exit-latency-us = <80>; 135 min-residency-us = <300>; 136 }; 137 }; 138 }; 139 140 cluster0_opp: opp-table-cluster0 { 141 compatible = "operating-points-v2-kryo-cpu"; 142 nvmem-cells = <&speedbin_efuse>; 143 opp-shared; 144 145 /* Nominal fmax for now */ 146 opp-307200000 { 147 opp-hz = /bits/ 64 <307200000>; 148 opp-supported-hw = <0xf>; 149 clock-latency-ns = <200000>; 150 }; 151 opp-422400000 { 152 opp-hz = /bits/ 64 <422400000>; 153 opp-supported-hw = <0xf>; 154 clock-latency-ns = <200000>; 155 }; 156 opp-480000000 { 157 opp-hz = /bits/ 64 <480000000>; 158 opp-supported-hw = <0xf>; 159 clock-latency-ns = <200000>; 160 }; 161 opp-556800000 { 162 opp-hz = /bits/ 64 <556800000>; 163 opp-supported-hw = <0xf>; 164 clock-latency-ns = <200000>; 165 }; 166 opp-652800000 { 167 opp-hz = /bits/ 64 <652800000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 }; 171 opp-729600000 { 172 opp-hz = /bits/ 64 <729600000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 }; 176 opp-844800000 { 177 opp-hz = /bits/ 64 <844800000>; 178 opp-supported-hw = <0xf>; 179 clock-latency-ns = <200000>; 180 }; 181 opp-960000000 { 182 opp-hz = /bits/ 64 <960000000>; 183 opp-supported-hw = <0xf>; 184 clock-latency-ns = <200000>; 185 }; 186 opp-1036800000 { 187 opp-hz = /bits/ 64 <1036800000>; 188 opp-supported-hw = <0xf>; 189 clock-latency-ns = <200000>; 190 }; 191 opp-1113600000 { 192 opp-hz = /bits/ 64 <1113600000>; 193 opp-supported-hw = <0xf>; 194 clock-latency-ns = <200000>; 195 }; 196 opp-1190400000 { 197 opp-hz = /bits/ 64 <1190400000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 }; 201 opp-1228800000 { 202 opp-hz = /bits/ 64 <1228800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 }; 206 opp-1324800000 { 207 opp-hz = /bits/ 64 <1324800000>; 208 opp-supported-hw = <0xd>; 209 clock-latency-ns = <200000>; 210 }; 211 opp-1363200000 { 212 opp-hz = /bits/ 64 <1363200000>; 213 opp-supported-hw = <0x2>; 214 clock-latency-ns = <200000>; 215 }; 216 opp-1401600000 { 217 opp-hz = /bits/ 64 <1401600000>; 218 opp-supported-hw = <0xd>; 219 clock-latency-ns = <200000>; 220 }; 221 opp-1478400000 { 222 opp-hz = /bits/ 64 <1478400000>; 223 opp-supported-hw = <0x9>; 224 clock-latency-ns = <200000>; 225 }; 226 opp-1497600000 { 227 opp-hz = /bits/ 64 <1497600000>; 228 opp-supported-hw = <0x04>; 229 clock-latency-ns = <200000>; 230 }; 231 opp-1593600000 { 232 opp-hz = /bits/ 64 <1593600000>; 233 opp-supported-hw = <0x9>; 234 clock-latency-ns = <200000>; 235 }; 236 }; 237 238 cluster1_opp: opp-table-cluster1 { 239 compatible = "operating-points-v2-kryo-cpu"; 240 nvmem-cells = <&speedbin_efuse>; 241 opp-shared; 242 243 /* Nominal fmax for now */ 244 opp-307200000 { 245 opp-hz = /bits/ 64 <307200000>; 246 opp-supported-hw = <0xf>; 247 clock-latency-ns = <200000>; 248 }; 249 opp-403200000 { 250 opp-hz = /bits/ 64 <403200000>; 251 opp-supported-hw = <0xf>; 252 clock-latency-ns = <200000>; 253 }; 254 opp-480000000 { 255 opp-hz = /bits/ 64 <480000000>; 256 opp-supported-hw = <0xf>; 257 clock-latency-ns = <200000>; 258 }; 259 opp-556800000 { 260 opp-hz = /bits/ 64 <556800000>; 261 opp-supported-hw = <0xf>; 262 clock-latency-ns = <200000>; 263 }; 264 opp-652800000 { 265 opp-hz = /bits/ 64 <652800000>; 266 opp-supported-hw = <0xf>; 267 clock-latency-ns = <200000>; 268 }; 269 opp-729600000 { 270 opp-hz = /bits/ 64 <729600000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 }; 274 opp-806400000 { 275 opp-hz = /bits/ 64 <806400000>; 276 opp-supported-hw = <0xf>; 277 clock-latency-ns = <200000>; 278 }; 279 opp-883200000 { 280 opp-hz = /bits/ 64 <883200000>; 281 opp-supported-hw = <0xf>; 282 clock-latency-ns = <200000>; 283 }; 284 opp-940800000 { 285 opp-hz = /bits/ 64 <940800000>; 286 opp-supported-hw = <0xf>; 287 clock-latency-ns = <200000>; 288 }; 289 opp-1036800000 { 290 opp-hz = /bits/ 64 <1036800000>; 291 opp-supported-hw = <0xf>; 292 clock-latency-ns = <200000>; 293 }; 294 opp-1113600000 { 295 opp-hz = /bits/ 64 <1113600000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 }; 299 opp-1190400000 { 300 opp-hz = /bits/ 64 <1190400000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 }; 304 opp-1248000000 { 305 opp-hz = /bits/ 64 <1248000000>; 306 opp-supported-hw = <0xf>; 307 clock-latency-ns = <200000>; 308 }; 309 opp-1324800000 { 310 opp-hz = /bits/ 64 <1324800000>; 311 opp-supported-hw = <0xf>; 312 clock-latency-ns = <200000>; 313 }; 314 opp-1401600000 { 315 opp-hz = /bits/ 64 <1401600000>; 316 opp-supported-hw = <0xf>; 317 clock-latency-ns = <200000>; 318 }; 319 opp-1478400000 { 320 opp-hz = /bits/ 64 <1478400000>; 321 opp-supported-hw = <0xf>; 322 clock-latency-ns = <200000>; 323 }; 324 opp-1555200000 { 325 opp-hz = /bits/ 64 <1555200000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 }; 329 opp-1632000000 { 330 opp-hz = /bits/ 64 <1632000000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 }; 334 opp-1708800000 { 335 opp-hz = /bits/ 64 <1708800000>; 336 opp-supported-hw = <0xf>; 337 clock-latency-ns = <200000>; 338 }; 339 opp-1785600000 { 340 opp-hz = /bits/ 64 <1785600000>; 341 opp-supported-hw = <0xf>; 342 clock-latency-ns = <200000>; 343 }; 344 opp-1804800000 { 345 opp-hz = /bits/ 64 <1804800000>; 346 opp-supported-hw = <0xe>; 347 clock-latency-ns = <200000>; 348 }; 349 opp-1824000000 { 350 opp-hz = /bits/ 64 <1824000000>; 351 opp-supported-hw = <0x1>; 352 clock-latency-ns = <200000>; 353 }; 354 opp-1900800000 { 355 opp-hz = /bits/ 64 <1900800000>; 356 opp-supported-hw = <0x4>; 357 clock-latency-ns = <200000>; 358 }; 359 opp-1920000000 { 360 opp-hz = /bits/ 64 <1920000000>; 361 opp-supported-hw = <0x1>; 362 clock-latency-ns = <200000>; 363 }; 364 opp-1996800000 { 365 opp-hz = /bits/ 64 <1996800000>; 366 opp-supported-hw = <0x1>; 367 clock-latency-ns = <200000>; 368 }; 369 opp-2073600000 { 370 opp-hz = /bits/ 64 <2073600000>; 371 opp-supported-hw = <0x1>; 372 clock-latency-ns = <200000>; 373 }; 374 opp-2150400000 { 375 opp-hz = /bits/ 64 <2150400000>; 376 opp-supported-hw = <0x1>; 377 clock-latency-ns = <200000>; 378 }; 379 }; 380 381 firmware { 382 scm { 383 compatible = "qcom,scm-msm8996", "qcom,scm"; 384 qcom,dload-mode = <&tcsr_2 0x13000>; 385 }; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the reg */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 psci { 395 compatible = "arm,psci-1.0"; 396 method = "smc"; 397 }; 398 399 reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@85800000 { 405 reg = <0x0 0x85800000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_mem: memory@85e00000 { 410 reg = <0x0 0x85e00000 0x0 0x200000>; 411 no-map; 412 }; 413 414 smem_mem: smem-mem@86000000 { 415 reg = <0x0 0x86000000 0x0 0x200000>; 416 no-map; 417 }; 418 419 tz_mem: memory@86200000 { 420 reg = <0x0 0x86200000 0x0 0x2600000>; 421 no-map; 422 }; 423 424 rmtfs_mem: rmtfs { 425 compatible = "qcom,rmtfs-mem"; 426 427 size = <0x0 0x200000>; 428 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 429 no-map; 430 431 qcom,client-id = <1>; 432 qcom,vmid = <15>; 433 }; 434 435 mpss_mem: mpss@88800000 { 436 reg = <0x0 0x88800000 0x0 0x6200000>; 437 no-map; 438 }; 439 440 adsp_mem: adsp@8ea00000 { 441 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 442 no-map; 443 }; 444 445 slpi_mem: slpi@90500000 { 446 reg = <0x0 0x90500000 0x0 0xa00000>; 447 no-map; 448 }; 449 450 gpu_mem: gpu@90f00000 { 451 compatible = "shared-dma-pool"; 452 reg = <0x0 0x90f00000 0x0 0x100000>; 453 no-map; 454 }; 455 456 venus_mem: venus@91000000 { 457 reg = <0x0 0x91000000 0x0 0x500000>; 458 no-map; 459 }; 460 461 mba_mem: mba@91500000 { 462 reg = <0x0 0x91500000 0x0 0x200000>; 463 no-map; 464 }; 465 466 mdata_mem: mpss-metadata { 467 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 468 size = <0x0 0x4000>; 469 no-map; 470 }; 471 }; 472 473 rpm-glink { 474 compatible = "qcom,glink-rpm"; 475 476 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 477 478 qcom,rpm-msg-ram = <&rpm_msg_ram>; 479 480 mboxes = <&apcs_glb 0>; 481 482 rpm_requests: rpm-requests { 483 compatible = "qcom,rpm-msm8996"; 484 qcom,glink-channels = "rpm_requests"; 485 486 rpmcc: qcom,rpmcc { 487 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 488 #clock-cells = <1>; 489 clocks = <&xo_board>; 490 clock-names = "xo"; 491 }; 492 493 rpmpd: power-controller { 494 compatible = "qcom,msm8996-rpmpd"; 495 #power-domain-cells = <1>; 496 operating-points-v2 = <&rpmpd_opp_table>; 497 498 rpmpd_opp_table: opp-table { 499 compatible = "operating-points-v2"; 500 501 rpmpd_opp1: opp1 { 502 opp-level = <1>; 503 }; 504 505 rpmpd_opp2: opp2 { 506 opp-level = <2>; 507 }; 508 509 rpmpd_opp3: opp3 { 510 opp-level = <3>; 511 }; 512 513 rpmpd_opp4: opp4 { 514 opp-level = <4>; 515 }; 516 517 rpmpd_opp5: opp5 { 518 opp-level = <5>; 519 }; 520 521 rpmpd_opp6: opp6 { 522 opp-level = <6>; 523 }; 524 }; 525 }; 526 }; 527 }; 528 529 smem { 530 compatible = "qcom,smem"; 531 memory-region = <&smem_mem>; 532 hwlocks = <&tcsr_mutex 3>; 533 }; 534 535 smp2p-adsp { 536 compatible = "qcom,smp2p"; 537 qcom,smem = <443>, <429>; 538 539 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 540 541 mboxes = <&apcs_glb 10>; 542 543 qcom,local-pid = <0>; 544 qcom,remote-pid = <2>; 545 546 adsp_smp2p_out: master-kernel { 547 qcom,entry-name = "master-kernel"; 548 #qcom,smem-state-cells = <1>; 549 }; 550 551 adsp_smp2p_in: slave-kernel { 552 qcom,entry-name = "slave-kernel"; 553 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 }; 558 559 smp2p-mpss { 560 compatible = "qcom,smp2p"; 561 qcom,smem = <435>, <428>; 562 563 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 564 565 mboxes = <&apcs_glb 14>; 566 567 qcom,local-pid = <0>; 568 qcom,remote-pid = <1>; 569 570 mpss_smp2p_out: master-kernel { 571 qcom,entry-name = "master-kernel"; 572 #qcom,smem-state-cells = <1>; 573 }; 574 575 mpss_smp2p_in: slave-kernel { 576 qcom,entry-name = "slave-kernel"; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-slpi { 584 compatible = "qcom,smp2p"; 585 qcom,smem = <481>, <430>; 586 587 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 588 589 mboxes = <&apcs_glb 26>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <3>; 593 594 slpi_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 slpi_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606 607 soc: soc { 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 0 0 0xffffffff>; 611 compatible = "simple-bus"; 612 613 pcie_phy: phy-wrapper@34000 { 614 compatible = "qcom,msm8996-qmp-pcie-phy"; 615 reg = <0x00034000 0x488>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0x00034000 0x4000>; 619 620 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 621 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 622 <&gcc GCC_PCIE_CLKREF_CLK>; 623 clock-names = "aux", "cfg_ahb", "ref"; 624 625 resets = <&gcc GCC_PCIE_PHY_BCR>, 626 <&gcc GCC_PCIE_PHY_COM_BCR>, 627 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 628 reset-names = "phy", "common", "cfg"; 629 630 status = "disabled"; 631 632 pciephy_0: phy@1000 { 633 reg = <0x1000 0x130>, 634 <0x1200 0x200>, 635 <0x1400 0x1dc>; 636 637 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 638 clock-names = "pipe0"; 639 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 640 reset-names = "lane0"; 641 642 #clock-cells = <0>; 643 clock-output-names = "pcie_0_pipe_clk_src"; 644 645 #phy-cells = <0>; 646 }; 647 648 pciephy_1: phy@2000 { 649 reg = <0x2000 0x130>, 650 <0x2200 0x200>, 651 <0x2400 0x1dc>; 652 653 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 654 clock-names = "pipe1"; 655 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 656 reset-names = "lane1"; 657 658 #clock-cells = <0>; 659 clock-output-names = "pcie_1_pipe_clk_src"; 660 661 #phy-cells = <0>; 662 }; 663 664 pciephy_2: phy@3000 { 665 reg = <0x3000 0x130>, 666 <0x3200 0x200>, 667 <0x3400 0x1dc>; 668 669 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 670 clock-names = "pipe2"; 671 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 672 reset-names = "lane2"; 673 674 #clock-cells = <0>; 675 clock-output-names = "pcie_2_pipe_clk_src"; 676 677 #phy-cells = <0>; 678 }; 679 }; 680 681 rpm_msg_ram: sram@68000 { 682 compatible = "qcom,rpm-msg-ram"; 683 reg = <0x00068000 0x6000>; 684 }; 685 686 qfprom@74000 { 687 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 688 reg = <0x00074000 0x8ff>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 692 qusb2p_hstx_trim: hstx_trim@24e { 693 reg = <0x24e 0x2>; 694 bits = <5 4>; 695 }; 696 697 qusb2s_hstx_trim: hstx_trim@24f { 698 reg = <0x24f 0x1>; 699 bits = <1 4>; 700 }; 701 702 speedbin_efuse: speedbin@133 { 703 reg = <0x133 0x1>; 704 bits = <5 3>; 705 }; 706 }; 707 708 rng: rng@83000 { 709 compatible = "qcom,prng-ee"; 710 reg = <0x00083000 0x1000>; 711 clocks = <&gcc GCC_PRNG_AHB_CLK>; 712 clock-names = "core"; 713 }; 714 715 gcc: clock-controller@300000 { 716 compatible = "qcom,gcc-msm8996"; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 #power-domain-cells = <1>; 720 reg = <0x00300000 0x90000>; 721 722 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 723 <&rpmcc RPM_SMD_LN_BB_CLK>, 724 <&sleep_clk>, 725 <&pciephy_0>, 726 <&pciephy_1>, 727 <&pciephy_2>, 728 <&ssusb_phy_0>, 729 <&ufsphy_lane 0>, 730 <&ufsphy_lane 1>, 731 <&ufsphy_lane 2>; 732 clock-names = "cxo", 733 "cxo2", 734 "sleep_clk", 735 "pcie_0_pipe_clk_src", 736 "pcie_1_pipe_clk_src", 737 "pcie_2_pipe_clk_src", 738 "usb3_phy_pipe_clk_src", 739 "ufs_rx_symbol_0_clk_src", 740 "ufs_rx_symbol_1_clk_src", 741 "ufs_tx_symbol_0_clk_src"; 742 }; 743 744 bimc: interconnect@408000 { 745 compatible = "qcom,msm8996-bimc"; 746 reg = <0x00408000 0x5a000>; 747 #interconnect-cells = <1>; 748 clock-names = "bus", "bus_a"; 749 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 750 <&rpmcc RPM_SMD_BIMC_A_CLK>; 751 }; 752 753 tsens0: thermal-sensor@4a9000 { 754 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 755 reg = <0x004a9000 0x1000>, /* TM */ 756 <0x004a8000 0x1000>; /* SROT */ 757 #qcom,sensors = <13>; 758 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "uplow", "critical"; 761 #thermal-sensor-cells = <1>; 762 }; 763 764 tsens1: thermal-sensor@4ad000 { 765 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 766 reg = <0x004ad000 0x1000>, /* TM */ 767 <0x004ac000 0x1000>; /* SROT */ 768 #qcom,sensors = <8>; 769 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-names = "uplow", "critical"; 772 #thermal-sensor-cells = <1>; 773 }; 774 775 cryptobam: dma-controller@644000 { 776 compatible = "qcom,bam-v1.7.0"; 777 reg = <0x00644000 0x24000>; 778 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&gcc GCC_CE1_CLK>; 780 clock-names = "bam_clk"; 781 #dma-cells = <1>; 782 qcom,ee = <0>; 783 qcom,controlled-remotely; 784 }; 785 786 crypto: crypto@67a000 { 787 compatible = "qcom,crypto-v5.4"; 788 reg = <0x0067a000 0x6000>; 789 clocks = <&gcc GCC_CE1_AHB_CLK>, 790 <&gcc GCC_CE1_AXI_CLK>, 791 <&gcc GCC_CE1_CLK>; 792 clock-names = "iface", "bus", "core"; 793 dmas = <&cryptobam 6>, <&cryptobam 7>; 794 dma-names = "rx", "tx"; 795 }; 796 797 cnoc: interconnect@500000 { 798 compatible = "qcom,msm8996-cnoc"; 799 reg = <0x00500000 0x1000>; 800 #interconnect-cells = <1>; 801 clock-names = "bus", "bus_a"; 802 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 803 <&rpmcc RPM_SMD_CNOC_A_CLK>; 804 }; 805 806 snoc: interconnect@524000 { 807 compatible = "qcom,msm8996-snoc"; 808 reg = <0x00524000 0x1c000>; 809 #interconnect-cells = <1>; 810 clock-names = "bus", "bus_a"; 811 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 812 <&rpmcc RPM_SMD_SNOC_A_CLK>; 813 }; 814 815 a0noc: interconnect@543000 { 816 compatible = "qcom,msm8996-a0noc"; 817 reg = <0x00543000 0x6000>; 818 #interconnect-cells = <1>; 819 clock-names = "aggre0_snoc_axi", 820 "aggre0_cnoc_ahb", 821 "aggre0_noc_mpu_cfg"; 822 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 823 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 824 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 825 power-domains = <&gcc AGGRE0_NOC_GDSC>; 826 }; 827 828 a1noc: interconnect@562000 { 829 compatible = "qcom,msm8996-a1noc"; 830 reg = <0x00562000 0x5000>; 831 #interconnect-cells = <1>; 832 clock-names = "bus", "bus_a"; 833 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 834 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 835 }; 836 837 a2noc: interconnect@583000 { 838 compatible = "qcom,msm8996-a2noc"; 839 reg = <0x00583000 0x7000>; 840 #interconnect-cells = <1>; 841 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 842 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 843 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 844 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 845 <&gcc GCC_UFS_AXI_CLK>; 846 }; 847 848 mnoc: interconnect@5a4000 { 849 compatible = "qcom,msm8996-mnoc"; 850 reg = <0x005a4000 0x1c000>; 851 #interconnect-cells = <1>; 852 clock-names = "bus", "bus_a", "iface"; 853 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 854 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 855 <&mmcc AHB_CLK_SRC>; 856 }; 857 858 pnoc: interconnect@5c0000 { 859 compatible = "qcom,msm8996-pnoc"; 860 reg = <0x005c0000 0x3000>; 861 #interconnect-cells = <1>; 862 clock-names = "bus", "bus_a"; 863 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 864 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 865 }; 866 867 tcsr_mutex: hwlock@740000 { 868 compatible = "qcom,tcsr-mutex"; 869 reg = <0x00740000 0x20000>; 870 #hwlock-cells = <1>; 871 }; 872 873 tcsr_1: syscon@760000 { 874 compatible = "qcom,tcsr-msm8996", "syscon"; 875 reg = <0x00760000 0x20000>; 876 }; 877 878 tcsr_2: syscon@7a0000 { 879 compatible = "qcom,tcsr-msm8996", "syscon"; 880 reg = <0x007a0000 0x18000>; 881 }; 882 883 mmcc: clock-controller@8c0000 { 884 compatible = "qcom,mmcc-msm8996"; 885 #clock-cells = <1>; 886 #reset-cells = <1>; 887 #power-domain-cells = <1>; 888 reg = <0x008c0000 0x40000>; 889 clocks = <&xo_board>, 890 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 891 <&gcc GPLL0>, 892 <&dsi0_phy 1>, 893 <&dsi0_phy 0>, 894 <&dsi1_phy 1>, 895 <&dsi1_phy 0>, 896 <&hdmi_phy>; 897 clock-names = "xo", 898 "gcc_mmss_noc_cfg_ahb_clk", 899 "gpll0", 900 "dsi0pll", 901 "dsi0pllbyte", 902 "dsi1pll", 903 "dsi1pllbyte", 904 "hdmipll"; 905 assigned-clocks = <&mmcc MMPLL9_PLL>, 906 <&mmcc MMPLL1_PLL>, 907 <&mmcc MMPLL3_PLL>, 908 <&mmcc MMPLL4_PLL>, 909 <&mmcc MMPLL5_PLL>; 910 assigned-clock-rates = <624000000>, 911 <810000000>, 912 <980000000>, 913 <960000000>, 914 <825000000>; 915 }; 916 917 mdss: display-subsystem@900000 { 918 compatible = "qcom,mdss"; 919 920 reg = <0x00900000 0x1000>, 921 <0x009b0000 0x1040>, 922 <0x009b8000 0x1040>; 923 reg-names = "mdss_phys", 924 "vbif_phys", 925 "vbif_nrt_phys"; 926 927 power-domains = <&mmcc MDSS_GDSC>; 928 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 929 930 interrupt-controller; 931 #interrupt-cells = <1>; 932 933 clocks = <&mmcc MDSS_AHB_CLK>, 934 <&mmcc MDSS_MDP_CLK>; 935 clock-names = "iface", "core"; 936 937 #address-cells = <1>; 938 #size-cells = <1>; 939 ranges; 940 941 status = "disabled"; 942 943 mdp: display-controller@901000 { 944 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 945 reg = <0x00901000 0x90000>; 946 reg-names = "mdp_phys"; 947 948 interrupt-parent = <&mdss>; 949 interrupts = <0>; 950 951 clocks = <&mmcc MDSS_AHB_CLK>, 952 <&mmcc MDSS_AXI_CLK>, 953 <&mmcc MDSS_MDP_CLK>, 954 <&mmcc SMMU_MDP_AXI_CLK>, 955 <&mmcc MDSS_VSYNC_CLK>; 956 clock-names = "iface", 957 "bus", 958 "core", 959 "iommu", 960 "vsync"; 961 962 iommus = <&mdp_smmu 0>; 963 964 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 965 <&mmcc MDSS_VSYNC_CLK>; 966 assigned-clock-rates = <300000000>, 967 <19200000>; 968 969 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 970 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 971 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 972 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 973 974 ports { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 port@0 { 979 reg = <0>; 980 mdp5_intf3_out: endpoint { 981 remote-endpoint = <&hdmi_in>; 982 }; 983 }; 984 985 port@1 { 986 reg = <1>; 987 mdp5_intf1_out: endpoint { 988 remote-endpoint = <&dsi0_in>; 989 }; 990 }; 991 992 port@2 { 993 reg = <2>; 994 mdp5_intf2_out: endpoint { 995 remote-endpoint = <&dsi1_in>; 996 }; 997 }; 998 }; 999 }; 1000 1001 dsi0: dsi@994000 { 1002 compatible = "qcom,msm8996-dsi-ctrl", 1003 "qcom,mdss-dsi-ctrl"; 1004 reg = <0x00994000 0x400>; 1005 reg-names = "dsi_ctrl"; 1006 1007 interrupt-parent = <&mdss>; 1008 interrupts = <4>; 1009 1010 clocks = <&mmcc MDSS_MDP_CLK>, 1011 <&mmcc MDSS_BYTE0_CLK>, 1012 <&mmcc MDSS_AHB_CLK>, 1013 <&mmcc MDSS_AXI_CLK>, 1014 <&mmcc MMSS_MISC_AHB_CLK>, 1015 <&mmcc MDSS_PCLK0_CLK>, 1016 <&mmcc MDSS_ESC0_CLK>; 1017 clock-names = "mdp_core", 1018 "byte", 1019 "iface", 1020 "bus", 1021 "core_mmss", 1022 "pixel", 1023 "core"; 1024 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1025 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1026 1027 phys = <&dsi0_phy>; 1028 status = "disabled"; 1029 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 port@0 { 1038 reg = <0>; 1039 dsi0_in: endpoint { 1040 remote-endpoint = <&mdp5_intf1_out>; 1041 }; 1042 }; 1043 1044 port@1 { 1045 reg = <1>; 1046 dsi0_out: endpoint { 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 dsi0_phy: phy@994400 { 1053 compatible = "qcom,dsi-phy-14nm"; 1054 reg = <0x00994400 0x100>, 1055 <0x00994500 0x300>, 1056 <0x00994800 0x188>; 1057 reg-names = "dsi_phy", 1058 "dsi_phy_lane", 1059 "dsi_pll"; 1060 1061 #clock-cells = <1>; 1062 #phy-cells = <0>; 1063 1064 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1065 clock-names = "iface", "ref"; 1066 status = "disabled"; 1067 }; 1068 1069 dsi1: dsi@996000 { 1070 compatible = "qcom,msm8996-dsi-ctrl", 1071 "qcom,mdss-dsi-ctrl"; 1072 reg = <0x00996000 0x400>; 1073 reg-names = "dsi_ctrl"; 1074 1075 interrupt-parent = <&mdss>; 1076 interrupts = <4>; 1077 1078 clocks = <&mmcc MDSS_MDP_CLK>, 1079 <&mmcc MDSS_BYTE1_CLK>, 1080 <&mmcc MDSS_AHB_CLK>, 1081 <&mmcc MDSS_AXI_CLK>, 1082 <&mmcc MMSS_MISC_AHB_CLK>, 1083 <&mmcc MDSS_PCLK1_CLK>, 1084 <&mmcc MDSS_ESC1_CLK>; 1085 clock-names = "mdp_core", 1086 "byte", 1087 "iface", 1088 "bus", 1089 "core_mmss", 1090 "pixel", 1091 "core"; 1092 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1093 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1094 1095 phys = <&dsi1_phy>; 1096 status = "disabled"; 1097 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 1105 port@0 { 1106 reg = <0>; 1107 dsi1_in: endpoint { 1108 remote-endpoint = <&mdp5_intf2_out>; 1109 }; 1110 }; 1111 1112 port@1 { 1113 reg = <1>; 1114 dsi1_out: endpoint { 1115 }; 1116 }; 1117 }; 1118 }; 1119 1120 dsi1_phy: phy@996400 { 1121 compatible = "qcom,dsi-phy-14nm"; 1122 reg = <0x00996400 0x100>, 1123 <0x00996500 0x300>, 1124 <0x00996800 0x188>; 1125 reg-names = "dsi_phy", 1126 "dsi_phy_lane", 1127 "dsi_pll"; 1128 1129 #clock-cells = <1>; 1130 #phy-cells = <0>; 1131 1132 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1133 clock-names = "iface", "ref"; 1134 status = "disabled"; 1135 }; 1136 1137 hdmi: hdmi-tx@9a0000 { 1138 compatible = "qcom,hdmi-tx-8996"; 1139 reg = <0x009a0000 0x50c>, 1140 <0x00070000 0x6158>, 1141 <0x009e0000 0xfff>; 1142 reg-names = "core_physical", 1143 "qfprom_physical", 1144 "hdcp_physical"; 1145 1146 interrupt-parent = <&mdss>; 1147 interrupts = <8>; 1148 1149 clocks = <&mmcc MDSS_MDP_CLK>, 1150 <&mmcc MDSS_AHB_CLK>, 1151 <&mmcc MDSS_HDMI_CLK>, 1152 <&mmcc MDSS_HDMI_AHB_CLK>, 1153 <&mmcc MDSS_EXTPCLK_CLK>; 1154 clock-names = 1155 "mdp_core", 1156 "iface", 1157 "core", 1158 "alt_iface", 1159 "extp"; 1160 1161 phys = <&hdmi_phy>; 1162 #sound-dai-cells = <1>; 1163 1164 status = "disabled"; 1165 1166 ports { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 port@0 { 1171 reg = <0>; 1172 hdmi_in: endpoint { 1173 remote-endpoint = <&mdp5_intf3_out>; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 hdmi_phy: phy@9a0600 { 1180 #phy-cells = <0>; 1181 compatible = "qcom,hdmi-phy-8996"; 1182 reg = <0x009a0600 0x1c4>, 1183 <0x009a0a00 0x124>, 1184 <0x009a0c00 0x124>, 1185 <0x009a0e00 0x124>, 1186 <0x009a1000 0x124>, 1187 <0x009a1200 0x0c8>; 1188 reg-names = "hdmi_pll", 1189 "hdmi_tx_l0", 1190 "hdmi_tx_l1", 1191 "hdmi_tx_l2", 1192 "hdmi_tx_l3", 1193 "hdmi_phy"; 1194 1195 clocks = <&mmcc MDSS_AHB_CLK>, 1196 <&gcc GCC_HDMI_CLKREF_CLK>, 1197 <&xo_board>; 1198 clock-names = "iface", 1199 "ref", 1200 "xo"; 1201 1202 #clock-cells = <0>; 1203 1204 status = "disabled"; 1205 }; 1206 }; 1207 1208 gpu: gpu@b00000 { 1209 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1210 1211 reg = <0x00b00000 0x3f000>; 1212 reg-names = "kgsl_3d0_reg_memory"; 1213 1214 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1215 1216 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1217 <&mmcc GPU_AHB_CLK>, 1218 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1219 <&gcc GCC_BIMC_GFX_CLK>, 1220 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1221 1222 clock-names = "core", 1223 "iface", 1224 "rbbmtimer", 1225 "mem", 1226 "mem_iface"; 1227 1228 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1229 interconnect-names = "gfx-mem"; 1230 1231 power-domains = <&mmcc GPU_GX_GDSC>; 1232 iommus = <&adreno_smmu 0>; 1233 1234 nvmem-cells = <&speedbin_efuse>; 1235 nvmem-cell-names = "speed_bin"; 1236 1237 operating-points-v2 = <&gpu_opp_table>; 1238 1239 status = "disabled"; 1240 1241 #cooling-cells = <2>; 1242 1243 gpu_opp_table: opp-table { 1244 compatible = "operating-points-v2"; 1245 1246 /* 1247 * 624Mhz is only available on speed bins 0 and 3. 1248 * 560Mhz is only available on speed bins 0, 2 and 3. 1249 * All the rest are available on all bins of the hardware. 1250 */ 1251 opp-624000000 { 1252 opp-hz = /bits/ 64 <624000000>; 1253 opp-supported-hw = <0x09>; 1254 }; 1255 opp-560000000 { 1256 opp-hz = /bits/ 64 <560000000>; 1257 opp-supported-hw = <0x0d>; 1258 }; 1259 opp-510000000 { 1260 opp-hz = /bits/ 64 <510000000>; 1261 opp-supported-hw = <0xff>; 1262 }; 1263 opp-401800000 { 1264 opp-hz = /bits/ 64 <401800000>; 1265 opp-supported-hw = <0xff>; 1266 }; 1267 opp-315000000 { 1268 opp-hz = /bits/ 64 <315000000>; 1269 opp-supported-hw = <0xff>; 1270 }; 1271 opp-214000000 { 1272 opp-hz = /bits/ 64 <214000000>; 1273 opp-supported-hw = <0xff>; 1274 }; 1275 opp-133000000 { 1276 opp-hz = /bits/ 64 <133000000>; 1277 opp-supported-hw = <0xff>; 1278 }; 1279 }; 1280 1281 zap-shader { 1282 memory-region = <&gpu_mem>; 1283 }; 1284 }; 1285 1286 tlmm: pinctrl@1010000 { 1287 compatible = "qcom,msm8996-pinctrl"; 1288 reg = <0x01010000 0x300000>; 1289 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1290 gpio-controller; 1291 gpio-ranges = <&tlmm 0 0 150>; 1292 #gpio-cells = <2>; 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 1296 blsp1_spi1_default: blsp1-spi1-default-state { 1297 spi-pins { 1298 pins = "gpio0", "gpio1", "gpio3"; 1299 function = "blsp_spi1"; 1300 drive-strength = <12>; 1301 bias-disable; 1302 }; 1303 1304 cs-pins { 1305 pins = "gpio2"; 1306 function = "gpio"; 1307 drive-strength = <16>; 1308 bias-disable; 1309 output-high; 1310 }; 1311 }; 1312 1313 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1314 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1315 function = "gpio"; 1316 drive-strength = <2>; 1317 bias-pull-down; 1318 }; 1319 1320 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1321 pins = "gpio4", "gpio5"; 1322 function = "blsp_uart8"; 1323 drive-strength = <16>; 1324 bias-disable; 1325 }; 1326 1327 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1328 pins = "gpio4", "gpio5"; 1329 function = "gpio"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 1334 blsp2_i2c2_default: blsp2-i2c2-state { 1335 pins = "gpio6", "gpio7"; 1336 function = "blsp_i2c8"; 1337 drive-strength = <16>; 1338 bias-disable; 1339 }; 1340 1341 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1342 pins = "gpio6", "gpio7"; 1343 function = "gpio"; 1344 drive-strength = <2>; 1345 bias-disable; 1346 }; 1347 1348 blsp1_i2c6_default: blsp1-i2c6-state { 1349 pins = "gpio27", "gpio28"; 1350 function = "blsp_i2c6"; 1351 drive-strength = <16>; 1352 bias-disable; 1353 }; 1354 1355 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1356 pins = "gpio27", "gpio28"; 1357 function = "gpio"; 1358 drive-strength = <2>; 1359 bias-pull-up; 1360 }; 1361 1362 cci0_default: cci0-default-state { 1363 pins = "gpio17", "gpio18"; 1364 function = "cci_i2c"; 1365 drive-strength = <16>; 1366 bias-disable; 1367 }; 1368 1369 camera0_state_on: 1370 camera_rear_default: camera-rear-default-state { 1371 camera0_mclk: mclk0-pins { 1372 pins = "gpio13"; 1373 function = "cam_mclk"; 1374 drive-strength = <16>; 1375 bias-disable; 1376 }; 1377 1378 camera0_rst: rst-pins { 1379 pins = "gpio25"; 1380 function = "gpio"; 1381 drive-strength = <16>; 1382 bias-disable; 1383 }; 1384 1385 camera0_pwdn: pwdn-pins { 1386 pins = "gpio26"; 1387 function = "gpio"; 1388 drive-strength = <16>; 1389 bias-disable; 1390 }; 1391 }; 1392 1393 cci1_default: cci1-default-state { 1394 pins = "gpio19", "gpio20"; 1395 function = "cci_i2c"; 1396 drive-strength = <16>; 1397 bias-disable; 1398 }; 1399 1400 camera1_state_on: 1401 camera_board_default: camera-board-default-state { 1402 mclk1-pins { 1403 pins = "gpio14"; 1404 function = "cam_mclk"; 1405 drive-strength = <16>; 1406 bias-disable; 1407 }; 1408 1409 pwdn-pins { 1410 pins = "gpio98"; 1411 function = "gpio"; 1412 drive-strength = <16>; 1413 bias-disable; 1414 }; 1415 1416 rst-pins { 1417 pins = "gpio104"; 1418 function = "gpio"; 1419 drive-strength = <16>; 1420 bias-disable; 1421 }; 1422 }; 1423 1424 camera2_state_on: 1425 camera_front_default: camera-front-default-state { 1426 camera2_mclk: mclk2-pins { 1427 pins = "gpio15"; 1428 function = "cam_mclk"; 1429 drive-strength = <16>; 1430 bias-disable; 1431 }; 1432 1433 camera2_rst: rst-pins { 1434 pins = "gpio23"; 1435 function = "gpio"; 1436 drive-strength = <16>; 1437 bias-disable; 1438 }; 1439 1440 pwdn-pins { 1441 pins = "gpio133"; 1442 function = "gpio"; 1443 drive-strength = <16>; 1444 bias-disable; 1445 }; 1446 }; 1447 1448 pcie0_state_on: pcie0-state-on-state { 1449 perst-pins { 1450 pins = "gpio35"; 1451 function = "gpio"; 1452 drive-strength = <2>; 1453 bias-pull-down; 1454 }; 1455 1456 clkreq-pins { 1457 pins = "gpio36"; 1458 function = "pci_e0"; 1459 drive-strength = <2>; 1460 bias-pull-up; 1461 }; 1462 1463 wake-pins { 1464 pins = "gpio37"; 1465 function = "gpio"; 1466 drive-strength = <2>; 1467 bias-pull-up; 1468 }; 1469 }; 1470 1471 pcie0_state_off: pcie0-state-off-state { 1472 perst-pins { 1473 pins = "gpio35"; 1474 function = "gpio"; 1475 drive-strength = <2>; 1476 bias-pull-down; 1477 }; 1478 1479 clkreq-pins { 1480 pins = "gpio36"; 1481 function = "gpio"; 1482 drive-strength = <2>; 1483 bias-disable; 1484 }; 1485 1486 wake-pins { 1487 pins = "gpio37"; 1488 function = "gpio"; 1489 drive-strength = <2>; 1490 bias-disable; 1491 }; 1492 }; 1493 1494 blsp1_uart2_default: blsp1-uart2-default-state { 1495 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1496 function = "blsp_uart2"; 1497 drive-strength = <16>; 1498 bias-disable; 1499 }; 1500 1501 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1502 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1503 function = "gpio"; 1504 drive-strength = <2>; 1505 bias-disable; 1506 }; 1507 1508 blsp1_i2c3_default: blsp1-i2c3-default-state { 1509 pins = "gpio47", "gpio48"; 1510 function = "blsp_i2c3"; 1511 drive-strength = <16>; 1512 bias-disable; 1513 }; 1514 1515 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1516 pins = "gpio47", "gpio48"; 1517 function = "gpio"; 1518 drive-strength = <2>; 1519 bias-disable; 1520 }; 1521 1522 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1523 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1524 function = "blsp_uart9"; 1525 drive-strength = <16>; 1526 bias-disable; 1527 }; 1528 1529 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1530 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1531 function = "blsp_uart9"; 1532 drive-strength = <2>; 1533 bias-disable; 1534 }; 1535 1536 blsp2_i2c3_default: blsp2-i2c3-state-state { 1537 pins = "gpio51", "gpio52"; 1538 function = "blsp_i2c9"; 1539 drive-strength = <16>; 1540 bias-disable; 1541 }; 1542 1543 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1544 pins = "gpio51", "gpio52"; 1545 function = "gpio"; 1546 drive-strength = <2>; 1547 bias-disable; 1548 }; 1549 1550 wcd_intr_default: wcd-intr-default-state { 1551 pins = "gpio54"; 1552 function = "gpio"; 1553 drive-strength = <2>; 1554 bias-pull-down; 1555 input-enable; 1556 }; 1557 1558 blsp2_i2c1_default: blsp2-i2c1-state { 1559 pins = "gpio55", "gpio56"; 1560 function = "blsp_i2c7"; 1561 drive-strength = <16>; 1562 bias-disable; 1563 }; 1564 1565 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1566 pins = "gpio55", "gpio56"; 1567 function = "gpio"; 1568 drive-strength = <2>; 1569 bias-disable; 1570 }; 1571 1572 blsp2_i2c5_default: blsp2-i2c5-state { 1573 pins = "gpio60", "gpio61"; 1574 function = "blsp_i2c11"; 1575 drive-strength = <2>; 1576 bias-disable; 1577 }; 1578 1579 /* Sleep state for BLSP2_I2C5 is missing.. */ 1580 1581 cdc_reset_active: cdc-reset-active-state { 1582 pins = "gpio64"; 1583 function = "gpio"; 1584 drive-strength = <16>; 1585 bias-pull-down; 1586 output-high; 1587 }; 1588 1589 cdc_reset_sleep: cdc-reset-sleep-state { 1590 pins = "gpio64"; 1591 function = "gpio"; 1592 drive-strength = <16>; 1593 bias-disable; 1594 output-low; 1595 }; 1596 1597 blsp2_spi6_default: blsp2-spi6-default-state { 1598 spi-pins { 1599 pins = "gpio85", "gpio86", "gpio88"; 1600 function = "blsp_spi12"; 1601 drive-strength = <12>; 1602 bias-disable; 1603 }; 1604 1605 cs-pins { 1606 pins = "gpio87"; 1607 function = "gpio"; 1608 drive-strength = <16>; 1609 bias-disable; 1610 output-high; 1611 }; 1612 }; 1613 1614 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1615 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1616 function = "gpio"; 1617 drive-strength = <2>; 1618 bias-pull-down; 1619 }; 1620 1621 blsp2_i2c6_default: blsp2-i2c6-state { 1622 pins = "gpio87", "gpio88"; 1623 function = "blsp_i2c12"; 1624 drive-strength = <16>; 1625 bias-disable; 1626 }; 1627 1628 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1629 pins = "gpio87", "gpio88"; 1630 function = "gpio"; 1631 drive-strength = <2>; 1632 bias-disable; 1633 }; 1634 1635 pcie1_state_on: pcie1-on-state { 1636 perst-pins { 1637 pins = "gpio130"; 1638 function = "gpio"; 1639 drive-strength = <2>; 1640 bias-pull-down; 1641 }; 1642 1643 clkreq-pins { 1644 pins = "gpio131"; 1645 function = "pci_e1"; 1646 drive-strength = <2>; 1647 bias-pull-up; 1648 }; 1649 1650 wake-pins { 1651 pins = "gpio132"; 1652 function = "gpio"; 1653 drive-strength = <2>; 1654 bias-pull-down; 1655 }; 1656 }; 1657 1658 pcie1_state_off: pcie1-off-state { 1659 /* Perst is missing? */ 1660 clkreq-pins { 1661 pins = "gpio131"; 1662 function = "gpio"; 1663 drive-strength = <2>; 1664 bias-disable; 1665 }; 1666 1667 wake-pins { 1668 pins = "gpio132"; 1669 function = "gpio"; 1670 drive-strength = <2>; 1671 bias-disable; 1672 }; 1673 }; 1674 1675 pcie2_state_on: pcie2-on-state { 1676 perst-pins { 1677 pins = "gpio114"; 1678 function = "gpio"; 1679 drive-strength = <2>; 1680 bias-pull-down; 1681 }; 1682 1683 clkreq-pins { 1684 pins = "gpio115"; 1685 function = "pci_e2"; 1686 drive-strength = <2>; 1687 bias-pull-up; 1688 }; 1689 1690 wake-pins { 1691 pins = "gpio116"; 1692 function = "gpio"; 1693 drive-strength = <2>; 1694 bias-pull-down; 1695 }; 1696 }; 1697 1698 pcie2_state_off: pcie2-off-state { 1699 /* Perst is missing? */ 1700 clkreq-pins { 1701 pins = "gpio115"; 1702 function = "gpio"; 1703 drive-strength = <2>; 1704 bias-disable; 1705 }; 1706 1707 wake-pins { 1708 pins = "gpio116"; 1709 function = "gpio"; 1710 drive-strength = <2>; 1711 bias-disable; 1712 }; 1713 }; 1714 1715 sdc1_state_on: sdc1-on-state { 1716 clk-pins { 1717 pins = "sdc1_clk"; 1718 bias-disable; 1719 drive-strength = <16>; 1720 }; 1721 1722 cmd-pins { 1723 pins = "sdc1_cmd"; 1724 bias-pull-up; 1725 drive-strength = <10>; 1726 }; 1727 1728 data-pins { 1729 pins = "sdc1_data"; 1730 bias-pull-up; 1731 drive-strength = <10>; 1732 }; 1733 1734 rclk-pins { 1735 pins = "sdc1_rclk"; 1736 bias-pull-down; 1737 }; 1738 }; 1739 1740 sdc1_state_off: sdc1-off-state { 1741 clk-pins { 1742 pins = "sdc1_clk"; 1743 bias-disable; 1744 drive-strength = <2>; 1745 }; 1746 1747 cmd-pins { 1748 pins = "sdc1_cmd"; 1749 bias-pull-up; 1750 drive-strength = <2>; 1751 }; 1752 1753 data-pins { 1754 pins = "sdc1_data"; 1755 bias-pull-up; 1756 drive-strength = <2>; 1757 }; 1758 1759 rclk-pins { 1760 pins = "sdc1_rclk"; 1761 bias-pull-down; 1762 }; 1763 }; 1764 1765 sdc2_state_on: sdc2-on-state { 1766 clk-pins { 1767 pins = "sdc2_clk"; 1768 bias-disable; 1769 drive-strength = <16>; 1770 }; 1771 1772 cmd-pins { 1773 pins = "sdc2_cmd"; 1774 bias-pull-up; 1775 drive-strength = <10>; 1776 }; 1777 1778 data-pins { 1779 pins = "sdc2_data"; 1780 bias-pull-up; 1781 drive-strength = <10>; 1782 }; 1783 }; 1784 1785 sdc2_state_off: sdc2-off-state { 1786 clk-pins { 1787 pins = "sdc2_clk"; 1788 bias-disable; 1789 drive-strength = <2>; 1790 }; 1791 1792 cmd-pins { 1793 pins = "sdc2_cmd"; 1794 bias-pull-up; 1795 drive-strength = <2>; 1796 }; 1797 1798 data-pins { 1799 pins = "sdc2_data"; 1800 bias-pull-up; 1801 drive-strength = <2>; 1802 }; 1803 }; 1804 }; 1805 1806 sram@290000 { 1807 compatible = "qcom,rpm-stats"; 1808 reg = <0x00290000 0x10000>; 1809 }; 1810 1811 spmi_bus: spmi@400f000 { 1812 compatible = "qcom,spmi-pmic-arb"; 1813 reg = <0x0400f000 0x1000>, 1814 <0x04400000 0x800000>, 1815 <0x04c00000 0x800000>, 1816 <0x05800000 0x200000>, 1817 <0x0400a000 0x002100>; 1818 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1819 interrupt-names = "periph_irq"; 1820 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1821 qcom,ee = <0>; 1822 qcom,channel = <0>; 1823 #address-cells = <2>; 1824 #size-cells = <0>; 1825 interrupt-controller; 1826 #interrupt-cells = <4>; 1827 }; 1828 1829 bus@0 { 1830 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1831 compatible = "simple-pm-bus"; 1832 #address-cells = <1>; 1833 #size-cells = <1>; 1834 ranges; 1835 1836 pcie0: pcie@600000 { 1837 compatible = "qcom,pcie-msm8996"; 1838 status = "disabled"; 1839 power-domains = <&gcc PCIE0_GDSC>; 1840 bus-range = <0x00 0xff>; 1841 num-lanes = <1>; 1842 1843 reg = <0x00600000 0x2000>, 1844 <0x0c000000 0xf1d>, 1845 <0x0c000f20 0xa8>, 1846 <0x0c100000 0x100000>; 1847 reg-names = "parf", "dbi", "elbi","config"; 1848 1849 phys = <&pciephy_0>; 1850 phy-names = "pciephy"; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1855 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1856 1857 device_type = "pci"; 1858 1859 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "msi"; 1861 #interrupt-cells = <1>; 1862 interrupt-map-mask = <0 0 0 0x7>; 1863 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1864 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1865 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1866 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1867 1868 pinctrl-names = "default", "sleep"; 1869 pinctrl-0 = <&pcie0_state_on>; 1870 pinctrl-1 = <&pcie0_state_off>; 1871 1872 linux,pci-domain = <0>; 1873 1874 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1875 <&gcc GCC_PCIE_0_AUX_CLK>, 1876 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1878 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1879 1880 clock-names = "pipe", 1881 "aux", 1882 "cfg", 1883 "bus_master", 1884 "bus_slave"; 1885 1886 }; 1887 1888 pcie1: pcie@608000 { 1889 compatible = "qcom,pcie-msm8996"; 1890 power-domains = <&gcc PCIE1_GDSC>; 1891 bus-range = <0x00 0xff>; 1892 num-lanes = <1>; 1893 1894 status = "disabled"; 1895 1896 reg = <0x00608000 0x2000>, 1897 <0x0d000000 0xf1d>, 1898 <0x0d000f20 0xa8>, 1899 <0x0d100000 0x100000>; 1900 1901 reg-names = "parf", "dbi", "elbi","config"; 1902 1903 phys = <&pciephy_1>; 1904 phy-names = "pciephy"; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1909 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1910 1911 device_type = "pci"; 1912 1913 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1914 interrupt-names = "msi"; 1915 #interrupt-cells = <1>; 1916 interrupt-map-mask = <0 0 0 0x7>; 1917 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1918 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1919 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1920 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1921 1922 pinctrl-names = "default", "sleep"; 1923 pinctrl-0 = <&pcie1_state_on>; 1924 pinctrl-1 = <&pcie1_state_off>; 1925 1926 linux,pci-domain = <1>; 1927 1928 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1929 <&gcc GCC_PCIE_1_AUX_CLK>, 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1933 1934 clock-names = "pipe", 1935 "aux", 1936 "cfg", 1937 "bus_master", 1938 "bus_slave"; 1939 }; 1940 1941 pcie2: pcie@610000 { 1942 compatible = "qcom,pcie-msm8996"; 1943 power-domains = <&gcc PCIE2_GDSC>; 1944 bus-range = <0x00 0xff>; 1945 num-lanes = <1>; 1946 status = "disabled"; 1947 reg = <0x00610000 0x2000>, 1948 <0x0e000000 0xf1d>, 1949 <0x0e000f20 0xa8>, 1950 <0x0e100000 0x100000>; 1951 1952 reg-names = "parf", "dbi", "elbi","config"; 1953 1954 phys = <&pciephy_2>; 1955 phy-names = "pciephy"; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1960 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1961 1962 device_type = "pci"; 1963 1964 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "msi"; 1966 #interrupt-cells = <1>; 1967 interrupt-map-mask = <0 0 0 0x7>; 1968 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1969 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1970 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1971 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1972 1973 pinctrl-names = "default", "sleep"; 1974 pinctrl-0 = <&pcie2_state_on>; 1975 pinctrl-1 = <&pcie2_state_off>; 1976 1977 linux,pci-domain = <2>; 1978 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1979 <&gcc GCC_PCIE_2_AUX_CLK>, 1980 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1981 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1982 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1983 1984 clock-names = "pipe", 1985 "aux", 1986 "cfg", 1987 "bus_master", 1988 "bus_slave"; 1989 }; 1990 }; 1991 1992 ufshc: ufshc@624000 { 1993 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1994 "jedec,ufs-2.0"; 1995 reg = <0x00624000 0x2500>; 1996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1997 1998 phys = <&ufsphy_lane>; 1999 phy-names = "ufsphy"; 2000 2001 power-domains = <&gcc UFS_GDSC>; 2002 2003 clock-names = 2004 "core_clk_src", 2005 "core_clk", 2006 "bus_clk", 2007 "bus_aggr_clk", 2008 "iface_clk", 2009 "core_clk_unipro_src", 2010 "core_clk_unipro", 2011 "core_clk_ice", 2012 "ref_clk", 2013 "tx_lane0_sync_clk", 2014 "rx_lane0_sync_clk"; 2015 clocks = 2016 <&gcc UFS_AXI_CLK_SRC>, 2017 <&gcc GCC_UFS_AXI_CLK>, 2018 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2019 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2020 <&gcc GCC_UFS_AHB_CLK>, 2021 <&gcc UFS_ICE_CORE_CLK_SRC>, 2022 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2023 <&gcc GCC_UFS_ICE_CORE_CLK>, 2024 <&rpmcc RPM_SMD_LN_BB_CLK>, 2025 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2026 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2027 freq-table-hz = 2028 <100000000 200000000>, 2029 <0 0>, 2030 <0 0>, 2031 <0 0>, 2032 <0 0>, 2033 <150000000 300000000>, 2034 <0 0>, 2035 <0 0>, 2036 <0 0>, 2037 <0 0>, 2038 <0 0>; 2039 2040 lanes-per-direction = <1>; 2041 #reset-cells = <1>; 2042 status = "disabled"; 2043 }; 2044 2045 ufsphy: phy@627000 { 2046 compatible = "qcom,msm8996-qmp-ufs-phy"; 2047 reg = <0x00627000 0x1c4>; 2048 #address-cells = <1>; 2049 #size-cells = <1>; 2050 ranges; 2051 2052 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2053 clock-names = "ref"; 2054 2055 resets = <&ufshc 0>; 2056 reset-names = "ufsphy"; 2057 status = "disabled"; 2058 2059 ufsphy_lane: phy@627400 { 2060 reg = <0x627400 0x12c>, 2061 <0x627600 0x200>, 2062 <0x627c00 0x1b4>; 2063 #clock-cells = <1>; 2064 #phy-cells = <0>; 2065 }; 2066 }; 2067 2068 camss: camss@a00000 { 2069 compatible = "qcom,msm8996-camss"; 2070 reg = <0x00a34000 0x1000>, 2071 <0x00a00030 0x4>, 2072 <0x00a35000 0x1000>, 2073 <0x00a00038 0x4>, 2074 <0x00a36000 0x1000>, 2075 <0x00a00040 0x4>, 2076 <0x00a30000 0x100>, 2077 <0x00a30400 0x100>, 2078 <0x00a30800 0x100>, 2079 <0x00a30c00 0x100>, 2080 <0x00a31000 0x500>, 2081 <0x00a00020 0x10>, 2082 <0x00a10000 0x1000>, 2083 <0x00a14000 0x1000>; 2084 reg-names = "csiphy0", 2085 "csiphy0_clk_mux", 2086 "csiphy1", 2087 "csiphy1_clk_mux", 2088 "csiphy2", 2089 "csiphy2_clk_mux", 2090 "csid0", 2091 "csid1", 2092 "csid2", 2093 "csid3", 2094 "ispif", 2095 "csi_clk_mux", 2096 "vfe0", 2097 "vfe1"; 2098 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2099 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2100 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2101 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2102 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2103 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2104 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2108 interrupt-names = "csiphy0", 2109 "csiphy1", 2110 "csiphy2", 2111 "csid0", 2112 "csid1", 2113 "csid2", 2114 "csid3", 2115 "ispif", 2116 "vfe0", 2117 "vfe1"; 2118 power-domains = <&mmcc VFE0_GDSC>, 2119 <&mmcc VFE1_GDSC>; 2120 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2121 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2122 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2123 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2124 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2125 <&mmcc CAMSS_CSI0_AHB_CLK>, 2126 <&mmcc CAMSS_CSI0_CLK>, 2127 <&mmcc CAMSS_CSI0PHY_CLK>, 2128 <&mmcc CAMSS_CSI0PIX_CLK>, 2129 <&mmcc CAMSS_CSI0RDI_CLK>, 2130 <&mmcc CAMSS_CSI1_AHB_CLK>, 2131 <&mmcc CAMSS_CSI1_CLK>, 2132 <&mmcc CAMSS_CSI1PHY_CLK>, 2133 <&mmcc CAMSS_CSI1PIX_CLK>, 2134 <&mmcc CAMSS_CSI1RDI_CLK>, 2135 <&mmcc CAMSS_CSI2_AHB_CLK>, 2136 <&mmcc CAMSS_CSI2_CLK>, 2137 <&mmcc CAMSS_CSI2PHY_CLK>, 2138 <&mmcc CAMSS_CSI2PIX_CLK>, 2139 <&mmcc CAMSS_CSI2RDI_CLK>, 2140 <&mmcc CAMSS_CSI3_AHB_CLK>, 2141 <&mmcc CAMSS_CSI3_CLK>, 2142 <&mmcc CAMSS_CSI3PHY_CLK>, 2143 <&mmcc CAMSS_CSI3PIX_CLK>, 2144 <&mmcc CAMSS_CSI3RDI_CLK>, 2145 <&mmcc CAMSS_AHB_CLK>, 2146 <&mmcc CAMSS_VFE0_CLK>, 2147 <&mmcc CAMSS_CSI_VFE0_CLK>, 2148 <&mmcc CAMSS_VFE0_AHB_CLK>, 2149 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2150 <&mmcc CAMSS_VFE1_CLK>, 2151 <&mmcc CAMSS_CSI_VFE1_CLK>, 2152 <&mmcc CAMSS_VFE1_AHB_CLK>, 2153 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2154 <&mmcc CAMSS_VFE_AHB_CLK>, 2155 <&mmcc CAMSS_VFE_AXI_CLK>; 2156 clock-names = "top_ahb", 2157 "ispif_ahb", 2158 "csiphy0_timer", 2159 "csiphy1_timer", 2160 "csiphy2_timer", 2161 "csi0_ahb", 2162 "csi0", 2163 "csi0_phy", 2164 "csi0_pix", 2165 "csi0_rdi", 2166 "csi1_ahb", 2167 "csi1", 2168 "csi1_phy", 2169 "csi1_pix", 2170 "csi1_rdi", 2171 "csi2_ahb", 2172 "csi2", 2173 "csi2_phy", 2174 "csi2_pix", 2175 "csi2_rdi", 2176 "csi3_ahb", 2177 "csi3", 2178 "csi3_phy", 2179 "csi3_pix", 2180 "csi3_rdi", 2181 "ahb", 2182 "vfe0", 2183 "csi_vfe0", 2184 "vfe0_ahb", 2185 "vfe0_stream", 2186 "vfe1", 2187 "csi_vfe1", 2188 "vfe1_ahb", 2189 "vfe1_stream", 2190 "vfe_ahb", 2191 "vfe_axi"; 2192 iommus = <&vfe_smmu 0>, 2193 <&vfe_smmu 1>, 2194 <&vfe_smmu 2>, 2195 <&vfe_smmu 3>; 2196 status = "disabled"; 2197 ports { 2198 #address-cells = <1>; 2199 #size-cells = <0>; 2200 }; 2201 }; 2202 2203 cci: cci@a0c000 { 2204 compatible = "qcom,msm8996-cci"; 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 reg = <0xa0c000 0x1000>; 2208 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2209 power-domains = <&mmcc CAMSS_GDSC>; 2210 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2211 <&mmcc CAMSS_CCI_AHB_CLK>, 2212 <&mmcc CAMSS_CCI_CLK>, 2213 <&mmcc CAMSS_AHB_CLK>; 2214 clock-names = "camss_top_ahb", 2215 "cci_ahb", 2216 "cci", 2217 "camss_ahb"; 2218 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2219 <&mmcc CAMSS_CCI_CLK>; 2220 assigned-clock-rates = <80000000>, <37500000>; 2221 pinctrl-names = "default"; 2222 pinctrl-0 = <&cci0_default &cci1_default>; 2223 status = "disabled"; 2224 2225 cci_i2c0: i2c-bus@0 { 2226 reg = <0>; 2227 clock-frequency = <400000>; 2228 #address-cells = <1>; 2229 #size-cells = <0>; 2230 }; 2231 2232 cci_i2c1: i2c-bus@1 { 2233 reg = <1>; 2234 clock-frequency = <400000>; 2235 #address-cells = <1>; 2236 #size-cells = <0>; 2237 }; 2238 }; 2239 2240 adreno_smmu: iommu@b40000 { 2241 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2242 reg = <0x00b40000 0x10000>; 2243 2244 #global-interrupts = <1>; 2245 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2248 #iommu-cells = <1>; 2249 2250 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2251 <&mmcc GPU_AHB_CLK>; 2252 clock-names = "bus", "iface"; 2253 2254 power-domains = <&mmcc GPU_GDSC>; 2255 }; 2256 2257 venus: video-codec@c00000 { 2258 compatible = "qcom,msm8996-venus"; 2259 reg = <0x00c00000 0xff000>; 2260 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2261 power-domains = <&mmcc VENUS_GDSC>; 2262 clocks = <&mmcc VIDEO_CORE_CLK>, 2263 <&mmcc VIDEO_AHB_CLK>, 2264 <&mmcc VIDEO_AXI_CLK>, 2265 <&mmcc VIDEO_MAXI_CLK>; 2266 clock-names = "core", "iface", "bus", "mbus"; 2267 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2268 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2269 interconnect-names = "video-mem", "cpu-cfg"; 2270 iommus = <&venus_smmu 0x00>, 2271 <&venus_smmu 0x01>, 2272 <&venus_smmu 0x0a>, 2273 <&venus_smmu 0x07>, 2274 <&venus_smmu 0x0e>, 2275 <&venus_smmu 0x0f>, 2276 <&venus_smmu 0x08>, 2277 <&venus_smmu 0x09>, 2278 <&venus_smmu 0x0b>, 2279 <&venus_smmu 0x0c>, 2280 <&venus_smmu 0x0d>, 2281 <&venus_smmu 0x10>, 2282 <&venus_smmu 0x11>, 2283 <&venus_smmu 0x21>, 2284 <&venus_smmu 0x28>, 2285 <&venus_smmu 0x29>, 2286 <&venus_smmu 0x2b>, 2287 <&venus_smmu 0x2c>, 2288 <&venus_smmu 0x2d>, 2289 <&venus_smmu 0x31>; 2290 memory-region = <&venus_mem>; 2291 status = "disabled"; 2292 2293 video-decoder { 2294 compatible = "venus-decoder"; 2295 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2296 clock-names = "core"; 2297 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2298 }; 2299 2300 video-encoder { 2301 compatible = "venus-encoder"; 2302 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2303 clock-names = "core"; 2304 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2305 }; 2306 }; 2307 2308 mdp_smmu: iommu@d00000 { 2309 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2310 reg = <0x00d00000 0x10000>; 2311 2312 #global-interrupts = <1>; 2313 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2314 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2315 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2316 #iommu-cells = <1>; 2317 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2318 <&mmcc SMMU_MDP_AHB_CLK>; 2319 clock-names = "bus", "iface"; 2320 2321 power-domains = <&mmcc MDSS_GDSC>; 2322 }; 2323 2324 venus_smmu: iommu@d40000 { 2325 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2326 reg = <0x00d40000 0x20000>; 2327 #global-interrupts = <1>; 2328 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2336 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2337 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2338 <&mmcc SMMU_VIDEO_AHB_CLK>; 2339 clock-names = "bus", "iface"; 2340 #iommu-cells = <1>; 2341 status = "okay"; 2342 }; 2343 2344 vfe_smmu: iommu@da0000 { 2345 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2346 reg = <0x00da0000 0x10000>; 2347 2348 #global-interrupts = <1>; 2349 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2352 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2353 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2354 <&mmcc SMMU_VFE_AHB_CLK>; 2355 clock-names = "bus", "iface"; 2356 #iommu-cells = <1>; 2357 }; 2358 2359 lpass_q6_smmu: iommu@1600000 { 2360 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2361 reg = <0x01600000 0x20000>; 2362 #iommu-cells = <1>; 2363 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2364 2365 #global-interrupts = <1>; 2366 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2379 2380 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2381 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2382 clock-names = "bus", "iface"; 2383 }; 2384 2385 slpi_pil: remoteproc@1c00000 { 2386 compatible = "qcom,msm8996-slpi-pil"; 2387 reg = <0x01c00000 0x4000>; 2388 2389 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2390 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2391 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2392 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2393 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2394 interrupt-names = "wdog", 2395 "fatal", 2396 "ready", 2397 "handover", 2398 "stop-ack"; 2399 2400 clocks = <&xo_board>, 2401 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2402 clock-names = "xo", "aggre2"; 2403 2404 memory-region = <&slpi_mem>; 2405 2406 qcom,smem-states = <&slpi_smp2p_out 0>; 2407 qcom,smem-state-names = "stop"; 2408 2409 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2410 power-domain-names = "ssc_cx"; 2411 2412 status = "disabled"; 2413 2414 smd-edge { 2415 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2416 2417 label = "dsps"; 2418 mboxes = <&apcs_glb 25>; 2419 qcom,smd-edge = <3>; 2420 qcom,remote-pid = <3>; 2421 }; 2422 }; 2423 2424 mss_pil: remoteproc@2080000 { 2425 compatible = "qcom,msm8996-mss-pil"; 2426 reg = <0x2080000 0x100>, 2427 <0x2180000 0x020>; 2428 reg-names = "qdsp6", "rmb"; 2429 2430 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2431 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2432 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2433 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2434 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2435 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2436 interrupt-names = "wdog", "fatal", "ready", 2437 "handover", "stop-ack", 2438 "shutdown-ack"; 2439 2440 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2441 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2442 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2443 <&xo_board>, 2444 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2445 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2446 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2447 <&rpmcc RPM_SMD_PCNOC_CLK>, 2448 <&rpmcc RPM_SMD_QDSS_CLK>; 2449 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2450 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2451 2452 resets = <&gcc GCC_MSS_RESTART>; 2453 reset-names = "mss_restart"; 2454 2455 power-domains = <&rpmpd MSM8996_VDDCX>, 2456 <&rpmpd MSM8996_VDDMX>; 2457 power-domain-names = "cx", "mx"; 2458 2459 qcom,smem-states = <&mpss_smp2p_out 0>; 2460 qcom,smem-state-names = "stop"; 2461 2462 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2463 2464 status = "disabled"; 2465 2466 mba { 2467 memory-region = <&mba_mem>; 2468 }; 2469 2470 mpss { 2471 memory-region = <&mpss_mem>; 2472 }; 2473 2474 metadata { 2475 memory-region = <&mdata_mem>; 2476 }; 2477 2478 smd-edge { 2479 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2480 2481 label = "mpss"; 2482 mboxes = <&apcs_glb 12>; 2483 qcom,smd-edge = <0>; 2484 qcom,remote-pid = <1>; 2485 }; 2486 }; 2487 2488 stm@3002000 { 2489 compatible = "arm,coresight-stm", "arm,primecell"; 2490 reg = <0x3002000 0x1000>, 2491 <0x8280000 0x180000>; 2492 reg-names = "stm-base", "stm-stimulus-base"; 2493 2494 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2495 clock-names = "apb_pclk", "atclk"; 2496 2497 out-ports { 2498 port { 2499 stm_out: endpoint { 2500 remote-endpoint = 2501 <&funnel0_in>; 2502 }; 2503 }; 2504 }; 2505 }; 2506 2507 tpiu@3020000 { 2508 compatible = "arm,coresight-tpiu", "arm,primecell"; 2509 reg = <0x3020000 0x1000>; 2510 2511 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2512 clock-names = "apb_pclk", "atclk"; 2513 2514 in-ports { 2515 port { 2516 tpiu_in: endpoint { 2517 remote-endpoint = 2518 <&replicator_out1>; 2519 }; 2520 }; 2521 }; 2522 }; 2523 2524 funnel@3021000 { 2525 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2526 reg = <0x3021000 0x1000>; 2527 2528 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2529 clock-names = "apb_pclk", "atclk"; 2530 2531 in-ports { 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 port@7 { 2536 reg = <7>; 2537 funnel0_in: endpoint { 2538 remote-endpoint = 2539 <&stm_out>; 2540 }; 2541 }; 2542 }; 2543 2544 out-ports { 2545 port { 2546 funnel0_out: endpoint { 2547 remote-endpoint = 2548 <&merge_funnel_in0>; 2549 }; 2550 }; 2551 }; 2552 }; 2553 2554 funnel@3022000 { 2555 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2556 reg = <0x3022000 0x1000>; 2557 2558 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2559 clock-names = "apb_pclk", "atclk"; 2560 2561 in-ports { 2562 #address-cells = <1>; 2563 #size-cells = <0>; 2564 2565 port@6 { 2566 reg = <6>; 2567 funnel1_in: endpoint { 2568 remote-endpoint = 2569 <&apss_merge_funnel_out>; 2570 }; 2571 }; 2572 }; 2573 2574 out-ports { 2575 port { 2576 funnel1_out: endpoint { 2577 remote-endpoint = 2578 <&merge_funnel_in1>; 2579 }; 2580 }; 2581 }; 2582 }; 2583 2584 funnel@3023000 { 2585 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2586 reg = <0x3023000 0x1000>; 2587 2588 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2589 clock-names = "apb_pclk", "atclk"; 2590 2591 2592 out-ports { 2593 port { 2594 funnel2_out: endpoint { 2595 remote-endpoint = 2596 <&merge_funnel_in2>; 2597 }; 2598 }; 2599 }; 2600 }; 2601 2602 funnel@3025000 { 2603 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2604 reg = <0x3025000 0x1000>; 2605 2606 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2607 clock-names = "apb_pclk", "atclk"; 2608 2609 in-ports { 2610 #address-cells = <1>; 2611 #size-cells = <0>; 2612 2613 port@0 { 2614 reg = <0>; 2615 merge_funnel_in0: endpoint { 2616 remote-endpoint = 2617 <&funnel0_out>; 2618 }; 2619 }; 2620 2621 port@1 { 2622 reg = <1>; 2623 merge_funnel_in1: endpoint { 2624 remote-endpoint = 2625 <&funnel1_out>; 2626 }; 2627 }; 2628 2629 port@2 { 2630 reg = <2>; 2631 merge_funnel_in2: endpoint { 2632 remote-endpoint = 2633 <&funnel2_out>; 2634 }; 2635 }; 2636 }; 2637 2638 out-ports { 2639 port { 2640 merge_funnel_out: endpoint { 2641 remote-endpoint = 2642 <&etf_in>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 replicator@3026000 { 2649 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2650 reg = <0x3026000 0x1000>; 2651 2652 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2653 clock-names = "apb_pclk", "atclk"; 2654 2655 in-ports { 2656 port { 2657 replicator_in: endpoint { 2658 remote-endpoint = 2659 <&etf_out>; 2660 }; 2661 }; 2662 }; 2663 2664 out-ports { 2665 #address-cells = <1>; 2666 #size-cells = <0>; 2667 2668 port@0 { 2669 reg = <0>; 2670 replicator_out0: endpoint { 2671 remote-endpoint = 2672 <&etr_in>; 2673 }; 2674 }; 2675 2676 port@1 { 2677 reg = <1>; 2678 replicator_out1: endpoint { 2679 remote-endpoint = 2680 <&tpiu_in>; 2681 }; 2682 }; 2683 }; 2684 }; 2685 2686 etf@3027000 { 2687 compatible = "arm,coresight-tmc", "arm,primecell"; 2688 reg = <0x3027000 0x1000>; 2689 2690 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2691 clock-names = "apb_pclk", "atclk"; 2692 2693 in-ports { 2694 port { 2695 etf_in: endpoint { 2696 remote-endpoint = 2697 <&merge_funnel_out>; 2698 }; 2699 }; 2700 }; 2701 2702 out-ports { 2703 port { 2704 etf_out: endpoint { 2705 remote-endpoint = 2706 <&replicator_in>; 2707 }; 2708 }; 2709 }; 2710 }; 2711 2712 etr@3028000 { 2713 compatible = "arm,coresight-tmc", "arm,primecell"; 2714 reg = <0x3028000 0x1000>; 2715 2716 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2717 clock-names = "apb_pclk", "atclk"; 2718 arm,scatter-gather; 2719 2720 in-ports { 2721 port { 2722 etr_in: endpoint { 2723 remote-endpoint = 2724 <&replicator_out0>; 2725 }; 2726 }; 2727 }; 2728 }; 2729 2730 debug@3810000 { 2731 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2732 reg = <0x3810000 0x1000>; 2733 2734 clocks = <&rpmcc RPM_QDSS_CLK>; 2735 clock-names = "apb_pclk"; 2736 2737 cpu = <&CPU0>; 2738 }; 2739 2740 etm@3840000 { 2741 compatible = "arm,coresight-etm4x", "arm,primecell"; 2742 reg = <0x3840000 0x1000>; 2743 2744 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2745 clock-names = "apb_pclk", "atclk"; 2746 2747 cpu = <&CPU0>; 2748 2749 out-ports { 2750 port { 2751 etm0_out: endpoint { 2752 remote-endpoint = 2753 <&apss_funnel0_in0>; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 debug@3910000 { 2760 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2761 reg = <0x3910000 0x1000>; 2762 2763 clocks = <&rpmcc RPM_QDSS_CLK>; 2764 clock-names = "apb_pclk"; 2765 2766 cpu = <&CPU1>; 2767 }; 2768 2769 etm@3940000 { 2770 compatible = "arm,coresight-etm4x", "arm,primecell"; 2771 reg = <0x3940000 0x1000>; 2772 2773 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2774 clock-names = "apb_pclk", "atclk"; 2775 2776 cpu = <&CPU1>; 2777 2778 out-ports { 2779 port { 2780 etm1_out: endpoint { 2781 remote-endpoint = 2782 <&apss_funnel0_in1>; 2783 }; 2784 }; 2785 }; 2786 }; 2787 2788 funnel@39b0000 { /* APSS Funnel 0 */ 2789 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2790 reg = <0x39b0000 0x1000>; 2791 2792 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2793 clock-names = "apb_pclk", "atclk"; 2794 2795 in-ports { 2796 #address-cells = <1>; 2797 #size-cells = <0>; 2798 2799 port@0 { 2800 reg = <0>; 2801 apss_funnel0_in0: endpoint { 2802 remote-endpoint = <&etm0_out>; 2803 }; 2804 }; 2805 2806 port@1 { 2807 reg = <1>; 2808 apss_funnel0_in1: endpoint { 2809 remote-endpoint = <&etm1_out>; 2810 }; 2811 }; 2812 }; 2813 2814 out-ports { 2815 port { 2816 apss_funnel0_out: endpoint { 2817 remote-endpoint = 2818 <&apss_merge_funnel_in0>; 2819 }; 2820 }; 2821 }; 2822 }; 2823 2824 debug@3a10000 { 2825 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2826 reg = <0x3a10000 0x1000>; 2827 2828 clocks = <&rpmcc RPM_QDSS_CLK>; 2829 clock-names = "apb_pclk"; 2830 2831 cpu = <&CPU2>; 2832 }; 2833 2834 etm@3a40000 { 2835 compatible = "arm,coresight-etm4x", "arm,primecell"; 2836 reg = <0x3a40000 0x1000>; 2837 2838 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2839 clock-names = "apb_pclk", "atclk"; 2840 2841 cpu = <&CPU2>; 2842 2843 out-ports { 2844 port { 2845 etm2_out: endpoint { 2846 remote-endpoint = 2847 <&apss_funnel1_in0>; 2848 }; 2849 }; 2850 }; 2851 }; 2852 2853 debug@3b10000 { 2854 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2855 reg = <0x3b10000 0x1000>; 2856 2857 clocks = <&rpmcc RPM_QDSS_CLK>; 2858 clock-names = "apb_pclk"; 2859 2860 cpu = <&CPU3>; 2861 }; 2862 2863 etm@3b40000 { 2864 compatible = "arm,coresight-etm4x", "arm,primecell"; 2865 reg = <0x3b40000 0x1000>; 2866 2867 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2868 clock-names = "apb_pclk", "atclk"; 2869 2870 cpu = <&CPU3>; 2871 2872 out-ports { 2873 port { 2874 etm3_out: endpoint { 2875 remote-endpoint = 2876 <&apss_funnel1_in1>; 2877 }; 2878 }; 2879 }; 2880 }; 2881 2882 funnel@3bb0000 { /* APSS Funnel 1 */ 2883 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2884 reg = <0x3bb0000 0x1000>; 2885 2886 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2887 clock-names = "apb_pclk", "atclk"; 2888 2889 in-ports { 2890 #address-cells = <1>; 2891 #size-cells = <0>; 2892 2893 port@0 { 2894 reg = <0>; 2895 apss_funnel1_in0: endpoint { 2896 remote-endpoint = <&etm2_out>; 2897 }; 2898 }; 2899 2900 port@1 { 2901 reg = <1>; 2902 apss_funnel1_in1: endpoint { 2903 remote-endpoint = <&etm3_out>; 2904 }; 2905 }; 2906 }; 2907 2908 out-ports { 2909 port { 2910 apss_funnel1_out: endpoint { 2911 remote-endpoint = 2912 <&apss_merge_funnel_in1>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 funnel@3bc0000 { 2919 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2920 reg = <0x3bc0000 0x1000>; 2921 2922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2923 clock-names = "apb_pclk", "atclk"; 2924 2925 in-ports { 2926 #address-cells = <1>; 2927 #size-cells = <0>; 2928 2929 port@0 { 2930 reg = <0>; 2931 apss_merge_funnel_in0: endpoint { 2932 remote-endpoint = 2933 <&apss_funnel0_out>; 2934 }; 2935 }; 2936 2937 port@1 { 2938 reg = <1>; 2939 apss_merge_funnel_in1: endpoint { 2940 remote-endpoint = 2941 <&apss_funnel1_out>; 2942 }; 2943 }; 2944 }; 2945 2946 out-ports { 2947 port { 2948 apss_merge_funnel_out: endpoint { 2949 remote-endpoint = 2950 <&funnel1_in>; 2951 }; 2952 }; 2953 }; 2954 }; 2955 2956 kryocc: clock-controller@6400000 { 2957 compatible = "qcom,msm8996-apcc"; 2958 reg = <0x06400000 0x90000>; 2959 2960 clock-names = "xo", "sys_apcs_aux"; 2961 clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; 2962 2963 #clock-cells = <1>; 2964 }; 2965 2966 usb3: usb@6af8800 { 2967 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2968 reg = <0x06af8800 0x400>; 2969 #address-cells = <1>; 2970 #size-cells = <1>; 2971 ranges; 2972 2973 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2975 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2976 2977 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2978 <&gcc GCC_USB30_MASTER_CLK>, 2979 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2980 <&gcc GCC_USB30_SLEEP_CLK>, 2981 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2982 clock-names = "cfg_noc", 2983 "core", 2984 "iface", 2985 "sleep", 2986 "mock_utmi"; 2987 2988 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2989 <&gcc GCC_USB30_MASTER_CLK>; 2990 assigned-clock-rates = <19200000>, <120000000>; 2991 2992 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2993 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2994 interconnect-names = "usb-ddr", "apps-usb"; 2995 2996 power-domains = <&gcc USB30_GDSC>; 2997 status = "disabled"; 2998 2999 usb3_dwc3: usb@6a00000 { 3000 compatible = "snps,dwc3"; 3001 reg = <0x06a00000 0xcc00>; 3002 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 3003 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3004 phy-names = "usb2-phy", "usb3-phy"; 3005 snps,dis_u2_susphy_quirk; 3006 snps,dis_enblslpm_quirk; 3007 }; 3008 }; 3009 3010 usb3phy: phy@7410000 { 3011 compatible = "qcom,msm8996-qmp-usb3-phy"; 3012 reg = <0x07410000 0x1c4>; 3013 #address-cells = <1>; 3014 #size-cells = <1>; 3015 ranges; 3016 3017 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3018 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3019 <&gcc GCC_USB3_CLKREF_CLK>; 3020 clock-names = "aux", "cfg_ahb", "ref"; 3021 3022 resets = <&gcc GCC_USB3_PHY_BCR>, 3023 <&gcc GCC_USB3PHY_PHY_BCR>; 3024 reset-names = "phy", "common"; 3025 status = "disabled"; 3026 3027 ssusb_phy_0: phy@7410200 { 3028 reg = <0x07410200 0x200>, 3029 <0x07410400 0x130>, 3030 <0x07410600 0x1a8>; 3031 #phy-cells = <0>; 3032 3033 #clock-cells = <0>; 3034 clock-output-names = "usb3_phy_pipe_clk_src"; 3035 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3036 clock-names = "pipe0"; 3037 }; 3038 }; 3039 3040 hsusb_phy1: phy@7411000 { 3041 compatible = "qcom,msm8996-qusb2-phy"; 3042 reg = <0x07411000 0x180>; 3043 #phy-cells = <0>; 3044 3045 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3046 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3047 clock-names = "cfg_ahb", "ref"; 3048 3049 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3050 nvmem-cells = <&qusb2p_hstx_trim>; 3051 status = "disabled"; 3052 }; 3053 3054 hsusb_phy2: phy@7412000 { 3055 compatible = "qcom,msm8996-qusb2-phy"; 3056 reg = <0x07412000 0x180>; 3057 #phy-cells = <0>; 3058 3059 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3060 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3061 clock-names = "cfg_ahb", "ref"; 3062 3063 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3064 nvmem-cells = <&qusb2s_hstx_trim>; 3065 status = "disabled"; 3066 }; 3067 3068 sdhc1: mmc@7464900 { 3069 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3070 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3071 reg-names = "hc", "core"; 3072 3073 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3075 interrupt-names = "hc_irq", "pwr_irq"; 3076 3077 clock-names = "iface", "core", "xo"; 3078 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3079 <&gcc GCC_SDCC1_APPS_CLK>, 3080 <&rpmcc RPM_SMD_BB_CLK1>; 3081 resets = <&gcc GCC_SDCC1_BCR>; 3082 3083 pinctrl-names = "default", "sleep"; 3084 pinctrl-0 = <&sdc1_state_on>; 3085 pinctrl-1 = <&sdc1_state_off>; 3086 3087 bus-width = <8>; 3088 non-removable; 3089 status = "disabled"; 3090 }; 3091 3092 sdhc2: mmc@74a4900 { 3093 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3094 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3095 reg-names = "hc", "core"; 3096 3097 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3099 interrupt-names = "hc_irq", "pwr_irq"; 3100 3101 clock-names = "iface", "core", "xo"; 3102 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3103 <&gcc GCC_SDCC2_APPS_CLK>, 3104 <&rpmcc RPM_SMD_BB_CLK1>; 3105 resets = <&gcc GCC_SDCC2_BCR>; 3106 3107 pinctrl-names = "default", "sleep"; 3108 pinctrl-0 = <&sdc2_state_on>; 3109 pinctrl-1 = <&sdc2_state_off>; 3110 3111 bus-width = <4>; 3112 status = "disabled"; 3113 }; 3114 3115 blsp1_dma: dma-controller@7544000 { 3116 compatible = "qcom,bam-v1.7.0"; 3117 reg = <0x07544000 0x2b000>; 3118 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3119 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3120 clock-names = "bam_clk"; 3121 qcom,controlled-remotely; 3122 #dma-cells = <1>; 3123 qcom,ee = <0>; 3124 }; 3125 3126 blsp1_uart2: serial@7570000 { 3127 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3128 reg = <0x07570000 0x1000>; 3129 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3130 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3131 <&gcc GCC_BLSP1_AHB_CLK>; 3132 clock-names = "core", "iface"; 3133 pinctrl-names = "default", "sleep"; 3134 pinctrl-0 = <&blsp1_uart2_default>; 3135 pinctrl-1 = <&blsp1_uart2_sleep>; 3136 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3137 dma-names = "tx", "rx"; 3138 status = "disabled"; 3139 }; 3140 3141 blsp1_spi1: spi@7575000 { 3142 compatible = "qcom,spi-qup-v2.2.1"; 3143 reg = <0x07575000 0x600>; 3144 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3145 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3146 <&gcc GCC_BLSP1_AHB_CLK>; 3147 clock-names = "core", "iface"; 3148 pinctrl-names = "default", "sleep"; 3149 pinctrl-0 = <&blsp1_spi1_default>; 3150 pinctrl-1 = <&blsp1_spi1_sleep>; 3151 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3152 dma-names = "tx", "rx"; 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 status = "disabled"; 3156 }; 3157 3158 blsp1_i2c3: i2c@7577000 { 3159 compatible = "qcom,i2c-qup-v2.2.1"; 3160 reg = <0x07577000 0x1000>; 3161 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3162 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3163 <&gcc GCC_BLSP1_AHB_CLK>; 3164 clock-names = "core", "iface"; 3165 pinctrl-names = "default", "sleep"; 3166 pinctrl-0 = <&blsp1_i2c3_default>; 3167 pinctrl-1 = <&blsp1_i2c3_sleep>; 3168 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3169 dma-names = "tx", "rx"; 3170 #address-cells = <1>; 3171 #size-cells = <0>; 3172 status = "disabled"; 3173 }; 3174 3175 blsp1_i2c6: i2c@757a000 { 3176 compatible = "qcom,i2c-qup-v2.2.1"; 3177 reg = <0x757a000 0x1000>; 3178 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3179 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3180 <&gcc GCC_BLSP1_AHB_CLK>; 3181 clock-names = "core", "iface"; 3182 pinctrl-names = "default", "sleep"; 3183 pinctrl-0 = <&blsp1_i2c6_default>; 3184 pinctrl-1 = <&blsp1_i2c6_sleep>; 3185 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3186 dma-names = "tx", "rx"; 3187 #address-cells = <1>; 3188 #size-cells = <0>; 3189 status = "disabled"; 3190 }; 3191 3192 blsp2_dma: dma-controller@7584000 { 3193 compatible = "qcom,bam-v1.7.0"; 3194 reg = <0x07584000 0x2b000>; 3195 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3196 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3197 clock-names = "bam_clk"; 3198 qcom,controlled-remotely; 3199 #dma-cells = <1>; 3200 qcom,ee = <0>; 3201 }; 3202 3203 blsp2_uart2: serial@75b0000 { 3204 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3205 reg = <0x075b0000 0x1000>; 3206 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3207 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3208 <&gcc GCC_BLSP2_AHB_CLK>; 3209 clock-names = "core", "iface"; 3210 status = "disabled"; 3211 }; 3212 3213 blsp2_uart3: serial@75b1000 { 3214 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3215 reg = <0x075b1000 0x1000>; 3216 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3217 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3218 <&gcc GCC_BLSP2_AHB_CLK>; 3219 clock-names = "core", "iface"; 3220 status = "disabled"; 3221 }; 3222 3223 blsp2_i2c1: i2c@75b5000 { 3224 compatible = "qcom,i2c-qup-v2.2.1"; 3225 reg = <0x075b5000 0x1000>; 3226 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3227 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3228 <&gcc GCC_BLSP2_AHB_CLK>; 3229 clock-names = "core", "iface"; 3230 pinctrl-names = "default", "sleep"; 3231 pinctrl-0 = <&blsp2_i2c1_default>; 3232 pinctrl-1 = <&blsp2_i2c1_sleep>; 3233 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3234 dma-names = "tx", "rx"; 3235 #address-cells = <1>; 3236 #size-cells = <0>; 3237 status = "disabled"; 3238 }; 3239 3240 blsp2_i2c2: i2c@75b6000 { 3241 compatible = "qcom,i2c-qup-v2.2.1"; 3242 reg = <0x075b6000 0x1000>; 3243 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3244 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3245 <&gcc GCC_BLSP2_AHB_CLK>; 3246 clock-names = "core", "iface"; 3247 pinctrl-names = "default", "sleep"; 3248 pinctrl-0 = <&blsp2_i2c2_default>; 3249 pinctrl-1 = <&blsp2_i2c2_sleep>; 3250 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3251 dma-names = "tx", "rx"; 3252 #address-cells = <1>; 3253 #size-cells = <0>; 3254 status = "disabled"; 3255 }; 3256 3257 blsp2_i2c3: i2c@75b7000 { 3258 compatible = "qcom,i2c-qup-v2.2.1"; 3259 reg = <0x075b7000 0x1000>; 3260 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3261 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3262 <&gcc GCC_BLSP2_AHB_CLK>; 3263 clock-names = "core", "iface"; 3264 clock-frequency = <400000>; 3265 pinctrl-names = "default", "sleep"; 3266 pinctrl-0 = <&blsp2_i2c3_default>; 3267 pinctrl-1 = <&blsp2_i2c3_sleep>; 3268 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3269 dma-names = "tx", "rx"; 3270 #address-cells = <1>; 3271 #size-cells = <0>; 3272 status = "disabled"; 3273 }; 3274 3275 blsp2_i2c5: i2c@75b9000 { 3276 compatible = "qcom,i2c-qup-v2.2.1"; 3277 reg = <0x75b9000 0x1000>; 3278 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3279 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3280 <&gcc GCC_BLSP2_AHB_CLK>; 3281 clock-names = "core", "iface"; 3282 pinctrl-names = "default"; 3283 pinctrl-0 = <&blsp2_i2c5_default>; 3284 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3285 dma-names = "tx", "rx"; 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 status = "disabled"; 3289 }; 3290 3291 blsp2_i2c6: i2c@75ba000 { 3292 compatible = "qcom,i2c-qup-v2.2.1"; 3293 reg = <0x75ba000 0x1000>; 3294 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3295 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3296 <&gcc GCC_BLSP2_AHB_CLK>; 3297 clock-names = "core", "iface"; 3298 pinctrl-names = "default", "sleep"; 3299 pinctrl-0 = <&blsp2_i2c6_default>; 3300 pinctrl-1 = <&blsp2_i2c6_sleep>; 3301 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3302 dma-names = "tx", "rx"; 3303 #address-cells = <1>; 3304 #size-cells = <0>; 3305 status = "disabled"; 3306 }; 3307 3308 blsp2_spi6: spi@75ba000 { 3309 compatible = "qcom,spi-qup-v2.2.1"; 3310 reg = <0x075ba000 0x600>; 3311 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3312 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3313 <&gcc GCC_BLSP2_AHB_CLK>; 3314 clock-names = "core", "iface"; 3315 pinctrl-names = "default", "sleep"; 3316 pinctrl-0 = <&blsp2_spi6_default>; 3317 pinctrl-1 = <&blsp2_spi6_sleep>; 3318 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3319 dma-names = "tx", "rx"; 3320 #address-cells = <1>; 3321 #size-cells = <0>; 3322 status = "disabled"; 3323 }; 3324 3325 usb2: usb@76f8800 { 3326 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3327 reg = <0x076f8800 0x400>; 3328 #address-cells = <1>; 3329 #size-cells = <1>; 3330 ranges; 3331 3332 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3333 <&gcc GCC_USB20_MASTER_CLK>, 3334 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3335 <&gcc GCC_USB20_SLEEP_CLK>, 3336 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3337 clock-names = "cfg_noc", 3338 "core", 3339 "iface", 3340 "sleep", 3341 "mock_utmi"; 3342 3343 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3344 <&gcc GCC_USB20_MASTER_CLK>; 3345 assigned-clock-rates = <19200000>, <60000000>; 3346 3347 power-domains = <&gcc USB30_GDSC>; 3348 qcom,select-utmi-as-pipe-clk; 3349 status = "disabled"; 3350 3351 usb2_dwc3: usb@7600000 { 3352 compatible = "snps,dwc3"; 3353 reg = <0x07600000 0xcc00>; 3354 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3355 phys = <&hsusb_phy2>; 3356 phy-names = "usb2-phy"; 3357 maximum-speed = "high-speed"; 3358 snps,dis_u2_susphy_quirk; 3359 snps,dis_enblslpm_quirk; 3360 }; 3361 }; 3362 3363 slimbam: dma-controller@9184000 { 3364 compatible = "qcom,bam-v1.7.0"; 3365 qcom,controlled-remotely; 3366 reg = <0x09184000 0x32000>; 3367 num-channels = <31>; 3368 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3369 #dma-cells = <1>; 3370 qcom,ee = <1>; 3371 qcom,num-ees = <2>; 3372 }; 3373 3374 slim_msm: slim-ngd@91c0000 { 3375 compatible = "qcom,slim-ngd-v1.5.0"; 3376 reg = <0x091c0000 0x2c000>; 3377 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3378 dmas = <&slimbam 3>, <&slimbam 4>; 3379 dma-names = "rx", "tx"; 3380 #address-cells = <1>; 3381 #size-cells = <0>; 3382 slim@1 { 3383 reg = <1>; 3384 #address-cells = <2>; 3385 #size-cells = <0>; 3386 3387 tasha_ifd: tas-ifd@0,0 { 3388 compatible = "slim217,1a0"; 3389 reg = <0 0>; 3390 }; 3391 3392 wcd9335: codec@1,0 { 3393 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3394 pinctrl-names = "default"; 3395 3396 compatible = "slim217,1a0"; 3397 reg = <1 0>; 3398 3399 interrupt-parent = <&tlmm>; 3400 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3401 <53 IRQ_TYPE_LEVEL_HIGH>; 3402 interrupt-names = "intr1", "intr2"; 3403 interrupt-controller; 3404 #interrupt-cells = <1>; 3405 reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 3406 3407 slim-ifc-dev = <&tasha_ifd>; 3408 3409 #sound-dai-cells = <1>; 3410 }; 3411 }; 3412 }; 3413 3414 adsp_pil: remoteproc@9300000 { 3415 compatible = "qcom,msm8996-adsp-pil"; 3416 reg = <0x09300000 0x80000>; 3417 3418 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3419 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3420 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3421 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3422 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3423 interrupt-names = "wdog", "fatal", "ready", 3424 "handover", "stop-ack"; 3425 3426 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3427 clock-names = "xo"; 3428 3429 memory-region = <&adsp_mem>; 3430 3431 qcom,smem-states = <&adsp_smp2p_out 0>; 3432 qcom,smem-state-names = "stop"; 3433 3434 power-domains = <&rpmpd MSM8996_VDDCX>; 3435 power-domain-names = "cx"; 3436 3437 status = "disabled"; 3438 3439 smd-edge { 3440 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3441 3442 label = "lpass"; 3443 mboxes = <&apcs_glb 8>; 3444 qcom,smd-edge = <1>; 3445 qcom,remote-pid = <2>; 3446 3447 apr { 3448 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3449 compatible = "qcom,apr-v2"; 3450 qcom,smd-channels = "apr_audio_svc"; 3451 qcom,domain = <APR_DOMAIN_ADSP>; 3452 #address-cells = <1>; 3453 #size-cells = <0>; 3454 3455 service@3 { 3456 reg = <APR_SVC_ADSP_CORE>; 3457 compatible = "qcom,q6core"; 3458 }; 3459 3460 q6afe: service@4 { 3461 compatible = "qcom,q6afe"; 3462 reg = <APR_SVC_AFE>; 3463 q6afedai: dais { 3464 compatible = "qcom,q6afe-dais"; 3465 #address-cells = <1>; 3466 #size-cells = <0>; 3467 #sound-dai-cells = <1>; 3468 dai@1 { 3469 reg = <1>; 3470 }; 3471 }; 3472 }; 3473 3474 q6asm: service@7 { 3475 compatible = "qcom,q6asm"; 3476 reg = <APR_SVC_ASM>; 3477 q6asmdai: dais { 3478 compatible = "qcom,q6asm-dais"; 3479 #address-cells = <1>; 3480 #size-cells = <0>; 3481 #sound-dai-cells = <1>; 3482 iommus = <&lpass_q6_smmu 1>; 3483 }; 3484 }; 3485 3486 q6adm: service@8 { 3487 compatible = "qcom,q6adm"; 3488 reg = <APR_SVC_ADM>; 3489 q6routing: routing { 3490 compatible = "qcom,q6adm-routing"; 3491 #sound-dai-cells = <0>; 3492 }; 3493 }; 3494 }; 3495 3496 }; 3497 }; 3498 3499 apcs_glb: mailbox@9820000 { 3500 compatible = "qcom,msm8996-apcs-hmss-global"; 3501 reg = <0x09820000 0x1000>; 3502 3503 #mbox-cells = <1>; 3504 #clock-cells = <0>; 3505 }; 3506 3507 timer@9840000 { 3508 #address-cells = <1>; 3509 #size-cells = <1>; 3510 ranges; 3511 compatible = "arm,armv7-timer-mem"; 3512 reg = <0x09840000 0x1000>; 3513 clock-frequency = <19200000>; 3514 3515 frame@9850000 { 3516 frame-number = <0>; 3517 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3519 reg = <0x09850000 0x1000>, 3520 <0x09860000 0x1000>; 3521 }; 3522 3523 frame@9870000 { 3524 frame-number = <1>; 3525 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3526 reg = <0x09870000 0x1000>; 3527 status = "disabled"; 3528 }; 3529 3530 frame@9880000 { 3531 frame-number = <2>; 3532 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3533 reg = <0x09880000 0x1000>; 3534 status = "disabled"; 3535 }; 3536 3537 frame@9890000 { 3538 frame-number = <3>; 3539 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3540 reg = <0x09890000 0x1000>; 3541 status = "disabled"; 3542 }; 3543 3544 frame@98a0000 { 3545 frame-number = <4>; 3546 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3547 reg = <0x098a0000 0x1000>; 3548 status = "disabled"; 3549 }; 3550 3551 frame@98b0000 { 3552 frame-number = <5>; 3553 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3554 reg = <0x098b0000 0x1000>; 3555 status = "disabled"; 3556 }; 3557 3558 frame@98c0000 { 3559 frame-number = <6>; 3560 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3561 reg = <0x098c0000 0x1000>; 3562 status = "disabled"; 3563 }; 3564 }; 3565 3566 saw3: syscon@9a10000 { 3567 compatible = "syscon"; 3568 reg = <0x09a10000 0x1000>; 3569 }; 3570 3571 intc: interrupt-controller@9bc0000 { 3572 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3573 #interrupt-cells = <3>; 3574 interrupt-controller; 3575 #redistributor-regions = <1>; 3576 redistributor-stride = <0x0 0x40000>; 3577 reg = <0x09bc0000 0x10000>, 3578 <0x09c00000 0x100000>; 3579 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3580 }; 3581 }; 3582 3583 sound: sound { 3584 }; 3585 3586 thermal-zones { 3587 cpu0-thermal { 3588 polling-delay-passive = <250>; 3589 polling-delay = <1000>; 3590 3591 thermal-sensors = <&tsens0 3>; 3592 3593 trips { 3594 cpu0_alert0: trip-point0 { 3595 temperature = <75000>; 3596 hysteresis = <2000>; 3597 type = "passive"; 3598 }; 3599 3600 cpu0_crit: cpu-crit { 3601 temperature = <110000>; 3602 hysteresis = <2000>; 3603 type = "critical"; 3604 }; 3605 }; 3606 }; 3607 3608 cpu1-thermal { 3609 polling-delay-passive = <250>; 3610 polling-delay = <1000>; 3611 3612 thermal-sensors = <&tsens0 5>; 3613 3614 trips { 3615 cpu1_alert0: trip-point0 { 3616 temperature = <75000>; 3617 hysteresis = <2000>; 3618 type = "passive"; 3619 }; 3620 3621 cpu1_crit: cpu-crit { 3622 temperature = <110000>; 3623 hysteresis = <2000>; 3624 type = "critical"; 3625 }; 3626 }; 3627 }; 3628 3629 cpu2-thermal { 3630 polling-delay-passive = <250>; 3631 polling-delay = <1000>; 3632 3633 thermal-sensors = <&tsens0 8>; 3634 3635 trips { 3636 cpu2_alert0: trip-point0 { 3637 temperature = <75000>; 3638 hysteresis = <2000>; 3639 type = "passive"; 3640 }; 3641 3642 cpu2_crit: cpu-crit { 3643 temperature = <110000>; 3644 hysteresis = <2000>; 3645 type = "critical"; 3646 }; 3647 }; 3648 }; 3649 3650 cpu3-thermal { 3651 polling-delay-passive = <250>; 3652 polling-delay = <1000>; 3653 3654 thermal-sensors = <&tsens0 10>; 3655 3656 trips { 3657 cpu3_alert0: trip-point0 { 3658 temperature = <75000>; 3659 hysteresis = <2000>; 3660 type = "passive"; 3661 }; 3662 3663 cpu3_crit: cpu-crit { 3664 temperature = <110000>; 3665 hysteresis = <2000>; 3666 type = "critical"; 3667 }; 3668 }; 3669 }; 3670 3671 gpu-top-thermal { 3672 polling-delay-passive = <250>; 3673 polling-delay = <1000>; 3674 3675 thermal-sensors = <&tsens1 6>; 3676 3677 trips { 3678 gpu1_alert0: trip-point0 { 3679 temperature = <90000>; 3680 hysteresis = <2000>; 3681 type = "passive"; 3682 }; 3683 }; 3684 3685 cooling-maps { 3686 map0 { 3687 trip = <&gpu1_alert0>; 3688 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3689 }; 3690 }; 3691 }; 3692 3693 gpu-bottom-thermal { 3694 polling-delay-passive = <250>; 3695 polling-delay = <1000>; 3696 3697 thermal-sensors = <&tsens1 7>; 3698 3699 trips { 3700 gpu2_alert0: trip-point0 { 3701 temperature = <90000>; 3702 hysteresis = <2000>; 3703 type = "passive"; 3704 }; 3705 }; 3706 3707 cooling-maps { 3708 map0 { 3709 trip = <&gpu2_alert0>; 3710 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3711 }; 3712 }; 3713 }; 3714 3715 m4m-thermal { 3716 polling-delay-passive = <250>; 3717 polling-delay = <1000>; 3718 3719 thermal-sensors = <&tsens0 1>; 3720 3721 trips { 3722 m4m_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "hot"; 3726 }; 3727 }; 3728 }; 3729 3730 l3-or-venus-thermal { 3731 polling-delay-passive = <250>; 3732 polling-delay = <1000>; 3733 3734 thermal-sensors = <&tsens0 2>; 3735 3736 trips { 3737 l3_or_venus_alert0: trip-point0 { 3738 temperature = <90000>; 3739 hysteresis = <2000>; 3740 type = "hot"; 3741 }; 3742 }; 3743 }; 3744 3745 cluster0-l2-thermal { 3746 polling-delay-passive = <250>; 3747 polling-delay = <1000>; 3748 3749 thermal-sensors = <&tsens0 7>; 3750 3751 trips { 3752 cluster0_l2_alert0: trip-point0 { 3753 temperature = <90000>; 3754 hysteresis = <2000>; 3755 type = "hot"; 3756 }; 3757 }; 3758 }; 3759 3760 cluster1-l2-thermal { 3761 polling-delay-passive = <250>; 3762 polling-delay = <1000>; 3763 3764 thermal-sensors = <&tsens0 12>; 3765 3766 trips { 3767 cluster1_l2_alert0: trip-point0 { 3768 temperature = <90000>; 3769 hysteresis = <2000>; 3770 type = "hot"; 3771 }; 3772 }; 3773 }; 3774 3775 camera-thermal { 3776 polling-delay-passive = <250>; 3777 polling-delay = <1000>; 3778 3779 thermal-sensors = <&tsens1 1>; 3780 3781 trips { 3782 camera_alert0: trip-point0 { 3783 temperature = <90000>; 3784 hysteresis = <2000>; 3785 type = "hot"; 3786 }; 3787 }; 3788 }; 3789 3790 q6-dsp-thermal { 3791 polling-delay-passive = <250>; 3792 polling-delay = <1000>; 3793 3794 thermal-sensors = <&tsens1 2>; 3795 3796 trips { 3797 q6_dsp_alert0: trip-point0 { 3798 temperature = <90000>; 3799 hysteresis = <2000>; 3800 type = "hot"; 3801 }; 3802 }; 3803 }; 3804 3805 mem-thermal { 3806 polling-delay-passive = <250>; 3807 polling-delay = <1000>; 3808 3809 thermal-sensors = <&tsens1 3>; 3810 3811 trips { 3812 mem_alert0: trip-point0 { 3813 temperature = <90000>; 3814 hysteresis = <2000>; 3815 type = "hot"; 3816 }; 3817 }; 3818 }; 3819 3820 modemtx-thermal { 3821 polling-delay-passive = <250>; 3822 polling-delay = <1000>; 3823 3824 thermal-sensors = <&tsens1 4>; 3825 3826 trips { 3827 modemtx_alert0: trip-point0 { 3828 temperature = <90000>; 3829 hysteresis = <2000>; 3830 type = "hot"; 3831 }; 3832 }; 3833 }; 3834 }; 3835 3836 timer { 3837 compatible = "arm,armv8-timer"; 3838 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3839 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3840 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3841 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3842 }; 3843}; 3844