xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision 48cc39c3) 
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x77>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x77>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x77>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x77>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x77>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x77>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x77>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x77>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x77>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x77>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x77>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x77>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x77>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1401600000 {
209			opp-hz = /bits/ 64 <1401600000>;
210			opp-supported-hw = <0x77>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1478400000 {
214			opp-hz = /bits/ 64 <1478400000>;
215			opp-supported-hw = <0x77>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1593600000 {
219			opp-hz = /bits/ 64 <1593600000>;
220			opp-supported-hw = <0x77>;
221			clock-latency-ns = <200000>;
222		};
223	};
224
225	cluster1_opp: opp_table1 {
226		compatible = "operating-points-v2-kryo-cpu";
227		nvmem-cells = <&speedbin_efuse>;
228		opp-shared;
229
230		/* Nominal fmax for now */
231		opp-307200000 {
232			opp-hz = /bits/ 64 <307200000>;
233			opp-supported-hw = <0x77>;
234			clock-latency-ns = <200000>;
235		};
236		opp-403200000 {
237			opp-hz = /bits/ 64 <403200000>;
238			opp-supported-hw = <0x77>;
239			clock-latency-ns = <200000>;
240		};
241		opp-480000000 {
242			opp-hz = /bits/ 64 <480000000>;
243			opp-supported-hw = <0x77>;
244			clock-latency-ns = <200000>;
245		};
246		opp-556800000 {
247			opp-hz = /bits/ 64 <556800000>;
248			opp-supported-hw = <0x77>;
249			clock-latency-ns = <200000>;
250		};
251		opp-652800000 {
252			opp-hz = /bits/ 64 <652800000>;
253			opp-supported-hw = <0x77>;
254			clock-latency-ns = <200000>;
255		};
256		opp-729600000 {
257			opp-hz = /bits/ 64 <729600000>;
258			opp-supported-hw = <0x77>;
259			clock-latency-ns = <200000>;
260		};
261		opp-806400000 {
262			opp-hz = /bits/ 64 <806400000>;
263			opp-supported-hw = <0x77>;
264			clock-latency-ns = <200000>;
265		};
266		opp-883200000 {
267			opp-hz = /bits/ 64 <883200000>;
268			opp-supported-hw = <0x77>;
269			clock-latency-ns = <200000>;
270		};
271		opp-940800000 {
272			opp-hz = /bits/ 64 <940800000>;
273			opp-supported-hw = <0x77>;
274			clock-latency-ns = <200000>;
275		};
276		opp-1036800000 {
277			opp-hz = /bits/ 64 <1036800000>;
278			opp-supported-hw = <0x77>;
279			clock-latency-ns = <200000>;
280		};
281		opp-1113600000 {
282			opp-hz = /bits/ 64 <1113600000>;
283			opp-supported-hw = <0x77>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1190400000 {
287			opp-hz = /bits/ 64 <1190400000>;
288			opp-supported-hw = <0x77>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1248000000 {
292			opp-hz = /bits/ 64 <1248000000>;
293			opp-supported-hw = <0x77>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1324800000 {
297			opp-hz = /bits/ 64 <1324800000>;
298			opp-supported-hw = <0x77>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1401600000 {
302			opp-hz = /bits/ 64 <1401600000>;
303			opp-supported-hw = <0x77>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1478400000 {
307			opp-hz = /bits/ 64 <1478400000>;
308			opp-supported-hw = <0x77>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1555200000 {
312			opp-hz = /bits/ 64 <1555200000>;
313			opp-supported-hw = <0x77>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1632000000 {
317			opp-hz = /bits/ 64 <1632000000>;
318			opp-supported-hw = <0x77>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1708800000 {
322			opp-hz = /bits/ 64 <1708800000>;
323			opp-supported-hw = <0x77>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1785600000 {
327			opp-hz = /bits/ 64 <1785600000>;
328			opp-supported-hw = <0x77>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1824000000 {
332			opp-hz = /bits/ 64 <1824000000>;
333			opp-supported-hw = <0x77>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1920000000 {
337			opp-hz = /bits/ 64 <1920000000>;
338			opp-supported-hw = <0x77>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1996800000 {
342			opp-hz = /bits/ 64 <1996800000>;
343			opp-supported-hw = <0x77>;
344			clock-latency-ns = <200000>;
345		};
346		opp-2073600000 {
347			opp-hz = /bits/ 64 <2073600000>;
348			opp-supported-hw = <0x77>;
349			clock-latency-ns = <200000>;
350		};
351		opp-2150400000 {
352			opp-hz = /bits/ 64 <2150400000>;
353			opp-supported-hw = <0x77>;
354			clock-latency-ns = <200000>;
355		};
356	};
357
358	firmware {
359		scm {
360			compatible = "qcom,scm-msm8996";
361			qcom,dload-mode = <&tcsr 0x13000>;
362		};
363	};
364
365	tcsr_mutex: hwlock {
366		compatible = "qcom,tcsr-mutex";
367		syscon = <&tcsr_mutex_regs 0 0x1000>;
368		#hwlock-cells = <1>;
369	};
370
371	memory@80000000 {
372		device_type = "memory";
373		/* We expect the bootloader to fill in the reg */
374		reg = <0x0 0x80000000 0x0 0x0>;
375	};
376
377	psci {
378		compatible = "arm,psci-1.0";
379		method = "smc";
380	};
381
382	reserved-memory {
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges;
386
387		mba_region: mba@91500000 {
388			reg = <0x0 0x91500000 0x0 0x200000>;
389			no-map;
390		};
391
392		slpi_region: slpi@90b00000 {
393			reg = <0x0 0x90b00000 0x0 0xa00000>;
394			no-map;
395		};
396
397		venus_region: venus@90400000 {
398			reg = <0x0 0x90400000 0x0 0x700000>;
399			no-map;
400		};
401
402		adsp_region: adsp@8ea00000 {
403			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
404			no-map;
405		};
406
407		mpss_region: mpss@88800000 {
408			reg = <0x0 0x88800000 0x0 0x6200000>;
409			no-map;
410		};
411
412		smem_mem: smem-mem@86000000 {
413			reg = <0x0 0x86000000 0x0 0x200000>;
414			no-map;
415		};
416
417		memory@85800000 {
418			reg = <0x0 0x85800000 0x0 0x800000>;
419			no-map;
420		};
421
422		memory@86200000 {
423			reg = <0x0 0x86200000 0x0 0x2600000>;
424			no-map;
425		};
426
427		rmtfs@86700000 {
428			compatible = "qcom,rmtfs-mem";
429
430			size = <0x0 0x200000>;
431			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432			no-map;
433
434			qcom,client-id = <1>;
435			qcom,vmid = <15>;
436		};
437
438		zap_shader_region: gpu@8f200000 {
439			compatible = "shared-dma-pool";
440			reg = <0x0 0x90b00000 0x0 0xa00000>;
441			no-map;
442		};
443	};
444
445	rpm-glink {
446		compatible = "qcom,glink-rpm";
447
448		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
449
450		qcom,rpm-msg-ram = <&rpm_msg_ram>;
451
452		mboxes = <&apcs_glb 0>;
453
454		rpm_requests: rpm-requests {
455			compatible = "qcom,rpm-msm8996";
456			qcom,glink-channels = "rpm_requests";
457
458			rpmcc: qcom,rpmcc {
459				compatible = "qcom,rpmcc-msm8996";
460				#clock-cells = <1>;
461			};
462
463			rpmpd: power-controller {
464				compatible = "qcom,msm8996-rpmpd";
465				#power-domain-cells = <1>;
466				operating-points-v2 = <&rpmpd_opp_table>;
467
468				rpmpd_opp_table: opp-table {
469					compatible = "operating-points-v2";
470
471					rpmpd_opp1: opp1 {
472						opp-level = <1>;
473					};
474
475					rpmpd_opp2: opp2 {
476						opp-level = <2>;
477					};
478
479					rpmpd_opp3: opp3 {
480						opp-level = <3>;
481					};
482
483					rpmpd_opp4: opp4 {
484						opp-level = <4>;
485					};
486
487					rpmpd_opp5: opp5 {
488						opp-level = <5>;
489					};
490
491					rpmpd_opp6: opp6 {
492						opp-level = <6>;
493					};
494				};
495			};
496		};
497	};
498
499	smem {
500		compatible = "qcom,smem";
501		memory-region = <&smem_mem>;
502		hwlocks = <&tcsr_mutex 3>;
503	};
504
505	smp2p-adsp {
506		compatible = "qcom,smp2p";
507		qcom,smem = <443>, <429>;
508
509		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
510
511		mboxes = <&apcs_glb 10>;
512
513		qcom,local-pid = <0>;
514		qcom,remote-pid = <2>;
515
516		smp2p_adsp_out: master-kernel {
517			qcom,entry-name = "master-kernel";
518			#qcom,smem-state-cells = <1>;
519		};
520
521		smp2p_adsp_in: slave-kernel {
522			qcom,entry-name = "slave-kernel";
523
524			interrupt-controller;
525			#interrupt-cells = <2>;
526		};
527	};
528
529	smp2p-modem {
530		compatible = "qcom,smp2p";
531		qcom,smem = <435>, <428>;
532
533		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
534
535		mboxes = <&apcs_glb 14>;
536
537		qcom,local-pid = <0>;
538		qcom,remote-pid = <1>;
539
540		modem_smp2p_out: master-kernel {
541			qcom,entry-name = "master-kernel";
542			#qcom,smem-state-cells = <1>;
543		};
544
545		modem_smp2p_in: slave-kernel {
546			qcom,entry-name = "slave-kernel";
547
548			interrupt-controller;
549			#interrupt-cells = <2>;
550		};
551	};
552
553	smp2p-slpi {
554		compatible = "qcom,smp2p";
555		qcom,smem = <481>, <430>;
556
557		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
558
559		mboxes = <&apcs_glb 26>;
560
561		qcom,local-pid = <0>;
562		qcom,remote-pid = <3>;
563
564		smp2p_slpi_in: slave-kernel {
565			qcom,entry-name = "slave-kernel";
566			interrupt-controller;
567			#interrupt-cells = <2>;
568		};
569
570		smp2p_slpi_out: master-kernel {
571			qcom,entry-name = "master-kernel";
572			#qcom,smem-state-cells = <1>;
573		};
574	};
575
576	soc: soc {
577		#address-cells = <1>;
578		#size-cells = <1>;
579		ranges = <0 0 0 0xffffffff>;
580		compatible = "simple-bus";
581
582		pcie_phy: phy@34000 {
583			compatible = "qcom,msm8996-qmp-pcie-phy";
584			reg = <0x00034000 0x488>;
585			#clock-cells = <1>;
586			#address-cells = <1>;
587			#size-cells = <1>;
588			ranges;
589
590			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592				<&gcc GCC_PCIE_CLKREF_CLK>;
593			clock-names = "aux", "cfg_ahb", "ref";
594
595			resets = <&gcc GCC_PCIE_PHY_BCR>,
596				<&gcc GCC_PCIE_PHY_COM_BCR>,
597				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
598			reset-names = "phy", "common", "cfg";
599			status = "disabled";
600
601			pciephy_0: lane@35000 {
602				reg = <0x00035000 0x130>,
603				      <0x00035200 0x200>,
604				      <0x00035400 0x1dc>;
605				#phy-cells = <0>;
606
607				clock-output-names = "pcie_0_pipe_clk_src";
608				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609				clock-names = "pipe0";
610				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611				reset-names = "lane0";
612			};
613
614			pciephy_1: lane@36000 {
615				reg = <0x00036000 0x130>,
616				      <0x00036200 0x200>,
617				      <0x00036400 0x1dc>;
618				#phy-cells = <0>;
619
620				clock-output-names = "pcie_1_pipe_clk_src";
621				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622				clock-names = "pipe1";
623				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624				reset-names = "lane1";
625			};
626
627			pciephy_2: lane@37000 {
628				reg = <0x00037000 0x130>,
629				      <0x00037200 0x200>,
630				      <0x00037400 0x1dc>;
631				#phy-cells = <0>;
632
633				clock-output-names = "pcie_2_pipe_clk_src";
634				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635				clock-names = "pipe2";
636				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637				reset-names = "lane2";
638			};
639		};
640
641		rpm_msg_ram: memory@68000 {
642			compatible = "qcom,rpm-msg-ram";
643			reg = <0x00068000 0x6000>;
644		};
645
646		qfprom@74000 {
647			compatible = "qcom,qfprom";
648			reg = <0x00074000 0x8ff>;
649			#address-cells = <1>;
650			#size-cells = <1>;
651
652			qusb2p_hstx_trim: hstx_trim@24e {
653				reg = <0x24e 0x2>;
654				bits = <5 4>;
655			};
656
657			qusb2s_hstx_trim: hstx_trim@24f {
658				reg = <0x24f 0x1>;
659				bits = <1 4>;
660			};
661
662			speedbin_efuse: speedbin@133 {
663				reg = <0x133 0x1>;
664				bits = <5 3>;
665			};
666		};
667
668		rng: rng@83000 {
669			compatible = "qcom,prng-ee";
670			reg = <0x00083000 0x1000>;
671			clocks = <&gcc GCC_PRNG_AHB_CLK>;
672			clock-names = "core";
673		};
674
675		gcc: clock-controller@300000 {
676			compatible = "qcom,gcc-msm8996";
677			#clock-cells = <1>;
678			#reset-cells = <1>;
679			#power-domain-cells = <1>;
680			reg = <0x00300000 0x90000>;
681
682			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683			clock-names = "cxo2";
684		};
685
686		tsens0: thermal-sensor@4a9000 {
687			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688			reg = <0x004a9000 0x1000>, /* TM */
689			      <0x004a8000 0x1000>; /* SROT */
690			#qcom,sensors = <13>;
691			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693			interrupt-names = "uplow", "critical";
694			#thermal-sensor-cells = <1>;
695		};
696
697		tsens1: thermal-sensor@4ad000 {
698			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699			reg = <0x004ad000 0x1000>, /* TM */
700			      <0x004ac000 0x1000>; /* SROT */
701			#qcom,sensors = <8>;
702			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "uplow", "critical";
705			#thermal-sensor-cells = <1>;
706		};
707
708		tcsr_mutex_regs: syscon@740000 {
709			compatible = "syscon";
710			reg = <0x00740000 0x40000>;
711		};
712
713		tcsr: syscon@7a0000 {
714			compatible = "qcom,tcsr-msm8996", "syscon";
715			reg = <0x007a0000 0x18000>;
716		};
717
718		mmcc: clock-controller@8c0000 {
719			compatible = "qcom,mmcc-msm8996";
720			#clock-cells = <1>;
721			#reset-cells = <1>;
722			#power-domain-cells = <1>;
723			reg = <0x008c0000 0x40000>;
724			assigned-clocks = <&mmcc MMPLL9_PLL>,
725					  <&mmcc MMPLL1_PLL>,
726					  <&mmcc MMPLL3_PLL>,
727					  <&mmcc MMPLL4_PLL>,
728					  <&mmcc MMPLL5_PLL>;
729			assigned-clock-rates = <624000000>,
730					       <810000000>,
731					       <980000000>,
732					       <960000000>,
733					       <825000000>;
734		};
735
736		mdss: mdss@900000 {
737			compatible = "qcom,mdss";
738
739			reg = <0x00900000 0x1000>,
740			      <0x009b0000 0x1040>,
741			      <0x009b8000 0x1040>;
742			reg-names = "mdss_phys",
743				    "vbif_phys",
744				    "vbif_nrt_phys";
745
746			power-domains = <&mmcc MDSS_GDSC>;
747			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
748
749			interrupt-controller;
750			#interrupt-cells = <1>;
751
752			clocks = <&mmcc MDSS_AHB_CLK>;
753			clock-names = "iface";
754
755			#address-cells = <1>;
756			#size-cells = <1>;
757			ranges;
758
759			status = "disabled";
760
761			mdp: mdp@901000 {
762				compatible = "qcom,mdp5";
763				reg = <0x00901000 0x90000>;
764				reg-names = "mdp_phys";
765
766				interrupt-parent = <&mdss>;
767				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
768
769				clocks = <&mmcc MDSS_AHB_CLK>,
770					 <&mmcc MDSS_AXI_CLK>,
771					 <&mmcc MDSS_MDP_CLK>,
772					 <&mmcc SMMU_MDP_AXI_CLK>,
773					 <&mmcc MDSS_VSYNC_CLK>;
774				clock-names = "iface",
775					      "bus",
776					      "core",
777					      "iommu",
778					      "vsync";
779
780				iommus = <&mdp_smmu 0>;
781
782				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
783					 <&mmcc MDSS_VSYNC_CLK>;
784				assigned-clock-rates = <300000000>,
785					 <19200000>;
786
787				ports {
788					#address-cells = <1>;
789					#size-cells = <0>;
790
791					port@0 {
792						reg = <0>;
793						mdp5_intf3_out: endpoint {
794							remote-endpoint = <&hdmi_in>;
795						};
796					};
797
798					port@1 {
799						reg = <1>;
800						mdp5_intf1_out: endpoint {
801							remote-endpoint = <&dsi0_in>;
802						};
803					};
804				};
805			};
806
807			dsi0: dsi@994000 {
808				compatible = "qcom,mdss-dsi-ctrl";
809				reg = <0x00994000 0x400>;
810				reg-names = "dsi_ctrl";
811
812				interrupt-parent = <&mdss>;
813				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
814
815				clocks = <&mmcc MDSS_MDP_CLK>,
816					 <&mmcc MDSS_BYTE0_CLK>,
817					 <&mmcc MDSS_AHB_CLK>,
818					 <&mmcc MDSS_AXI_CLK>,
819					 <&mmcc MMSS_MISC_AHB_CLK>,
820					 <&mmcc MDSS_PCLK0_CLK>,
821					 <&mmcc MDSS_ESC0_CLK>;
822				clock-names = "mdp_core",
823					      "byte",
824					      "iface",
825					      "bus",
826					      "core_mmss",
827					      "pixel",
828					      "core";
829
830				phys = <&dsi0_phy>;
831				phy-names = "dsi";
832				status = "disabled";
833
834				#address-cells = <1>;
835				#size-cells = <0>;
836
837				ports {
838					#address-cells = <1>;
839					#size-cells = <0>;
840
841					port@0 {
842						reg = <0>;
843						dsi0_in: endpoint {
844							remote-endpoint = <&mdp5_intf1_out>;
845						};
846					};
847
848					port@1 {
849						reg = <1>;
850						dsi0_out: endpoint {
851						};
852					};
853				};
854			};
855
856			dsi0_phy: dsi-phy@994400 {
857				compatible = "qcom,dsi-phy-14nm";
858				reg = <0x00994400 0x100>,
859				      <0x00994500 0x300>,
860				      <0x00994800 0x188>;
861				reg-names = "dsi_phy",
862					    "dsi_phy_lane",
863					    "dsi_pll";
864
865				#clock-cells = <1>;
866				#phy-cells = <0>;
867
868				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
869				clock-names = "iface", "ref";
870				status = "disabled";
871			};
872
873			hdmi: hdmi-tx@9a0000 {
874				compatible = "qcom,hdmi-tx-8996";
875				reg =	<0x009a0000 0x50c>,
876					<0x00070000 0x6158>,
877					<0x009e0000 0xfff>;
878				reg-names = "core_physical",
879					    "qfprom_physical",
880					    "hdcp_physical";
881
882				interrupt-parent = <&mdss>;
883				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
884
885				clocks = <&mmcc MDSS_MDP_CLK>,
886					 <&mmcc MDSS_AHB_CLK>,
887					 <&mmcc MDSS_HDMI_CLK>,
888					 <&mmcc MDSS_HDMI_AHB_CLK>,
889					 <&mmcc MDSS_EXTPCLK_CLK>;
890				clock-names =
891					"mdp_core",
892					"iface",
893					"core",
894					"alt_iface",
895					"extp";
896
897				phys = <&hdmi_phy>;
898				phy-names = "hdmi_phy";
899				#sound-dai-cells = <1>;
900
901				status = "disabled";
902
903				ports {
904					#address-cells = <1>;
905					#size-cells = <0>;
906
907					port@0 {
908						reg = <0>;
909						hdmi_in: endpoint {
910							remote-endpoint = <&mdp5_intf3_out>;
911						};
912					};
913				};
914			};
915
916			hdmi_phy: hdmi-phy@9a0600 {
917				#phy-cells = <0>;
918				compatible = "qcom,hdmi-phy-8996";
919				reg = <0x009a0600 0x1c4>,
920				      <0x009a0a00 0x124>,
921				      <0x009a0c00 0x124>,
922				      <0x009a0e00 0x124>,
923				      <0x009a1000 0x124>,
924				      <0x009a1200 0x0c8>;
925				reg-names = "hdmi_pll",
926					    "hdmi_tx_l0",
927					    "hdmi_tx_l1",
928					    "hdmi_tx_l2",
929					    "hdmi_tx_l3",
930					    "hdmi_phy";
931
932				clocks = <&mmcc MDSS_AHB_CLK>,
933					 <&gcc GCC_HDMI_CLKREF_CLK>;
934				clock-names = "iface",
935					      "ref";
936
937				status = "disabled";
938			};
939		};
940
941		gpu: gpu@b00000 {
942			compatible = "qcom,adreno-530.2", "qcom,adreno";
943			#stream-id-cells = <16>;
944
945			reg = <0x00b00000 0x3f000>;
946			reg-names = "kgsl_3d0_reg_memory";
947
948			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
949
950			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
951				<&mmcc GPU_AHB_CLK>,
952				<&mmcc GPU_GX_RBBMTIMER_CLK>,
953				<&gcc GCC_BIMC_GFX_CLK>,
954				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
955
956			clock-names = "core",
957				"iface",
958				"rbbmtimer",
959				"mem",
960				"mem_iface";
961
962			power-domains = <&mmcc GPU_GX_GDSC>;
963			iommus = <&adreno_smmu 0>;
964
965			nvmem-cells = <&speedbin_efuse>;
966			nvmem-cell-names = "speed_bin";
967
968			qcom,gpu-quirk-two-pass-use-wfi;
969			qcom,gpu-quirk-fault-detect-mask;
970
971			operating-points-v2 = <&gpu_opp_table>;
972
973			status = "disabled";
974
975			#cooling-cells = <2>;
976
977			gpu_opp_table: opp-table {
978				compatible  ="operating-points-v2";
979
980				/*
981				 * 624Mhz and 560Mhz are only available on speed
982				 * bin (1 << 0). All the rest are available on
983				 * all bins of the hardware
984				 */
985				opp-624000000 {
986					opp-hz = /bits/ 64 <624000000>;
987					opp-supported-hw = <0x01>;
988				};
989				opp-560000000 {
990					opp-hz = /bits/ 64 <560000000>;
991					opp-supported-hw = <0x01>;
992				};
993				opp-510000000 {
994					opp-hz = /bits/ 64 <510000000>;
995					opp-supported-hw = <0xFF>;
996				};
997				opp-401800000 {
998					opp-hz = /bits/ 64 <401800000>;
999					opp-supported-hw = <0xFF>;
1000				};
1001				opp-315000000 {
1002					opp-hz = /bits/ 64 <315000000>;
1003					opp-supported-hw = <0xFF>;
1004				};
1005				opp-214000000 {
1006					opp-hz = /bits/ 64 <214000000>;
1007					opp-supported-hw = <0xFF>;
1008				};
1009				opp-133000000 {
1010					opp-hz = /bits/ 64 <133000000>;
1011					opp-supported-hw = <0xFF>;
1012				};
1013			};
1014
1015			zap-shader {
1016				memory-region = <&zap_shader_region>;
1017			};
1018		};
1019
1020		tlmm: pinctrl@1010000 {
1021			compatible = "qcom,msm8996-pinctrl";
1022			reg = <0x01010000 0x300000>;
1023			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1024			gpio-controller;
1025			gpio-ranges = <&tlmm 0 0 150>;
1026			#gpio-cells = <2>;
1027			interrupt-controller;
1028			#interrupt-cells = <2>;
1029
1030			blsp1_spi1_default: blsp1-spi1-default {
1031				spi {
1032					pins = "gpio0", "gpio1", "gpio3";
1033					function = "blsp_spi1";
1034					drive-strength = <12>;
1035					bias-disable;
1036				};
1037
1038				cs {
1039					pins = "gpio2";
1040					function = "gpio";
1041					drive-strength = <16>;
1042					bias-disable;
1043					output-high;
1044				};
1045			};
1046
1047			blsp1_spi1_sleep: blsp1-spi1-sleep {
1048				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1049				function = "gpio";
1050				drive-strength = <2>;
1051				bias-pull-down;
1052			};
1053
1054			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1055				pins = "gpio4", "gpio5";
1056				function = "blsp_uart8";
1057				drive-strength = <16>;
1058				bias-disable;
1059			};
1060
1061			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1062				pins = "gpio4", "gpio5";
1063				function = "gpio";
1064				drive-strength = <2>;
1065				bias-disable;
1066			};
1067
1068			blsp2_i2c2_default: blsp2-i2c2 {
1069				pins = "gpio6", "gpio7";
1070				function = "blsp_i2c8";
1071				drive-strength = <16>;
1072				bias-disable;
1073			};
1074
1075			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1076				pins = "gpio6", "gpio7";
1077				function = "gpio";
1078				drive-strength = <2>;
1079				bias-disable;
1080			};
1081
1082			cci0_default: cci0-default {
1083				pins = "gpio17", "gpio18";
1084				function = "cci_i2c";
1085				drive-strength = <16>;
1086				bias-disable;
1087			};
1088
1089			camera0_state_on:
1090			camera_rear_default: camera-rear-default {
1091				camera0_mclk: mclk0 {
1092					pins = "gpio13";
1093					function = "cam_mclk";
1094					drive-strength = <16>;
1095					bias-disable;
1096				};
1097
1098				camera0_rst: rst {
1099					pins = "gpio25";
1100					function = "gpio";
1101					drive-strength = <16>;
1102					bias-disable;
1103				};
1104
1105				camera0_pwdn: pwdn {
1106					pins = "gpio26";
1107					function = "gpio";
1108					drive-strength = <16>;
1109					bias-disable;
1110				};
1111			};
1112
1113			cci1_default: cci1-default {
1114				pins = "gpio19", "gpio20";
1115				function = "cci_i2c";
1116				drive-strength = <16>;
1117				bias-disable;
1118			};
1119
1120			camera1_state_on:
1121			camera_board_default: camera-board-default {
1122				mclk1 {
1123					pins = "gpio14";
1124					function = "cam_mclk";
1125					drive-strength = <16>;
1126					bias-disable;
1127				};
1128
1129				pwdn {
1130					pins = "gpio98";
1131					function = "gpio";
1132					drive-strength = <16>;
1133					bias-disable;
1134				};
1135
1136				rst {
1137					pins = "gpio104";
1138					function = "gpio";
1139					drive-strength = <16>;
1140					bias-disable;
1141				};
1142			};
1143
1144			camera2_state_on:
1145			camera_front_default: camera-front-default {
1146				camera2_mclk: mclk2 {
1147					pins = "gpio15";
1148					function = "cam_mclk";
1149					drive-strength = <16>;
1150					bias-disable;
1151				};
1152
1153				camera2_rst: rst {
1154					pins = "gpio23";
1155					function = "gpio";
1156					drive-strength = <16>;
1157					bias-disable;
1158				};
1159
1160				pwdn {
1161					pins = "gpio133";
1162					function = "gpio";
1163					drive-strength = <16>;
1164					bias-disable;
1165				};
1166			};
1167
1168			pcie0_state_on: pcie0-state-on {
1169				perst {
1170					pins = "gpio35";
1171					function = "gpio";
1172					drive-strength = <2>;
1173					bias-pull-down;
1174				};
1175
1176				clkreq {
1177					pins = "gpio36";
1178					function = "pci_e0";
1179					drive-strength = <2>;
1180					bias-pull-up;
1181				};
1182
1183				wake {
1184					pins = "gpio37";
1185					function = "gpio";
1186					drive-strength = <2>;
1187					bias-pull-up;
1188				};
1189			};
1190
1191			pcie0_state_off: pcie0-state-off {
1192				perst {
1193					pins = "gpio35";
1194					function = "gpio";
1195					drive-strength = <2>;
1196					bias-pull-down;
1197				};
1198
1199				clkreq {
1200					pins = "gpio36";
1201					function = "gpio";
1202					drive-strength = <2>;
1203					bias-disable;
1204				};
1205
1206				wake {
1207					pins = "gpio37";
1208					function = "gpio";
1209					drive-strength = <2>;
1210					bias-disable;
1211				};
1212			};
1213
1214			blsp1_uart2_default: blsp1-uart2-default {
1215				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1216				function = "blsp_uart2";
1217				drive-strength = <16>;
1218				bias-disable;
1219			};
1220
1221			blsp1_uart2_sleep: blsp1-uart2-sleep {
1222				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1223				function = "gpio";
1224				drive-strength = <2>;
1225				bias-disable;
1226			};
1227
1228			blsp1_i2c3_default: blsp1-i2c2-default {
1229				pins = "gpio47", "gpio48";
1230				function = "blsp_i2c3";
1231				drive-strength = <16>;
1232				bias-disable = <0>;
1233			};
1234
1235			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1236				pins = "gpio47", "gpio48";
1237				function = "gpio";
1238				drive-strength = <2>;
1239				bias-disable = <0>;
1240			};
1241
1242			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1243				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1244				function = "blsp_uart9";
1245				drive-strength = <16>;
1246				bias-disable;
1247			};
1248
1249			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1250				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1251				function = "blsp_uart9";
1252				drive-strength = <2>;
1253				bias-disable;
1254			};
1255
1256			blsp2_i2c3_default: blsp2-i2c3 {
1257				pins = "gpio51", "gpio52";
1258				function = "blsp_i2c9";
1259				drive-strength = <16>;
1260				bias-disable;
1261			};
1262
1263			blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1264				pins = "gpio51", "gpio52";
1265				function = "gpio";
1266				drive-strength = <2>;
1267				bias-disable;
1268			};
1269
1270			wcd_intr_default: wcd-intr-default{
1271				pins = "gpio54";
1272				function = "gpio";
1273				drive-strength = <2>;
1274				bias-pull-down;
1275				input-enable;
1276			};
1277
1278			blsp2_i2c1_default: blsp2-i2c1 {
1279				pins = "gpio55", "gpio56";
1280				function = "blsp_i2c7";
1281				drive-strength = <16>;
1282				bias-disable;
1283			};
1284
1285			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1286				pins = "gpio55", "gpio56";
1287				function = "gpio";
1288				drive-strength = <2>;
1289				bias-disable;
1290			};
1291
1292			blsp2_i2c5_default: blsp2-i2c5 {
1293				pins = "gpio60", "gpio61";
1294				function = "blsp_i2c11";
1295				drive-strength = <2>;
1296				bias-disable;
1297			};
1298
1299			/* Sleep state for BLSP2_I2C5 is missing.. */
1300
1301			cdc_reset_active: cdc-reset-active {
1302				pins = "gpio64";
1303				function = "gpio";
1304				drive-strength = <16>;
1305				bias-pull-down;
1306				output-high;
1307			};
1308
1309			cdc_reset_sleep: cdc-reset-sleep {
1310				pins = "gpio64";
1311				function = "gpio";
1312				drive-strength = <16>;
1313				bias-disable;
1314				output-low;
1315			};
1316
1317			blsp2_spi6_default: blsp2-spi5-default {
1318				spi {
1319					pins = "gpio85", "gpio86", "gpio88";
1320					function = "blsp_spi12";
1321					drive-strength = <12>;
1322					bias-disable;
1323				};
1324
1325				cs {
1326					pins = "gpio87";
1327					function = "gpio";
1328					drive-strength = <16>;
1329					bias-disable;
1330					output-high;
1331				};
1332			};
1333
1334			blsp2_spi6_sleep: blsp2-spi5-sleep {
1335				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1336				function = "gpio";
1337				drive-strength = <2>;
1338				bias-pull-down;
1339			};
1340
1341			blsp2_i2c6_default: blsp2-i2c6 {
1342				pins = "gpio87", "gpio88";
1343				function = "blsp_i2c12";
1344				drive-strength = <16>;
1345				bias-disable;
1346			};
1347
1348			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1349				pins = "gpio87", "gpio88";
1350				function = "gpio";
1351				drive-strength = <2>;
1352				bias-disable;
1353			};
1354
1355			pcie1_state_on: pcie1-state-on {
1356				perst {
1357					pins = "gpio130";
1358					function = "gpio";
1359					drive-strength = <2>;
1360					bias-pull-down;
1361				};
1362
1363				clkreq {
1364					pins = "gpio131";
1365					function = "pci_e1";
1366					drive-strength = <2>;
1367					bias-pull-up;
1368				};
1369
1370				wake {
1371					pins = "gpio132";
1372					function = "gpio";
1373					drive-strength = <2>;
1374					bias-pull-down;
1375				};
1376			};
1377
1378			pcie1_state_off: pcie1-state-off {
1379				/* Perst is missing? */
1380				clkreq {
1381					pins = "gpio131";
1382					function = "gpio";
1383					drive-strength = <2>;
1384					bias-disable;
1385				};
1386
1387				wake {
1388					pins = "gpio132";
1389					function = "gpio";
1390					drive-strength = <2>;
1391					bias-disable;
1392				};
1393			};
1394
1395			pcie2_state_on: pcie2-state-on {
1396				perst {
1397					pins = "gpio114";
1398					function = "gpio";
1399					drive-strength = <2>;
1400					bias-pull-down;
1401				};
1402
1403				clkreq {
1404					pins = "gpio115";
1405					function = "pci_e2";
1406					drive-strength = <2>;
1407					bias-pull-up;
1408				};
1409
1410				wake {
1411					pins = "gpio116";
1412					function = "gpio";
1413					drive-strength = <2>;
1414					bias-pull-down;
1415				};
1416			};
1417
1418			pcie2_state_off: pcie2-state-off {
1419				/* Perst is missing? */
1420				clkreq {
1421					pins = "gpio115";
1422					function = "gpio";
1423					drive-strength = <2>;
1424					bias-disable;
1425				};
1426
1427				wake {
1428					pins = "gpio116";
1429					function = "gpio";
1430					drive-strength = <2>;
1431					bias-disable;
1432				};
1433			};
1434
1435			sdc1_state_on: sdc1-state-on {
1436				clk {
1437					pins = "sdc1_clk";
1438					bias-disable;
1439					drive-strength = <16>;
1440				};
1441
1442				cmd {
1443					pins = "sdc1_cmd";
1444					bias-pull-up;
1445					drive-strength = <10>;
1446				};
1447
1448				data {
1449					pins = "sdc1_data";
1450					bias-pull-up;
1451					drive-strength = <10>;
1452				};
1453
1454				rclk {
1455					pins = "sdc1_rclk";
1456					bias-pull-down;
1457				};
1458			};
1459
1460			sdc1_state_off: sdc1-state-off {
1461				clk {
1462					pins = "sdc1_clk";
1463					bias-disable;
1464					drive-strength = <2>;
1465				};
1466
1467				cmd {
1468					pins = "sdc1_cmd";
1469					bias-pull-up;
1470					drive-strength = <2>;
1471				};
1472
1473				data {
1474					pins = "sdc1_data";
1475					bias-pull-up;
1476					drive-strength = <2>;
1477				};
1478
1479				rclk {
1480					pins = "sdc1_rclk";
1481					bias-pull-down;
1482				};
1483			};
1484
1485			sdc2_state_on: sdc2-clk-on {
1486				clk {
1487					pins = "sdc2_clk";
1488					bias-disable;
1489					drive-strength = <16>;
1490				};
1491
1492				cmd {
1493					pins = "sdc2_cmd";
1494					bias-pull-up;
1495					drive-strength = <10>;
1496				};
1497
1498				data {
1499					pins = "sdc2_data";
1500					bias-pull-up;
1501					drive-strength = <10>;
1502				};
1503			};
1504
1505			sdc2_state_off: sdc2-clk-off {
1506				clk {
1507					pins = "sdc2_clk";
1508					bias-disable;
1509					drive-strength = <2>;
1510				};
1511
1512				cmd {
1513					pins = "sdc2_cmd";
1514					bias-pull-up;
1515					drive-strength = <2>;
1516				};
1517
1518				data {
1519					pins = "sdc2_data";
1520					bias-pull-up;
1521					drive-strength = <2>;
1522				};
1523			};
1524		};
1525
1526		sram@290000 {
1527			compatible = "qcom,rpm-stats";
1528			reg = <0x00290000 0x10000>;
1529		};
1530
1531		spmi_bus: qcom,spmi@400f000 {
1532			compatible = "qcom,spmi-pmic-arb";
1533			reg = <0x0400f000 0x1000>,
1534			      <0x04400000 0x800000>,
1535			      <0x04c00000 0x800000>,
1536			      <0x05800000 0x200000>,
1537			      <0x0400a000 0x002100>;
1538			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1539			interrupt-names = "periph_irq";
1540			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1541			qcom,ee = <0>;
1542			qcom,channel = <0>;
1543			#address-cells = <2>;
1544			#size-cells = <0>;
1545			interrupt-controller;
1546			#interrupt-cells = <4>;
1547		};
1548
1549		agnoc@0 {
1550			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1551			compatible = "simple-pm-bus";
1552			#address-cells = <1>;
1553			#size-cells = <1>;
1554			ranges;
1555
1556			pcie0: pcie@600000 {
1557				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1558				status = "disabled";
1559				power-domains = <&gcc PCIE0_GDSC>;
1560				bus-range = <0x00 0xff>;
1561				num-lanes = <1>;
1562
1563				reg = <0x00600000 0x2000>,
1564				      <0x0c000000 0xf1d>,
1565				      <0x0c000f20 0xa8>,
1566				      <0x0c100000 0x100000>;
1567				reg-names = "parf", "dbi", "elbi","config";
1568
1569				phys = <&pciephy_0>;
1570				phy-names = "pciephy";
1571
1572				#address-cells = <3>;
1573				#size-cells = <2>;
1574				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1575					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1576
1577				device_type = "pci";
1578
1579				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1580				interrupt-names = "msi";
1581				#interrupt-cells = <1>;
1582				interrupt-map-mask = <0 0 0 0x7>;
1583				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1584						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1585						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1586						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1587
1588				pinctrl-names = "default", "sleep";
1589				pinctrl-0 = <&pcie0_state_on>;
1590				pinctrl-1 = <&pcie0_state_off>;
1591
1592				linux,pci-domain = <0>;
1593
1594				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1595					<&gcc GCC_PCIE_0_AUX_CLK>,
1596					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1597					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1598					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1599
1600				clock-names =  "pipe",
1601						"aux",
1602						"cfg",
1603						"bus_master",
1604						"bus_slave";
1605
1606			};
1607
1608			pcie1: pcie@608000 {
1609				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1610				power-domains = <&gcc PCIE1_GDSC>;
1611				bus-range = <0x00 0xff>;
1612				num-lanes = <1>;
1613
1614				status  = "disabled";
1615
1616				reg = <0x00608000 0x2000>,
1617				      <0x0d000000 0xf1d>,
1618				      <0x0d000f20 0xa8>,
1619				      <0x0d100000 0x100000>;
1620
1621				reg-names = "parf", "dbi", "elbi","config";
1622
1623				phys = <&pciephy_1>;
1624				phy-names = "pciephy";
1625
1626				#address-cells = <3>;
1627				#size-cells = <2>;
1628				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1629					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1630
1631				device_type = "pci";
1632
1633				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1634				interrupt-names = "msi";
1635				#interrupt-cells = <1>;
1636				interrupt-map-mask = <0 0 0 0x7>;
1637				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1638						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1639						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1640						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1641
1642				pinctrl-names = "default", "sleep";
1643				pinctrl-0 = <&pcie1_state_on>;
1644				pinctrl-1 = <&pcie1_state_off>;
1645
1646				linux,pci-domain = <1>;
1647
1648				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1649					<&gcc GCC_PCIE_1_AUX_CLK>,
1650					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1651					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1652					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1653
1654				clock-names =  "pipe",
1655						"aux",
1656						"cfg",
1657						"bus_master",
1658						"bus_slave";
1659			};
1660
1661			pcie2: pcie@610000 {
1662				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1663				power-domains = <&gcc PCIE2_GDSC>;
1664				bus-range = <0x00 0xff>;
1665				num-lanes = <1>;
1666				status = "disabled";
1667				reg = <0x00610000 0x2000>,
1668				      <0x0e000000 0xf1d>,
1669				      <0x0e000f20 0xa8>,
1670				      <0x0e100000 0x100000>;
1671
1672				reg-names = "parf", "dbi", "elbi","config";
1673
1674				phys = <&pciephy_2>;
1675				phy-names = "pciephy";
1676
1677				#address-cells = <3>;
1678				#size-cells = <2>;
1679				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1680					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1681
1682				device_type = "pci";
1683
1684				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1685				interrupt-names = "msi";
1686				#interrupt-cells = <1>;
1687				interrupt-map-mask = <0 0 0 0x7>;
1688				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1689						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1690						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1691						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1692
1693				pinctrl-names = "default", "sleep";
1694				pinctrl-0 = <&pcie2_state_on>;
1695				pinctrl-1 = <&pcie2_state_off>;
1696
1697				linux,pci-domain = <2>;
1698				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1699					<&gcc GCC_PCIE_2_AUX_CLK>,
1700					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1701					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1702					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1703
1704				clock-names =  "pipe",
1705						"aux",
1706						"cfg",
1707						"bus_master",
1708						"bus_slave";
1709			};
1710		};
1711
1712		ufshc: ufshc@624000 {
1713			compatible = "qcom,ufshc";
1714			reg = <0x00624000 0x2500>;
1715			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1716
1717			phys = <&ufsphy_lane>;
1718			phy-names = "ufsphy";
1719
1720			power-domains = <&gcc UFS_GDSC>;
1721
1722			clock-names =
1723				"core_clk_src",
1724				"core_clk",
1725				"bus_clk",
1726				"bus_aggr_clk",
1727				"iface_clk",
1728				"core_clk_unipro_src",
1729				"core_clk_unipro",
1730				"core_clk_ice",
1731				"ref_clk",
1732				"tx_lane0_sync_clk",
1733				"rx_lane0_sync_clk";
1734			clocks =
1735				<&gcc UFS_AXI_CLK_SRC>,
1736				<&gcc GCC_UFS_AXI_CLK>,
1737				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1738				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1739				<&gcc GCC_UFS_AHB_CLK>,
1740				<&gcc UFS_ICE_CORE_CLK_SRC>,
1741				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1742				<&gcc GCC_UFS_ICE_CORE_CLK>,
1743				<&rpmcc RPM_SMD_LN_BB_CLK>,
1744				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1745				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1746			freq-table-hz =
1747				<100000000 200000000>,
1748				<0 0>,
1749				<0 0>,
1750				<0 0>,
1751				<0 0>,
1752				<150000000 300000000>,
1753				<0 0>,
1754				<0 0>,
1755				<0 0>,
1756				<0 0>,
1757				<0 0>;
1758
1759			lanes-per-direction = <1>;
1760			#reset-cells = <1>;
1761			status = "disabled";
1762
1763			ufs_variant {
1764				compatible = "qcom,ufs_variant";
1765			};
1766		};
1767
1768		ufsphy: phy@627000 {
1769			compatible = "qcom,msm8996-qmp-ufs-phy";
1770			reg = <0x00627000 0x1c4>;
1771			#address-cells = <1>;
1772			#size-cells = <1>;
1773			ranges;
1774
1775			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1776			clock-names = "ref";
1777
1778			resets = <&ufshc 0>;
1779			reset-names = "ufsphy";
1780			status = "disabled";
1781
1782			ufsphy_lane: lanes@627400 {
1783				reg = <0x627400 0x12c>,
1784				      <0x627600 0x200>,
1785				      <0x627c00 0x1b4>;
1786				#phy-cells = <0>;
1787			};
1788		};
1789
1790		camss: camss@a00000 {
1791			compatible = "qcom,msm8996-camss";
1792			reg = <0x00a34000 0x1000>,
1793			      <0x00a00030 0x4>,
1794			      <0x00a35000 0x1000>,
1795			      <0x00a00038 0x4>,
1796			      <0x00a36000 0x1000>,
1797			      <0x00a00040 0x4>,
1798			      <0x00a30000 0x100>,
1799			      <0x00a30400 0x100>,
1800			      <0x00a30800 0x100>,
1801			      <0x00a30c00 0x100>,
1802			      <0x00a31000 0x500>,
1803			      <0x00a00020 0x10>,
1804			      <0x00a10000 0x1000>,
1805			      <0x00a14000 0x1000>;
1806			reg-names = "csiphy0",
1807				"csiphy0_clk_mux",
1808				"csiphy1",
1809				"csiphy1_clk_mux",
1810				"csiphy2",
1811				"csiphy2_clk_mux",
1812				"csid0",
1813				"csid1",
1814				"csid2",
1815				"csid3",
1816				"ispif",
1817				"csi_clk_mux",
1818				"vfe0",
1819				"vfe1";
1820			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1821				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1822				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1823				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1824				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1825				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1826				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1827				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1828				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1829				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1830			interrupt-names = "csiphy0",
1831				"csiphy1",
1832				"csiphy2",
1833				"csid0",
1834				"csid1",
1835				"csid2",
1836				"csid3",
1837				"ispif",
1838				"vfe0",
1839				"vfe1";
1840			power-domains = <&mmcc VFE0_GDSC>,
1841					<&mmcc VFE1_GDSC>;
1842			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1843				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1844				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1845				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1846				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1847				<&mmcc CAMSS_CSI0_AHB_CLK>,
1848				<&mmcc CAMSS_CSI0_CLK>,
1849				<&mmcc CAMSS_CSI0PHY_CLK>,
1850				<&mmcc CAMSS_CSI0PIX_CLK>,
1851				<&mmcc CAMSS_CSI0RDI_CLK>,
1852				<&mmcc CAMSS_CSI1_AHB_CLK>,
1853				<&mmcc CAMSS_CSI1_CLK>,
1854				<&mmcc CAMSS_CSI1PHY_CLK>,
1855				<&mmcc CAMSS_CSI1PIX_CLK>,
1856				<&mmcc CAMSS_CSI1RDI_CLK>,
1857				<&mmcc CAMSS_CSI2_AHB_CLK>,
1858				<&mmcc CAMSS_CSI2_CLK>,
1859				<&mmcc CAMSS_CSI2PHY_CLK>,
1860				<&mmcc CAMSS_CSI2PIX_CLK>,
1861				<&mmcc CAMSS_CSI2RDI_CLK>,
1862				<&mmcc CAMSS_CSI3_AHB_CLK>,
1863				<&mmcc CAMSS_CSI3_CLK>,
1864				<&mmcc CAMSS_CSI3PHY_CLK>,
1865				<&mmcc CAMSS_CSI3PIX_CLK>,
1866				<&mmcc CAMSS_CSI3RDI_CLK>,
1867				<&mmcc CAMSS_AHB_CLK>,
1868				<&mmcc CAMSS_VFE0_CLK>,
1869				<&mmcc CAMSS_CSI_VFE0_CLK>,
1870				<&mmcc CAMSS_VFE0_AHB_CLK>,
1871				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1872				<&mmcc CAMSS_VFE1_CLK>,
1873				<&mmcc CAMSS_CSI_VFE1_CLK>,
1874				<&mmcc CAMSS_VFE1_AHB_CLK>,
1875				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1876				<&mmcc CAMSS_VFE_AHB_CLK>,
1877				<&mmcc CAMSS_VFE_AXI_CLK>;
1878			clock-names = "top_ahb",
1879				"ispif_ahb",
1880				"csiphy0_timer",
1881				"csiphy1_timer",
1882				"csiphy2_timer",
1883				"csi0_ahb",
1884				"csi0",
1885				"csi0_phy",
1886				"csi0_pix",
1887				"csi0_rdi",
1888				"csi1_ahb",
1889				"csi1",
1890				"csi1_phy",
1891				"csi1_pix",
1892				"csi1_rdi",
1893				"csi2_ahb",
1894				"csi2",
1895				"csi2_phy",
1896				"csi2_pix",
1897				"csi2_rdi",
1898				"csi3_ahb",
1899				"csi3",
1900				"csi3_phy",
1901				"csi3_pix",
1902				"csi3_rdi",
1903				"ahb",
1904				"vfe0",
1905				"csi_vfe0",
1906				"vfe0_ahb",
1907				"vfe0_stream",
1908				"vfe1",
1909				"csi_vfe1",
1910				"vfe1_ahb",
1911				"vfe1_stream",
1912				"vfe_ahb",
1913				"vfe_axi";
1914			iommus = <&vfe_smmu 0>,
1915				 <&vfe_smmu 1>,
1916				 <&vfe_smmu 2>,
1917				 <&vfe_smmu 3>;
1918			status = "disabled";
1919			ports {
1920				#address-cells = <1>;
1921				#size-cells = <0>;
1922			};
1923		};
1924
1925		cci: cci@a0c000 {
1926			compatible = "qcom,msm8996-cci";
1927			#address-cells = <1>;
1928			#size-cells = <0>;
1929			reg = <0xa0c000 0x1000>;
1930			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1931			power-domains = <&mmcc CAMSS_GDSC>;
1932			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1933				 <&mmcc CAMSS_CCI_AHB_CLK>,
1934				 <&mmcc CAMSS_CCI_CLK>,
1935				 <&mmcc CAMSS_AHB_CLK>;
1936			clock-names = "camss_top_ahb",
1937				      "cci_ahb",
1938				      "cci",
1939				      "camss_ahb";
1940			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1941					  <&mmcc CAMSS_CCI_CLK>;
1942			assigned-clock-rates = <80000000>, <37500000>;
1943			pinctrl-names = "default";
1944			pinctrl-0 = <&cci0_default &cci1_default>;
1945			status = "disabled";
1946
1947			cci_i2c0: i2c-bus@0 {
1948				reg = <0>;
1949				clock-frequency = <400000>;
1950				#address-cells = <1>;
1951				#size-cells = <0>;
1952			};
1953
1954			cci_i2c1: i2c-bus@1 {
1955				reg = <1>;
1956				clock-frequency = <400000>;
1957				#address-cells = <1>;
1958				#size-cells = <0>;
1959			};
1960		};
1961
1962		adreno_smmu: iommu@b40000 {
1963			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1964			reg = <0x00b40000 0x10000>;
1965
1966			#global-interrupts = <1>;
1967			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1968				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1969				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1970			#iommu-cells = <1>;
1971
1972			clocks = <&mmcc GPU_AHB_CLK>,
1973				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1974			clock-names = "iface", "bus";
1975
1976			power-domains = <&mmcc GPU_GDSC>;
1977		};
1978
1979		venus: video-codec@c00000 {
1980			compatible = "qcom,msm8996-venus";
1981			reg = <0x00c00000 0xff000>;
1982			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1983			power-domains = <&mmcc VENUS_GDSC>;
1984			clocks = <&mmcc VIDEO_CORE_CLK>,
1985				 <&mmcc VIDEO_AHB_CLK>,
1986				 <&mmcc VIDEO_AXI_CLK>,
1987				 <&mmcc VIDEO_MAXI_CLK>;
1988			clock-names = "core", "iface", "bus", "mbus";
1989			iommus = <&venus_smmu 0x00>,
1990				 <&venus_smmu 0x01>,
1991				 <&venus_smmu 0x0a>,
1992				 <&venus_smmu 0x07>,
1993				 <&venus_smmu 0x0e>,
1994				 <&venus_smmu 0x0f>,
1995				 <&venus_smmu 0x08>,
1996				 <&venus_smmu 0x09>,
1997				 <&venus_smmu 0x0b>,
1998				 <&venus_smmu 0x0c>,
1999				 <&venus_smmu 0x0d>,
2000				 <&venus_smmu 0x10>,
2001				 <&venus_smmu 0x11>,
2002				 <&venus_smmu 0x21>,
2003				 <&venus_smmu 0x28>,
2004				 <&venus_smmu 0x29>,
2005				 <&venus_smmu 0x2b>,
2006				 <&venus_smmu 0x2c>,
2007				 <&venus_smmu 0x2d>,
2008				 <&venus_smmu 0x31>;
2009			memory-region = <&venus_region>;
2010			status = "disabled";
2011
2012			video-decoder {
2013				compatible = "venus-decoder";
2014				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2015				clock-names = "core";
2016				power-domains = <&mmcc VENUS_CORE0_GDSC>;
2017			};
2018
2019			video-encoder {
2020				compatible = "venus-encoder";
2021				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2022				clock-names = "core";
2023				power-domains = <&mmcc VENUS_CORE1_GDSC>;
2024			};
2025		};
2026
2027		mdp_smmu: iommu@d00000 {
2028			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2029			reg = <0x00d00000 0x10000>;
2030
2031			#global-interrupts = <1>;
2032			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2033				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2034				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2035			#iommu-cells = <1>;
2036			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2037				 <&mmcc SMMU_MDP_AXI_CLK>;
2038			clock-names = "iface", "bus";
2039
2040			power-domains = <&mmcc MDSS_GDSC>;
2041		};
2042
2043		venus_smmu: iommu@d40000 {
2044			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2045			reg = <0x00d40000 0x20000>;
2046			#global-interrupts = <1>;
2047			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2048				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2049				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2050				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2051				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2052				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2053				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2054				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2055			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2056			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2057				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2058			clock-names = "iface", "bus";
2059			#iommu-cells = <1>;
2060			status = "okay";
2061		};
2062
2063		vfe_smmu: iommu@da0000 {
2064			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2065			reg = <0x00da0000 0x10000>;
2066
2067			#global-interrupts = <1>;
2068			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2069				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2070				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2071			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2072			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2073				 <&mmcc SMMU_VFE_AXI_CLK>;
2074			clock-names = "iface",
2075				      "bus";
2076			#iommu-cells = <1>;
2077		};
2078
2079		lpass_q6_smmu: iommu@1600000 {
2080			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2081			reg = <0x01600000 0x20000>;
2082			#iommu-cells = <1>;
2083			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2084
2085			#global-interrupts = <1>;
2086			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2087		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2088		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2089		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2090		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2091		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2092		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2093		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2094		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2095		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2096		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2097		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2098		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2099
2100			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2101				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2102			clock-names = "iface", "bus";
2103		};
2104
2105		stm@3002000 {
2106			compatible = "arm,coresight-stm", "arm,primecell";
2107			reg = <0x3002000 0x1000>,
2108			      <0x8280000 0x180000>;
2109			reg-names = "stm-base", "stm-stimulus-base";
2110
2111			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2112			clock-names = "apb_pclk", "atclk";
2113
2114			out-ports {
2115				port {
2116					stm_out: endpoint {
2117						remote-endpoint =
2118						  <&funnel0_in>;
2119					};
2120				};
2121			};
2122		};
2123
2124		tpiu@3020000 {
2125			compatible = "arm,coresight-tpiu", "arm,primecell";
2126			reg = <0x3020000 0x1000>;
2127
2128			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2129			clock-names = "apb_pclk", "atclk";
2130
2131			in-ports {
2132				port {
2133					tpiu_in: endpoint {
2134						remote-endpoint =
2135						  <&replicator_out1>;
2136					};
2137				};
2138			};
2139		};
2140
2141		funnel@3021000 {
2142			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2143			reg = <0x3021000 0x1000>;
2144
2145			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2146			clock-names = "apb_pclk", "atclk";
2147
2148			in-ports {
2149				#address-cells = <1>;
2150				#size-cells = <0>;
2151
2152				port@7 {
2153					reg = <7>;
2154					funnel0_in: endpoint {
2155						remote-endpoint =
2156						  <&stm_out>;
2157					};
2158				};
2159			};
2160
2161			out-ports {
2162				port {
2163					funnel0_out: endpoint {
2164						remote-endpoint =
2165						  <&merge_funnel_in0>;
2166					};
2167				};
2168			};
2169		};
2170
2171		funnel@3022000 {
2172			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2173			reg = <0x3022000 0x1000>;
2174
2175			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2176			clock-names = "apb_pclk", "atclk";
2177
2178			in-ports {
2179				#address-cells = <1>;
2180				#size-cells = <0>;
2181
2182				port@6 {
2183					reg = <6>;
2184					funnel1_in: endpoint {
2185						remote-endpoint =
2186						  <&apss_merge_funnel_out>;
2187					};
2188				};
2189			};
2190
2191			out-ports {
2192				port {
2193					funnel1_out: endpoint {
2194						remote-endpoint =
2195						  <&merge_funnel_in1>;
2196					};
2197				};
2198			};
2199		};
2200
2201		funnel@3023000 {
2202			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2203			reg = <0x3023000 0x1000>;
2204
2205			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2206			clock-names = "apb_pclk", "atclk";
2207
2208
2209			out-ports {
2210				port {
2211					funnel2_out: endpoint {
2212						remote-endpoint =
2213						  <&merge_funnel_in2>;
2214					};
2215				};
2216			};
2217		};
2218
2219		funnel@3025000 {
2220			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2221			reg = <0x3025000 0x1000>;
2222
2223			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2224			clock-names = "apb_pclk", "atclk";
2225
2226			in-ports {
2227				#address-cells = <1>;
2228				#size-cells = <0>;
2229
2230				port@0 {
2231					reg = <0>;
2232					merge_funnel_in0: endpoint {
2233						remote-endpoint =
2234						  <&funnel0_out>;
2235					};
2236				};
2237
2238				port@1 {
2239					reg = <1>;
2240					merge_funnel_in1: endpoint {
2241						remote-endpoint =
2242						  <&funnel1_out>;
2243					};
2244				};
2245
2246				port@2 {
2247					reg = <2>;
2248					merge_funnel_in2: endpoint {
2249						remote-endpoint =
2250						  <&funnel2_out>;
2251					};
2252				};
2253			};
2254
2255			out-ports {
2256				port {
2257					merge_funnel_out: endpoint {
2258						remote-endpoint =
2259						  <&etf_in>;
2260					};
2261				};
2262			};
2263		};
2264
2265		replicator@3026000 {
2266			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2267			reg = <0x3026000 0x1000>;
2268
2269			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2270			clock-names = "apb_pclk", "atclk";
2271
2272			in-ports {
2273				port {
2274					replicator_in: endpoint {
2275						remote-endpoint =
2276						  <&etf_out>;
2277					};
2278				};
2279			};
2280
2281			out-ports {
2282				#address-cells = <1>;
2283				#size-cells = <0>;
2284
2285				port@0 {
2286					reg = <0>;
2287					replicator_out0: endpoint {
2288						remote-endpoint =
2289						  <&etr_in>;
2290					};
2291				};
2292
2293				port@1 {
2294					reg = <1>;
2295					replicator_out1: endpoint {
2296						remote-endpoint =
2297						  <&tpiu_in>;
2298					};
2299				};
2300			};
2301		};
2302
2303		etf@3027000 {
2304			compatible = "arm,coresight-tmc", "arm,primecell";
2305			reg = <0x3027000 0x1000>;
2306
2307			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2308			clock-names = "apb_pclk", "atclk";
2309
2310			in-ports {
2311				port {
2312					etf_in: endpoint {
2313						remote-endpoint =
2314						  <&merge_funnel_out>;
2315					};
2316				};
2317			};
2318
2319			out-ports {
2320				port {
2321					etf_out: endpoint {
2322						remote-endpoint =
2323						  <&replicator_in>;
2324					};
2325				};
2326			};
2327		};
2328
2329		etr@3028000 {
2330			compatible = "arm,coresight-tmc", "arm,primecell";
2331			reg = <0x3028000 0x1000>;
2332
2333			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2334			clock-names = "apb_pclk", "atclk";
2335			arm,scatter-gather;
2336
2337			in-ports {
2338				port {
2339					etr_in: endpoint {
2340						remote-endpoint =
2341						  <&replicator_out0>;
2342					};
2343				};
2344			};
2345		};
2346
2347		debug@3810000 {
2348			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2349			reg = <0x3810000 0x1000>;
2350
2351			clocks = <&rpmcc RPM_QDSS_CLK>;
2352			clock-names = "apb_pclk";
2353
2354			cpu = <&CPU0>;
2355		};
2356
2357		etm@3840000 {
2358			compatible = "arm,coresight-etm4x", "arm,primecell";
2359			reg = <0x3840000 0x1000>;
2360
2361			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2362			clock-names = "apb_pclk", "atclk";
2363
2364			cpu = <&CPU0>;
2365
2366			out-ports {
2367				port {
2368					etm0_out: endpoint {
2369						remote-endpoint =
2370						  <&apss_funnel0_in0>;
2371					};
2372				};
2373			};
2374		};
2375
2376		debug@3910000 {
2377			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2378			reg = <0x3910000 0x1000>;
2379
2380			clocks = <&rpmcc RPM_QDSS_CLK>;
2381			clock-names = "apb_pclk";
2382
2383			cpu = <&CPU1>;
2384		};
2385
2386		etm@3940000 {
2387			compatible = "arm,coresight-etm4x", "arm,primecell";
2388			reg = <0x3940000 0x1000>;
2389
2390			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2391			clock-names = "apb_pclk", "atclk";
2392
2393			cpu = <&CPU1>;
2394
2395			out-ports {
2396				port {
2397					etm1_out: endpoint {
2398						remote-endpoint =
2399						  <&apss_funnel0_in1>;
2400					};
2401				};
2402			};
2403		};
2404
2405		funnel@39b0000 { /* APSS Funnel 0 */
2406			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2407			reg = <0x39b0000 0x1000>;
2408
2409			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2410			clock-names = "apb_pclk", "atclk";
2411
2412			in-ports {
2413				#address-cells = <1>;
2414				#size-cells = <0>;
2415
2416				port@0 {
2417					reg = <0>;
2418					apss_funnel0_in0: endpoint {
2419						remote-endpoint = <&etm0_out>;
2420					};
2421				};
2422
2423				port@1 {
2424					reg = <1>;
2425					apss_funnel0_in1: endpoint {
2426						remote-endpoint = <&etm1_out>;
2427					};
2428				};
2429			};
2430
2431			out-ports {
2432				port {
2433					apss_funnel0_out: endpoint {
2434						remote-endpoint =
2435						  <&apss_merge_funnel_in0>;
2436					};
2437				};
2438			};
2439		};
2440
2441		debug@3a10000 {
2442			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2443			reg = <0x3a10000 0x1000>;
2444
2445			clocks = <&rpmcc RPM_QDSS_CLK>;
2446			clock-names = "apb_pclk";
2447
2448			cpu = <&CPU2>;
2449		};
2450
2451		etm@3a40000 {
2452			compatible = "arm,coresight-etm4x", "arm,primecell";
2453			reg = <0x3a40000 0x1000>;
2454
2455			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2456			clock-names = "apb_pclk", "atclk";
2457
2458			cpu = <&CPU2>;
2459
2460			out-ports {
2461				port {
2462					etm2_out: endpoint {
2463						remote-endpoint =
2464						  <&apss_funnel1_in0>;
2465					};
2466				};
2467			};
2468		};
2469
2470		debug@3b10000 {
2471			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2472			reg = <0x3b10000 0x1000>;
2473
2474			clocks = <&rpmcc RPM_QDSS_CLK>;
2475			clock-names = "apb_pclk";
2476
2477			cpu = <&CPU3>;
2478		};
2479
2480		etm@3b40000 {
2481			compatible = "arm,coresight-etm4x", "arm,primecell";
2482			reg = <0x3b40000 0x1000>;
2483
2484			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2485			clock-names = "apb_pclk", "atclk";
2486
2487			cpu = <&CPU3>;
2488
2489			out-ports {
2490				port {
2491					etm3_out: endpoint {
2492						remote-endpoint =
2493						  <&apss_funnel1_in1>;
2494					};
2495				};
2496			};
2497		};
2498
2499		funnel@3bb0000 { /* APSS Funnel 1 */
2500			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2501			reg = <0x3bb0000 0x1000>;
2502
2503			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2504			clock-names = "apb_pclk", "atclk";
2505
2506			in-ports {
2507				#address-cells = <1>;
2508				#size-cells = <0>;
2509
2510				port@0 {
2511					reg = <0>;
2512					apss_funnel1_in0: endpoint {
2513						remote-endpoint = <&etm2_out>;
2514					};
2515				};
2516
2517				port@1 {
2518					reg = <1>;
2519					apss_funnel1_in1: endpoint {
2520						remote-endpoint = <&etm3_out>;
2521					};
2522				};
2523			};
2524
2525			out-ports {
2526				port {
2527					apss_funnel1_out: endpoint {
2528						remote-endpoint =
2529						  <&apss_merge_funnel_in1>;
2530					};
2531				};
2532			};
2533		};
2534
2535		funnel@3bc0000 {
2536			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2537			reg = <0x3bc0000 0x1000>;
2538
2539			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2540			clock-names = "apb_pclk", "atclk";
2541
2542			in-ports {
2543				#address-cells = <1>;
2544				#size-cells = <0>;
2545
2546				port@0 {
2547					reg = <0>;
2548					apss_merge_funnel_in0: endpoint {
2549						remote-endpoint =
2550						  <&apss_funnel0_out>;
2551					};
2552				};
2553
2554				port@1 {
2555					reg = <1>;
2556					apss_merge_funnel_in1: endpoint {
2557						remote-endpoint =
2558						  <&apss_funnel1_out>;
2559					};
2560				};
2561			};
2562
2563			out-ports {
2564				port {
2565					apss_merge_funnel_out: endpoint {
2566						remote-endpoint =
2567						  <&funnel1_in>;
2568					};
2569				};
2570			};
2571		};
2572
2573		kryocc: clock-controller@6400000 {
2574			compatible = "qcom,msm8996-apcc";
2575			reg = <0x06400000 0x90000>;
2576
2577			clock-names = "xo";
2578			clocks = <&xo_board>;
2579
2580			#clock-cells = <1>;
2581		};
2582
2583		usb3: usb@6af8800 {
2584			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2585			reg = <0x06af8800 0x400>;
2586			#address-cells = <1>;
2587			#size-cells = <1>;
2588			ranges;
2589
2590			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2591				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2592			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2593
2594			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2595				<&gcc GCC_USB30_MASTER_CLK>,
2596				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2597				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2598				<&gcc GCC_USB30_SLEEP_CLK>,
2599				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2600
2601			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2602					  <&gcc GCC_USB30_MASTER_CLK>;
2603			assigned-clock-rates = <19200000>, <120000000>;
2604
2605			power-domains = <&gcc USB30_GDSC>;
2606			status = "disabled";
2607
2608			usb3_dwc3: dwc3@6a00000 {
2609				compatible = "snps,dwc3";
2610				reg = <0x06a00000 0xcc00>;
2611				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2612				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2613				phy-names = "usb2-phy", "usb3-phy";
2614				snps,dis_u2_susphy_quirk;
2615				snps,dis_enblslpm_quirk;
2616			};
2617		};
2618
2619		usb3phy: phy@7410000 {
2620			compatible = "qcom,msm8996-qmp-usb3-phy";
2621			reg = <0x07410000 0x1c4>;
2622			#clock-cells = <1>;
2623			#address-cells = <1>;
2624			#size-cells = <1>;
2625			ranges;
2626
2627			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2628				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2629				<&gcc GCC_USB3_CLKREF_CLK>;
2630			clock-names = "aux", "cfg_ahb", "ref";
2631
2632			resets = <&gcc GCC_USB3_PHY_BCR>,
2633				<&gcc GCC_USB3PHY_PHY_BCR>;
2634			reset-names = "phy", "common";
2635			status = "disabled";
2636
2637			ssusb_phy_0: lane@7410200 {
2638				reg = <0x07410200 0x200>,
2639				      <0x07410400 0x130>,
2640				      <0x07410600 0x1a8>;
2641				#phy-cells = <0>;
2642
2643				clock-output-names = "usb3_phy_pipe_clk_src";
2644				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2645				clock-names = "pipe0";
2646			};
2647		};
2648
2649		hsusb_phy1: phy@7411000 {
2650			compatible = "qcom,msm8996-qusb2-phy";
2651			reg = <0x07411000 0x180>;
2652			#phy-cells = <0>;
2653
2654			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2655				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2656			clock-names = "cfg_ahb", "ref";
2657
2658			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2659			nvmem-cells = <&qusb2p_hstx_trim>;
2660			status = "disabled";
2661		};
2662
2663		hsusb_phy2: phy@7412000 {
2664			compatible = "qcom,msm8996-qusb2-phy";
2665			reg = <0x07412000 0x180>;
2666			#phy-cells = <0>;
2667
2668			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2669				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2670			clock-names = "cfg_ahb", "ref";
2671
2672			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2673			nvmem-cells = <&qusb2s_hstx_trim>;
2674			status = "disabled";
2675		};
2676
2677		sdhc1: sdhci@7464900 {
2678			compatible = "qcom,sdhci-msm-v4";
2679			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2680			reg-names = "hc_mem", "core_mem";
2681
2682			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2683					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2684			interrupt-names = "hc_irq", "pwr_irq";
2685
2686			clock-names = "iface", "core", "xo";
2687			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2688				<&gcc GCC_SDCC1_APPS_CLK>,
2689				<&xo_board>;
2690
2691			pinctrl-names = "default", "sleep";
2692			pinctrl-0 = <&sdc1_state_on>;
2693			pinctrl-1 = <&sdc1_state_off>;
2694
2695			bus-width = <8>;
2696			non-removable;
2697			status = "disabled";
2698		};
2699
2700		sdhc2: sdhci@74a4900 {
2701			compatible = "qcom,sdhci-msm-v4";
2702			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2703			reg-names = "hc_mem", "core_mem";
2704
2705			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2706				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2707			interrupt-names = "hc_irq", "pwr_irq";
2708
2709			clock-names = "iface", "core", "xo";
2710			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2711				<&gcc GCC_SDCC2_APPS_CLK>,
2712				<&xo_board>;
2713
2714			pinctrl-names = "default", "sleep";
2715			pinctrl-0 = <&sdc2_state_on>;
2716			pinctrl-1 = <&sdc2_state_off>;
2717
2718			bus-width = <4>;
2719			status = "disabled";
2720		 };
2721
2722		blsp1_dma: dma-controller@7544000 {
2723			compatible = "qcom,bam-v1.7.0";
2724			reg = <0x07544000 0x2b000>;
2725			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2726			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2727			clock-names = "bam_clk";
2728			qcom,controlled-remotely;
2729			#dma-cells = <1>;
2730			qcom,ee = <0>;
2731		};
2732
2733		blsp1_uart2: serial@7570000 {
2734			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2735			reg = <0x07570000 0x1000>;
2736			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2737			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2738				 <&gcc GCC_BLSP1_AHB_CLK>;
2739			clock-names = "core", "iface";
2740			pinctrl-names = "default", "sleep";
2741			pinctrl-0 = <&blsp1_uart2_default>;
2742			pinctrl-1 = <&blsp1_uart2_sleep>;
2743			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2744			dma-names = "tx", "rx";
2745			status = "disabled";
2746		};
2747
2748		blsp1_spi1: spi@7575000 {
2749			compatible = "qcom,spi-qup-v2.2.1";
2750			reg = <0x07575000 0x600>;
2751			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2752			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2753				 <&gcc GCC_BLSP1_AHB_CLK>;
2754			clock-names = "core", "iface";
2755			pinctrl-names = "default", "sleep";
2756			pinctrl-0 = <&blsp1_spi1_default>;
2757			pinctrl-1 = <&blsp1_spi1_sleep>;
2758			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2759			dma-names = "tx", "rx";
2760			#address-cells = <1>;
2761			#size-cells = <0>;
2762			status = "disabled";
2763		};
2764
2765		blsp1_i2c3: i2c@7577000 {
2766			compatible = "qcom,i2c-qup-v2.2.1";
2767			reg = <0x07577000 0x1000>;
2768			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2769			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2770				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2771			clock-names = "iface", "core";
2772			pinctrl-names = "default", "sleep";
2773			pinctrl-0 = <&blsp1_i2c3_default>;
2774			pinctrl-1 = <&blsp1_i2c3_sleep>;
2775			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2776			dma-names = "tx", "rx";
2777			#address-cells = <1>;
2778			#size-cells = <0>;
2779			status = "disabled";
2780		};
2781
2782		blsp2_dma: dma-controller@7584000 {
2783			compatible = "qcom,bam-v1.7.0";
2784			reg = <0x07584000 0x2b000>;
2785			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2786			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2787			clock-names = "bam_clk";
2788			qcom,controlled-remotely;
2789			#dma-cells = <1>;
2790			qcom,ee = <0>;
2791		};
2792
2793		blsp2_uart2: serial@75b0000 {
2794			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2795			reg = <0x075b0000 0x1000>;
2796			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2797			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2798				 <&gcc GCC_BLSP2_AHB_CLK>;
2799			clock-names = "core", "iface";
2800			status = "disabled";
2801		};
2802
2803		blsp2_uart3: serial@75b1000 {
2804			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2805			reg = <0x075b1000 0x1000>;
2806			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2807			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2808				 <&gcc GCC_BLSP2_AHB_CLK>;
2809			clock-names = "core", "iface";
2810			status = "disabled";
2811		};
2812
2813		blsp2_i2c1: i2c@75b5000 {
2814			compatible = "qcom,i2c-qup-v2.2.1";
2815			reg = <0x075b5000 0x1000>;
2816			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2817			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2818				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2819			clock-names = "iface", "core";
2820			pinctrl-names = "default", "sleep";
2821			pinctrl-0 = <&blsp2_i2c1_default>;
2822			pinctrl-1 = <&blsp2_i2c1_sleep>;
2823			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2824			dma-names = "tx", "rx";
2825			#address-cells = <1>;
2826			#size-cells = <0>;
2827			status = "disabled";
2828		};
2829
2830		blsp2_i2c2: i2c@75b6000 {
2831			compatible = "qcom,i2c-qup-v2.2.1";
2832			reg = <0x075b6000 0x1000>;
2833			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2834			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2835				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2836			clock-names = "iface", "core";
2837			pinctrl-names = "default", "sleep";
2838			pinctrl-0 = <&blsp2_i2c2_default>;
2839			pinctrl-1 = <&blsp2_i2c2_sleep>;
2840			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2841			dma-names = "tx", "rx";
2842			#address-cells = <1>;
2843			#size-cells = <0>;
2844			status = "disabled";
2845		};
2846
2847		blsp2_i2c3: i2c@75b7000 {
2848			compatible = "qcom,i2c-qup-v2.2.1";
2849			reg = <0x075b7000 0x1000>;
2850			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2851			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2852				<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
2853			clock-names = "iface", "core";
2854			clock-frequency = <400000>;
2855			pinctrl-names = "default", "sleep";
2856			pinctrl-0 = <&blsp2_i2c3_default>;
2857			pinctrl-1 = <&blsp2_i2c3_sleep>;
2858			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2859			dma-names = "tx", "rx";
2860			#address-cells = <1>;
2861			#size-cells = <0>;
2862			status = "disabled";
2863		};
2864
2865		blsp2_i2c5: i2c@75b9000 {
2866			compatible = "qcom,i2c-qup-v2.2.1";
2867			reg = <0x75b9000 0x1000>;
2868			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2869			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2870				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2871			clock-names = "iface", "core";
2872			pinctrl-names = "default";
2873			pinctrl-0 = <&blsp2_i2c5_default>;
2874			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2875			dma-names = "tx", "rx";
2876			#address-cells = <1>;
2877			#size-cells = <0>;
2878			status = "disabled";
2879		};
2880
2881		blsp2_i2c6: i2c@75ba000 {
2882			compatible = "qcom,i2c-qup-v2.2.1";
2883			reg = <0x75ba000 0x1000>;
2884			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2885			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2886				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2887			clock-names = "iface", "core";
2888			pinctrl-names = "default", "sleep";
2889			pinctrl-0 = <&blsp2_i2c6_default>;
2890			pinctrl-1 = <&blsp2_i2c6_sleep>;
2891			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2892			dma-names = "tx", "rx";
2893			#address-cells = <1>;
2894			#size-cells = <0>;
2895			status = "disabled";
2896		};
2897
2898		blsp2_spi6: spi@75ba000{
2899			compatible = "qcom,spi-qup-v2.2.1";
2900			reg = <0x075ba000 0x600>;
2901			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2902			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2903				 <&gcc GCC_BLSP2_AHB_CLK>;
2904			clock-names = "core", "iface";
2905			pinctrl-names = "default", "sleep";
2906			pinctrl-0 = <&blsp2_spi6_default>;
2907			pinctrl-1 = <&blsp2_spi6_sleep>;
2908			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2909			dma-names = "tx", "rx";
2910			#address-cells = <1>;
2911			#size-cells = <0>;
2912			status = "disabled";
2913		};
2914
2915		usb2: usb@76f8800 {
2916			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2917			reg = <0x076f8800 0x400>;
2918			#address-cells = <1>;
2919			#size-cells = <1>;
2920			ranges;
2921
2922			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2923				<&gcc GCC_USB20_MASTER_CLK>,
2924				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2925				<&gcc GCC_USB20_SLEEP_CLK>,
2926				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2927
2928			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2929					  <&gcc GCC_USB20_MASTER_CLK>;
2930			assigned-clock-rates = <19200000>, <60000000>;
2931
2932			power-domains = <&gcc USB30_GDSC>;
2933			qcom,select-utmi-as-pipe-clk;
2934			status = "disabled";
2935
2936			dwc3@7600000 {
2937				compatible = "snps,dwc3";
2938				reg = <0x07600000 0xcc00>;
2939				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2940				phys = <&hsusb_phy2>;
2941				phy-names = "usb2-phy";
2942				maximum-speed = "high-speed";
2943				snps,dis_u2_susphy_quirk;
2944				snps,dis_enblslpm_quirk;
2945			};
2946		};
2947
2948		slimbam: dma-controller@9184000 {
2949			compatible = "qcom,bam-v1.7.0";
2950			qcom,controlled-remotely;
2951			reg = <0x09184000 0x32000>;
2952			num-channels  = <31>;
2953			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2954			#dma-cells = <1>;
2955			qcom,ee = <1>;
2956			qcom,num-ees = <2>;
2957		};
2958
2959		slim_msm: slim@91c0000 {
2960			compatible = "qcom,slim-ngd-v1.5.0";
2961			reg = <0x091c0000 0x2C000>;
2962			reg-names = "ctrl";
2963			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2964			dmas =	<&slimbam 3>, <&slimbam 4>,
2965				<&slimbam 5>, <&slimbam 6>;
2966			dma-names = "rx", "tx", "tx2", "rx2";
2967			#address-cells = <1>;
2968			#size-cells = <0>;
2969			ngd@1 {
2970				reg = <1>;
2971				#address-cells = <1>;
2972				#size-cells = <1>;
2973
2974				tasha_ifd: tas-ifd {
2975					compatible = "slim217,1a0";
2976					reg  = <0 0>;
2977				};
2978
2979				wcd9335: codec@1{
2980					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2981					pinctrl-names = "default";
2982
2983					compatible = "slim217,1a0";
2984					reg  = <1 0>;
2985
2986					interrupt-parent = <&tlmm>;
2987					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2988						     <53 IRQ_TYPE_LEVEL_HIGH>;
2989					interrupt-names  = "intr1", "intr2";
2990					interrupt-controller;
2991					#interrupt-cells = <1>;
2992					reset-gpios = <&tlmm 64 0>;
2993
2994					slim-ifc-dev  = <&tasha_ifd>;
2995
2996					#sound-dai-cells = <1>;
2997				};
2998			};
2999		};
3000
3001		adsp_pil: remoteproc@9300000 {
3002			compatible = "qcom,msm8996-adsp-pil";
3003			reg = <0x09300000 0x80000>;
3004
3005			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3006					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3007					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3008					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3009					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3010			interrupt-names = "wdog", "fatal", "ready",
3011					  "handover", "stop-ack";
3012
3013			clocks = <&xo_board>;
3014			clock-names = "xo";
3015
3016			memory-region = <&adsp_region>;
3017
3018			qcom,smem-states = <&smp2p_adsp_out 0>;
3019			qcom,smem-state-names = "stop";
3020
3021			power-domains = <&rpmpd MSM8996_VDDCX>;
3022			power-domain-names = "cx";
3023
3024			status = "disabled";
3025
3026			smd-edge {
3027				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3028
3029				label = "lpass";
3030				mboxes = <&apcs_glb 8>;
3031				qcom,smd-edge = <1>;
3032				qcom,remote-pid = <2>;
3033				#address-cells = <1>;
3034				#size-cells = <0>;
3035				apr {
3036					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3037					compatible = "qcom,apr-v2";
3038					qcom,smd-channels = "apr_audio_svc";
3039					qcom,apr-domain = <APR_DOMAIN_ADSP>;
3040					#address-cells = <1>;
3041					#size-cells = <0>;
3042
3043					q6core {
3044						reg = <APR_SVC_ADSP_CORE>;
3045						compatible = "qcom,q6core";
3046					};
3047
3048					q6afe: q6afe {
3049						compatible = "qcom,q6afe";
3050						reg = <APR_SVC_AFE>;
3051						q6afedai: dais {
3052							compatible = "qcom,q6afe-dais";
3053							#address-cells = <1>;
3054							#size-cells = <0>;
3055							#sound-dai-cells = <1>;
3056							hdmi@1 {
3057								reg = <1>;
3058							};
3059						};
3060					};
3061
3062					q6asm: q6asm {
3063						compatible = "qcom,q6asm";
3064						reg = <APR_SVC_ASM>;
3065						q6asmdai: dais {
3066							compatible = "qcom,q6asm-dais";
3067							#address-cells = <1>;
3068							#size-cells = <0>;
3069							#sound-dai-cells = <1>;
3070							iommus = <&lpass_q6_smmu 1>;
3071						};
3072					};
3073
3074					q6adm: q6adm {
3075						compatible = "qcom,q6adm";
3076						reg = <APR_SVC_ADM>;
3077						q6routing: routing {
3078							compatible = "qcom,q6adm-routing";
3079							#sound-dai-cells = <0>;
3080						};
3081					};
3082				};
3083
3084			};
3085		};
3086
3087		apcs_glb: mailbox@9820000 {
3088			compatible = "qcom,msm8996-apcs-hmss-global";
3089			reg = <0x09820000 0x1000>;
3090
3091			#mbox-cells = <1>;
3092		};
3093
3094		timer@9840000 {
3095			#address-cells = <1>;
3096			#size-cells = <1>;
3097			ranges;
3098			compatible = "arm,armv7-timer-mem";
3099			reg = <0x09840000 0x1000>;
3100			clock-frequency = <19200000>;
3101
3102			frame@9850000 {
3103				frame-number = <0>;
3104				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3105					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3106				reg = <0x09850000 0x1000>,
3107				      <0x09860000 0x1000>;
3108			};
3109
3110			frame@9870000 {
3111				frame-number = <1>;
3112				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3113				reg = <0x09870000 0x1000>;
3114				status = "disabled";
3115			};
3116
3117			frame@9880000 {
3118				frame-number = <2>;
3119				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3120				reg = <0x09880000 0x1000>;
3121				status = "disabled";
3122			};
3123
3124			frame@9890000 {
3125				frame-number = <3>;
3126				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3127				reg = <0x09890000 0x1000>;
3128				status = "disabled";
3129			};
3130
3131			frame@98a0000 {
3132				frame-number = <4>;
3133				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3134				reg = <0x098a0000 0x1000>;
3135				status = "disabled";
3136			};
3137
3138			frame@98b0000 {
3139				frame-number = <5>;
3140				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3141				reg = <0x098b0000 0x1000>;
3142				status = "disabled";
3143			};
3144
3145			frame@98c0000 {
3146				frame-number = <6>;
3147				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3148				reg = <0x098c0000 0x1000>;
3149				status = "disabled";
3150			};
3151		};
3152
3153		saw3: syscon@9a10000 {
3154			compatible = "syscon";
3155			reg = <0x09a10000 0x1000>;
3156		};
3157
3158		intc: interrupt-controller@9bc0000 {
3159			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3160			#interrupt-cells = <3>;
3161			interrupt-controller;
3162			#redistributor-regions = <1>;
3163			redistributor-stride = <0x0 0x40000>;
3164			reg = <0x09bc0000 0x10000>,
3165			      <0x09c00000 0x100000>;
3166			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3167		};
3168	};
3169
3170	sound: sound {
3171	};
3172
3173	thermal-zones {
3174		cpu0-thermal {
3175			polling-delay-passive = <250>;
3176			polling-delay = <1000>;
3177
3178			thermal-sensors = <&tsens0 3>;
3179
3180			trips {
3181				cpu0_alert0: trip-point0 {
3182					temperature = <75000>;
3183					hysteresis = <2000>;
3184					type = "passive";
3185				};
3186
3187				cpu0_crit: cpu_crit {
3188					temperature = <110000>;
3189					hysteresis = <2000>;
3190					type = "critical";
3191				};
3192			};
3193		};
3194
3195		cpu1-thermal {
3196			polling-delay-passive = <250>;
3197			polling-delay = <1000>;
3198
3199			thermal-sensors = <&tsens0 5>;
3200
3201			trips {
3202				cpu1_alert0: trip-point0 {
3203					temperature = <75000>;
3204					hysteresis = <2000>;
3205					type = "passive";
3206				};
3207
3208				cpu1_crit: cpu_crit {
3209					temperature = <110000>;
3210					hysteresis = <2000>;
3211					type = "critical";
3212				};
3213			};
3214		};
3215
3216		cpu2-thermal {
3217			polling-delay-passive = <250>;
3218			polling-delay = <1000>;
3219
3220			thermal-sensors = <&tsens0 8>;
3221
3222			trips {
3223				cpu2_alert0: trip-point0 {
3224					temperature = <75000>;
3225					hysteresis = <2000>;
3226					type = "passive";
3227				};
3228
3229				cpu2_crit: cpu_crit {
3230					temperature = <110000>;
3231					hysteresis = <2000>;
3232					type = "critical";
3233				};
3234			};
3235		};
3236
3237		cpu3-thermal {
3238			polling-delay-passive = <250>;
3239			polling-delay = <1000>;
3240
3241			thermal-sensors = <&tsens0 10>;
3242
3243			trips {
3244				cpu3_alert0: trip-point0 {
3245					temperature = <75000>;
3246					hysteresis = <2000>;
3247					type = "passive";
3248				};
3249
3250				cpu3_crit: cpu_crit {
3251					temperature = <110000>;
3252					hysteresis = <2000>;
3253					type = "critical";
3254				};
3255			};
3256		};
3257
3258		gpu-thermal-top {
3259			polling-delay-passive = <250>;
3260			polling-delay = <1000>;
3261
3262			thermal-sensors = <&tsens1 6>;
3263
3264			trips {
3265				gpu1_alert0: trip-point0 {
3266					temperature = <90000>;
3267					hysteresis = <2000>;
3268					type = "passive";
3269				};
3270			};
3271
3272			cooling-maps {
3273				map0 {
3274					trip = <&gpu1_alert0>;
3275					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3276				};
3277			};
3278		};
3279
3280		gpu-thermal-bottom {
3281			polling-delay-passive = <250>;
3282			polling-delay = <1000>;
3283
3284			thermal-sensors = <&tsens1 7>;
3285
3286			trips {
3287				gpu2_alert0: trip-point0 {
3288					temperature = <90000>;
3289					hysteresis = <2000>;
3290					type = "passive";
3291				};
3292			};
3293
3294			cooling-maps {
3295				map0 {
3296					trip = <&gpu2_alert0>;
3297					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3298				};
3299			};
3300		};
3301
3302		m4m-thermal {
3303			polling-delay-passive = <250>;
3304			polling-delay = <1000>;
3305
3306			thermal-sensors = <&tsens0 1>;
3307
3308			trips {
3309				m4m_alert0: trip-point0 {
3310					temperature = <90000>;
3311					hysteresis = <2000>;
3312					type = "hot";
3313				};
3314			};
3315		};
3316
3317		l3-or-venus-thermal {
3318			polling-delay-passive = <250>;
3319			polling-delay = <1000>;
3320
3321			thermal-sensors = <&tsens0 2>;
3322
3323			trips {
3324				l3_or_venus_alert0: trip-point0 {
3325					temperature = <90000>;
3326					hysteresis = <2000>;
3327					type = "hot";
3328				};
3329			};
3330		};
3331
3332		cluster0-l2-thermal {
3333			polling-delay-passive = <250>;
3334			polling-delay = <1000>;
3335
3336			thermal-sensors = <&tsens0 7>;
3337
3338			trips {
3339				cluster0_l2_alert0: trip-point0 {
3340					temperature = <90000>;
3341					hysteresis = <2000>;
3342					type = "hot";
3343				};
3344			};
3345		};
3346
3347		cluster1-l2-thermal {
3348			polling-delay-passive = <250>;
3349			polling-delay = <1000>;
3350
3351			thermal-sensors = <&tsens0 12>;
3352
3353			trips {
3354				cluster1_l2_alert0: trip-point0 {
3355					temperature = <90000>;
3356					hysteresis = <2000>;
3357					type = "hot";
3358				};
3359			};
3360		};
3361
3362		camera-thermal {
3363			polling-delay-passive = <250>;
3364			polling-delay = <1000>;
3365
3366			thermal-sensors = <&tsens1 1>;
3367
3368			trips {
3369				camera_alert0: trip-point0 {
3370					temperature = <90000>;
3371					hysteresis = <2000>;
3372					type = "hot";
3373				};
3374			};
3375		};
3376
3377		q6-dsp-thermal {
3378			polling-delay-passive = <250>;
3379			polling-delay = <1000>;
3380
3381			thermal-sensors = <&tsens1 2>;
3382
3383			trips {
3384				q6_dsp_alert0: trip-point0 {
3385					temperature = <90000>;
3386					hysteresis = <2000>;
3387					type = "hot";
3388				};
3389			};
3390		};
3391
3392		mem-thermal {
3393			polling-delay-passive = <250>;
3394			polling-delay = <1000>;
3395
3396			thermal-sensors = <&tsens1 3>;
3397
3398			trips {
3399				mem_alert0: trip-point0 {
3400					temperature = <90000>;
3401					hysteresis = <2000>;
3402					type = "hot";
3403				};
3404			};
3405		};
3406
3407		modemtx-thermal {
3408			polling-delay-passive = <250>;
3409			polling-delay = <1000>;
3410
3411			thermal-sensors = <&tsens1 4>;
3412
3413			trips {
3414				modemtx_alert0: trip-point0 {
3415					temperature = <90000>;
3416					hysteresis = <2000>;
3417					type = "hot";
3418				};
3419			};
3420		};
3421	};
3422
3423	timer {
3424		compatible = "arm,armv8-timer";
3425		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3426			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3427			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3428			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3429	};
3430};
3431