xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision 405db98b) 
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x77>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x77>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x77>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x77>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x77>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x77>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x77>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x77>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x77>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x77>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x77>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x77>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x77>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1401600000 {
209			opp-hz = /bits/ 64 <1401600000>;
210			opp-supported-hw = <0x77>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1478400000 {
214			opp-hz = /bits/ 64 <1478400000>;
215			opp-supported-hw = <0x77>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1593600000 {
219			opp-hz = /bits/ 64 <1593600000>;
220			opp-supported-hw = <0x77>;
221			clock-latency-ns = <200000>;
222		};
223	};
224
225	cluster1_opp: opp_table1 {
226		compatible = "operating-points-v2-kryo-cpu";
227		nvmem-cells = <&speedbin_efuse>;
228		opp-shared;
229
230		/* Nominal fmax for now */
231		opp-307200000 {
232			opp-hz = /bits/ 64 <307200000>;
233			opp-supported-hw = <0x77>;
234			clock-latency-ns = <200000>;
235		};
236		opp-403200000 {
237			opp-hz = /bits/ 64 <403200000>;
238			opp-supported-hw = <0x77>;
239			clock-latency-ns = <200000>;
240		};
241		opp-480000000 {
242			opp-hz = /bits/ 64 <480000000>;
243			opp-supported-hw = <0x77>;
244			clock-latency-ns = <200000>;
245		};
246		opp-556800000 {
247			opp-hz = /bits/ 64 <556800000>;
248			opp-supported-hw = <0x77>;
249			clock-latency-ns = <200000>;
250		};
251		opp-652800000 {
252			opp-hz = /bits/ 64 <652800000>;
253			opp-supported-hw = <0x77>;
254			clock-latency-ns = <200000>;
255		};
256		opp-729600000 {
257			opp-hz = /bits/ 64 <729600000>;
258			opp-supported-hw = <0x77>;
259			clock-latency-ns = <200000>;
260		};
261		opp-806400000 {
262			opp-hz = /bits/ 64 <806400000>;
263			opp-supported-hw = <0x77>;
264			clock-latency-ns = <200000>;
265		};
266		opp-883200000 {
267			opp-hz = /bits/ 64 <883200000>;
268			opp-supported-hw = <0x77>;
269			clock-latency-ns = <200000>;
270		};
271		opp-940800000 {
272			opp-hz = /bits/ 64 <940800000>;
273			opp-supported-hw = <0x77>;
274			clock-latency-ns = <200000>;
275		};
276		opp-1036800000 {
277			opp-hz = /bits/ 64 <1036800000>;
278			opp-supported-hw = <0x77>;
279			clock-latency-ns = <200000>;
280		};
281		opp-1113600000 {
282			opp-hz = /bits/ 64 <1113600000>;
283			opp-supported-hw = <0x77>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1190400000 {
287			opp-hz = /bits/ 64 <1190400000>;
288			opp-supported-hw = <0x77>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1248000000 {
292			opp-hz = /bits/ 64 <1248000000>;
293			opp-supported-hw = <0x77>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1324800000 {
297			opp-hz = /bits/ 64 <1324800000>;
298			opp-supported-hw = <0x77>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1401600000 {
302			opp-hz = /bits/ 64 <1401600000>;
303			opp-supported-hw = <0x77>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1478400000 {
307			opp-hz = /bits/ 64 <1478400000>;
308			opp-supported-hw = <0x77>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1555200000 {
312			opp-hz = /bits/ 64 <1555200000>;
313			opp-supported-hw = <0x77>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1632000000 {
317			opp-hz = /bits/ 64 <1632000000>;
318			opp-supported-hw = <0x77>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1708800000 {
322			opp-hz = /bits/ 64 <1708800000>;
323			opp-supported-hw = <0x77>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1785600000 {
327			opp-hz = /bits/ 64 <1785600000>;
328			opp-supported-hw = <0x77>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1824000000 {
332			opp-hz = /bits/ 64 <1824000000>;
333			opp-supported-hw = <0x77>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1920000000 {
337			opp-hz = /bits/ 64 <1920000000>;
338			opp-supported-hw = <0x77>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1996800000 {
342			opp-hz = /bits/ 64 <1996800000>;
343			opp-supported-hw = <0x77>;
344			clock-latency-ns = <200000>;
345		};
346		opp-2073600000 {
347			opp-hz = /bits/ 64 <2073600000>;
348			opp-supported-hw = <0x77>;
349			clock-latency-ns = <200000>;
350		};
351		opp-2150400000 {
352			opp-hz = /bits/ 64 <2150400000>;
353			opp-supported-hw = <0x77>;
354			clock-latency-ns = <200000>;
355		};
356	};
357
358	firmware {
359		scm {
360			compatible = "qcom,scm-msm8996";
361			qcom,dload-mode = <&tcsr 0x13000>;
362		};
363	};
364
365	tcsr_mutex: hwlock {
366		compatible = "qcom,tcsr-mutex";
367		syscon = <&tcsr_mutex_regs 0 0x1000>;
368		#hwlock-cells = <1>;
369	};
370
371	memory@80000000 {
372		device_type = "memory";
373		/* We expect the bootloader to fill in the reg */
374		reg = <0x0 0x80000000 0x0 0x0>;
375	};
376
377	psci {
378		compatible = "arm,psci-1.0";
379		method = "smc";
380	};
381
382	reserved-memory {
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges;
386
387		mba_region: mba@91500000 {
388			reg = <0x0 0x91500000 0x0 0x200000>;
389			no-map;
390		};
391
392		slpi_region: slpi@90b00000 {
393			reg = <0x0 0x90b00000 0x0 0xa00000>;
394			no-map;
395		};
396
397		venus_region: venus@90400000 {
398			reg = <0x0 0x90400000 0x0 0x700000>;
399			no-map;
400		};
401
402		adsp_region: adsp@8ea00000 {
403			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
404			no-map;
405		};
406
407		mpss_region: mpss@88800000 {
408			reg = <0x0 0x88800000 0x0 0x6200000>;
409			no-map;
410		};
411
412		smem_mem: smem-mem@86000000 {
413			reg = <0x0 0x86000000 0x0 0x200000>;
414			no-map;
415		};
416
417		memory@85800000 {
418			reg = <0x0 0x85800000 0x0 0x800000>;
419			no-map;
420		};
421
422		memory@86200000 {
423			reg = <0x0 0x86200000 0x0 0x2600000>;
424			no-map;
425		};
426
427		rmtfs@86700000 {
428			compatible = "qcom,rmtfs-mem";
429
430			size = <0x0 0x200000>;
431			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432			no-map;
433
434			qcom,client-id = <1>;
435			qcom,vmid = <15>;
436		};
437
438		zap_shader_region: gpu@8f200000 {
439			compatible = "shared-dma-pool";
440			reg = <0x0 0x90b00000 0x0 0xa00000>;
441			no-map;
442		};
443	};
444
445	rpm-glink {
446		compatible = "qcom,glink-rpm";
447
448		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
449
450		qcom,rpm-msg-ram = <&rpm_msg_ram>;
451
452		mboxes = <&apcs_glb 0>;
453
454		rpm_requests: rpm-requests {
455			compatible = "qcom,rpm-msm8996";
456			qcom,glink-channels = "rpm_requests";
457
458			rpmcc: qcom,rpmcc {
459				compatible = "qcom,rpmcc-msm8996";
460				#clock-cells = <1>;
461			};
462
463			rpmpd: power-controller {
464				compatible = "qcom,msm8996-rpmpd";
465				#power-domain-cells = <1>;
466				operating-points-v2 = <&rpmpd_opp_table>;
467
468				rpmpd_opp_table: opp-table {
469					compatible = "operating-points-v2";
470
471					rpmpd_opp1: opp1 {
472						opp-level = <1>;
473					};
474
475					rpmpd_opp2: opp2 {
476						opp-level = <2>;
477					};
478
479					rpmpd_opp3: opp3 {
480						opp-level = <3>;
481					};
482
483					rpmpd_opp4: opp4 {
484						opp-level = <4>;
485					};
486
487					rpmpd_opp5: opp5 {
488						opp-level = <5>;
489					};
490
491					rpmpd_opp6: opp6 {
492						opp-level = <6>;
493					};
494				};
495			};
496		};
497	};
498
499	smem {
500		compatible = "qcom,smem";
501		memory-region = <&smem_mem>;
502		hwlocks = <&tcsr_mutex 3>;
503	};
504
505	smp2p-adsp {
506		compatible = "qcom,smp2p";
507		qcom,smem = <443>, <429>;
508
509		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
510
511		mboxes = <&apcs_glb 10>;
512
513		qcom,local-pid = <0>;
514		qcom,remote-pid = <2>;
515
516		smp2p_adsp_out: master-kernel {
517			qcom,entry-name = "master-kernel";
518			#qcom,smem-state-cells = <1>;
519		};
520
521		smp2p_adsp_in: slave-kernel {
522			qcom,entry-name = "slave-kernel";
523
524			interrupt-controller;
525			#interrupt-cells = <2>;
526		};
527	};
528
529	smp2p-modem {
530		compatible = "qcom,smp2p";
531		qcom,smem = <435>, <428>;
532
533		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
534
535		mboxes = <&apcs_glb 14>;
536
537		qcom,local-pid = <0>;
538		qcom,remote-pid = <1>;
539
540		modem_smp2p_out: master-kernel {
541			qcom,entry-name = "master-kernel";
542			#qcom,smem-state-cells = <1>;
543		};
544
545		modem_smp2p_in: slave-kernel {
546			qcom,entry-name = "slave-kernel";
547
548			interrupt-controller;
549			#interrupt-cells = <2>;
550		};
551	};
552
553	smp2p-slpi {
554		compatible = "qcom,smp2p";
555		qcom,smem = <481>, <430>;
556
557		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
558
559		mboxes = <&apcs_glb 26>;
560
561		qcom,local-pid = <0>;
562		qcom,remote-pid = <3>;
563
564		smp2p_slpi_in: slave-kernel {
565			qcom,entry-name = "slave-kernel";
566			interrupt-controller;
567			#interrupt-cells = <2>;
568		};
569
570		smp2p_slpi_out: master-kernel {
571			qcom,entry-name = "master-kernel";
572			#qcom,smem-state-cells = <1>;
573		};
574	};
575
576	soc: soc {
577		#address-cells = <1>;
578		#size-cells = <1>;
579		ranges = <0 0 0 0xffffffff>;
580		compatible = "simple-bus";
581
582		pcie_phy: phy@34000 {
583			compatible = "qcom,msm8996-qmp-pcie-phy";
584			reg = <0x00034000 0x488>;
585			#address-cells = <1>;
586			#size-cells = <1>;
587			ranges;
588
589			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
590				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
591				<&gcc GCC_PCIE_CLKREF_CLK>;
592			clock-names = "aux", "cfg_ahb", "ref";
593
594			resets = <&gcc GCC_PCIE_PHY_BCR>,
595				<&gcc GCC_PCIE_PHY_COM_BCR>,
596				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
597			reset-names = "phy", "common", "cfg";
598			status = "disabled";
599
600			pciephy_0: phy@35000 {
601				reg = <0x00035000 0x130>,
602				      <0x00035200 0x200>,
603				      <0x00035400 0x1dc>;
604				#phy-cells = <0>;
605
606				#clock-cells = <1>;
607				clock-output-names = "pcie_0_pipe_clk_src";
608				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609				clock-names = "pipe0";
610				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611				reset-names = "lane0";
612			};
613
614			pciephy_1: phy@36000 {
615				reg = <0x00036000 0x130>,
616				      <0x00036200 0x200>,
617				      <0x00036400 0x1dc>;
618				#phy-cells = <0>;
619
620				clock-output-names = "pcie_1_pipe_clk_src";
621				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622				clock-names = "pipe1";
623				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624				reset-names = "lane1";
625			};
626
627			pciephy_2: phy@37000 {
628				reg = <0x00037000 0x130>,
629				      <0x00037200 0x200>,
630				      <0x00037400 0x1dc>;
631				#phy-cells = <0>;
632
633				clock-output-names = "pcie_2_pipe_clk_src";
634				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635				clock-names = "pipe2";
636				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637				reset-names = "lane2";
638			};
639		};
640
641		rpm_msg_ram: sram@68000 {
642			compatible = "qcom,rpm-msg-ram";
643			reg = <0x00068000 0x6000>;
644		};
645
646		qfprom@74000 {
647			compatible = "qcom,qfprom";
648			reg = <0x00074000 0x8ff>;
649			#address-cells = <1>;
650			#size-cells = <1>;
651
652			qusb2p_hstx_trim: hstx_trim@24e {
653				reg = <0x24e 0x2>;
654				bits = <5 4>;
655			};
656
657			qusb2s_hstx_trim: hstx_trim@24f {
658				reg = <0x24f 0x1>;
659				bits = <1 4>;
660			};
661
662			speedbin_efuse: speedbin@133 {
663				reg = <0x133 0x1>;
664				bits = <5 3>;
665			};
666		};
667
668		rng: rng@83000 {
669			compatible = "qcom,prng-ee";
670			reg = <0x00083000 0x1000>;
671			clocks = <&gcc GCC_PRNG_AHB_CLK>;
672			clock-names = "core";
673		};
674
675		gcc: clock-controller@300000 {
676			compatible = "qcom,gcc-msm8996";
677			#clock-cells = <1>;
678			#reset-cells = <1>;
679			#power-domain-cells = <1>;
680			reg = <0x00300000 0x90000>;
681
682			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683			clock-names = "cxo2";
684		};
685
686		tsens0: thermal-sensor@4a9000 {
687			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688			reg = <0x004a9000 0x1000>, /* TM */
689			      <0x004a8000 0x1000>; /* SROT */
690			#qcom,sensors = <13>;
691			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693			interrupt-names = "uplow", "critical";
694			#thermal-sensor-cells = <1>;
695		};
696
697		tsens1: thermal-sensor@4ad000 {
698			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699			reg = <0x004ad000 0x1000>, /* TM */
700			      <0x004ac000 0x1000>; /* SROT */
701			#qcom,sensors = <8>;
702			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "uplow", "critical";
705			#thermal-sensor-cells = <1>;
706		};
707
708		cryptobam: dma@644000 {
709			compatible = "qcom,bam-v1.7.0";
710			reg = <0x00644000 0x24000>;
711			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
712			clocks = <&gcc GCC_CE1_CLK>;
713			clock-names = "bam_clk";
714			#dma-cells = <1>;
715			qcom,ee = <0>;
716			qcom,controlled-remotely = <1>;
717		};
718
719		crypto: crypto@67a000 {
720			compatible = "qcom,crypto-v5.4";
721			reg = <0x0067a000 0x6000>;
722			clocks = <&gcc GCC_CE1_AHB_CLK>,
723				 <&gcc GCC_CE1_AXI_CLK>,
724				 <&gcc GCC_CE1_CLK>;
725			clock-names = "iface", "bus", "core";
726			dmas = <&cryptobam 6>, <&cryptobam 7>;
727			dma-names = "rx", "tx";
728		};
729
730		tcsr_mutex_regs: syscon@740000 {
731			compatible = "syscon";
732			reg = <0x00740000 0x40000>;
733		};
734
735		tcsr: syscon@7a0000 {
736			compatible = "qcom,tcsr-msm8996", "syscon";
737			reg = <0x007a0000 0x18000>;
738		};
739
740		mmcc: clock-controller@8c0000 {
741			compatible = "qcom,mmcc-msm8996";
742			#clock-cells = <1>;
743			#reset-cells = <1>;
744			#power-domain-cells = <1>;
745			reg = <0x008c0000 0x40000>;
746			assigned-clocks = <&mmcc MMPLL9_PLL>,
747					  <&mmcc MMPLL1_PLL>,
748					  <&mmcc MMPLL3_PLL>,
749					  <&mmcc MMPLL4_PLL>,
750					  <&mmcc MMPLL5_PLL>;
751			assigned-clock-rates = <624000000>,
752					       <810000000>,
753					       <980000000>,
754					       <960000000>,
755					       <825000000>;
756		};
757
758		mdss: mdss@900000 {
759			compatible = "qcom,mdss";
760
761			reg = <0x00900000 0x1000>,
762			      <0x009b0000 0x1040>,
763			      <0x009b8000 0x1040>;
764			reg-names = "mdss_phys",
765				    "vbif_phys",
766				    "vbif_nrt_phys";
767
768			power-domains = <&mmcc MDSS_GDSC>;
769			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
770
771			interrupt-controller;
772			#interrupt-cells = <1>;
773
774			clocks = <&mmcc MDSS_AHB_CLK>;
775			clock-names = "iface";
776
777			#address-cells = <1>;
778			#size-cells = <1>;
779			ranges;
780
781			status = "disabled";
782
783			mdp: mdp@901000 {
784				compatible = "qcom,mdp5";
785				reg = <0x00901000 0x90000>;
786				reg-names = "mdp_phys";
787
788				interrupt-parent = <&mdss>;
789				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
790
791				clocks = <&mmcc MDSS_AHB_CLK>,
792					 <&mmcc MDSS_AXI_CLK>,
793					 <&mmcc MDSS_MDP_CLK>,
794					 <&mmcc SMMU_MDP_AXI_CLK>,
795					 <&mmcc MDSS_VSYNC_CLK>;
796				clock-names = "iface",
797					      "bus",
798					      "core",
799					      "iommu",
800					      "vsync";
801
802				iommus = <&mdp_smmu 0>;
803
804				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
805					 <&mmcc MDSS_VSYNC_CLK>;
806				assigned-clock-rates = <300000000>,
807					 <19200000>;
808
809				ports {
810					#address-cells = <1>;
811					#size-cells = <0>;
812
813					port@0 {
814						reg = <0>;
815						mdp5_intf3_out: endpoint {
816							remote-endpoint = <&hdmi_in>;
817						};
818					};
819
820					port@1 {
821						reg = <1>;
822						mdp5_intf1_out: endpoint {
823							remote-endpoint = <&dsi0_in>;
824						};
825					};
826				};
827			};
828
829			dsi0: dsi@994000 {
830				compatible = "qcom,mdss-dsi-ctrl";
831				reg = <0x00994000 0x400>;
832				reg-names = "dsi_ctrl";
833
834				interrupt-parent = <&mdss>;
835				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
836
837				clocks = <&mmcc MDSS_MDP_CLK>,
838					 <&mmcc MDSS_BYTE0_CLK>,
839					 <&mmcc MDSS_AHB_CLK>,
840					 <&mmcc MDSS_AXI_CLK>,
841					 <&mmcc MMSS_MISC_AHB_CLK>,
842					 <&mmcc MDSS_PCLK0_CLK>,
843					 <&mmcc MDSS_ESC0_CLK>;
844				clock-names = "mdp_core",
845					      "byte",
846					      "iface",
847					      "bus",
848					      "core_mmss",
849					      "pixel",
850					      "core";
851
852				phys = <&dsi0_phy>;
853				phy-names = "dsi";
854				status = "disabled";
855
856				#address-cells = <1>;
857				#size-cells = <0>;
858
859				ports {
860					#address-cells = <1>;
861					#size-cells = <0>;
862
863					port@0 {
864						reg = <0>;
865						dsi0_in: endpoint {
866							remote-endpoint = <&mdp5_intf1_out>;
867						};
868					};
869
870					port@1 {
871						reg = <1>;
872						dsi0_out: endpoint {
873						};
874					};
875				};
876			};
877
878			dsi0_phy: dsi-phy@994400 {
879				compatible = "qcom,dsi-phy-14nm";
880				reg = <0x00994400 0x100>,
881				      <0x00994500 0x300>,
882				      <0x00994800 0x188>;
883				reg-names = "dsi_phy",
884					    "dsi_phy_lane",
885					    "dsi_pll";
886
887				#clock-cells = <1>;
888				#phy-cells = <0>;
889
890				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
891				clock-names = "iface", "ref";
892				status = "disabled";
893			};
894
895			hdmi: hdmi-tx@9a0000 {
896				compatible = "qcom,hdmi-tx-8996";
897				reg =	<0x009a0000 0x50c>,
898					<0x00070000 0x6158>,
899					<0x009e0000 0xfff>;
900				reg-names = "core_physical",
901					    "qfprom_physical",
902					    "hdcp_physical";
903
904				interrupt-parent = <&mdss>;
905				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
906
907				clocks = <&mmcc MDSS_MDP_CLK>,
908					 <&mmcc MDSS_AHB_CLK>,
909					 <&mmcc MDSS_HDMI_CLK>,
910					 <&mmcc MDSS_HDMI_AHB_CLK>,
911					 <&mmcc MDSS_EXTPCLK_CLK>;
912				clock-names =
913					"mdp_core",
914					"iface",
915					"core",
916					"alt_iface",
917					"extp";
918
919				phys = <&hdmi_phy>;
920				phy-names = "hdmi_phy";
921				#sound-dai-cells = <1>;
922
923				status = "disabled";
924
925				ports {
926					#address-cells = <1>;
927					#size-cells = <0>;
928
929					port@0 {
930						reg = <0>;
931						hdmi_in: endpoint {
932							remote-endpoint = <&mdp5_intf3_out>;
933						};
934					};
935				};
936			};
937
938			hdmi_phy: hdmi-phy@9a0600 {
939				#phy-cells = <0>;
940				compatible = "qcom,hdmi-phy-8996";
941				reg = <0x009a0600 0x1c4>,
942				      <0x009a0a00 0x124>,
943				      <0x009a0c00 0x124>,
944				      <0x009a0e00 0x124>,
945				      <0x009a1000 0x124>,
946				      <0x009a1200 0x0c8>;
947				reg-names = "hdmi_pll",
948					    "hdmi_tx_l0",
949					    "hdmi_tx_l1",
950					    "hdmi_tx_l2",
951					    "hdmi_tx_l3",
952					    "hdmi_phy";
953
954				clocks = <&mmcc MDSS_AHB_CLK>,
955					 <&gcc GCC_HDMI_CLKREF_CLK>;
956				clock-names = "iface",
957					      "ref";
958
959				status = "disabled";
960			};
961		};
962
963		gpu: gpu@b00000 {
964			compatible = "qcom,adreno-530.2", "qcom,adreno";
965			#stream-id-cells = <16>;
966
967			reg = <0x00b00000 0x3f000>;
968			reg-names = "kgsl_3d0_reg_memory";
969
970			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
971
972			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
973				<&mmcc GPU_AHB_CLK>,
974				<&mmcc GPU_GX_RBBMTIMER_CLK>,
975				<&gcc GCC_BIMC_GFX_CLK>,
976				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
977
978			clock-names = "core",
979				"iface",
980				"rbbmtimer",
981				"mem",
982				"mem_iface";
983
984			power-domains = <&mmcc GPU_GX_GDSC>;
985			iommus = <&adreno_smmu 0>;
986
987			nvmem-cells = <&speedbin_efuse>;
988			nvmem-cell-names = "speed_bin";
989
990			qcom,gpu-quirk-two-pass-use-wfi;
991			qcom,gpu-quirk-fault-detect-mask;
992
993			operating-points-v2 = <&gpu_opp_table>;
994
995			status = "disabled";
996
997			#cooling-cells = <2>;
998
999			gpu_opp_table: opp-table {
1000				compatible  ="operating-points-v2";
1001
1002				/*
1003				 * 624Mhz and 560Mhz are only available on speed
1004				 * bin (1 << 0). All the rest are available on
1005				 * all bins of the hardware
1006				 */
1007				opp-624000000 {
1008					opp-hz = /bits/ 64 <624000000>;
1009					opp-supported-hw = <0x01>;
1010				};
1011				opp-560000000 {
1012					opp-hz = /bits/ 64 <560000000>;
1013					opp-supported-hw = <0x01>;
1014				};
1015				opp-510000000 {
1016					opp-hz = /bits/ 64 <510000000>;
1017					opp-supported-hw = <0xFF>;
1018				};
1019				opp-401800000 {
1020					opp-hz = /bits/ 64 <401800000>;
1021					opp-supported-hw = <0xFF>;
1022				};
1023				opp-315000000 {
1024					opp-hz = /bits/ 64 <315000000>;
1025					opp-supported-hw = <0xFF>;
1026				};
1027				opp-214000000 {
1028					opp-hz = /bits/ 64 <214000000>;
1029					opp-supported-hw = <0xFF>;
1030				};
1031				opp-133000000 {
1032					opp-hz = /bits/ 64 <133000000>;
1033					opp-supported-hw = <0xFF>;
1034				};
1035			};
1036
1037			zap-shader {
1038				memory-region = <&zap_shader_region>;
1039			};
1040		};
1041
1042		tlmm: pinctrl@1010000 {
1043			compatible = "qcom,msm8996-pinctrl";
1044			reg = <0x01010000 0x300000>;
1045			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1046			gpio-controller;
1047			gpio-ranges = <&tlmm 0 0 150>;
1048			#gpio-cells = <2>;
1049			interrupt-controller;
1050			#interrupt-cells = <2>;
1051
1052			blsp1_spi1_default: blsp1-spi1-default {
1053				spi {
1054					pins = "gpio0", "gpio1", "gpio3";
1055					function = "blsp_spi1";
1056					drive-strength = <12>;
1057					bias-disable;
1058				};
1059
1060				cs {
1061					pins = "gpio2";
1062					function = "gpio";
1063					drive-strength = <16>;
1064					bias-disable;
1065					output-high;
1066				};
1067			};
1068
1069			blsp1_spi1_sleep: blsp1-spi1-sleep {
1070				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1071				function = "gpio";
1072				drive-strength = <2>;
1073				bias-pull-down;
1074			};
1075
1076			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1077				pins = "gpio4", "gpio5";
1078				function = "blsp_uart8";
1079				drive-strength = <16>;
1080				bias-disable;
1081			};
1082
1083			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1084				pins = "gpio4", "gpio5";
1085				function = "gpio";
1086				drive-strength = <2>;
1087				bias-disable;
1088			};
1089
1090			blsp2_i2c2_default: blsp2-i2c2 {
1091				pins = "gpio6", "gpio7";
1092				function = "blsp_i2c8";
1093				drive-strength = <16>;
1094				bias-disable;
1095			};
1096
1097			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1098				pins = "gpio6", "gpio7";
1099				function = "gpio";
1100				drive-strength = <2>;
1101				bias-disable;
1102			};
1103
1104			cci0_default: cci0-default {
1105				pins = "gpio17", "gpio18";
1106				function = "cci_i2c";
1107				drive-strength = <16>;
1108				bias-disable;
1109			};
1110
1111			camera0_state_on:
1112			camera_rear_default: camera-rear-default {
1113				camera0_mclk: mclk0 {
1114					pins = "gpio13";
1115					function = "cam_mclk";
1116					drive-strength = <16>;
1117					bias-disable;
1118				};
1119
1120				camera0_rst: rst {
1121					pins = "gpio25";
1122					function = "gpio";
1123					drive-strength = <16>;
1124					bias-disable;
1125				};
1126
1127				camera0_pwdn: pwdn {
1128					pins = "gpio26";
1129					function = "gpio";
1130					drive-strength = <16>;
1131					bias-disable;
1132				};
1133			};
1134
1135			cci1_default: cci1-default {
1136				pins = "gpio19", "gpio20";
1137				function = "cci_i2c";
1138				drive-strength = <16>;
1139				bias-disable;
1140			};
1141
1142			camera1_state_on:
1143			camera_board_default: camera-board-default {
1144				mclk1 {
1145					pins = "gpio14";
1146					function = "cam_mclk";
1147					drive-strength = <16>;
1148					bias-disable;
1149				};
1150
1151				pwdn {
1152					pins = "gpio98";
1153					function = "gpio";
1154					drive-strength = <16>;
1155					bias-disable;
1156				};
1157
1158				rst {
1159					pins = "gpio104";
1160					function = "gpio";
1161					drive-strength = <16>;
1162					bias-disable;
1163				};
1164			};
1165
1166			camera2_state_on:
1167			camera_front_default: camera-front-default {
1168				camera2_mclk: mclk2 {
1169					pins = "gpio15";
1170					function = "cam_mclk";
1171					drive-strength = <16>;
1172					bias-disable;
1173				};
1174
1175				camera2_rst: rst {
1176					pins = "gpio23";
1177					function = "gpio";
1178					drive-strength = <16>;
1179					bias-disable;
1180				};
1181
1182				pwdn {
1183					pins = "gpio133";
1184					function = "gpio";
1185					drive-strength = <16>;
1186					bias-disable;
1187				};
1188			};
1189
1190			pcie0_state_on: pcie0-state-on {
1191				perst {
1192					pins = "gpio35";
1193					function = "gpio";
1194					drive-strength = <2>;
1195					bias-pull-down;
1196				};
1197
1198				clkreq {
1199					pins = "gpio36";
1200					function = "pci_e0";
1201					drive-strength = <2>;
1202					bias-pull-up;
1203				};
1204
1205				wake {
1206					pins = "gpio37";
1207					function = "gpio";
1208					drive-strength = <2>;
1209					bias-pull-up;
1210				};
1211			};
1212
1213			pcie0_state_off: pcie0-state-off {
1214				perst {
1215					pins = "gpio35";
1216					function = "gpio";
1217					drive-strength = <2>;
1218					bias-pull-down;
1219				};
1220
1221				clkreq {
1222					pins = "gpio36";
1223					function = "gpio";
1224					drive-strength = <2>;
1225					bias-disable;
1226				};
1227
1228				wake {
1229					pins = "gpio37";
1230					function = "gpio";
1231					drive-strength = <2>;
1232					bias-disable;
1233				};
1234			};
1235
1236			blsp1_uart2_default: blsp1-uart2-default {
1237				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1238				function = "blsp_uart2";
1239				drive-strength = <16>;
1240				bias-disable;
1241			};
1242
1243			blsp1_uart2_sleep: blsp1-uart2-sleep {
1244				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1245				function = "gpio";
1246				drive-strength = <2>;
1247				bias-disable;
1248			};
1249
1250			blsp1_i2c3_default: blsp1-i2c2-default {
1251				pins = "gpio47", "gpio48";
1252				function = "blsp_i2c3";
1253				drive-strength = <16>;
1254				bias-disable = <0>;
1255			};
1256
1257			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1258				pins = "gpio47", "gpio48";
1259				function = "gpio";
1260				drive-strength = <2>;
1261				bias-disable = <0>;
1262			};
1263
1264			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1265				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1266				function = "blsp_uart9";
1267				drive-strength = <16>;
1268				bias-disable;
1269			};
1270
1271			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1272				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1273				function = "blsp_uart9";
1274				drive-strength = <2>;
1275				bias-disable;
1276			};
1277
1278			blsp2_i2c3_default: blsp2-i2c3 {
1279				pins = "gpio51", "gpio52";
1280				function = "blsp_i2c9";
1281				drive-strength = <16>;
1282				bias-disable;
1283			};
1284
1285			blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1286				pins = "gpio51", "gpio52";
1287				function = "gpio";
1288				drive-strength = <2>;
1289				bias-disable;
1290			};
1291
1292			wcd_intr_default: wcd-intr-default{
1293				pins = "gpio54";
1294				function = "gpio";
1295				drive-strength = <2>;
1296				bias-pull-down;
1297				input-enable;
1298			};
1299
1300			blsp2_i2c1_default: blsp2-i2c1 {
1301				pins = "gpio55", "gpio56";
1302				function = "blsp_i2c7";
1303				drive-strength = <16>;
1304				bias-disable;
1305			};
1306
1307			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1308				pins = "gpio55", "gpio56";
1309				function = "gpio";
1310				drive-strength = <2>;
1311				bias-disable;
1312			};
1313
1314			blsp2_i2c5_default: blsp2-i2c5 {
1315				pins = "gpio60", "gpio61";
1316				function = "blsp_i2c11";
1317				drive-strength = <2>;
1318				bias-disable;
1319			};
1320
1321			/* Sleep state for BLSP2_I2C5 is missing.. */
1322
1323			cdc_reset_active: cdc-reset-active {
1324				pins = "gpio64";
1325				function = "gpio";
1326				drive-strength = <16>;
1327				bias-pull-down;
1328				output-high;
1329			};
1330
1331			cdc_reset_sleep: cdc-reset-sleep {
1332				pins = "gpio64";
1333				function = "gpio";
1334				drive-strength = <16>;
1335				bias-disable;
1336				output-low;
1337			};
1338
1339			blsp2_spi6_default: blsp2-spi5-default {
1340				spi {
1341					pins = "gpio85", "gpio86", "gpio88";
1342					function = "blsp_spi12";
1343					drive-strength = <12>;
1344					bias-disable;
1345				};
1346
1347				cs {
1348					pins = "gpio87";
1349					function = "gpio";
1350					drive-strength = <16>;
1351					bias-disable;
1352					output-high;
1353				};
1354			};
1355
1356			blsp2_spi6_sleep: blsp2-spi5-sleep {
1357				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1358				function = "gpio";
1359				drive-strength = <2>;
1360				bias-pull-down;
1361			};
1362
1363			blsp2_i2c6_default: blsp2-i2c6 {
1364				pins = "gpio87", "gpio88";
1365				function = "blsp_i2c12";
1366				drive-strength = <16>;
1367				bias-disable;
1368			};
1369
1370			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1371				pins = "gpio87", "gpio88";
1372				function = "gpio";
1373				drive-strength = <2>;
1374				bias-disable;
1375			};
1376
1377			pcie1_state_on: pcie1-state-on {
1378				perst {
1379					pins = "gpio130";
1380					function = "gpio";
1381					drive-strength = <2>;
1382					bias-pull-down;
1383				};
1384
1385				clkreq {
1386					pins = "gpio131";
1387					function = "pci_e1";
1388					drive-strength = <2>;
1389					bias-pull-up;
1390				};
1391
1392				wake {
1393					pins = "gpio132";
1394					function = "gpio";
1395					drive-strength = <2>;
1396					bias-pull-down;
1397				};
1398			};
1399
1400			pcie1_state_off: pcie1-state-off {
1401				/* Perst is missing? */
1402				clkreq {
1403					pins = "gpio131";
1404					function = "gpio";
1405					drive-strength = <2>;
1406					bias-disable;
1407				};
1408
1409				wake {
1410					pins = "gpio132";
1411					function = "gpio";
1412					drive-strength = <2>;
1413					bias-disable;
1414				};
1415			};
1416
1417			pcie2_state_on: pcie2-state-on {
1418				perst {
1419					pins = "gpio114";
1420					function = "gpio";
1421					drive-strength = <2>;
1422					bias-pull-down;
1423				};
1424
1425				clkreq {
1426					pins = "gpio115";
1427					function = "pci_e2";
1428					drive-strength = <2>;
1429					bias-pull-up;
1430				};
1431
1432				wake {
1433					pins = "gpio116";
1434					function = "gpio";
1435					drive-strength = <2>;
1436					bias-pull-down;
1437				};
1438			};
1439
1440			pcie2_state_off: pcie2-state-off {
1441				/* Perst is missing? */
1442				clkreq {
1443					pins = "gpio115";
1444					function = "gpio";
1445					drive-strength = <2>;
1446					bias-disable;
1447				};
1448
1449				wake {
1450					pins = "gpio116";
1451					function = "gpio";
1452					drive-strength = <2>;
1453					bias-disable;
1454				};
1455			};
1456
1457			sdc1_state_on: sdc1-state-on {
1458				clk {
1459					pins = "sdc1_clk";
1460					bias-disable;
1461					drive-strength = <16>;
1462				};
1463
1464				cmd {
1465					pins = "sdc1_cmd";
1466					bias-pull-up;
1467					drive-strength = <10>;
1468				};
1469
1470				data {
1471					pins = "sdc1_data";
1472					bias-pull-up;
1473					drive-strength = <10>;
1474				};
1475
1476				rclk {
1477					pins = "sdc1_rclk";
1478					bias-pull-down;
1479				};
1480			};
1481
1482			sdc1_state_off: sdc1-state-off {
1483				clk {
1484					pins = "sdc1_clk";
1485					bias-disable;
1486					drive-strength = <2>;
1487				};
1488
1489				cmd {
1490					pins = "sdc1_cmd";
1491					bias-pull-up;
1492					drive-strength = <2>;
1493				};
1494
1495				data {
1496					pins = "sdc1_data";
1497					bias-pull-up;
1498					drive-strength = <2>;
1499				};
1500
1501				rclk {
1502					pins = "sdc1_rclk";
1503					bias-pull-down;
1504				};
1505			};
1506
1507			sdc2_state_on: sdc2-clk-on {
1508				clk {
1509					pins = "sdc2_clk";
1510					bias-disable;
1511					drive-strength = <16>;
1512				};
1513
1514				cmd {
1515					pins = "sdc2_cmd";
1516					bias-pull-up;
1517					drive-strength = <10>;
1518				};
1519
1520				data {
1521					pins = "sdc2_data";
1522					bias-pull-up;
1523					drive-strength = <10>;
1524				};
1525			};
1526
1527			sdc2_state_off: sdc2-clk-off {
1528				clk {
1529					pins = "sdc2_clk";
1530					bias-disable;
1531					drive-strength = <2>;
1532				};
1533
1534				cmd {
1535					pins = "sdc2_cmd";
1536					bias-pull-up;
1537					drive-strength = <2>;
1538				};
1539
1540				data {
1541					pins = "sdc2_data";
1542					bias-pull-up;
1543					drive-strength = <2>;
1544				};
1545			};
1546		};
1547
1548		sram@290000 {
1549			compatible = "qcom,rpm-stats";
1550			reg = <0x00290000 0x10000>;
1551		};
1552
1553		spmi_bus: qcom,spmi@400f000 {
1554			compatible = "qcom,spmi-pmic-arb";
1555			reg = <0x0400f000 0x1000>,
1556			      <0x04400000 0x800000>,
1557			      <0x04c00000 0x800000>,
1558			      <0x05800000 0x200000>,
1559			      <0x0400a000 0x002100>;
1560			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1561			interrupt-names = "periph_irq";
1562			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1563			qcom,ee = <0>;
1564			qcom,channel = <0>;
1565			#address-cells = <2>;
1566			#size-cells = <0>;
1567			interrupt-controller;
1568			#interrupt-cells = <4>;
1569		};
1570
1571		agnoc@0 {
1572			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1573			compatible = "simple-pm-bus";
1574			#address-cells = <1>;
1575			#size-cells = <1>;
1576			ranges;
1577
1578			pcie0: pcie@600000 {
1579				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1580				status = "disabled";
1581				power-domains = <&gcc PCIE0_GDSC>;
1582				bus-range = <0x00 0xff>;
1583				num-lanes = <1>;
1584
1585				reg = <0x00600000 0x2000>,
1586				      <0x0c000000 0xf1d>,
1587				      <0x0c000f20 0xa8>,
1588				      <0x0c100000 0x100000>;
1589				reg-names = "parf", "dbi", "elbi","config";
1590
1591				phys = <&pciephy_0>;
1592				phy-names = "pciephy";
1593
1594				#address-cells = <3>;
1595				#size-cells = <2>;
1596				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1597					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1598
1599				device_type = "pci";
1600
1601				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1602				interrupt-names = "msi";
1603				#interrupt-cells = <1>;
1604				interrupt-map-mask = <0 0 0 0x7>;
1605				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1606						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1607						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1608						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1609
1610				pinctrl-names = "default", "sleep";
1611				pinctrl-0 = <&pcie0_state_on>;
1612				pinctrl-1 = <&pcie0_state_off>;
1613
1614				linux,pci-domain = <0>;
1615
1616				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1617					<&gcc GCC_PCIE_0_AUX_CLK>,
1618					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1619					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1620					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1621
1622				clock-names =  "pipe",
1623						"aux",
1624						"cfg",
1625						"bus_master",
1626						"bus_slave";
1627
1628			};
1629
1630			pcie1: pcie@608000 {
1631				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1632				power-domains = <&gcc PCIE1_GDSC>;
1633				bus-range = <0x00 0xff>;
1634				num-lanes = <1>;
1635
1636				status  = "disabled";
1637
1638				reg = <0x00608000 0x2000>,
1639				      <0x0d000000 0xf1d>,
1640				      <0x0d000f20 0xa8>,
1641				      <0x0d100000 0x100000>;
1642
1643				reg-names = "parf", "dbi", "elbi","config";
1644
1645				phys = <&pciephy_1>;
1646				phy-names = "pciephy";
1647
1648				#address-cells = <3>;
1649				#size-cells = <2>;
1650				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1651					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1652
1653				device_type = "pci";
1654
1655				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1656				interrupt-names = "msi";
1657				#interrupt-cells = <1>;
1658				interrupt-map-mask = <0 0 0 0x7>;
1659				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1660						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1661						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1662						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1663
1664				pinctrl-names = "default", "sleep";
1665				pinctrl-0 = <&pcie1_state_on>;
1666				pinctrl-1 = <&pcie1_state_off>;
1667
1668				linux,pci-domain = <1>;
1669
1670				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1671					<&gcc GCC_PCIE_1_AUX_CLK>,
1672					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1673					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1674					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1675
1676				clock-names =  "pipe",
1677						"aux",
1678						"cfg",
1679						"bus_master",
1680						"bus_slave";
1681			};
1682
1683			pcie2: pcie@610000 {
1684				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1685				power-domains = <&gcc PCIE2_GDSC>;
1686				bus-range = <0x00 0xff>;
1687				num-lanes = <1>;
1688				status = "disabled";
1689				reg = <0x00610000 0x2000>,
1690				      <0x0e000000 0xf1d>,
1691				      <0x0e000f20 0xa8>,
1692				      <0x0e100000 0x100000>;
1693
1694				reg-names = "parf", "dbi", "elbi","config";
1695
1696				phys = <&pciephy_2>;
1697				phy-names = "pciephy";
1698
1699				#address-cells = <3>;
1700				#size-cells = <2>;
1701				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1702					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1703
1704				device_type = "pci";
1705
1706				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1707				interrupt-names = "msi";
1708				#interrupt-cells = <1>;
1709				interrupt-map-mask = <0 0 0 0x7>;
1710				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1712						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1713						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1714
1715				pinctrl-names = "default", "sleep";
1716				pinctrl-0 = <&pcie2_state_on>;
1717				pinctrl-1 = <&pcie2_state_off>;
1718
1719				linux,pci-domain = <2>;
1720				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1721					<&gcc GCC_PCIE_2_AUX_CLK>,
1722					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1723					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1724					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1725
1726				clock-names =  "pipe",
1727						"aux",
1728						"cfg",
1729						"bus_master",
1730						"bus_slave";
1731			};
1732		};
1733
1734		ufshc: ufshc@624000 {
1735			compatible = "qcom,ufshc";
1736			reg = <0x00624000 0x2500>;
1737			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1738
1739			phys = <&ufsphy_lane>;
1740			phy-names = "ufsphy";
1741
1742			power-domains = <&gcc UFS_GDSC>;
1743
1744			clock-names =
1745				"core_clk_src",
1746				"core_clk",
1747				"bus_clk",
1748				"bus_aggr_clk",
1749				"iface_clk",
1750				"core_clk_unipro_src",
1751				"core_clk_unipro",
1752				"core_clk_ice",
1753				"ref_clk",
1754				"tx_lane0_sync_clk",
1755				"rx_lane0_sync_clk";
1756			clocks =
1757				<&gcc UFS_AXI_CLK_SRC>,
1758				<&gcc GCC_UFS_AXI_CLK>,
1759				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1760				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1761				<&gcc GCC_UFS_AHB_CLK>,
1762				<&gcc UFS_ICE_CORE_CLK_SRC>,
1763				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1764				<&gcc GCC_UFS_ICE_CORE_CLK>,
1765				<&rpmcc RPM_SMD_LN_BB_CLK>,
1766				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1767				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1768			freq-table-hz =
1769				<100000000 200000000>,
1770				<0 0>,
1771				<0 0>,
1772				<0 0>,
1773				<0 0>,
1774				<150000000 300000000>,
1775				<0 0>,
1776				<0 0>,
1777				<0 0>,
1778				<0 0>,
1779				<0 0>;
1780
1781			lanes-per-direction = <1>;
1782			#reset-cells = <1>;
1783			status = "disabled";
1784
1785			ufs_variant {
1786				compatible = "qcom,ufs_variant";
1787			};
1788		};
1789
1790		ufsphy: phy@627000 {
1791			compatible = "qcom,msm8996-qmp-ufs-phy";
1792			reg = <0x00627000 0x1c4>;
1793			#address-cells = <1>;
1794			#size-cells = <1>;
1795			ranges;
1796
1797			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1798			clock-names = "ref";
1799
1800			resets = <&ufshc 0>;
1801			reset-names = "ufsphy";
1802			status = "disabled";
1803
1804			ufsphy_lane: phy@627400 {
1805				reg = <0x627400 0x12c>,
1806				      <0x627600 0x200>,
1807				      <0x627c00 0x1b4>;
1808				#phy-cells = <0>;
1809			};
1810		};
1811
1812		camss: camss@a00000 {
1813			compatible = "qcom,msm8996-camss";
1814			reg = <0x00a34000 0x1000>,
1815			      <0x00a00030 0x4>,
1816			      <0x00a35000 0x1000>,
1817			      <0x00a00038 0x4>,
1818			      <0x00a36000 0x1000>,
1819			      <0x00a00040 0x4>,
1820			      <0x00a30000 0x100>,
1821			      <0x00a30400 0x100>,
1822			      <0x00a30800 0x100>,
1823			      <0x00a30c00 0x100>,
1824			      <0x00a31000 0x500>,
1825			      <0x00a00020 0x10>,
1826			      <0x00a10000 0x1000>,
1827			      <0x00a14000 0x1000>;
1828			reg-names = "csiphy0",
1829				"csiphy0_clk_mux",
1830				"csiphy1",
1831				"csiphy1_clk_mux",
1832				"csiphy2",
1833				"csiphy2_clk_mux",
1834				"csid0",
1835				"csid1",
1836				"csid2",
1837				"csid3",
1838				"ispif",
1839				"csi_clk_mux",
1840				"vfe0",
1841				"vfe1";
1842			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1843				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1844				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1845				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1846				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1847				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1848				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1849				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1850				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1851				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1852			interrupt-names = "csiphy0",
1853				"csiphy1",
1854				"csiphy2",
1855				"csid0",
1856				"csid1",
1857				"csid2",
1858				"csid3",
1859				"ispif",
1860				"vfe0",
1861				"vfe1";
1862			power-domains = <&mmcc VFE0_GDSC>,
1863					<&mmcc VFE1_GDSC>;
1864			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1865				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1866				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1867				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1868				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1869				<&mmcc CAMSS_CSI0_AHB_CLK>,
1870				<&mmcc CAMSS_CSI0_CLK>,
1871				<&mmcc CAMSS_CSI0PHY_CLK>,
1872				<&mmcc CAMSS_CSI0PIX_CLK>,
1873				<&mmcc CAMSS_CSI0RDI_CLK>,
1874				<&mmcc CAMSS_CSI1_AHB_CLK>,
1875				<&mmcc CAMSS_CSI1_CLK>,
1876				<&mmcc CAMSS_CSI1PHY_CLK>,
1877				<&mmcc CAMSS_CSI1PIX_CLK>,
1878				<&mmcc CAMSS_CSI1RDI_CLK>,
1879				<&mmcc CAMSS_CSI2_AHB_CLK>,
1880				<&mmcc CAMSS_CSI2_CLK>,
1881				<&mmcc CAMSS_CSI2PHY_CLK>,
1882				<&mmcc CAMSS_CSI2PIX_CLK>,
1883				<&mmcc CAMSS_CSI2RDI_CLK>,
1884				<&mmcc CAMSS_CSI3_AHB_CLK>,
1885				<&mmcc CAMSS_CSI3_CLK>,
1886				<&mmcc CAMSS_CSI3PHY_CLK>,
1887				<&mmcc CAMSS_CSI3PIX_CLK>,
1888				<&mmcc CAMSS_CSI3RDI_CLK>,
1889				<&mmcc CAMSS_AHB_CLK>,
1890				<&mmcc CAMSS_VFE0_CLK>,
1891				<&mmcc CAMSS_CSI_VFE0_CLK>,
1892				<&mmcc CAMSS_VFE0_AHB_CLK>,
1893				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1894				<&mmcc CAMSS_VFE1_CLK>,
1895				<&mmcc CAMSS_CSI_VFE1_CLK>,
1896				<&mmcc CAMSS_VFE1_AHB_CLK>,
1897				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1898				<&mmcc CAMSS_VFE_AHB_CLK>,
1899				<&mmcc CAMSS_VFE_AXI_CLK>;
1900			clock-names = "top_ahb",
1901				"ispif_ahb",
1902				"csiphy0_timer",
1903				"csiphy1_timer",
1904				"csiphy2_timer",
1905				"csi0_ahb",
1906				"csi0",
1907				"csi0_phy",
1908				"csi0_pix",
1909				"csi0_rdi",
1910				"csi1_ahb",
1911				"csi1",
1912				"csi1_phy",
1913				"csi1_pix",
1914				"csi1_rdi",
1915				"csi2_ahb",
1916				"csi2",
1917				"csi2_phy",
1918				"csi2_pix",
1919				"csi2_rdi",
1920				"csi3_ahb",
1921				"csi3",
1922				"csi3_phy",
1923				"csi3_pix",
1924				"csi3_rdi",
1925				"ahb",
1926				"vfe0",
1927				"csi_vfe0",
1928				"vfe0_ahb",
1929				"vfe0_stream",
1930				"vfe1",
1931				"csi_vfe1",
1932				"vfe1_ahb",
1933				"vfe1_stream",
1934				"vfe_ahb",
1935				"vfe_axi";
1936			iommus = <&vfe_smmu 0>,
1937				 <&vfe_smmu 1>,
1938				 <&vfe_smmu 2>,
1939				 <&vfe_smmu 3>;
1940			status = "disabled";
1941			ports {
1942				#address-cells = <1>;
1943				#size-cells = <0>;
1944			};
1945		};
1946
1947		cci: cci@a0c000 {
1948			compatible = "qcom,msm8996-cci";
1949			#address-cells = <1>;
1950			#size-cells = <0>;
1951			reg = <0xa0c000 0x1000>;
1952			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1953			power-domains = <&mmcc CAMSS_GDSC>;
1954			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1955				 <&mmcc CAMSS_CCI_AHB_CLK>,
1956				 <&mmcc CAMSS_CCI_CLK>,
1957				 <&mmcc CAMSS_AHB_CLK>;
1958			clock-names = "camss_top_ahb",
1959				      "cci_ahb",
1960				      "cci",
1961				      "camss_ahb";
1962			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1963					  <&mmcc CAMSS_CCI_CLK>;
1964			assigned-clock-rates = <80000000>, <37500000>;
1965			pinctrl-names = "default";
1966			pinctrl-0 = <&cci0_default &cci1_default>;
1967			status = "disabled";
1968
1969			cci_i2c0: i2c-bus@0 {
1970				reg = <0>;
1971				clock-frequency = <400000>;
1972				#address-cells = <1>;
1973				#size-cells = <0>;
1974			};
1975
1976			cci_i2c1: i2c-bus@1 {
1977				reg = <1>;
1978				clock-frequency = <400000>;
1979				#address-cells = <1>;
1980				#size-cells = <0>;
1981			};
1982		};
1983
1984		adreno_smmu: iommu@b40000 {
1985			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1986			reg = <0x00b40000 0x10000>;
1987
1988			#global-interrupts = <1>;
1989			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1990				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1991				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1992			#iommu-cells = <1>;
1993
1994			clocks = <&mmcc GPU_AHB_CLK>,
1995				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1996			clock-names = "iface", "bus";
1997
1998			power-domains = <&mmcc GPU_GDSC>;
1999		};
2000
2001		venus: video-codec@c00000 {
2002			compatible = "qcom,msm8996-venus";
2003			reg = <0x00c00000 0xff000>;
2004			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2005			power-domains = <&mmcc VENUS_GDSC>;
2006			clocks = <&mmcc VIDEO_CORE_CLK>,
2007				 <&mmcc VIDEO_AHB_CLK>,
2008				 <&mmcc VIDEO_AXI_CLK>,
2009				 <&mmcc VIDEO_MAXI_CLK>;
2010			clock-names = "core", "iface", "bus", "mbus";
2011			iommus = <&venus_smmu 0x00>,
2012				 <&venus_smmu 0x01>,
2013				 <&venus_smmu 0x0a>,
2014				 <&venus_smmu 0x07>,
2015				 <&venus_smmu 0x0e>,
2016				 <&venus_smmu 0x0f>,
2017				 <&venus_smmu 0x08>,
2018				 <&venus_smmu 0x09>,
2019				 <&venus_smmu 0x0b>,
2020				 <&venus_smmu 0x0c>,
2021				 <&venus_smmu 0x0d>,
2022				 <&venus_smmu 0x10>,
2023				 <&venus_smmu 0x11>,
2024				 <&venus_smmu 0x21>,
2025				 <&venus_smmu 0x28>,
2026				 <&venus_smmu 0x29>,
2027				 <&venus_smmu 0x2b>,
2028				 <&venus_smmu 0x2c>,
2029				 <&venus_smmu 0x2d>,
2030				 <&venus_smmu 0x31>;
2031			memory-region = <&venus_region>;
2032			status = "disabled";
2033
2034			video-decoder {
2035				compatible = "venus-decoder";
2036				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2037				clock-names = "core";
2038				power-domains = <&mmcc VENUS_CORE0_GDSC>;
2039			};
2040
2041			video-encoder {
2042				compatible = "venus-encoder";
2043				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2044				clock-names = "core";
2045				power-domains = <&mmcc VENUS_CORE1_GDSC>;
2046			};
2047		};
2048
2049		mdp_smmu: iommu@d00000 {
2050			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2051			reg = <0x00d00000 0x10000>;
2052
2053			#global-interrupts = <1>;
2054			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2055				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2056				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2057			#iommu-cells = <1>;
2058			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2059				 <&mmcc SMMU_MDP_AXI_CLK>;
2060			clock-names = "iface", "bus";
2061
2062			power-domains = <&mmcc MDSS_GDSC>;
2063		};
2064
2065		venus_smmu: iommu@d40000 {
2066			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2067			reg = <0x00d40000 0x20000>;
2068			#global-interrupts = <1>;
2069			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2070				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2071				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2072				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2073				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2074				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2075				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2076				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2077			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2078			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2079				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2080			clock-names = "iface", "bus";
2081			#iommu-cells = <1>;
2082			status = "okay";
2083		};
2084
2085		vfe_smmu: iommu@da0000 {
2086			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2087			reg = <0x00da0000 0x10000>;
2088
2089			#global-interrupts = <1>;
2090			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2091				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2092				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2093			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2094			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2095				 <&mmcc SMMU_VFE_AXI_CLK>;
2096			clock-names = "iface",
2097				      "bus";
2098			#iommu-cells = <1>;
2099		};
2100
2101		lpass_q6_smmu: iommu@1600000 {
2102			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2103			reg = <0x01600000 0x20000>;
2104			#iommu-cells = <1>;
2105			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2106
2107			#global-interrupts = <1>;
2108			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2109		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2110		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2111		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2112		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2113		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2114		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2115		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2116		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2117		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2118		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2119		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2120		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2121
2122			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2123				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2124			clock-names = "iface", "bus";
2125		};
2126
2127		stm@3002000 {
2128			compatible = "arm,coresight-stm", "arm,primecell";
2129			reg = <0x3002000 0x1000>,
2130			      <0x8280000 0x180000>;
2131			reg-names = "stm-base", "stm-stimulus-base";
2132
2133			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2134			clock-names = "apb_pclk", "atclk";
2135
2136			out-ports {
2137				port {
2138					stm_out: endpoint {
2139						remote-endpoint =
2140						  <&funnel0_in>;
2141					};
2142				};
2143			};
2144		};
2145
2146		tpiu@3020000 {
2147			compatible = "arm,coresight-tpiu", "arm,primecell";
2148			reg = <0x3020000 0x1000>;
2149
2150			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2151			clock-names = "apb_pclk", "atclk";
2152
2153			in-ports {
2154				port {
2155					tpiu_in: endpoint {
2156						remote-endpoint =
2157						  <&replicator_out1>;
2158					};
2159				};
2160			};
2161		};
2162
2163		funnel@3021000 {
2164			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2165			reg = <0x3021000 0x1000>;
2166
2167			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2168			clock-names = "apb_pclk", "atclk";
2169
2170			in-ports {
2171				#address-cells = <1>;
2172				#size-cells = <0>;
2173
2174				port@7 {
2175					reg = <7>;
2176					funnel0_in: endpoint {
2177						remote-endpoint =
2178						  <&stm_out>;
2179					};
2180				};
2181			};
2182
2183			out-ports {
2184				port {
2185					funnel0_out: endpoint {
2186						remote-endpoint =
2187						  <&merge_funnel_in0>;
2188					};
2189				};
2190			};
2191		};
2192
2193		funnel@3022000 {
2194			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2195			reg = <0x3022000 0x1000>;
2196
2197			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2198			clock-names = "apb_pclk", "atclk";
2199
2200			in-ports {
2201				#address-cells = <1>;
2202				#size-cells = <0>;
2203
2204				port@6 {
2205					reg = <6>;
2206					funnel1_in: endpoint {
2207						remote-endpoint =
2208						  <&apss_merge_funnel_out>;
2209					};
2210				};
2211			};
2212
2213			out-ports {
2214				port {
2215					funnel1_out: endpoint {
2216						remote-endpoint =
2217						  <&merge_funnel_in1>;
2218					};
2219				};
2220			};
2221		};
2222
2223		funnel@3023000 {
2224			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2225			reg = <0x3023000 0x1000>;
2226
2227			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2228			clock-names = "apb_pclk", "atclk";
2229
2230
2231			out-ports {
2232				port {
2233					funnel2_out: endpoint {
2234						remote-endpoint =
2235						  <&merge_funnel_in2>;
2236					};
2237				};
2238			};
2239		};
2240
2241		funnel@3025000 {
2242			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2243			reg = <0x3025000 0x1000>;
2244
2245			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2246			clock-names = "apb_pclk", "atclk";
2247
2248			in-ports {
2249				#address-cells = <1>;
2250				#size-cells = <0>;
2251
2252				port@0 {
2253					reg = <0>;
2254					merge_funnel_in0: endpoint {
2255						remote-endpoint =
2256						  <&funnel0_out>;
2257					};
2258				};
2259
2260				port@1 {
2261					reg = <1>;
2262					merge_funnel_in1: endpoint {
2263						remote-endpoint =
2264						  <&funnel1_out>;
2265					};
2266				};
2267
2268				port@2 {
2269					reg = <2>;
2270					merge_funnel_in2: endpoint {
2271						remote-endpoint =
2272						  <&funnel2_out>;
2273					};
2274				};
2275			};
2276
2277			out-ports {
2278				port {
2279					merge_funnel_out: endpoint {
2280						remote-endpoint =
2281						  <&etf_in>;
2282					};
2283				};
2284			};
2285		};
2286
2287		replicator@3026000 {
2288			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2289			reg = <0x3026000 0x1000>;
2290
2291			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2292			clock-names = "apb_pclk", "atclk";
2293
2294			in-ports {
2295				port {
2296					replicator_in: endpoint {
2297						remote-endpoint =
2298						  <&etf_out>;
2299					};
2300				};
2301			};
2302
2303			out-ports {
2304				#address-cells = <1>;
2305				#size-cells = <0>;
2306
2307				port@0 {
2308					reg = <0>;
2309					replicator_out0: endpoint {
2310						remote-endpoint =
2311						  <&etr_in>;
2312					};
2313				};
2314
2315				port@1 {
2316					reg = <1>;
2317					replicator_out1: endpoint {
2318						remote-endpoint =
2319						  <&tpiu_in>;
2320					};
2321				};
2322			};
2323		};
2324
2325		etf@3027000 {
2326			compatible = "arm,coresight-tmc", "arm,primecell";
2327			reg = <0x3027000 0x1000>;
2328
2329			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2330			clock-names = "apb_pclk", "atclk";
2331
2332			in-ports {
2333				port {
2334					etf_in: endpoint {
2335						remote-endpoint =
2336						  <&merge_funnel_out>;
2337					};
2338				};
2339			};
2340
2341			out-ports {
2342				port {
2343					etf_out: endpoint {
2344						remote-endpoint =
2345						  <&replicator_in>;
2346					};
2347				};
2348			};
2349		};
2350
2351		etr@3028000 {
2352			compatible = "arm,coresight-tmc", "arm,primecell";
2353			reg = <0x3028000 0x1000>;
2354
2355			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2356			clock-names = "apb_pclk", "atclk";
2357			arm,scatter-gather;
2358
2359			in-ports {
2360				port {
2361					etr_in: endpoint {
2362						remote-endpoint =
2363						  <&replicator_out0>;
2364					};
2365				};
2366			};
2367		};
2368
2369		debug@3810000 {
2370			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2371			reg = <0x3810000 0x1000>;
2372
2373			clocks = <&rpmcc RPM_QDSS_CLK>;
2374			clock-names = "apb_pclk";
2375
2376			cpu = <&CPU0>;
2377		};
2378
2379		etm@3840000 {
2380			compatible = "arm,coresight-etm4x", "arm,primecell";
2381			reg = <0x3840000 0x1000>;
2382
2383			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2384			clock-names = "apb_pclk", "atclk";
2385
2386			cpu = <&CPU0>;
2387
2388			out-ports {
2389				port {
2390					etm0_out: endpoint {
2391						remote-endpoint =
2392						  <&apss_funnel0_in0>;
2393					};
2394				};
2395			};
2396		};
2397
2398		debug@3910000 {
2399			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2400			reg = <0x3910000 0x1000>;
2401
2402			clocks = <&rpmcc RPM_QDSS_CLK>;
2403			clock-names = "apb_pclk";
2404
2405			cpu = <&CPU1>;
2406		};
2407
2408		etm@3940000 {
2409			compatible = "arm,coresight-etm4x", "arm,primecell";
2410			reg = <0x3940000 0x1000>;
2411
2412			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2413			clock-names = "apb_pclk", "atclk";
2414
2415			cpu = <&CPU1>;
2416
2417			out-ports {
2418				port {
2419					etm1_out: endpoint {
2420						remote-endpoint =
2421						  <&apss_funnel0_in1>;
2422					};
2423				};
2424			};
2425		};
2426
2427		funnel@39b0000 { /* APSS Funnel 0 */
2428			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2429			reg = <0x39b0000 0x1000>;
2430
2431			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2432			clock-names = "apb_pclk", "atclk";
2433
2434			in-ports {
2435				#address-cells = <1>;
2436				#size-cells = <0>;
2437
2438				port@0 {
2439					reg = <0>;
2440					apss_funnel0_in0: endpoint {
2441						remote-endpoint = <&etm0_out>;
2442					};
2443				};
2444
2445				port@1 {
2446					reg = <1>;
2447					apss_funnel0_in1: endpoint {
2448						remote-endpoint = <&etm1_out>;
2449					};
2450				};
2451			};
2452
2453			out-ports {
2454				port {
2455					apss_funnel0_out: endpoint {
2456						remote-endpoint =
2457						  <&apss_merge_funnel_in0>;
2458					};
2459				};
2460			};
2461		};
2462
2463		debug@3a10000 {
2464			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2465			reg = <0x3a10000 0x1000>;
2466
2467			clocks = <&rpmcc RPM_QDSS_CLK>;
2468			clock-names = "apb_pclk";
2469
2470			cpu = <&CPU2>;
2471		};
2472
2473		etm@3a40000 {
2474			compatible = "arm,coresight-etm4x", "arm,primecell";
2475			reg = <0x3a40000 0x1000>;
2476
2477			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2478			clock-names = "apb_pclk", "atclk";
2479
2480			cpu = <&CPU2>;
2481
2482			out-ports {
2483				port {
2484					etm2_out: endpoint {
2485						remote-endpoint =
2486						  <&apss_funnel1_in0>;
2487					};
2488				};
2489			};
2490		};
2491
2492		debug@3b10000 {
2493			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2494			reg = <0x3b10000 0x1000>;
2495
2496			clocks = <&rpmcc RPM_QDSS_CLK>;
2497			clock-names = "apb_pclk";
2498
2499			cpu = <&CPU3>;
2500		};
2501
2502		etm@3b40000 {
2503			compatible = "arm,coresight-etm4x", "arm,primecell";
2504			reg = <0x3b40000 0x1000>;
2505
2506			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2507			clock-names = "apb_pclk", "atclk";
2508
2509			cpu = <&CPU3>;
2510
2511			out-ports {
2512				port {
2513					etm3_out: endpoint {
2514						remote-endpoint =
2515						  <&apss_funnel1_in1>;
2516					};
2517				};
2518			};
2519		};
2520
2521		funnel@3bb0000 { /* APSS Funnel 1 */
2522			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2523			reg = <0x3bb0000 0x1000>;
2524
2525			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2526			clock-names = "apb_pclk", "atclk";
2527
2528			in-ports {
2529				#address-cells = <1>;
2530				#size-cells = <0>;
2531
2532				port@0 {
2533					reg = <0>;
2534					apss_funnel1_in0: endpoint {
2535						remote-endpoint = <&etm2_out>;
2536					};
2537				};
2538
2539				port@1 {
2540					reg = <1>;
2541					apss_funnel1_in1: endpoint {
2542						remote-endpoint = <&etm3_out>;
2543					};
2544				};
2545			};
2546
2547			out-ports {
2548				port {
2549					apss_funnel1_out: endpoint {
2550						remote-endpoint =
2551						  <&apss_merge_funnel_in1>;
2552					};
2553				};
2554			};
2555		};
2556
2557		funnel@3bc0000 {
2558			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2559			reg = <0x3bc0000 0x1000>;
2560
2561			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2562			clock-names = "apb_pclk", "atclk";
2563
2564			in-ports {
2565				#address-cells = <1>;
2566				#size-cells = <0>;
2567
2568				port@0 {
2569					reg = <0>;
2570					apss_merge_funnel_in0: endpoint {
2571						remote-endpoint =
2572						  <&apss_funnel0_out>;
2573					};
2574				};
2575
2576				port@1 {
2577					reg = <1>;
2578					apss_merge_funnel_in1: endpoint {
2579						remote-endpoint =
2580						  <&apss_funnel1_out>;
2581					};
2582				};
2583			};
2584
2585			out-ports {
2586				port {
2587					apss_merge_funnel_out: endpoint {
2588						remote-endpoint =
2589						  <&funnel1_in>;
2590					};
2591				};
2592			};
2593		};
2594
2595		kryocc: clock-controller@6400000 {
2596			compatible = "qcom,msm8996-apcc";
2597			reg = <0x06400000 0x90000>;
2598
2599			clock-names = "xo";
2600			clocks = <&xo_board>;
2601
2602			#clock-cells = <1>;
2603		};
2604
2605		usb3: usb@6af8800 {
2606			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2607			reg = <0x06af8800 0x400>;
2608			#address-cells = <1>;
2609			#size-cells = <1>;
2610			ranges;
2611
2612			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2613				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2614			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2615
2616			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2617				<&gcc GCC_USB30_MASTER_CLK>,
2618				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2619				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2620				<&gcc GCC_USB30_SLEEP_CLK>,
2621				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2622
2623			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2624					  <&gcc GCC_USB30_MASTER_CLK>;
2625			assigned-clock-rates = <19200000>, <120000000>;
2626
2627			power-domains = <&gcc USB30_GDSC>;
2628			status = "disabled";
2629
2630			usb3_dwc3: dwc3@6a00000 {
2631				compatible = "snps,dwc3";
2632				reg = <0x06a00000 0xcc00>;
2633				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2634				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2635				phy-names = "usb2-phy", "usb3-phy";
2636				snps,dis_u2_susphy_quirk;
2637				snps,dis_enblslpm_quirk;
2638			};
2639		};
2640
2641		usb3phy: phy@7410000 {
2642			compatible = "qcom,msm8996-qmp-usb3-phy";
2643			reg = <0x07410000 0x1c4>;
2644			#address-cells = <1>;
2645			#size-cells = <1>;
2646			ranges;
2647
2648			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2649				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2650				<&gcc GCC_USB3_CLKREF_CLK>;
2651			clock-names = "aux", "cfg_ahb", "ref";
2652
2653			resets = <&gcc GCC_USB3_PHY_BCR>,
2654				<&gcc GCC_USB3PHY_PHY_BCR>;
2655			reset-names = "phy", "common";
2656			status = "disabled";
2657
2658			ssusb_phy_0: phy@7410200 {
2659				reg = <0x07410200 0x200>,
2660				      <0x07410400 0x130>,
2661				      <0x07410600 0x1a8>;
2662				#phy-cells = <0>;
2663
2664				#clock-cells = <1>;
2665				clock-output-names = "usb3_phy_pipe_clk_src";
2666				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2667				clock-names = "pipe0";
2668			};
2669		};
2670
2671		hsusb_phy1: phy@7411000 {
2672			compatible = "qcom,msm8996-qusb2-phy";
2673			reg = <0x07411000 0x180>;
2674			#phy-cells = <0>;
2675
2676			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2677				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2678			clock-names = "cfg_ahb", "ref";
2679
2680			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2681			nvmem-cells = <&qusb2p_hstx_trim>;
2682			status = "disabled";
2683		};
2684
2685		hsusb_phy2: phy@7412000 {
2686			compatible = "qcom,msm8996-qusb2-phy";
2687			reg = <0x07412000 0x180>;
2688			#phy-cells = <0>;
2689
2690			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2691				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2692			clock-names = "cfg_ahb", "ref";
2693
2694			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2695			nvmem-cells = <&qusb2s_hstx_trim>;
2696			status = "disabled";
2697		};
2698
2699		sdhc1: sdhci@7464900 {
2700			compatible = "qcom,sdhci-msm-v4";
2701			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2702			reg-names = "hc_mem", "core_mem";
2703
2704			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2705					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2706			interrupt-names = "hc_irq", "pwr_irq";
2707
2708			clock-names = "iface", "core", "xo";
2709			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2710				<&gcc GCC_SDCC1_APPS_CLK>,
2711				<&xo_board>;
2712
2713			pinctrl-names = "default", "sleep";
2714			pinctrl-0 = <&sdc1_state_on>;
2715			pinctrl-1 = <&sdc1_state_off>;
2716
2717			bus-width = <8>;
2718			non-removable;
2719			status = "disabled";
2720		};
2721
2722		sdhc2: sdhci@74a4900 {
2723			compatible = "qcom,sdhci-msm-v4";
2724			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2725			reg-names = "hc_mem", "core_mem";
2726
2727			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2728				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2729			interrupt-names = "hc_irq", "pwr_irq";
2730
2731			clock-names = "iface", "core", "xo";
2732			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2733				<&gcc GCC_SDCC2_APPS_CLK>,
2734				<&xo_board>;
2735
2736			pinctrl-names = "default", "sleep";
2737			pinctrl-0 = <&sdc2_state_on>;
2738			pinctrl-1 = <&sdc2_state_off>;
2739
2740			bus-width = <4>;
2741			status = "disabled";
2742		 };
2743
2744		blsp1_dma: dma-controller@7544000 {
2745			compatible = "qcom,bam-v1.7.0";
2746			reg = <0x07544000 0x2b000>;
2747			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2748			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2749			clock-names = "bam_clk";
2750			qcom,controlled-remotely;
2751			#dma-cells = <1>;
2752			qcom,ee = <0>;
2753		};
2754
2755		blsp1_uart2: serial@7570000 {
2756			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2757			reg = <0x07570000 0x1000>;
2758			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2759			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2760				 <&gcc GCC_BLSP1_AHB_CLK>;
2761			clock-names = "core", "iface";
2762			pinctrl-names = "default", "sleep";
2763			pinctrl-0 = <&blsp1_uart2_default>;
2764			pinctrl-1 = <&blsp1_uart2_sleep>;
2765			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2766			dma-names = "tx", "rx";
2767			status = "disabled";
2768		};
2769
2770		blsp1_spi1: spi@7575000 {
2771			compatible = "qcom,spi-qup-v2.2.1";
2772			reg = <0x07575000 0x600>;
2773			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2774			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2775				 <&gcc GCC_BLSP1_AHB_CLK>;
2776			clock-names = "core", "iface";
2777			pinctrl-names = "default", "sleep";
2778			pinctrl-0 = <&blsp1_spi1_default>;
2779			pinctrl-1 = <&blsp1_spi1_sleep>;
2780			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2781			dma-names = "tx", "rx";
2782			#address-cells = <1>;
2783			#size-cells = <0>;
2784			status = "disabled";
2785		};
2786
2787		blsp1_i2c3: i2c@7577000 {
2788			compatible = "qcom,i2c-qup-v2.2.1";
2789			reg = <0x07577000 0x1000>;
2790			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2791			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2792				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2793			clock-names = "iface", "core";
2794			pinctrl-names = "default", "sleep";
2795			pinctrl-0 = <&blsp1_i2c3_default>;
2796			pinctrl-1 = <&blsp1_i2c3_sleep>;
2797			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2798			dma-names = "tx", "rx";
2799			#address-cells = <1>;
2800			#size-cells = <0>;
2801			status = "disabled";
2802		};
2803
2804		blsp2_dma: dma-controller@7584000 {
2805			compatible = "qcom,bam-v1.7.0";
2806			reg = <0x07584000 0x2b000>;
2807			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2808			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2809			clock-names = "bam_clk";
2810			qcom,controlled-remotely;
2811			#dma-cells = <1>;
2812			qcom,ee = <0>;
2813		};
2814
2815		blsp2_uart2: serial@75b0000 {
2816			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2817			reg = <0x075b0000 0x1000>;
2818			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2819			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2820				 <&gcc GCC_BLSP2_AHB_CLK>;
2821			clock-names = "core", "iface";
2822			status = "disabled";
2823		};
2824
2825		blsp2_uart3: serial@75b1000 {
2826			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2827			reg = <0x075b1000 0x1000>;
2828			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2829			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2830				 <&gcc GCC_BLSP2_AHB_CLK>;
2831			clock-names = "core", "iface";
2832			status = "disabled";
2833		};
2834
2835		blsp2_i2c1: i2c@75b5000 {
2836			compatible = "qcom,i2c-qup-v2.2.1";
2837			reg = <0x075b5000 0x1000>;
2838			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2839			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2840				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2841			clock-names = "iface", "core";
2842			pinctrl-names = "default", "sleep";
2843			pinctrl-0 = <&blsp2_i2c1_default>;
2844			pinctrl-1 = <&blsp2_i2c1_sleep>;
2845			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2846			dma-names = "tx", "rx";
2847			#address-cells = <1>;
2848			#size-cells = <0>;
2849			status = "disabled";
2850		};
2851
2852		blsp2_i2c2: i2c@75b6000 {
2853			compatible = "qcom,i2c-qup-v2.2.1";
2854			reg = <0x075b6000 0x1000>;
2855			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2856			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2857				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2858			clock-names = "iface", "core";
2859			pinctrl-names = "default", "sleep";
2860			pinctrl-0 = <&blsp2_i2c2_default>;
2861			pinctrl-1 = <&blsp2_i2c2_sleep>;
2862			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2863			dma-names = "tx", "rx";
2864			#address-cells = <1>;
2865			#size-cells = <0>;
2866			status = "disabled";
2867		};
2868
2869		blsp2_i2c3: i2c@75b7000 {
2870			compatible = "qcom,i2c-qup-v2.2.1";
2871			reg = <0x075b7000 0x1000>;
2872			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2873			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2874				<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
2875			clock-names = "iface", "core";
2876			clock-frequency = <400000>;
2877			pinctrl-names = "default", "sleep";
2878			pinctrl-0 = <&blsp2_i2c3_default>;
2879			pinctrl-1 = <&blsp2_i2c3_sleep>;
2880			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2881			dma-names = "tx", "rx";
2882			#address-cells = <1>;
2883			#size-cells = <0>;
2884			status = "disabled";
2885		};
2886
2887		blsp2_i2c5: i2c@75b9000 {
2888			compatible = "qcom,i2c-qup-v2.2.1";
2889			reg = <0x75b9000 0x1000>;
2890			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2891			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2892				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2893			clock-names = "iface", "core";
2894			pinctrl-names = "default";
2895			pinctrl-0 = <&blsp2_i2c5_default>;
2896			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2897			dma-names = "tx", "rx";
2898			#address-cells = <1>;
2899			#size-cells = <0>;
2900			status = "disabled";
2901		};
2902
2903		blsp2_i2c6: i2c@75ba000 {
2904			compatible = "qcom,i2c-qup-v2.2.1";
2905			reg = <0x75ba000 0x1000>;
2906			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2907			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2908				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2909			clock-names = "iface", "core";
2910			pinctrl-names = "default", "sleep";
2911			pinctrl-0 = <&blsp2_i2c6_default>;
2912			pinctrl-1 = <&blsp2_i2c6_sleep>;
2913			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2914			dma-names = "tx", "rx";
2915			#address-cells = <1>;
2916			#size-cells = <0>;
2917			status = "disabled";
2918		};
2919
2920		blsp2_spi6: spi@75ba000{
2921			compatible = "qcom,spi-qup-v2.2.1";
2922			reg = <0x075ba000 0x600>;
2923			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2924			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2925				 <&gcc GCC_BLSP2_AHB_CLK>;
2926			clock-names = "core", "iface";
2927			pinctrl-names = "default", "sleep";
2928			pinctrl-0 = <&blsp2_spi6_default>;
2929			pinctrl-1 = <&blsp2_spi6_sleep>;
2930			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2931			dma-names = "tx", "rx";
2932			#address-cells = <1>;
2933			#size-cells = <0>;
2934			status = "disabled";
2935		};
2936
2937		usb2: usb@76f8800 {
2938			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2939			reg = <0x076f8800 0x400>;
2940			#address-cells = <1>;
2941			#size-cells = <1>;
2942			ranges;
2943
2944			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2945				<&gcc GCC_USB20_MASTER_CLK>,
2946				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2947				<&gcc GCC_USB20_SLEEP_CLK>,
2948				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2949
2950			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2951					  <&gcc GCC_USB20_MASTER_CLK>;
2952			assigned-clock-rates = <19200000>, <60000000>;
2953
2954			power-domains = <&gcc USB30_GDSC>;
2955			qcom,select-utmi-as-pipe-clk;
2956			status = "disabled";
2957
2958			dwc3@7600000 {
2959				compatible = "snps,dwc3";
2960				reg = <0x07600000 0xcc00>;
2961				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2962				phys = <&hsusb_phy2>;
2963				phy-names = "usb2-phy";
2964				maximum-speed = "high-speed";
2965				snps,dis_u2_susphy_quirk;
2966				snps,dis_enblslpm_quirk;
2967			};
2968		};
2969
2970		slimbam: dma-controller@9184000 {
2971			compatible = "qcom,bam-v1.7.0";
2972			qcom,controlled-remotely;
2973			reg = <0x09184000 0x32000>;
2974			num-channels  = <31>;
2975			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2976			#dma-cells = <1>;
2977			qcom,ee = <1>;
2978			qcom,num-ees = <2>;
2979		};
2980
2981		slim_msm: slim@91c0000 {
2982			compatible = "qcom,slim-ngd-v1.5.0";
2983			reg = <0x091c0000 0x2C000>;
2984			reg-names = "ctrl";
2985			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2986			dmas =	<&slimbam 3>, <&slimbam 4>,
2987				<&slimbam 5>, <&slimbam 6>;
2988			dma-names = "rx", "tx", "tx2", "rx2";
2989			#address-cells = <1>;
2990			#size-cells = <0>;
2991			ngd@1 {
2992				reg = <1>;
2993				#address-cells = <1>;
2994				#size-cells = <1>;
2995
2996				tasha_ifd: tas-ifd {
2997					compatible = "slim217,1a0";
2998					reg  = <0 0>;
2999				};
3000
3001				wcd9335: codec@1{
3002					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3003					pinctrl-names = "default";
3004
3005					compatible = "slim217,1a0";
3006					reg  = <1 0>;
3007
3008					interrupt-parent = <&tlmm>;
3009					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3010						     <53 IRQ_TYPE_LEVEL_HIGH>;
3011					interrupt-names  = "intr1", "intr2";
3012					interrupt-controller;
3013					#interrupt-cells = <1>;
3014					reset-gpios = <&tlmm 64 0>;
3015
3016					slim-ifc-dev  = <&tasha_ifd>;
3017
3018					#sound-dai-cells = <1>;
3019				};
3020			};
3021		};
3022
3023		adsp_pil: remoteproc@9300000 {
3024			compatible = "qcom,msm8996-adsp-pil";
3025			reg = <0x09300000 0x80000>;
3026
3027			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3028					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3029					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3030					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3031					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3032			interrupt-names = "wdog", "fatal", "ready",
3033					  "handover", "stop-ack";
3034
3035			clocks = <&xo_board>;
3036			clock-names = "xo";
3037
3038			memory-region = <&adsp_region>;
3039
3040			qcom,smem-states = <&smp2p_adsp_out 0>;
3041			qcom,smem-state-names = "stop";
3042
3043			power-domains = <&rpmpd MSM8996_VDDCX>;
3044			power-domain-names = "cx";
3045
3046			status = "disabled";
3047
3048			smd-edge {
3049				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3050
3051				label = "lpass";
3052				mboxes = <&apcs_glb 8>;
3053				qcom,smd-edge = <1>;
3054				qcom,remote-pid = <2>;
3055				#address-cells = <1>;
3056				#size-cells = <0>;
3057				apr {
3058					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3059					compatible = "qcom,apr-v2";
3060					qcom,smd-channels = "apr_audio_svc";
3061					qcom,apr-domain = <APR_DOMAIN_ADSP>;
3062					#address-cells = <1>;
3063					#size-cells = <0>;
3064
3065					q6core {
3066						reg = <APR_SVC_ADSP_CORE>;
3067						compatible = "qcom,q6core";
3068					};
3069
3070					q6afe: q6afe {
3071						compatible = "qcom,q6afe";
3072						reg = <APR_SVC_AFE>;
3073						q6afedai: dais {
3074							compatible = "qcom,q6afe-dais";
3075							#address-cells = <1>;
3076							#size-cells = <0>;
3077							#sound-dai-cells = <1>;
3078							hdmi@1 {
3079								reg = <1>;
3080							};
3081						};
3082					};
3083
3084					q6asm: q6asm {
3085						compatible = "qcom,q6asm";
3086						reg = <APR_SVC_ASM>;
3087						q6asmdai: dais {
3088							compatible = "qcom,q6asm-dais";
3089							#address-cells = <1>;
3090							#size-cells = <0>;
3091							#sound-dai-cells = <1>;
3092							iommus = <&lpass_q6_smmu 1>;
3093						};
3094					};
3095
3096					q6adm: q6adm {
3097						compatible = "qcom,q6adm";
3098						reg = <APR_SVC_ADM>;
3099						q6routing: routing {
3100							compatible = "qcom,q6adm-routing";
3101							#sound-dai-cells = <0>;
3102						};
3103					};
3104				};
3105
3106			};
3107		};
3108
3109		apcs_glb: mailbox@9820000 {
3110			compatible = "qcom,msm8996-apcs-hmss-global";
3111			reg = <0x09820000 0x1000>;
3112
3113			#mbox-cells = <1>;
3114		};
3115
3116		timer@9840000 {
3117			#address-cells = <1>;
3118			#size-cells = <1>;
3119			ranges;
3120			compatible = "arm,armv7-timer-mem";
3121			reg = <0x09840000 0x1000>;
3122			clock-frequency = <19200000>;
3123
3124			frame@9850000 {
3125				frame-number = <0>;
3126				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3127					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3128				reg = <0x09850000 0x1000>,
3129				      <0x09860000 0x1000>;
3130			};
3131
3132			frame@9870000 {
3133				frame-number = <1>;
3134				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3135				reg = <0x09870000 0x1000>;
3136				status = "disabled";
3137			};
3138
3139			frame@9880000 {
3140				frame-number = <2>;
3141				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3142				reg = <0x09880000 0x1000>;
3143				status = "disabled";
3144			};
3145
3146			frame@9890000 {
3147				frame-number = <3>;
3148				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3149				reg = <0x09890000 0x1000>;
3150				status = "disabled";
3151			};
3152
3153			frame@98a0000 {
3154				frame-number = <4>;
3155				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3156				reg = <0x098a0000 0x1000>;
3157				status = "disabled";
3158			};
3159
3160			frame@98b0000 {
3161				frame-number = <5>;
3162				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3163				reg = <0x098b0000 0x1000>;
3164				status = "disabled";
3165			};
3166
3167			frame@98c0000 {
3168				frame-number = <6>;
3169				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3170				reg = <0x098c0000 0x1000>;
3171				status = "disabled";
3172			};
3173		};
3174
3175		saw3: syscon@9a10000 {
3176			compatible = "syscon";
3177			reg = <0x09a10000 0x1000>;
3178		};
3179
3180		intc: interrupt-controller@9bc0000 {
3181			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3182			#interrupt-cells = <3>;
3183			interrupt-controller;
3184			#redistributor-regions = <1>;
3185			redistributor-stride = <0x0 0x40000>;
3186			reg = <0x09bc0000 0x10000>,
3187			      <0x09c00000 0x100000>;
3188			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3189		};
3190	};
3191
3192	sound: sound {
3193	};
3194
3195	thermal-zones {
3196		cpu0-thermal {
3197			polling-delay-passive = <250>;
3198			polling-delay = <1000>;
3199
3200			thermal-sensors = <&tsens0 3>;
3201
3202			trips {
3203				cpu0_alert0: trip-point0 {
3204					temperature = <75000>;
3205					hysteresis = <2000>;
3206					type = "passive";
3207				};
3208
3209				cpu0_crit: cpu_crit {
3210					temperature = <110000>;
3211					hysteresis = <2000>;
3212					type = "critical";
3213				};
3214			};
3215		};
3216
3217		cpu1-thermal {
3218			polling-delay-passive = <250>;
3219			polling-delay = <1000>;
3220
3221			thermal-sensors = <&tsens0 5>;
3222
3223			trips {
3224				cpu1_alert0: trip-point0 {
3225					temperature = <75000>;
3226					hysteresis = <2000>;
3227					type = "passive";
3228				};
3229
3230				cpu1_crit: cpu_crit {
3231					temperature = <110000>;
3232					hysteresis = <2000>;
3233					type = "critical";
3234				};
3235			};
3236		};
3237
3238		cpu2-thermal {
3239			polling-delay-passive = <250>;
3240			polling-delay = <1000>;
3241
3242			thermal-sensors = <&tsens0 8>;
3243
3244			trips {
3245				cpu2_alert0: trip-point0 {
3246					temperature = <75000>;
3247					hysteresis = <2000>;
3248					type = "passive";
3249				};
3250
3251				cpu2_crit: cpu_crit {
3252					temperature = <110000>;
3253					hysteresis = <2000>;
3254					type = "critical";
3255				};
3256			};
3257		};
3258
3259		cpu3-thermal {
3260			polling-delay-passive = <250>;
3261			polling-delay = <1000>;
3262
3263			thermal-sensors = <&tsens0 10>;
3264
3265			trips {
3266				cpu3_alert0: trip-point0 {
3267					temperature = <75000>;
3268					hysteresis = <2000>;
3269					type = "passive";
3270				};
3271
3272				cpu3_crit: cpu_crit {
3273					temperature = <110000>;
3274					hysteresis = <2000>;
3275					type = "critical";
3276				};
3277			};
3278		};
3279
3280		gpu-thermal-top {
3281			polling-delay-passive = <250>;
3282			polling-delay = <1000>;
3283
3284			thermal-sensors = <&tsens1 6>;
3285
3286			trips {
3287				gpu1_alert0: trip-point0 {
3288					temperature = <90000>;
3289					hysteresis = <2000>;
3290					type = "passive";
3291				};
3292			};
3293
3294			cooling-maps {
3295				map0 {
3296					trip = <&gpu1_alert0>;
3297					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3298				};
3299			};
3300		};
3301
3302		gpu-thermal-bottom {
3303			polling-delay-passive = <250>;
3304			polling-delay = <1000>;
3305
3306			thermal-sensors = <&tsens1 7>;
3307
3308			trips {
3309				gpu2_alert0: trip-point0 {
3310					temperature = <90000>;
3311					hysteresis = <2000>;
3312					type = "passive";
3313				};
3314			};
3315
3316			cooling-maps {
3317				map0 {
3318					trip = <&gpu2_alert0>;
3319					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3320				};
3321			};
3322		};
3323
3324		m4m-thermal {
3325			polling-delay-passive = <250>;
3326			polling-delay = <1000>;
3327
3328			thermal-sensors = <&tsens0 1>;
3329
3330			trips {
3331				m4m_alert0: trip-point0 {
3332					temperature = <90000>;
3333					hysteresis = <2000>;
3334					type = "hot";
3335				};
3336			};
3337		};
3338
3339		l3-or-venus-thermal {
3340			polling-delay-passive = <250>;
3341			polling-delay = <1000>;
3342
3343			thermal-sensors = <&tsens0 2>;
3344
3345			trips {
3346				l3_or_venus_alert0: trip-point0 {
3347					temperature = <90000>;
3348					hysteresis = <2000>;
3349					type = "hot";
3350				};
3351			};
3352		};
3353
3354		cluster0-l2-thermal {
3355			polling-delay-passive = <250>;
3356			polling-delay = <1000>;
3357
3358			thermal-sensors = <&tsens0 7>;
3359
3360			trips {
3361				cluster0_l2_alert0: trip-point0 {
3362					temperature = <90000>;
3363					hysteresis = <2000>;
3364					type = "hot";
3365				};
3366			};
3367		};
3368
3369		cluster1-l2-thermal {
3370			polling-delay-passive = <250>;
3371			polling-delay = <1000>;
3372
3373			thermal-sensors = <&tsens0 12>;
3374
3375			trips {
3376				cluster1_l2_alert0: trip-point0 {
3377					temperature = <90000>;
3378					hysteresis = <2000>;
3379					type = "hot";
3380				};
3381			};
3382		};
3383
3384		camera-thermal {
3385			polling-delay-passive = <250>;
3386			polling-delay = <1000>;
3387
3388			thermal-sensors = <&tsens1 1>;
3389
3390			trips {
3391				camera_alert0: trip-point0 {
3392					temperature = <90000>;
3393					hysteresis = <2000>;
3394					type = "hot";
3395				};
3396			};
3397		};
3398
3399		q6-dsp-thermal {
3400			polling-delay-passive = <250>;
3401			polling-delay = <1000>;
3402
3403			thermal-sensors = <&tsens1 2>;
3404
3405			trips {
3406				q6_dsp_alert0: trip-point0 {
3407					temperature = <90000>;
3408					hysteresis = <2000>;
3409					type = "hot";
3410				};
3411			};
3412		};
3413
3414		mem-thermal {
3415			polling-delay-passive = <250>;
3416			polling-delay = <1000>;
3417
3418			thermal-sensors = <&tsens1 3>;
3419
3420			trips {
3421				mem_alert0: trip-point0 {
3422					temperature = <90000>;
3423					hysteresis = <2000>;
3424					type = "hot";
3425				};
3426			};
3427		};
3428
3429		modemtx-thermal {
3430			polling-delay-passive = <250>;
3431			polling-delay = <1000>;
3432
3433			thermal-sensors = <&tsens1 4>;
3434
3435			trips {
3436				modemtx_alert0: trip-point0 {
3437					temperature = <90000>;
3438					hysteresis = <2000>;
3439					type = "hot";
3440				};
3441			};
3442		};
3443	};
3444
3445	timer {
3446		compatible = "arm,armv8-timer";
3447		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3448			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3449			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3450			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3451	};
3452};
3453