1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,apr.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <19200000>; 30 clock-output-names = "xo_board"; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 cpu-idle-states = <&CPU_SLEEP_0>; 51 capacity-dmips-mhz = <1024>; 52 clocks = <&kryocc 0>; 53 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 54 operating-points-v2 = <&cluster0_opp>; 55 #cooling-cells = <2>; 56 next-level-cache = <&L2_0>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 }; 62 }; 63 64 CPU1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo"; 67 reg = <0x0 0x1>; 68 enable-method = "psci"; 69 cpu-idle-states = <&CPU_SLEEP_0>; 70 capacity-dmips-mhz = <1024>; 71 clocks = <&kryocc 0>; 72 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 73 operating-points-v2 = <&cluster0_opp>; 74 #cooling-cells = <2>; 75 next-level-cache = <&L2_0>; 76 }; 77 78 CPU2: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 capacity-dmips-mhz = <1024>; 85 clocks = <&kryocc 1>; 86 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 87 operating-points-v2 = <&cluster1_opp>; 88 #cooling-cells = <2>; 89 next-level-cache = <&L2_1>; 90 L2_1: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 }; 95 }; 96 97 CPU3: cpu@101 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo"; 100 reg = <0x0 0x101>; 101 enable-method = "psci"; 102 cpu-idle-states = <&CPU_SLEEP_0>; 103 capacity-dmips-mhz = <1024>; 104 clocks = <&kryocc 1>; 105 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 106 operating-points-v2 = <&cluster1_opp>; 107 #cooling-cells = <2>; 108 next-level-cache = <&L2_1>; 109 }; 110 111 cpu-map { 112 cluster0 { 113 core0 { 114 cpu = <&CPU0>; 115 }; 116 117 core1 { 118 cpu = <&CPU1>; 119 }; 120 }; 121 122 cluster1 { 123 core0 { 124 cpu = <&CPU2>; 125 }; 126 127 core1 { 128 cpu = <&CPU3>; 129 }; 130 }; 131 }; 132 133 idle-states { 134 entry-method = "psci"; 135 136 CPU_SLEEP_0: cpu-sleep-0 { 137 compatible = "arm,idle-state"; 138 idle-state-name = "standalone-power-collapse"; 139 arm,psci-suspend-param = <0x00000004>; 140 entry-latency-us = <130>; 141 exit-latency-us = <80>; 142 min-residency-us = <300>; 143 }; 144 }; 145 }; 146 147 cluster0_opp: opp-table-cluster0 { 148 compatible = "operating-points-v2-kryo-cpu"; 149 nvmem-cells = <&speedbin_efuse>; 150 opp-shared; 151 152 /* Nominal fmax for now */ 153 opp-307200000 { 154 opp-hz = /bits/ 64 <307200000>; 155 opp-supported-hw = <0xf>; 156 clock-latency-ns = <200000>; 157 opp-peak-kBps = <307200>; 158 }; 159 opp-422400000 { 160 opp-hz = /bits/ 64 <422400000>; 161 opp-supported-hw = <0xf>; 162 clock-latency-ns = <200000>; 163 opp-peak-kBps = <307200>; 164 }; 165 opp-480000000 { 166 opp-hz = /bits/ 64 <480000000>; 167 opp-supported-hw = <0xf>; 168 clock-latency-ns = <200000>; 169 opp-peak-kBps = <307200>; 170 }; 171 opp-556800000 { 172 opp-hz = /bits/ 64 <556800000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 opp-peak-kBps = <307200>; 176 }; 177 opp-652800000 { 178 opp-hz = /bits/ 64 <652800000>; 179 opp-supported-hw = <0xf>; 180 clock-latency-ns = <200000>; 181 opp-peak-kBps = <384000>; 182 }; 183 opp-729600000 { 184 opp-hz = /bits/ 64 <729600000>; 185 opp-supported-hw = <0xf>; 186 clock-latency-ns = <200000>; 187 opp-peak-kBps = <460800>; 188 }; 189 opp-844800000 { 190 opp-hz = /bits/ 64 <844800000>; 191 opp-supported-hw = <0xf>; 192 clock-latency-ns = <200000>; 193 opp-peak-kBps = <537600>; 194 }; 195 opp-960000000 { 196 opp-hz = /bits/ 64 <960000000>; 197 opp-supported-hw = <0xf>; 198 clock-latency-ns = <200000>; 199 opp-peak-kBps = <672000>; 200 }; 201 opp-1036800000 { 202 opp-hz = /bits/ 64 <1036800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 opp-peak-kBps = <672000>; 206 }; 207 opp-1113600000 { 208 opp-hz = /bits/ 64 <1113600000>; 209 opp-supported-hw = <0xf>; 210 clock-latency-ns = <200000>; 211 opp-peak-kBps = <825600>; 212 }; 213 opp-1190400000 { 214 opp-hz = /bits/ 64 <1190400000>; 215 opp-supported-hw = <0xf>; 216 clock-latency-ns = <200000>; 217 opp-peak-kBps = <825600>; 218 }; 219 opp-1228800000 { 220 opp-hz = /bits/ 64 <1228800000>; 221 opp-supported-hw = <0xf>; 222 clock-latency-ns = <200000>; 223 opp-peak-kBps = <902400>; 224 }; 225 opp-1324800000 { 226 opp-hz = /bits/ 64 <1324800000>; 227 opp-supported-hw = <0xd>; 228 clock-latency-ns = <200000>; 229 opp-peak-kBps = <1056000>; 230 }; 231 opp-1363200000 { 232 opp-hz = /bits/ 64 <1363200000>; 233 opp-supported-hw = <0x2>; 234 clock-latency-ns = <200000>; 235 opp-peak-kBps = <1132800>; 236 }; 237 opp-1401600000 { 238 opp-hz = /bits/ 64 <1401600000>; 239 opp-supported-hw = <0xd>; 240 clock-latency-ns = <200000>; 241 opp-peak-kBps = <1132800>; 242 }; 243 opp-1478400000 { 244 opp-hz = /bits/ 64 <1478400000>; 245 opp-supported-hw = <0x9>; 246 clock-latency-ns = <200000>; 247 opp-peak-kBps = <1190400>; 248 }; 249 opp-1497600000 { 250 opp-hz = /bits/ 64 <1497600000>; 251 opp-supported-hw = <0x04>; 252 clock-latency-ns = <200000>; 253 opp-peak-kBps = <1305600>; 254 }; 255 opp-1593600000 { 256 opp-hz = /bits/ 64 <1593600000>; 257 opp-supported-hw = <0x9>; 258 clock-latency-ns = <200000>; 259 opp-peak-kBps = <1382400>; 260 }; 261 }; 262 263 cluster1_opp: opp-table-cluster1 { 264 compatible = "operating-points-v2-kryo-cpu"; 265 nvmem-cells = <&speedbin_efuse>; 266 opp-shared; 267 268 /* Nominal fmax for now */ 269 opp-307200000 { 270 opp-hz = /bits/ 64 <307200000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 opp-peak-kBps = <307200>; 274 }; 275 opp-403200000 { 276 opp-hz = /bits/ 64 <403200000>; 277 opp-supported-hw = <0xf>; 278 clock-latency-ns = <200000>; 279 opp-peak-kBps = <307200>; 280 }; 281 opp-480000000 { 282 opp-hz = /bits/ 64 <480000000>; 283 opp-supported-hw = <0xf>; 284 clock-latency-ns = <200000>; 285 opp-peak-kBps = <307200>; 286 }; 287 opp-556800000 { 288 opp-hz = /bits/ 64 <556800000>; 289 opp-supported-hw = <0xf>; 290 clock-latency-ns = <200000>; 291 opp-peak-kBps = <307200>; 292 }; 293 opp-652800000 { 294 opp-hz = /bits/ 64 <652800000>; 295 opp-supported-hw = <0xf>; 296 clock-latency-ns = <200000>; 297 opp-peak-kBps = <307200>; 298 }; 299 opp-729600000 { 300 opp-hz = /bits/ 64 <729600000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 opp-peak-kBps = <307200>; 304 }; 305 opp-806400000 { 306 opp-hz = /bits/ 64 <806400000>; 307 opp-supported-hw = <0xf>; 308 clock-latency-ns = <200000>; 309 opp-peak-kBps = <384000>; 310 }; 311 opp-883200000 { 312 opp-hz = /bits/ 64 <883200000>; 313 opp-supported-hw = <0xf>; 314 clock-latency-ns = <200000>; 315 opp-peak-kBps = <460800>; 316 }; 317 opp-940800000 { 318 opp-hz = /bits/ 64 <940800000>; 319 opp-supported-hw = <0xf>; 320 clock-latency-ns = <200000>; 321 opp-peak-kBps = <537600>; 322 }; 323 opp-1036800000 { 324 opp-hz = /bits/ 64 <1036800000>; 325 opp-supported-hw = <0xf>; 326 clock-latency-ns = <200000>; 327 opp-peak-kBps = <595200>; 328 }; 329 opp-1113600000 { 330 opp-hz = /bits/ 64 <1113600000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 opp-peak-kBps = <672000>; 334 }; 335 opp-1190400000 { 336 opp-hz = /bits/ 64 <1190400000>; 337 opp-supported-hw = <0xf>; 338 clock-latency-ns = <200000>; 339 opp-peak-kBps = <672000>; 340 }; 341 opp-1248000000 { 342 opp-hz = /bits/ 64 <1248000000>; 343 opp-supported-hw = <0xf>; 344 clock-latency-ns = <200000>; 345 opp-peak-kBps = <748800>; 346 }; 347 opp-1324800000 { 348 opp-hz = /bits/ 64 <1324800000>; 349 opp-supported-hw = <0xf>; 350 clock-latency-ns = <200000>; 351 opp-peak-kBps = <825600>; 352 }; 353 opp-1401600000 { 354 opp-hz = /bits/ 64 <1401600000>; 355 opp-supported-hw = <0xf>; 356 clock-latency-ns = <200000>; 357 opp-peak-kBps = <902400>; 358 }; 359 opp-1478400000 { 360 opp-hz = /bits/ 64 <1478400000>; 361 opp-supported-hw = <0xf>; 362 clock-latency-ns = <200000>; 363 opp-peak-kBps = <979200>; 364 }; 365 opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-supported-hw = <0xf>; 368 clock-latency-ns = <200000>; 369 opp-peak-kBps = <1056000>; 370 }; 371 opp-1632000000 { 372 opp-hz = /bits/ 64 <1632000000>; 373 opp-supported-hw = <0xf>; 374 clock-latency-ns = <200000>; 375 opp-peak-kBps = <1190400>; 376 }; 377 opp-1708800000 { 378 opp-hz = /bits/ 64 <1708800000>; 379 opp-supported-hw = <0xf>; 380 clock-latency-ns = <200000>; 381 opp-peak-kBps = <1228800>; 382 }; 383 opp-1785600000 { 384 opp-hz = /bits/ 64 <1785600000>; 385 opp-supported-hw = <0xf>; 386 clock-latency-ns = <200000>; 387 opp-peak-kBps = <1305600>; 388 }; 389 opp-1804800000 { 390 opp-hz = /bits/ 64 <1804800000>; 391 opp-supported-hw = <0xe>; 392 clock-latency-ns = <200000>; 393 opp-peak-kBps = <1305600>; 394 }; 395 opp-1824000000 { 396 opp-hz = /bits/ 64 <1824000000>; 397 opp-supported-hw = <0x1>; 398 clock-latency-ns = <200000>; 399 opp-peak-kBps = <1382400>; 400 }; 401 opp-1900800000 { 402 opp-hz = /bits/ 64 <1900800000>; 403 opp-supported-hw = <0x4>; 404 clock-latency-ns = <200000>; 405 opp-peak-kBps = <1305600>; 406 }; 407 opp-1920000000 { 408 opp-hz = /bits/ 64 <1920000000>; 409 opp-supported-hw = <0x1>; 410 clock-latency-ns = <200000>; 411 opp-peak-kBps = <1459200>; 412 }; 413 opp-1996800000 { 414 opp-hz = /bits/ 64 <1996800000>; 415 opp-supported-hw = <0x1>; 416 clock-latency-ns = <200000>; 417 opp-peak-kBps = <1593600>; 418 }; 419 opp-2073600000 { 420 opp-hz = /bits/ 64 <2073600000>; 421 opp-supported-hw = <0x1>; 422 clock-latency-ns = <200000>; 423 opp-peak-kBps = <1593600>; 424 }; 425 opp-2150400000 { 426 opp-hz = /bits/ 64 <2150400000>; 427 opp-supported-hw = <0x1>; 428 clock-latency-ns = <200000>; 429 opp-peak-kBps = <1593600>; 430 }; 431 }; 432 433 firmware { 434 scm { 435 compatible = "qcom,scm-msm8996", "qcom,scm"; 436 qcom,dload-mode = <&tcsr_2 0x13000>; 437 }; 438 }; 439 440 memory@80000000 { 441 device_type = "memory"; 442 /* We expect the bootloader to fill in the reg */ 443 reg = <0x0 0x80000000 0x0 0x0>; 444 }; 445 446 psci { 447 compatible = "arm,psci-1.0"; 448 method = "smc"; 449 }; 450 451 rpm: remoteproc { 452 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 453 454 glink-edge { 455 compatible = "qcom,glink-rpm"; 456 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 457 qcom,rpm-msg-ram = <&rpm_msg_ram>; 458 mboxes = <&apcs_glb 0>; 459 460 rpm_requests: rpm-requests { 461 compatible = "qcom,rpm-msm8996"; 462 qcom,glink-channels = "rpm_requests"; 463 464 rpmcc: clock-controller { 465 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 466 #clock-cells = <1>; 467 clocks = <&xo_board>; 468 clock-names = "xo"; 469 }; 470 471 rpmpd: power-controller { 472 compatible = "qcom,msm8996-rpmpd"; 473 #power-domain-cells = <1>; 474 operating-points-v2 = <&rpmpd_opp_table>; 475 476 rpmpd_opp_table: opp-table { 477 compatible = "operating-points-v2"; 478 479 rpmpd_opp1: opp1 { 480 opp-level = <1>; 481 }; 482 483 rpmpd_opp2: opp2 { 484 opp-level = <2>; 485 }; 486 487 rpmpd_opp3: opp3 { 488 opp-level = <3>; 489 }; 490 491 rpmpd_opp4: opp4 { 492 opp-level = <4>; 493 }; 494 495 rpmpd_opp5: opp5 { 496 opp-level = <5>; 497 }; 498 499 rpmpd_opp6: opp6 { 500 opp-level = <6>; 501 }; 502 }; 503 }; 504 }; 505 }; 506 }; 507 508 reserved-memory { 509 #address-cells = <2>; 510 #size-cells = <2>; 511 ranges; 512 513 hyp_mem: memory@85800000 { 514 reg = <0x0 0x85800000 0x0 0x600000>; 515 no-map; 516 }; 517 518 xbl_mem: memory@85e00000 { 519 reg = <0x0 0x85e00000 0x0 0x200000>; 520 no-map; 521 }; 522 523 smem_mem: smem-mem@86000000 { 524 reg = <0x0 0x86000000 0x0 0x200000>; 525 no-map; 526 }; 527 528 tz_mem: memory@86200000 { 529 reg = <0x0 0x86200000 0x0 0x2600000>; 530 no-map; 531 }; 532 533 rmtfs_mem: rmtfs { 534 compatible = "qcom,rmtfs-mem"; 535 536 size = <0x0 0x200000>; 537 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 538 no-map; 539 540 qcom,client-id = <1>; 541 qcom,vmid = <15>; 542 }; 543 544 mpss_mem: mpss@88800000 { 545 reg = <0x0 0x88800000 0x0 0x6200000>; 546 no-map; 547 }; 548 549 adsp_mem: adsp@8ea00000 { 550 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 551 no-map; 552 }; 553 554 slpi_mem: slpi@90500000 { 555 reg = <0x0 0x90500000 0x0 0xa00000>; 556 no-map; 557 }; 558 559 gpu_mem: gpu@90f00000 { 560 compatible = "shared-dma-pool"; 561 reg = <0x0 0x90f00000 0x0 0x100000>; 562 no-map; 563 }; 564 565 venus_mem: venus@91000000 { 566 reg = <0x0 0x91000000 0x0 0x500000>; 567 no-map; 568 }; 569 570 mba_mem: mba@91500000 { 571 reg = <0x0 0x91500000 0x0 0x200000>; 572 no-map; 573 }; 574 575 mdata_mem: mpss-metadata { 576 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 577 size = <0x0 0x4000>; 578 no-map; 579 }; 580 }; 581 582 smem { 583 compatible = "qcom,smem"; 584 memory-region = <&smem_mem>; 585 hwlocks = <&tcsr_mutex 3>; 586 }; 587 588 smp2p-adsp { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <443>, <429>; 591 592 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 593 594 mboxes = <&apcs_glb 10>; 595 596 qcom,local-pid = <0>; 597 qcom,remote-pid = <2>; 598 599 adsp_smp2p_out: master-kernel { 600 qcom,entry-name = "master-kernel"; 601 #qcom,smem-state-cells = <1>; 602 }; 603 604 adsp_smp2p_in: slave-kernel { 605 qcom,entry-name = "slave-kernel"; 606 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 }; 611 612 smp2p-mpss { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <435>, <428>; 615 616 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 617 618 mboxes = <&apcs_glb 14>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <1>; 622 623 mpss_smp2p_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 mpss_smp2p_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-slpi { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <481>, <430>; 639 640 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&apcs_glb 26>; 643 644 qcom,local-pid = <0>; 645 qcom,remote-pid = <3>; 646 647 slpi_smp2p_out: master-kernel { 648 qcom,entry-name = "master-kernel"; 649 #qcom,smem-state-cells = <1>; 650 }; 651 652 slpi_smp2p_in: slave-kernel { 653 qcom,entry-name = "slave-kernel"; 654 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 soc: soc@0 { 661 #address-cells = <1>; 662 #size-cells = <1>; 663 ranges = <0 0 0 0xffffffff>; 664 compatible = "simple-bus"; 665 666 pcie_phy: phy-wrapper@34000 { 667 compatible = "qcom,msm8996-qmp-pcie-phy"; 668 reg = <0x00034000 0x488>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 ranges = <0x0 0x00034000 0x4000>; 672 673 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 674 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 675 <&gcc GCC_PCIE_CLKREF_CLK>; 676 clock-names = "aux", "cfg_ahb", "ref"; 677 678 resets = <&gcc GCC_PCIE_PHY_BCR>, 679 <&gcc GCC_PCIE_PHY_COM_BCR>, 680 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 681 reset-names = "phy", "common", "cfg"; 682 683 status = "disabled"; 684 685 pciephy_0: phy@1000 { 686 reg = <0x1000 0x130>, 687 <0x1200 0x200>, 688 <0x1400 0x1dc>; 689 690 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 691 clock-names = "pipe0"; 692 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 693 reset-names = "lane0"; 694 695 #clock-cells = <0>; 696 clock-output-names = "pcie_0_pipe_clk_src"; 697 698 #phy-cells = <0>; 699 }; 700 701 pciephy_1: phy@2000 { 702 reg = <0x2000 0x130>, 703 <0x2200 0x200>, 704 <0x2400 0x1dc>; 705 706 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 707 clock-names = "pipe1"; 708 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 709 reset-names = "lane1"; 710 711 #clock-cells = <0>; 712 clock-output-names = "pcie_1_pipe_clk_src"; 713 714 #phy-cells = <0>; 715 }; 716 717 pciephy_2: phy@3000 { 718 reg = <0x3000 0x130>, 719 <0x3200 0x200>, 720 <0x3400 0x1dc>; 721 722 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 723 clock-names = "pipe2"; 724 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 725 reset-names = "lane2"; 726 727 #clock-cells = <0>; 728 clock-output-names = "pcie_2_pipe_clk_src"; 729 730 #phy-cells = <0>; 731 }; 732 }; 733 734 rpm_msg_ram: sram@68000 { 735 compatible = "qcom,rpm-msg-ram"; 736 reg = <0x00068000 0x6000>; 737 }; 738 739 qfprom@74000 { 740 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 741 reg = <0x00074000 0x8ff>; 742 #address-cells = <1>; 743 #size-cells = <1>; 744 745 qusb2p_hstx_trim: hstx_trim@24e { 746 reg = <0x24e 0x2>; 747 bits = <5 4>; 748 }; 749 750 qusb2s_hstx_trim: hstx_trim@24f { 751 reg = <0x24f 0x1>; 752 bits = <1 4>; 753 }; 754 755 speedbin_efuse: speedbin@133 { 756 reg = <0x133 0x1>; 757 bits = <5 3>; 758 }; 759 }; 760 761 rng: rng@83000 { 762 compatible = "qcom,prng-ee"; 763 reg = <0x00083000 0x1000>; 764 clocks = <&gcc GCC_PRNG_AHB_CLK>; 765 clock-names = "core"; 766 }; 767 768 gcc: clock-controller@300000 { 769 compatible = "qcom,gcc-msm8996"; 770 #clock-cells = <1>; 771 #reset-cells = <1>; 772 #power-domain-cells = <1>; 773 reg = <0x00300000 0x90000>; 774 775 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 776 <&rpmcc RPM_SMD_LN_BB_CLK>, 777 <&sleep_clk>, 778 <&pciephy_0>, 779 <&pciephy_1>, 780 <&pciephy_2>, 781 <&ssusb_phy_0>, 782 <&ufsphy_lane 0>, 783 <&ufsphy_lane 1>, 784 <&ufsphy_lane 2>; 785 clock-names = "cxo", 786 "cxo2", 787 "sleep_clk", 788 "pcie_0_pipe_clk_src", 789 "pcie_1_pipe_clk_src", 790 "pcie_2_pipe_clk_src", 791 "usb3_phy_pipe_clk_src", 792 "ufs_rx_symbol_0_clk_src", 793 "ufs_rx_symbol_1_clk_src", 794 "ufs_tx_symbol_0_clk_src"; 795 }; 796 797 bimc: interconnect@408000 { 798 compatible = "qcom,msm8996-bimc"; 799 reg = <0x00408000 0x5a000>; 800 #interconnect-cells = <1>; 801 clock-names = "bus", "bus_a"; 802 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 803 <&rpmcc RPM_SMD_BIMC_A_CLK>; 804 }; 805 806 tsens0: thermal-sensor@4a9000 { 807 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 808 reg = <0x004a9000 0x1000>, /* TM */ 809 <0x004a8000 0x1000>; /* SROT */ 810 #qcom,sensors = <13>; 811 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 813 interrupt-names = "uplow", "critical"; 814 #thermal-sensor-cells = <1>; 815 }; 816 817 tsens1: thermal-sensor@4ad000 { 818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 819 reg = <0x004ad000 0x1000>, /* TM */ 820 <0x004ac000 0x1000>; /* SROT */ 821 #qcom,sensors = <8>; 822 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 824 interrupt-names = "uplow", "critical"; 825 #thermal-sensor-cells = <1>; 826 }; 827 828 cryptobam: dma-controller@644000 { 829 compatible = "qcom,bam-v1.7.0"; 830 reg = <0x00644000 0x24000>; 831 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&gcc GCC_CE1_CLK>; 833 clock-names = "bam_clk"; 834 #dma-cells = <1>; 835 qcom,ee = <0>; 836 qcom,controlled-remotely; 837 }; 838 839 crypto: crypto@67a000 { 840 compatible = "qcom,crypto-v5.4"; 841 reg = <0x0067a000 0x6000>; 842 clocks = <&gcc GCC_CE1_AHB_CLK>, 843 <&gcc GCC_CE1_AXI_CLK>, 844 <&gcc GCC_CE1_CLK>; 845 clock-names = "iface", "bus", "core"; 846 dmas = <&cryptobam 6>, <&cryptobam 7>; 847 dma-names = "rx", "tx"; 848 }; 849 850 cnoc: interconnect@500000 { 851 compatible = "qcom,msm8996-cnoc"; 852 reg = <0x00500000 0x1000>; 853 #interconnect-cells = <1>; 854 clock-names = "bus", "bus_a"; 855 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 856 <&rpmcc RPM_SMD_CNOC_A_CLK>; 857 }; 858 859 snoc: interconnect@524000 { 860 compatible = "qcom,msm8996-snoc"; 861 reg = <0x00524000 0x1c000>; 862 #interconnect-cells = <1>; 863 clock-names = "bus", "bus_a"; 864 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 865 <&rpmcc RPM_SMD_SNOC_A_CLK>; 866 }; 867 868 a0noc: interconnect@543000 { 869 compatible = "qcom,msm8996-a0noc"; 870 reg = <0x00543000 0x6000>; 871 #interconnect-cells = <1>; 872 clock-names = "aggre0_snoc_axi", 873 "aggre0_cnoc_ahb", 874 "aggre0_noc_mpu_cfg"; 875 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 876 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 877 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 878 power-domains = <&gcc AGGRE0_NOC_GDSC>; 879 }; 880 881 a1noc: interconnect@562000 { 882 compatible = "qcom,msm8996-a1noc"; 883 reg = <0x00562000 0x5000>; 884 #interconnect-cells = <1>; 885 clock-names = "bus", "bus_a"; 886 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 887 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 888 }; 889 890 a2noc: interconnect@583000 { 891 compatible = "qcom,msm8996-a2noc"; 892 reg = <0x00583000 0x7000>; 893 #interconnect-cells = <1>; 894 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 895 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 896 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 897 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 898 <&gcc GCC_UFS_AXI_CLK>; 899 }; 900 901 mnoc: interconnect@5a4000 { 902 compatible = "qcom,msm8996-mnoc"; 903 reg = <0x005a4000 0x1c000>; 904 #interconnect-cells = <1>; 905 clock-names = "bus", "bus_a", "iface"; 906 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 907 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 908 <&mmcc AHB_CLK_SRC>; 909 }; 910 911 pnoc: interconnect@5c0000 { 912 compatible = "qcom,msm8996-pnoc"; 913 reg = <0x005c0000 0x3000>; 914 #interconnect-cells = <1>; 915 clock-names = "bus", "bus_a"; 916 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 917 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 918 }; 919 920 tcsr_mutex: hwlock@740000 { 921 compatible = "qcom,tcsr-mutex"; 922 reg = <0x00740000 0x20000>; 923 #hwlock-cells = <1>; 924 }; 925 926 tcsr_1: syscon@760000 { 927 compatible = "qcom,tcsr-msm8996", "syscon"; 928 reg = <0x00760000 0x20000>; 929 }; 930 931 tcsr_2: syscon@7a0000 { 932 compatible = "qcom,tcsr-msm8996", "syscon"; 933 reg = <0x007a0000 0x18000>; 934 }; 935 936 mmcc: clock-controller@8c0000 { 937 compatible = "qcom,mmcc-msm8996"; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 #power-domain-cells = <1>; 941 reg = <0x008c0000 0x40000>; 942 clocks = <&xo_board>, 943 <&gcc GPLL0>, 944 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 945 <&mdss_dsi0_phy 1>, 946 <&mdss_dsi0_phy 0>, 947 <&mdss_dsi1_phy 1>, 948 <&mdss_dsi1_phy 0>, 949 <&mdss_hdmi_phy>; 950 clock-names = "xo", 951 "gpll0", 952 "gcc_mmss_noc_cfg_ahb_clk", 953 "dsi0pll", 954 "dsi0pllbyte", 955 "dsi1pll", 956 "dsi1pllbyte", 957 "hdmipll"; 958 assigned-clocks = <&mmcc MMPLL9_PLL>, 959 <&mmcc MMPLL1_PLL>, 960 <&mmcc MMPLL3_PLL>, 961 <&mmcc MMPLL4_PLL>, 962 <&mmcc MMPLL5_PLL>; 963 assigned-clock-rates = <624000000>, 964 <810000000>, 965 <980000000>, 966 <960000000>, 967 <825000000>; 968 }; 969 970 mdss: display-subsystem@900000 { 971 compatible = "qcom,mdss"; 972 973 reg = <0x00900000 0x1000>, 974 <0x009b0000 0x1040>, 975 <0x009b8000 0x1040>; 976 reg-names = "mdss_phys", 977 "vbif_phys", 978 "vbif_nrt_phys"; 979 980 power-domains = <&mmcc MDSS_GDSC>; 981 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 982 983 interrupt-controller; 984 #interrupt-cells = <1>; 985 986 clocks = <&mmcc MDSS_AHB_CLK>, 987 <&mmcc MDSS_MDP_CLK>; 988 clock-names = "iface", "core"; 989 990 #address-cells = <1>; 991 #size-cells = <1>; 992 ranges; 993 994 status = "disabled"; 995 996 mdp: display-controller@901000 { 997 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 998 reg = <0x00901000 0x90000>; 999 reg-names = "mdp_phys"; 1000 1001 interrupt-parent = <&mdss>; 1002 interrupts = <0>; 1003 1004 clocks = <&mmcc MDSS_AHB_CLK>, 1005 <&mmcc MDSS_AXI_CLK>, 1006 <&mmcc MDSS_MDP_CLK>, 1007 <&mmcc SMMU_MDP_AXI_CLK>, 1008 <&mmcc MDSS_VSYNC_CLK>; 1009 clock-names = "iface", 1010 "bus", 1011 "core", 1012 "iommu", 1013 "vsync"; 1014 1015 iommus = <&mdp_smmu 0>; 1016 1017 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1018 <&mmcc MDSS_VSYNC_CLK>; 1019 assigned-clock-rates = <300000000>, 1020 <19200000>; 1021 1022 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1023 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1024 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1025 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1026 1027 ports { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 1031 port@0 { 1032 reg = <0>; 1033 mdp5_intf3_out: endpoint { 1034 remote-endpoint = <&mdss_hdmi_in>; 1035 }; 1036 }; 1037 1038 port@1 { 1039 reg = <1>; 1040 mdp5_intf1_out: endpoint { 1041 remote-endpoint = <&mdss_dsi0_in>; 1042 }; 1043 }; 1044 1045 port@2 { 1046 reg = <2>; 1047 mdp5_intf2_out: endpoint { 1048 remote-endpoint = <&mdss_dsi1_in>; 1049 }; 1050 }; 1051 }; 1052 }; 1053 1054 mdss_dsi0: dsi@994000 { 1055 compatible = "qcom,msm8996-dsi-ctrl", 1056 "qcom,mdss-dsi-ctrl"; 1057 reg = <0x00994000 0x400>; 1058 reg-names = "dsi_ctrl"; 1059 1060 interrupt-parent = <&mdss>; 1061 interrupts = <4>; 1062 1063 clocks = <&mmcc MDSS_MDP_CLK>, 1064 <&mmcc MDSS_BYTE0_CLK>, 1065 <&mmcc MDSS_AHB_CLK>, 1066 <&mmcc MDSS_AXI_CLK>, 1067 <&mmcc MMSS_MISC_AHB_CLK>, 1068 <&mmcc MDSS_PCLK0_CLK>, 1069 <&mmcc MDSS_ESC0_CLK>; 1070 clock-names = "mdp_core", 1071 "byte", 1072 "iface", 1073 "bus", 1074 "core_mmss", 1075 "pixel", 1076 "core"; 1077 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1078 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1079 1080 phys = <&mdss_dsi0_phy>; 1081 status = "disabled"; 1082 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 ports { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 port@0 { 1091 reg = <0>; 1092 mdss_dsi0_in: endpoint { 1093 remote-endpoint = <&mdp5_intf1_out>; 1094 }; 1095 }; 1096 1097 port@1 { 1098 reg = <1>; 1099 mdss_dsi0_out: endpoint { 1100 }; 1101 }; 1102 }; 1103 }; 1104 1105 mdss_dsi0_phy: phy@994400 { 1106 compatible = "qcom,dsi-phy-14nm"; 1107 reg = <0x00994400 0x100>, 1108 <0x00994500 0x300>, 1109 <0x00994800 0x188>; 1110 reg-names = "dsi_phy", 1111 "dsi_phy_lane", 1112 "dsi_pll"; 1113 1114 #clock-cells = <1>; 1115 #phy-cells = <0>; 1116 1117 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1118 clock-names = "iface", "ref"; 1119 status = "disabled"; 1120 }; 1121 1122 mdss_dsi1: dsi@996000 { 1123 compatible = "qcom,msm8996-dsi-ctrl", 1124 "qcom,mdss-dsi-ctrl"; 1125 reg = <0x00996000 0x400>; 1126 reg-names = "dsi_ctrl"; 1127 1128 interrupt-parent = <&mdss>; 1129 interrupts = <5>; 1130 1131 clocks = <&mmcc MDSS_MDP_CLK>, 1132 <&mmcc MDSS_BYTE1_CLK>, 1133 <&mmcc MDSS_AHB_CLK>, 1134 <&mmcc MDSS_AXI_CLK>, 1135 <&mmcc MMSS_MISC_AHB_CLK>, 1136 <&mmcc MDSS_PCLK1_CLK>, 1137 <&mmcc MDSS_ESC1_CLK>; 1138 clock-names = "mdp_core", 1139 "byte", 1140 "iface", 1141 "bus", 1142 "core_mmss", 1143 "pixel", 1144 "core"; 1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1146 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1147 1148 phys = <&mdss_dsi1_phy>; 1149 status = "disabled"; 1150 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 1154 ports { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 port@0 { 1159 reg = <0>; 1160 mdss_dsi1_in: endpoint { 1161 remote-endpoint = <&mdp5_intf2_out>; 1162 }; 1163 }; 1164 1165 port@1 { 1166 reg = <1>; 1167 mdss_dsi1_out: endpoint { 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 mdss_dsi1_phy: phy@996400 { 1174 compatible = "qcom,dsi-phy-14nm"; 1175 reg = <0x00996400 0x100>, 1176 <0x00996500 0x300>, 1177 <0x00996800 0x188>; 1178 reg-names = "dsi_phy", 1179 "dsi_phy_lane", 1180 "dsi_pll"; 1181 1182 #clock-cells = <1>; 1183 #phy-cells = <0>; 1184 1185 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1186 clock-names = "iface", "ref"; 1187 status = "disabled"; 1188 }; 1189 1190 mdss_hdmi: hdmi-tx@9a0000 { 1191 compatible = "qcom,hdmi-tx-8996"; 1192 reg = <0x009a0000 0x50c>, 1193 <0x00070000 0x6158>, 1194 <0x009e0000 0xfff>; 1195 reg-names = "core_physical", 1196 "qfprom_physical", 1197 "hdcp_physical"; 1198 1199 interrupt-parent = <&mdss>; 1200 interrupts = <8>; 1201 1202 clocks = <&mmcc MDSS_MDP_CLK>, 1203 <&mmcc MDSS_AHB_CLK>, 1204 <&mmcc MDSS_HDMI_CLK>, 1205 <&mmcc MDSS_HDMI_AHB_CLK>, 1206 <&mmcc MDSS_EXTPCLK_CLK>; 1207 clock-names = 1208 "mdp_core", 1209 "iface", 1210 "core", 1211 "alt_iface", 1212 "extp"; 1213 1214 phys = <&mdss_hdmi_phy>; 1215 #sound-dai-cells = <1>; 1216 1217 status = "disabled"; 1218 1219 ports { 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 1223 port@0 { 1224 reg = <0>; 1225 mdss_hdmi_in: endpoint { 1226 remote-endpoint = <&mdp5_intf3_out>; 1227 }; 1228 }; 1229 }; 1230 }; 1231 1232 mdss_hdmi_phy: phy@9a0600 { 1233 #phy-cells = <0>; 1234 compatible = "qcom,hdmi-phy-8996"; 1235 reg = <0x009a0600 0x1c4>, 1236 <0x009a0a00 0x124>, 1237 <0x009a0c00 0x124>, 1238 <0x009a0e00 0x124>, 1239 <0x009a1000 0x124>, 1240 <0x009a1200 0x0c8>; 1241 reg-names = "hdmi_pll", 1242 "hdmi_tx_l0", 1243 "hdmi_tx_l1", 1244 "hdmi_tx_l2", 1245 "hdmi_tx_l3", 1246 "hdmi_phy"; 1247 1248 clocks = <&mmcc MDSS_AHB_CLK>, 1249 <&gcc GCC_HDMI_CLKREF_CLK>, 1250 <&xo_board>; 1251 clock-names = "iface", 1252 "ref", 1253 "xo"; 1254 1255 #clock-cells = <0>; 1256 1257 status = "disabled"; 1258 }; 1259 }; 1260 1261 gpu: gpu@b00000 { 1262 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1263 1264 reg = <0x00b00000 0x3f000>; 1265 reg-names = "kgsl_3d0_reg_memory"; 1266 1267 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1268 1269 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1270 <&mmcc GPU_AHB_CLK>, 1271 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1272 <&gcc GCC_BIMC_GFX_CLK>, 1273 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1274 1275 clock-names = "core", 1276 "iface", 1277 "rbbmtimer", 1278 "mem", 1279 "mem_iface"; 1280 1281 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1282 interconnect-names = "gfx-mem"; 1283 1284 power-domains = <&mmcc GPU_GX_GDSC>; 1285 iommus = <&adreno_smmu 0>; 1286 1287 nvmem-cells = <&speedbin_efuse>; 1288 nvmem-cell-names = "speed_bin"; 1289 1290 operating-points-v2 = <&gpu_opp_table>; 1291 1292 status = "disabled"; 1293 1294 #cooling-cells = <2>; 1295 1296 gpu_opp_table: opp-table { 1297 compatible = "operating-points-v2"; 1298 1299 /* 1300 * 624Mhz is only available on speed bins 0 and 3. 1301 * 560Mhz is only available on speed bins 0, 2 and 3. 1302 * All the rest are available on all bins of the hardware. 1303 */ 1304 opp-624000000 { 1305 opp-hz = /bits/ 64 <624000000>; 1306 opp-supported-hw = <0x09>; 1307 }; 1308 opp-560000000 { 1309 opp-hz = /bits/ 64 <560000000>; 1310 opp-supported-hw = <0x0d>; 1311 }; 1312 opp-510000000 { 1313 opp-hz = /bits/ 64 <510000000>; 1314 opp-supported-hw = <0xff>; 1315 }; 1316 opp-401800000 { 1317 opp-hz = /bits/ 64 <401800000>; 1318 opp-supported-hw = <0xff>; 1319 }; 1320 opp-315000000 { 1321 opp-hz = /bits/ 64 <315000000>; 1322 opp-supported-hw = <0xff>; 1323 }; 1324 opp-214000000 { 1325 opp-hz = /bits/ 64 <214000000>; 1326 opp-supported-hw = <0xff>; 1327 }; 1328 opp-133000000 { 1329 opp-hz = /bits/ 64 <133000000>; 1330 opp-supported-hw = <0xff>; 1331 }; 1332 }; 1333 1334 zap-shader { 1335 memory-region = <&gpu_mem>; 1336 }; 1337 }; 1338 1339 tlmm: pinctrl@1010000 { 1340 compatible = "qcom,msm8996-pinctrl"; 1341 reg = <0x01010000 0x300000>; 1342 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1343 gpio-controller; 1344 gpio-ranges = <&tlmm 0 0 150>; 1345 #gpio-cells = <2>; 1346 interrupt-controller; 1347 #interrupt-cells = <2>; 1348 1349 blsp1_spi1_default: blsp1-spi1-default-state { 1350 spi-pins { 1351 pins = "gpio0", "gpio1", "gpio3"; 1352 function = "blsp_spi1"; 1353 drive-strength = <12>; 1354 bias-disable; 1355 }; 1356 1357 cs-pins { 1358 pins = "gpio2"; 1359 function = "gpio"; 1360 drive-strength = <16>; 1361 bias-disable; 1362 output-high; 1363 }; 1364 }; 1365 1366 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1367 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1368 function = "gpio"; 1369 drive-strength = <2>; 1370 bias-pull-down; 1371 }; 1372 1373 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1374 pins = "gpio4", "gpio5"; 1375 function = "blsp_uart8"; 1376 drive-strength = <16>; 1377 bias-disable; 1378 }; 1379 1380 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1381 pins = "gpio4", "gpio5"; 1382 function = "gpio"; 1383 drive-strength = <2>; 1384 bias-disable; 1385 }; 1386 1387 blsp2_i2c2_default: blsp2-i2c2-state { 1388 pins = "gpio6", "gpio7"; 1389 function = "blsp_i2c8"; 1390 drive-strength = <16>; 1391 bias-disable; 1392 }; 1393 1394 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1395 pins = "gpio6", "gpio7"; 1396 function = "gpio"; 1397 drive-strength = <2>; 1398 bias-disable; 1399 }; 1400 1401 blsp1_i2c6_default: blsp1-i2c6-state { 1402 pins = "gpio27", "gpio28"; 1403 function = "blsp_i2c6"; 1404 drive-strength = <16>; 1405 bias-disable; 1406 }; 1407 1408 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1409 pins = "gpio27", "gpio28"; 1410 function = "gpio"; 1411 drive-strength = <2>; 1412 bias-pull-up; 1413 }; 1414 1415 cci0_default: cci0-default-state { 1416 pins = "gpio17", "gpio18"; 1417 function = "cci_i2c"; 1418 drive-strength = <16>; 1419 bias-disable; 1420 }; 1421 1422 camera0_state_on: 1423 camera_rear_default: camera-rear-default-state { 1424 camera0_mclk: mclk0-pins { 1425 pins = "gpio13"; 1426 function = "cam_mclk"; 1427 drive-strength = <16>; 1428 bias-disable; 1429 }; 1430 1431 camera0_rst: rst-pins { 1432 pins = "gpio25"; 1433 function = "gpio"; 1434 drive-strength = <16>; 1435 bias-disable; 1436 }; 1437 1438 camera0_pwdn: pwdn-pins { 1439 pins = "gpio26"; 1440 function = "gpio"; 1441 drive-strength = <16>; 1442 bias-disable; 1443 }; 1444 }; 1445 1446 cci1_default: cci1-default-state { 1447 pins = "gpio19", "gpio20"; 1448 function = "cci_i2c"; 1449 drive-strength = <16>; 1450 bias-disable; 1451 }; 1452 1453 camera1_state_on: 1454 camera_board_default: camera-board-default-state { 1455 mclk1-pins { 1456 pins = "gpio14"; 1457 function = "cam_mclk"; 1458 drive-strength = <16>; 1459 bias-disable; 1460 }; 1461 1462 pwdn-pins { 1463 pins = "gpio98"; 1464 function = "gpio"; 1465 drive-strength = <16>; 1466 bias-disable; 1467 }; 1468 1469 rst-pins { 1470 pins = "gpio104"; 1471 function = "gpio"; 1472 drive-strength = <16>; 1473 bias-disable; 1474 }; 1475 }; 1476 1477 camera2_state_on: 1478 camera_front_default: camera-front-default-state { 1479 camera2_mclk: mclk2-pins { 1480 pins = "gpio15"; 1481 function = "cam_mclk"; 1482 drive-strength = <16>; 1483 bias-disable; 1484 }; 1485 1486 camera2_rst: rst-pins { 1487 pins = "gpio23"; 1488 function = "gpio"; 1489 drive-strength = <16>; 1490 bias-disable; 1491 }; 1492 1493 pwdn-pins { 1494 pins = "gpio133"; 1495 function = "gpio"; 1496 drive-strength = <16>; 1497 bias-disable; 1498 }; 1499 }; 1500 1501 pcie0_state_on: pcie0-state-on-state { 1502 perst-pins { 1503 pins = "gpio35"; 1504 function = "gpio"; 1505 drive-strength = <2>; 1506 bias-pull-down; 1507 }; 1508 1509 clkreq-pins { 1510 pins = "gpio36"; 1511 function = "pci_e0"; 1512 drive-strength = <2>; 1513 bias-pull-up; 1514 }; 1515 1516 wake-pins { 1517 pins = "gpio37"; 1518 function = "gpio"; 1519 drive-strength = <2>; 1520 bias-pull-up; 1521 }; 1522 }; 1523 1524 pcie0_state_off: pcie0-state-off-state { 1525 perst-pins { 1526 pins = "gpio35"; 1527 function = "gpio"; 1528 drive-strength = <2>; 1529 bias-pull-down; 1530 }; 1531 1532 clkreq-pins { 1533 pins = "gpio36"; 1534 function = "gpio"; 1535 drive-strength = <2>; 1536 bias-disable; 1537 }; 1538 1539 wake-pins { 1540 pins = "gpio37"; 1541 function = "gpio"; 1542 drive-strength = <2>; 1543 bias-disable; 1544 }; 1545 }; 1546 1547 blsp1_uart2_default: blsp1-uart2-default-state { 1548 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1549 function = "blsp_uart2"; 1550 drive-strength = <16>; 1551 bias-disable; 1552 }; 1553 1554 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1555 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1556 function = "gpio"; 1557 drive-strength = <2>; 1558 bias-disable; 1559 }; 1560 1561 blsp1_i2c3_default: blsp1-i2c3-default-state { 1562 pins = "gpio47", "gpio48"; 1563 function = "blsp_i2c3"; 1564 drive-strength = <16>; 1565 bias-disable; 1566 }; 1567 1568 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1569 pins = "gpio47", "gpio48"; 1570 function = "gpio"; 1571 drive-strength = <2>; 1572 bias-disable; 1573 }; 1574 1575 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1576 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1577 function = "blsp_uart9"; 1578 drive-strength = <16>; 1579 bias-disable; 1580 }; 1581 1582 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1583 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1584 function = "blsp_uart9"; 1585 drive-strength = <2>; 1586 bias-disable; 1587 }; 1588 1589 blsp2_i2c3_default: blsp2-i2c3-state-state { 1590 pins = "gpio51", "gpio52"; 1591 function = "blsp_i2c9"; 1592 drive-strength = <16>; 1593 bias-disable; 1594 }; 1595 1596 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1597 pins = "gpio51", "gpio52"; 1598 function = "gpio"; 1599 drive-strength = <2>; 1600 bias-disable; 1601 }; 1602 1603 wcd_intr_default: wcd-intr-default-state { 1604 pins = "gpio54"; 1605 function = "gpio"; 1606 drive-strength = <2>; 1607 bias-pull-down; 1608 }; 1609 1610 blsp2_i2c1_default: blsp2-i2c1-state { 1611 pins = "gpio55", "gpio56"; 1612 function = "blsp_i2c7"; 1613 drive-strength = <16>; 1614 bias-disable; 1615 }; 1616 1617 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1618 pins = "gpio55", "gpio56"; 1619 function = "gpio"; 1620 drive-strength = <2>; 1621 bias-disable; 1622 }; 1623 1624 blsp2_i2c5_default: blsp2-i2c5-state { 1625 pins = "gpio60", "gpio61"; 1626 function = "blsp_i2c11"; 1627 drive-strength = <2>; 1628 bias-disable; 1629 }; 1630 1631 /* Sleep state for BLSP2_I2C5 is missing.. */ 1632 1633 cdc_reset_active: cdc-reset-active-state { 1634 pins = "gpio64"; 1635 function = "gpio"; 1636 drive-strength = <16>; 1637 bias-pull-down; 1638 output-high; 1639 }; 1640 1641 cdc_reset_sleep: cdc-reset-sleep-state { 1642 pins = "gpio64"; 1643 function = "gpio"; 1644 drive-strength = <16>; 1645 bias-disable; 1646 output-low; 1647 }; 1648 1649 blsp2_spi6_default: blsp2-spi6-default-state { 1650 spi-pins { 1651 pins = "gpio85", "gpio86", "gpio88"; 1652 function = "blsp_spi12"; 1653 drive-strength = <12>; 1654 bias-disable; 1655 }; 1656 1657 cs-pins { 1658 pins = "gpio87"; 1659 function = "gpio"; 1660 drive-strength = <16>; 1661 bias-disable; 1662 output-high; 1663 }; 1664 }; 1665 1666 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1667 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1668 function = "gpio"; 1669 drive-strength = <2>; 1670 bias-pull-down; 1671 }; 1672 1673 blsp2_i2c6_default: blsp2-i2c6-state { 1674 pins = "gpio87", "gpio88"; 1675 function = "blsp_i2c12"; 1676 drive-strength = <16>; 1677 bias-disable; 1678 }; 1679 1680 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1681 pins = "gpio87", "gpio88"; 1682 function = "gpio"; 1683 drive-strength = <2>; 1684 bias-disable; 1685 }; 1686 1687 pcie1_state_on: pcie1-on-state { 1688 perst-pins { 1689 pins = "gpio130"; 1690 function = "gpio"; 1691 drive-strength = <2>; 1692 bias-pull-down; 1693 }; 1694 1695 clkreq-pins { 1696 pins = "gpio131"; 1697 function = "pci_e1"; 1698 drive-strength = <2>; 1699 bias-pull-up; 1700 }; 1701 1702 wake-pins { 1703 pins = "gpio132"; 1704 function = "gpio"; 1705 drive-strength = <2>; 1706 bias-pull-down; 1707 }; 1708 }; 1709 1710 pcie1_state_off: pcie1-off-state { 1711 /* Perst is missing? */ 1712 clkreq-pins { 1713 pins = "gpio131"; 1714 function = "gpio"; 1715 drive-strength = <2>; 1716 bias-disable; 1717 }; 1718 1719 wake-pins { 1720 pins = "gpio132"; 1721 function = "gpio"; 1722 drive-strength = <2>; 1723 bias-disable; 1724 }; 1725 }; 1726 1727 pcie2_state_on: pcie2-on-state { 1728 perst-pins { 1729 pins = "gpio114"; 1730 function = "gpio"; 1731 drive-strength = <2>; 1732 bias-pull-down; 1733 }; 1734 1735 clkreq-pins { 1736 pins = "gpio115"; 1737 function = "pci_e2"; 1738 drive-strength = <2>; 1739 bias-pull-up; 1740 }; 1741 1742 wake-pins { 1743 pins = "gpio116"; 1744 function = "gpio"; 1745 drive-strength = <2>; 1746 bias-pull-down; 1747 }; 1748 }; 1749 1750 pcie2_state_off: pcie2-off-state { 1751 /* Perst is missing? */ 1752 clkreq-pins { 1753 pins = "gpio115"; 1754 function = "gpio"; 1755 drive-strength = <2>; 1756 bias-disable; 1757 }; 1758 1759 wake-pins { 1760 pins = "gpio116"; 1761 function = "gpio"; 1762 drive-strength = <2>; 1763 bias-disable; 1764 }; 1765 }; 1766 1767 sdc1_state_on: sdc1-on-state { 1768 clk-pins { 1769 pins = "sdc1_clk"; 1770 bias-disable; 1771 drive-strength = <16>; 1772 }; 1773 1774 cmd-pins { 1775 pins = "sdc1_cmd"; 1776 bias-pull-up; 1777 drive-strength = <10>; 1778 }; 1779 1780 data-pins { 1781 pins = "sdc1_data"; 1782 bias-pull-up; 1783 drive-strength = <10>; 1784 }; 1785 1786 rclk-pins { 1787 pins = "sdc1_rclk"; 1788 bias-pull-down; 1789 }; 1790 }; 1791 1792 sdc1_state_off: sdc1-off-state { 1793 clk-pins { 1794 pins = "sdc1_clk"; 1795 bias-disable; 1796 drive-strength = <2>; 1797 }; 1798 1799 cmd-pins { 1800 pins = "sdc1_cmd"; 1801 bias-pull-up; 1802 drive-strength = <2>; 1803 }; 1804 1805 data-pins { 1806 pins = "sdc1_data"; 1807 bias-pull-up; 1808 drive-strength = <2>; 1809 }; 1810 1811 rclk-pins { 1812 pins = "sdc1_rclk"; 1813 bias-pull-down; 1814 }; 1815 }; 1816 1817 sdc2_state_on: sdc2-on-state { 1818 clk-pins { 1819 pins = "sdc2_clk"; 1820 bias-disable; 1821 drive-strength = <16>; 1822 }; 1823 1824 cmd-pins { 1825 pins = "sdc2_cmd"; 1826 bias-pull-up; 1827 drive-strength = <10>; 1828 }; 1829 1830 data-pins { 1831 pins = "sdc2_data"; 1832 bias-pull-up; 1833 drive-strength = <10>; 1834 }; 1835 }; 1836 1837 sdc2_state_off: sdc2-off-state { 1838 clk-pins { 1839 pins = "sdc2_clk"; 1840 bias-disable; 1841 drive-strength = <2>; 1842 }; 1843 1844 cmd-pins { 1845 pins = "sdc2_cmd"; 1846 bias-pull-up; 1847 drive-strength = <2>; 1848 }; 1849 1850 data-pins { 1851 pins = "sdc2_data"; 1852 bias-pull-up; 1853 drive-strength = <2>; 1854 }; 1855 }; 1856 }; 1857 1858 sram@290000 { 1859 compatible = "qcom,rpm-stats"; 1860 reg = <0x00290000 0x10000>; 1861 }; 1862 1863 spmi_bus: spmi@400f000 { 1864 compatible = "qcom,spmi-pmic-arb"; 1865 reg = <0x0400f000 0x1000>, 1866 <0x04400000 0x800000>, 1867 <0x04c00000 0x800000>, 1868 <0x05800000 0x200000>, 1869 <0x0400a000 0x002100>; 1870 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1871 interrupt-names = "periph_irq"; 1872 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1873 qcom,ee = <0>; 1874 qcom,channel = <0>; 1875 #address-cells = <2>; 1876 #size-cells = <0>; 1877 interrupt-controller; 1878 #interrupt-cells = <4>; 1879 }; 1880 1881 bus@0 { 1882 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1883 compatible = "simple-pm-bus"; 1884 #address-cells = <1>; 1885 #size-cells = <1>; 1886 ranges = <0x0 0x0 0xffffffff>; 1887 1888 pcie0: pcie@600000 { 1889 compatible = "qcom,pcie-msm8996"; 1890 status = "disabled"; 1891 power-domains = <&gcc PCIE0_GDSC>; 1892 bus-range = <0x00 0xff>; 1893 num-lanes = <1>; 1894 1895 reg = <0x00600000 0x2000>, 1896 <0x0c000000 0xf1d>, 1897 <0x0c000f20 0xa8>, 1898 <0x0c100000 0x100000>; 1899 reg-names = "parf", "dbi", "elbi","config"; 1900 1901 phys = <&pciephy_0>; 1902 phy-names = "pciephy"; 1903 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1907 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1908 1909 device_type = "pci"; 1910 1911 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1912 interrupt-names = "msi"; 1913 #interrupt-cells = <1>; 1914 interrupt-map-mask = <0 0 0 0x7>; 1915 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1916 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1917 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1918 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1919 1920 pinctrl-names = "default", "sleep"; 1921 pinctrl-0 = <&pcie0_state_on>; 1922 pinctrl-1 = <&pcie0_state_off>; 1923 1924 linux,pci-domain = <0>; 1925 1926 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1927 <&gcc GCC_PCIE_0_AUX_CLK>, 1928 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1929 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1930 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1931 1932 clock-names = "pipe", 1933 "aux", 1934 "cfg", 1935 "bus_master", 1936 "bus_slave"; 1937 }; 1938 1939 pcie1: pcie@608000 { 1940 compatible = "qcom,pcie-msm8996"; 1941 power-domains = <&gcc PCIE1_GDSC>; 1942 bus-range = <0x00 0xff>; 1943 num-lanes = <1>; 1944 1945 status = "disabled"; 1946 1947 reg = <0x00608000 0x2000>, 1948 <0x0d000000 0xf1d>, 1949 <0x0d000f20 0xa8>, 1950 <0x0d100000 0x100000>; 1951 1952 reg-names = "parf", "dbi", "elbi","config"; 1953 1954 phys = <&pciephy_1>; 1955 phy-names = "pciephy"; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1960 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1961 1962 device_type = "pci"; 1963 1964 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "msi"; 1966 #interrupt-cells = <1>; 1967 interrupt-map-mask = <0 0 0 0x7>; 1968 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1969 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1970 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1971 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1972 1973 pinctrl-names = "default", "sleep"; 1974 pinctrl-0 = <&pcie1_state_on>; 1975 pinctrl-1 = <&pcie1_state_off>; 1976 1977 linux,pci-domain = <1>; 1978 1979 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1980 <&gcc GCC_PCIE_1_AUX_CLK>, 1981 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1982 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1983 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1984 1985 clock-names = "pipe", 1986 "aux", 1987 "cfg", 1988 "bus_master", 1989 "bus_slave"; 1990 }; 1991 1992 pcie2: pcie@610000 { 1993 compatible = "qcom,pcie-msm8996"; 1994 power-domains = <&gcc PCIE2_GDSC>; 1995 bus-range = <0x00 0xff>; 1996 num-lanes = <1>; 1997 status = "disabled"; 1998 reg = <0x00610000 0x2000>, 1999 <0x0e000000 0xf1d>, 2000 <0x0e000f20 0xa8>, 2001 <0x0e100000 0x100000>; 2002 2003 reg-names = "parf", "dbi", "elbi","config"; 2004 2005 phys = <&pciephy_2>; 2006 phy-names = "pciephy"; 2007 2008 #address-cells = <3>; 2009 #size-cells = <2>; 2010 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2011 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2012 2013 device_type = "pci"; 2014 2015 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "msi"; 2017 #interrupt-cells = <1>; 2018 interrupt-map-mask = <0 0 0 0x7>; 2019 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2020 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2021 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2022 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2023 2024 pinctrl-names = "default", "sleep"; 2025 pinctrl-0 = <&pcie2_state_on>; 2026 pinctrl-1 = <&pcie2_state_off>; 2027 2028 linux,pci-domain = <2>; 2029 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2030 <&gcc GCC_PCIE_2_AUX_CLK>, 2031 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2032 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2033 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2034 2035 clock-names = "pipe", 2036 "aux", 2037 "cfg", 2038 "bus_master", 2039 "bus_slave"; 2040 }; 2041 }; 2042 2043 ufshc: ufshc@624000 { 2044 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2045 "jedec,ufs-2.0"; 2046 reg = <0x00624000 0x2500>; 2047 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2048 2049 phys = <&ufsphy_lane>; 2050 phy-names = "ufsphy"; 2051 2052 power-domains = <&gcc UFS_GDSC>; 2053 2054 clock-names = 2055 "core_clk_src", 2056 "core_clk", 2057 "bus_clk", 2058 "bus_aggr_clk", 2059 "iface_clk", 2060 "core_clk_unipro_src", 2061 "core_clk_unipro", 2062 "core_clk_ice", 2063 "ref_clk", 2064 "tx_lane0_sync_clk", 2065 "rx_lane0_sync_clk"; 2066 clocks = 2067 <&gcc UFS_AXI_CLK_SRC>, 2068 <&gcc GCC_UFS_AXI_CLK>, 2069 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2070 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2071 <&gcc GCC_UFS_AHB_CLK>, 2072 <&gcc UFS_ICE_CORE_CLK_SRC>, 2073 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2074 <&gcc GCC_UFS_ICE_CORE_CLK>, 2075 <&rpmcc RPM_SMD_LN_BB_CLK>, 2076 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2077 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2078 freq-table-hz = 2079 <100000000 200000000>, 2080 <0 0>, 2081 <0 0>, 2082 <0 0>, 2083 <0 0>, 2084 <150000000 300000000>, 2085 <0 0>, 2086 <0 0>, 2087 <0 0>, 2088 <0 0>, 2089 <0 0>; 2090 2091 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2092 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2093 interconnect-names = "ufs-ddr", "cpu-ufs"; 2094 2095 lanes-per-direction = <1>; 2096 #reset-cells = <1>; 2097 status = "disabled"; 2098 }; 2099 2100 ufsphy: phy@627000 { 2101 compatible = "qcom,msm8996-qmp-ufs-phy"; 2102 reg = <0x00627000 0x1c4>; 2103 #address-cells = <1>; 2104 #size-cells = <1>; 2105 ranges; 2106 2107 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2108 clock-names = "ref"; 2109 2110 resets = <&ufshc 0>; 2111 reset-names = "ufsphy"; 2112 status = "disabled"; 2113 2114 ufsphy_lane: phy@627400 { 2115 reg = <0x627400 0x12c>, 2116 <0x627600 0x200>, 2117 <0x627c00 0x1b4>; 2118 #clock-cells = <1>; 2119 #phy-cells = <0>; 2120 }; 2121 }; 2122 2123 camss: camss@a34000 { 2124 compatible = "qcom,msm8996-camss"; 2125 reg = <0x00a34000 0x1000>, 2126 <0x00a00030 0x4>, 2127 <0x00a35000 0x1000>, 2128 <0x00a00038 0x4>, 2129 <0x00a36000 0x1000>, 2130 <0x00a00040 0x4>, 2131 <0x00a30000 0x100>, 2132 <0x00a30400 0x100>, 2133 <0x00a30800 0x100>, 2134 <0x00a30c00 0x100>, 2135 <0x00a31000 0x500>, 2136 <0x00a00020 0x10>, 2137 <0x00a10000 0x1000>, 2138 <0x00a14000 0x1000>; 2139 reg-names = "csiphy0", 2140 "csiphy0_clk_mux", 2141 "csiphy1", 2142 "csiphy1_clk_mux", 2143 "csiphy2", 2144 "csiphy2_clk_mux", 2145 "csid0", 2146 "csid1", 2147 "csid2", 2148 "csid3", 2149 "ispif", 2150 "csi_clk_mux", 2151 "vfe0", 2152 "vfe1"; 2153 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2154 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2155 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2156 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2157 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2158 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2159 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2160 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2161 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2162 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2163 interrupt-names = "csiphy0", 2164 "csiphy1", 2165 "csiphy2", 2166 "csid0", 2167 "csid1", 2168 "csid2", 2169 "csid3", 2170 "ispif", 2171 "vfe0", 2172 "vfe1"; 2173 power-domains = <&mmcc VFE0_GDSC>, 2174 <&mmcc VFE1_GDSC>; 2175 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2176 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2177 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2178 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2179 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2180 <&mmcc CAMSS_CSI0_AHB_CLK>, 2181 <&mmcc CAMSS_CSI0_CLK>, 2182 <&mmcc CAMSS_CSI0PHY_CLK>, 2183 <&mmcc CAMSS_CSI0PIX_CLK>, 2184 <&mmcc CAMSS_CSI0RDI_CLK>, 2185 <&mmcc CAMSS_CSI1_AHB_CLK>, 2186 <&mmcc CAMSS_CSI1_CLK>, 2187 <&mmcc CAMSS_CSI1PHY_CLK>, 2188 <&mmcc CAMSS_CSI1PIX_CLK>, 2189 <&mmcc CAMSS_CSI1RDI_CLK>, 2190 <&mmcc CAMSS_CSI2_AHB_CLK>, 2191 <&mmcc CAMSS_CSI2_CLK>, 2192 <&mmcc CAMSS_CSI2PHY_CLK>, 2193 <&mmcc CAMSS_CSI2PIX_CLK>, 2194 <&mmcc CAMSS_CSI2RDI_CLK>, 2195 <&mmcc CAMSS_CSI3_AHB_CLK>, 2196 <&mmcc CAMSS_CSI3_CLK>, 2197 <&mmcc CAMSS_CSI3PHY_CLK>, 2198 <&mmcc CAMSS_CSI3PIX_CLK>, 2199 <&mmcc CAMSS_CSI3RDI_CLK>, 2200 <&mmcc CAMSS_AHB_CLK>, 2201 <&mmcc CAMSS_VFE0_CLK>, 2202 <&mmcc CAMSS_CSI_VFE0_CLK>, 2203 <&mmcc CAMSS_VFE0_AHB_CLK>, 2204 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2205 <&mmcc CAMSS_VFE1_CLK>, 2206 <&mmcc CAMSS_CSI_VFE1_CLK>, 2207 <&mmcc CAMSS_VFE1_AHB_CLK>, 2208 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2209 <&mmcc CAMSS_VFE_AHB_CLK>, 2210 <&mmcc CAMSS_VFE_AXI_CLK>; 2211 clock-names = "top_ahb", 2212 "ispif_ahb", 2213 "csiphy0_timer", 2214 "csiphy1_timer", 2215 "csiphy2_timer", 2216 "csi0_ahb", 2217 "csi0", 2218 "csi0_phy", 2219 "csi0_pix", 2220 "csi0_rdi", 2221 "csi1_ahb", 2222 "csi1", 2223 "csi1_phy", 2224 "csi1_pix", 2225 "csi1_rdi", 2226 "csi2_ahb", 2227 "csi2", 2228 "csi2_phy", 2229 "csi2_pix", 2230 "csi2_rdi", 2231 "csi3_ahb", 2232 "csi3", 2233 "csi3_phy", 2234 "csi3_pix", 2235 "csi3_rdi", 2236 "ahb", 2237 "vfe0", 2238 "csi_vfe0", 2239 "vfe0_ahb", 2240 "vfe0_stream", 2241 "vfe1", 2242 "csi_vfe1", 2243 "vfe1_ahb", 2244 "vfe1_stream", 2245 "vfe_ahb", 2246 "vfe_axi"; 2247 iommus = <&vfe_smmu 0>, 2248 <&vfe_smmu 1>, 2249 <&vfe_smmu 2>, 2250 <&vfe_smmu 3>; 2251 status = "disabled"; 2252 ports { 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 }; 2256 }; 2257 2258 cci: cci@a0c000 { 2259 compatible = "qcom,msm8996-cci"; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 reg = <0xa0c000 0x1000>; 2263 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2264 power-domains = <&mmcc CAMSS_GDSC>; 2265 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2266 <&mmcc CAMSS_CCI_AHB_CLK>, 2267 <&mmcc CAMSS_CCI_CLK>, 2268 <&mmcc CAMSS_AHB_CLK>; 2269 clock-names = "camss_top_ahb", 2270 "cci_ahb", 2271 "cci", 2272 "camss_ahb"; 2273 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2274 <&mmcc CAMSS_CCI_CLK>; 2275 assigned-clock-rates = <80000000>, <37500000>; 2276 pinctrl-names = "default"; 2277 pinctrl-0 = <&cci0_default &cci1_default>; 2278 status = "disabled"; 2279 2280 cci_i2c0: i2c-bus@0 { 2281 reg = <0>; 2282 clock-frequency = <400000>; 2283 #address-cells = <1>; 2284 #size-cells = <0>; 2285 }; 2286 2287 cci_i2c1: i2c-bus@1 { 2288 reg = <1>; 2289 clock-frequency = <400000>; 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 }; 2293 }; 2294 2295 adreno_smmu: iommu@b40000 { 2296 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2297 reg = <0x00b40000 0x10000>; 2298 2299 #global-interrupts = <1>; 2300 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2303 #iommu-cells = <1>; 2304 2305 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2306 <&mmcc GPU_AHB_CLK>; 2307 clock-names = "bus", "iface"; 2308 2309 power-domains = <&mmcc GPU_GDSC>; 2310 }; 2311 2312 venus: video-codec@c00000 { 2313 compatible = "qcom,msm8996-venus"; 2314 reg = <0x00c00000 0xff000>; 2315 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2316 power-domains = <&mmcc VENUS_GDSC>; 2317 clocks = <&mmcc VIDEO_CORE_CLK>, 2318 <&mmcc VIDEO_AHB_CLK>, 2319 <&mmcc VIDEO_AXI_CLK>, 2320 <&mmcc VIDEO_MAXI_CLK>; 2321 clock-names = "core", "iface", "bus", "mbus"; 2322 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2323 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2324 interconnect-names = "video-mem", "cpu-cfg"; 2325 iommus = <&venus_smmu 0x00>, 2326 <&venus_smmu 0x01>, 2327 <&venus_smmu 0x0a>, 2328 <&venus_smmu 0x07>, 2329 <&venus_smmu 0x0e>, 2330 <&venus_smmu 0x0f>, 2331 <&venus_smmu 0x08>, 2332 <&venus_smmu 0x09>, 2333 <&venus_smmu 0x0b>, 2334 <&venus_smmu 0x0c>, 2335 <&venus_smmu 0x0d>, 2336 <&venus_smmu 0x10>, 2337 <&venus_smmu 0x11>, 2338 <&venus_smmu 0x21>, 2339 <&venus_smmu 0x28>, 2340 <&venus_smmu 0x29>, 2341 <&venus_smmu 0x2b>, 2342 <&venus_smmu 0x2c>, 2343 <&venus_smmu 0x2d>, 2344 <&venus_smmu 0x31>; 2345 memory-region = <&venus_mem>; 2346 status = "disabled"; 2347 2348 video-decoder { 2349 compatible = "venus-decoder"; 2350 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2351 clock-names = "core"; 2352 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2353 }; 2354 2355 video-encoder { 2356 compatible = "venus-encoder"; 2357 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2358 clock-names = "core"; 2359 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2360 }; 2361 }; 2362 2363 mdp_smmu: iommu@d00000 { 2364 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2365 reg = <0x00d00000 0x10000>; 2366 2367 #global-interrupts = <1>; 2368 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2371 #iommu-cells = <1>; 2372 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2373 <&mmcc SMMU_MDP_AHB_CLK>; 2374 clock-names = "bus", "iface"; 2375 2376 power-domains = <&mmcc MDSS_GDSC>; 2377 }; 2378 2379 venus_smmu: iommu@d40000 { 2380 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2381 reg = <0x00d40000 0x20000>; 2382 #global-interrupts = <1>; 2383 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2391 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2392 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2393 <&mmcc SMMU_VIDEO_AHB_CLK>; 2394 clock-names = "bus", "iface"; 2395 #iommu-cells = <1>; 2396 status = "okay"; 2397 }; 2398 2399 vfe_smmu: iommu@da0000 { 2400 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2401 reg = <0x00da0000 0x10000>; 2402 2403 #global-interrupts = <1>; 2404 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2407 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2408 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2409 <&mmcc SMMU_VFE_AHB_CLK>; 2410 clock-names = "bus", "iface"; 2411 #iommu-cells = <1>; 2412 }; 2413 2414 lpass_q6_smmu: iommu@1600000 { 2415 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2416 reg = <0x01600000 0x20000>; 2417 #iommu-cells = <1>; 2418 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2419 2420 #global-interrupts = <1>; 2421 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2434 2435 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2436 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2437 clock-names = "bus", "iface"; 2438 }; 2439 2440 slpi_pil: remoteproc@1c00000 { 2441 compatible = "qcom,msm8996-slpi-pil"; 2442 reg = <0x01c00000 0x4000>; 2443 2444 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2445 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2446 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2447 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2448 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2449 interrupt-names = "wdog", 2450 "fatal", 2451 "ready", 2452 "handover", 2453 "stop-ack"; 2454 2455 clocks = <&xo_board>, 2456 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2457 clock-names = "xo", "aggre2"; 2458 2459 memory-region = <&slpi_mem>; 2460 2461 qcom,smem-states = <&slpi_smp2p_out 0>; 2462 qcom,smem-state-names = "stop"; 2463 2464 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2465 power-domain-names = "ssc_cx"; 2466 2467 status = "disabled"; 2468 2469 smd-edge { 2470 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2471 2472 label = "dsps"; 2473 mboxes = <&apcs_glb 25>; 2474 qcom,smd-edge = <3>; 2475 qcom,remote-pid = <3>; 2476 }; 2477 }; 2478 2479 mss_pil: remoteproc@2080000 { 2480 compatible = "qcom,msm8996-mss-pil"; 2481 reg = <0x2080000 0x100>, 2482 <0x2180000 0x020>; 2483 reg-names = "qdsp6", "rmb"; 2484 2485 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2486 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2487 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2488 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2489 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2490 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2491 interrupt-names = "wdog", "fatal", "ready", 2492 "handover", "stop-ack", 2493 "shutdown-ack"; 2494 2495 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2496 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2497 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2498 <&xo_board>, 2499 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2500 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2501 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2502 <&rpmcc RPM_SMD_PCNOC_CLK>, 2503 <&rpmcc RPM_SMD_QDSS_CLK>; 2504 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2505 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2506 2507 resets = <&gcc GCC_MSS_RESTART>; 2508 reset-names = "mss_restart"; 2509 2510 power-domains = <&rpmpd MSM8996_VDDCX>, 2511 <&rpmpd MSM8996_VDDMX>; 2512 power-domain-names = "cx", "mx"; 2513 2514 qcom,smem-states = <&mpss_smp2p_out 0>; 2515 qcom,smem-state-names = "stop"; 2516 2517 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2518 2519 status = "disabled"; 2520 2521 mba { 2522 memory-region = <&mba_mem>; 2523 }; 2524 2525 mpss { 2526 memory-region = <&mpss_mem>; 2527 }; 2528 2529 metadata { 2530 memory-region = <&mdata_mem>; 2531 }; 2532 2533 smd-edge { 2534 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2535 2536 label = "mpss"; 2537 mboxes = <&apcs_glb 12>; 2538 qcom,smd-edge = <0>; 2539 qcom,remote-pid = <1>; 2540 }; 2541 }; 2542 2543 stm@3002000 { 2544 compatible = "arm,coresight-stm", "arm,primecell"; 2545 reg = <0x3002000 0x1000>, 2546 <0x8280000 0x180000>; 2547 reg-names = "stm-base", "stm-stimulus-base"; 2548 2549 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2550 clock-names = "apb_pclk", "atclk"; 2551 2552 out-ports { 2553 port { 2554 stm_out: endpoint { 2555 remote-endpoint = 2556 <&funnel0_in>; 2557 }; 2558 }; 2559 }; 2560 }; 2561 2562 tpiu@3020000 { 2563 compatible = "arm,coresight-tpiu", "arm,primecell"; 2564 reg = <0x3020000 0x1000>; 2565 2566 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2567 clock-names = "apb_pclk", "atclk"; 2568 2569 in-ports { 2570 port { 2571 tpiu_in: endpoint { 2572 remote-endpoint = 2573 <&replicator_out1>; 2574 }; 2575 }; 2576 }; 2577 }; 2578 2579 funnel@3021000 { 2580 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2581 reg = <0x3021000 0x1000>; 2582 2583 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2584 clock-names = "apb_pclk", "atclk"; 2585 2586 in-ports { 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 2590 port@7 { 2591 reg = <7>; 2592 funnel0_in: endpoint { 2593 remote-endpoint = 2594 <&stm_out>; 2595 }; 2596 }; 2597 }; 2598 2599 out-ports { 2600 port { 2601 funnel0_out: endpoint { 2602 remote-endpoint = 2603 <&merge_funnel_in0>; 2604 }; 2605 }; 2606 }; 2607 }; 2608 2609 funnel@3022000 { 2610 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2611 reg = <0x3022000 0x1000>; 2612 2613 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2614 clock-names = "apb_pclk", "atclk"; 2615 2616 in-ports { 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 2620 port@6 { 2621 reg = <6>; 2622 funnel1_in: endpoint { 2623 remote-endpoint = 2624 <&apss_merge_funnel_out>; 2625 }; 2626 }; 2627 }; 2628 2629 out-ports { 2630 port { 2631 funnel1_out: endpoint { 2632 remote-endpoint = 2633 <&merge_funnel_in1>; 2634 }; 2635 }; 2636 }; 2637 }; 2638 2639 funnel@3023000 { 2640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2641 reg = <0x3023000 0x1000>; 2642 2643 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2644 clock-names = "apb_pclk", "atclk"; 2645 2646 2647 out-ports { 2648 port { 2649 funnel2_out: endpoint { 2650 remote-endpoint = 2651 <&merge_funnel_in2>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 funnel@3025000 { 2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2659 reg = <0x3025000 0x1000>; 2660 2661 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2662 clock-names = "apb_pclk", "atclk"; 2663 2664 in-ports { 2665 #address-cells = <1>; 2666 #size-cells = <0>; 2667 2668 port@0 { 2669 reg = <0>; 2670 merge_funnel_in0: endpoint { 2671 remote-endpoint = 2672 <&funnel0_out>; 2673 }; 2674 }; 2675 2676 port@1 { 2677 reg = <1>; 2678 merge_funnel_in1: endpoint { 2679 remote-endpoint = 2680 <&funnel1_out>; 2681 }; 2682 }; 2683 2684 port@2 { 2685 reg = <2>; 2686 merge_funnel_in2: endpoint { 2687 remote-endpoint = 2688 <&funnel2_out>; 2689 }; 2690 }; 2691 }; 2692 2693 out-ports { 2694 port { 2695 merge_funnel_out: endpoint { 2696 remote-endpoint = 2697 <&etf_in>; 2698 }; 2699 }; 2700 }; 2701 }; 2702 2703 replicator@3026000 { 2704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2705 reg = <0x3026000 0x1000>; 2706 2707 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2708 clock-names = "apb_pclk", "atclk"; 2709 2710 in-ports { 2711 port { 2712 replicator_in: endpoint { 2713 remote-endpoint = 2714 <&etf_out>; 2715 }; 2716 }; 2717 }; 2718 2719 out-ports { 2720 #address-cells = <1>; 2721 #size-cells = <0>; 2722 2723 port@0 { 2724 reg = <0>; 2725 replicator_out0: endpoint { 2726 remote-endpoint = 2727 <&etr_in>; 2728 }; 2729 }; 2730 2731 port@1 { 2732 reg = <1>; 2733 replicator_out1: endpoint { 2734 remote-endpoint = 2735 <&tpiu_in>; 2736 }; 2737 }; 2738 }; 2739 }; 2740 2741 etf@3027000 { 2742 compatible = "arm,coresight-tmc", "arm,primecell"; 2743 reg = <0x3027000 0x1000>; 2744 2745 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2746 clock-names = "apb_pclk", "atclk"; 2747 2748 in-ports { 2749 port { 2750 etf_in: endpoint { 2751 remote-endpoint = 2752 <&merge_funnel_out>; 2753 }; 2754 }; 2755 }; 2756 2757 out-ports { 2758 port { 2759 etf_out: endpoint { 2760 remote-endpoint = 2761 <&replicator_in>; 2762 }; 2763 }; 2764 }; 2765 }; 2766 2767 etr@3028000 { 2768 compatible = "arm,coresight-tmc", "arm,primecell"; 2769 reg = <0x3028000 0x1000>; 2770 2771 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2772 clock-names = "apb_pclk", "atclk"; 2773 arm,scatter-gather; 2774 2775 in-ports { 2776 port { 2777 etr_in: endpoint { 2778 remote-endpoint = 2779 <&replicator_out0>; 2780 }; 2781 }; 2782 }; 2783 }; 2784 2785 debug@3810000 { 2786 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2787 reg = <0x3810000 0x1000>; 2788 2789 clocks = <&rpmcc RPM_QDSS_CLK>; 2790 clock-names = "apb_pclk"; 2791 2792 cpu = <&CPU0>; 2793 }; 2794 2795 etm@3840000 { 2796 compatible = "arm,coresight-etm4x", "arm,primecell"; 2797 reg = <0x3840000 0x1000>; 2798 2799 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2800 clock-names = "apb_pclk", "atclk"; 2801 2802 cpu = <&CPU0>; 2803 2804 out-ports { 2805 port { 2806 etm0_out: endpoint { 2807 remote-endpoint = 2808 <&apss_funnel0_in0>; 2809 }; 2810 }; 2811 }; 2812 }; 2813 2814 debug@3910000 { 2815 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2816 reg = <0x3910000 0x1000>; 2817 2818 clocks = <&rpmcc RPM_QDSS_CLK>; 2819 clock-names = "apb_pclk"; 2820 2821 cpu = <&CPU1>; 2822 }; 2823 2824 etm@3940000 { 2825 compatible = "arm,coresight-etm4x", "arm,primecell"; 2826 reg = <0x3940000 0x1000>; 2827 2828 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2829 clock-names = "apb_pclk", "atclk"; 2830 2831 cpu = <&CPU1>; 2832 2833 out-ports { 2834 port { 2835 etm1_out: endpoint { 2836 remote-endpoint = 2837 <&apss_funnel0_in1>; 2838 }; 2839 }; 2840 }; 2841 }; 2842 2843 funnel@39b0000 { /* APSS Funnel 0 */ 2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2845 reg = <0x39b0000 0x1000>; 2846 2847 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2848 clock-names = "apb_pclk", "atclk"; 2849 2850 in-ports { 2851 #address-cells = <1>; 2852 #size-cells = <0>; 2853 2854 port@0 { 2855 reg = <0>; 2856 apss_funnel0_in0: endpoint { 2857 remote-endpoint = <&etm0_out>; 2858 }; 2859 }; 2860 2861 port@1 { 2862 reg = <1>; 2863 apss_funnel0_in1: endpoint { 2864 remote-endpoint = <&etm1_out>; 2865 }; 2866 }; 2867 }; 2868 2869 out-ports { 2870 port { 2871 apss_funnel0_out: endpoint { 2872 remote-endpoint = 2873 <&apss_merge_funnel_in0>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 debug@3a10000 { 2880 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2881 reg = <0x3a10000 0x1000>; 2882 2883 clocks = <&rpmcc RPM_QDSS_CLK>; 2884 clock-names = "apb_pclk"; 2885 2886 cpu = <&CPU2>; 2887 }; 2888 2889 etm@3a40000 { 2890 compatible = "arm,coresight-etm4x", "arm,primecell"; 2891 reg = <0x3a40000 0x1000>; 2892 2893 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2894 clock-names = "apb_pclk", "atclk"; 2895 2896 cpu = <&CPU2>; 2897 2898 out-ports { 2899 port { 2900 etm2_out: endpoint { 2901 remote-endpoint = 2902 <&apss_funnel1_in0>; 2903 }; 2904 }; 2905 }; 2906 }; 2907 2908 debug@3b10000 { 2909 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2910 reg = <0x3b10000 0x1000>; 2911 2912 clocks = <&rpmcc RPM_QDSS_CLK>; 2913 clock-names = "apb_pclk"; 2914 2915 cpu = <&CPU3>; 2916 }; 2917 2918 etm@3b40000 { 2919 compatible = "arm,coresight-etm4x", "arm,primecell"; 2920 reg = <0x3b40000 0x1000>; 2921 2922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2923 clock-names = "apb_pclk", "atclk"; 2924 2925 cpu = <&CPU3>; 2926 2927 out-ports { 2928 port { 2929 etm3_out: endpoint { 2930 remote-endpoint = 2931 <&apss_funnel1_in1>; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 funnel@3bb0000 { /* APSS Funnel 1 */ 2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2939 reg = <0x3bb0000 0x1000>; 2940 2941 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2942 clock-names = "apb_pclk", "atclk"; 2943 2944 in-ports { 2945 #address-cells = <1>; 2946 #size-cells = <0>; 2947 2948 port@0 { 2949 reg = <0>; 2950 apss_funnel1_in0: endpoint { 2951 remote-endpoint = <&etm2_out>; 2952 }; 2953 }; 2954 2955 port@1 { 2956 reg = <1>; 2957 apss_funnel1_in1: endpoint { 2958 remote-endpoint = <&etm3_out>; 2959 }; 2960 }; 2961 }; 2962 2963 out-ports { 2964 port { 2965 apss_funnel1_out: endpoint { 2966 remote-endpoint = 2967 <&apss_merge_funnel_in1>; 2968 }; 2969 }; 2970 }; 2971 }; 2972 2973 funnel@3bc0000 { 2974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2975 reg = <0x3bc0000 0x1000>; 2976 2977 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2978 clock-names = "apb_pclk", "atclk"; 2979 2980 in-ports { 2981 #address-cells = <1>; 2982 #size-cells = <0>; 2983 2984 port@0 { 2985 reg = <0>; 2986 apss_merge_funnel_in0: endpoint { 2987 remote-endpoint = 2988 <&apss_funnel0_out>; 2989 }; 2990 }; 2991 2992 port@1 { 2993 reg = <1>; 2994 apss_merge_funnel_in1: endpoint { 2995 remote-endpoint = 2996 <&apss_funnel1_out>; 2997 }; 2998 }; 2999 }; 3000 3001 out-ports { 3002 port { 3003 apss_merge_funnel_out: endpoint { 3004 remote-endpoint = 3005 <&funnel1_in>; 3006 }; 3007 }; 3008 }; 3009 }; 3010 3011 kryocc: clock-controller@6400000 { 3012 compatible = "qcom,msm8996-apcc"; 3013 reg = <0x06400000 0x90000>; 3014 3015 clock-names = "xo", "sys_apcs_aux"; 3016 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3017 3018 #clock-cells = <1>; 3019 }; 3020 3021 usb3: usb@6af8800 { 3022 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3023 reg = <0x06af8800 0x400>; 3024 #address-cells = <1>; 3025 #size-cells = <1>; 3026 ranges; 3027 3028 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 3030 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3031 3032 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3033 <&gcc GCC_USB30_MASTER_CLK>, 3034 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3035 <&gcc GCC_USB30_SLEEP_CLK>, 3036 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3037 clock-names = "cfg_noc", 3038 "core", 3039 "iface", 3040 "sleep", 3041 "mock_utmi"; 3042 3043 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3044 <&gcc GCC_USB30_MASTER_CLK>; 3045 assigned-clock-rates = <19200000>, <120000000>; 3046 3047 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3048 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3049 interconnect-names = "usb-ddr", "apps-usb"; 3050 3051 power-domains = <&gcc USB30_GDSC>; 3052 status = "disabled"; 3053 3054 usb3_dwc3: usb@6a00000 { 3055 compatible = "snps,dwc3"; 3056 reg = <0x06a00000 0xcc00>; 3057 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3058 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3059 phy-names = "usb2-phy", "usb3-phy"; 3060 snps,hird-threshold = /bits/ 8 <0>; 3061 snps,dis_u2_susphy_quirk; 3062 snps,dis_enblslpm_quirk; 3063 snps,is-utmi-l1-suspend; 3064 tx-fifo-resize; 3065 }; 3066 }; 3067 3068 usb3phy: phy@7410000 { 3069 compatible = "qcom,msm8996-qmp-usb3-phy"; 3070 reg = <0x07410000 0x1c4>; 3071 #address-cells = <1>; 3072 #size-cells = <1>; 3073 ranges; 3074 3075 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3076 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3077 <&gcc GCC_USB3_CLKREF_CLK>; 3078 clock-names = "aux", "cfg_ahb", "ref"; 3079 3080 resets = <&gcc GCC_USB3_PHY_BCR>, 3081 <&gcc GCC_USB3PHY_PHY_BCR>; 3082 reset-names = "phy", "common"; 3083 status = "disabled"; 3084 3085 ssusb_phy_0: phy@7410200 { 3086 reg = <0x07410200 0x200>, 3087 <0x07410400 0x130>, 3088 <0x07410600 0x1a8>; 3089 #phy-cells = <0>; 3090 3091 #clock-cells = <0>; 3092 clock-output-names = "usb3_phy_pipe_clk_src"; 3093 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3094 clock-names = "pipe0"; 3095 }; 3096 }; 3097 3098 hsusb_phy1: phy@7411000 { 3099 compatible = "qcom,msm8996-qusb2-phy"; 3100 reg = <0x07411000 0x180>; 3101 #phy-cells = <0>; 3102 3103 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3104 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3105 clock-names = "cfg_ahb", "ref"; 3106 3107 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3108 nvmem-cells = <&qusb2p_hstx_trim>; 3109 status = "disabled"; 3110 }; 3111 3112 hsusb_phy2: phy@7412000 { 3113 compatible = "qcom,msm8996-qusb2-phy"; 3114 reg = <0x07412000 0x180>; 3115 #phy-cells = <0>; 3116 3117 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3118 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3119 clock-names = "cfg_ahb", "ref"; 3120 3121 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3122 nvmem-cells = <&qusb2s_hstx_trim>; 3123 status = "disabled"; 3124 }; 3125 3126 sdhc1: mmc@7464900 { 3127 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3128 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3129 reg-names = "hc", "core"; 3130 3131 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3133 interrupt-names = "hc_irq", "pwr_irq"; 3134 3135 clock-names = "iface", "core", "xo"; 3136 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3137 <&gcc GCC_SDCC1_APPS_CLK>, 3138 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3139 resets = <&gcc GCC_SDCC1_BCR>; 3140 3141 pinctrl-names = "default", "sleep"; 3142 pinctrl-0 = <&sdc1_state_on>; 3143 pinctrl-1 = <&sdc1_state_off>; 3144 3145 bus-width = <8>; 3146 non-removable; 3147 status = "disabled"; 3148 }; 3149 3150 sdhc2: mmc@74a4900 { 3151 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3152 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3153 reg-names = "hc", "core"; 3154 3155 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3157 interrupt-names = "hc_irq", "pwr_irq"; 3158 3159 clock-names = "iface", "core", "xo"; 3160 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3161 <&gcc GCC_SDCC2_APPS_CLK>, 3162 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3163 resets = <&gcc GCC_SDCC2_BCR>; 3164 3165 pinctrl-names = "default", "sleep"; 3166 pinctrl-0 = <&sdc2_state_on>; 3167 pinctrl-1 = <&sdc2_state_off>; 3168 3169 bus-width = <4>; 3170 status = "disabled"; 3171 }; 3172 3173 blsp1_dma: dma-controller@7544000 { 3174 compatible = "qcom,bam-v1.7.0"; 3175 reg = <0x07544000 0x2b000>; 3176 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3177 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3178 clock-names = "bam_clk"; 3179 qcom,controlled-remotely; 3180 #dma-cells = <1>; 3181 qcom,ee = <0>; 3182 }; 3183 3184 blsp1_uart2: serial@7570000 { 3185 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3186 reg = <0x07570000 0x1000>; 3187 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3188 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3189 <&gcc GCC_BLSP1_AHB_CLK>; 3190 clock-names = "core", "iface"; 3191 pinctrl-names = "default", "sleep"; 3192 pinctrl-0 = <&blsp1_uart2_default>; 3193 pinctrl-1 = <&blsp1_uart2_sleep>; 3194 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3195 dma-names = "tx", "rx"; 3196 status = "disabled"; 3197 }; 3198 3199 blsp1_spi1: spi@7575000 { 3200 compatible = "qcom,spi-qup-v2.2.1"; 3201 reg = <0x07575000 0x600>; 3202 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3203 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3204 <&gcc GCC_BLSP1_AHB_CLK>; 3205 clock-names = "core", "iface"; 3206 pinctrl-names = "default", "sleep"; 3207 pinctrl-0 = <&blsp1_spi1_default>; 3208 pinctrl-1 = <&blsp1_spi1_sleep>; 3209 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3210 dma-names = "tx", "rx"; 3211 #address-cells = <1>; 3212 #size-cells = <0>; 3213 status = "disabled"; 3214 }; 3215 3216 blsp1_i2c3: i2c@7577000 { 3217 compatible = "qcom,i2c-qup-v2.2.1"; 3218 reg = <0x07577000 0x1000>; 3219 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3220 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3221 <&gcc GCC_BLSP1_AHB_CLK>; 3222 clock-names = "core", "iface"; 3223 pinctrl-names = "default", "sleep"; 3224 pinctrl-0 = <&blsp1_i2c3_default>; 3225 pinctrl-1 = <&blsp1_i2c3_sleep>; 3226 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3227 dma-names = "tx", "rx"; 3228 #address-cells = <1>; 3229 #size-cells = <0>; 3230 status = "disabled"; 3231 }; 3232 3233 blsp1_i2c6: i2c@757a000 { 3234 compatible = "qcom,i2c-qup-v2.2.1"; 3235 reg = <0x757a000 0x1000>; 3236 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3237 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3238 <&gcc GCC_BLSP1_AHB_CLK>; 3239 clock-names = "core", "iface"; 3240 pinctrl-names = "default", "sleep"; 3241 pinctrl-0 = <&blsp1_i2c6_default>; 3242 pinctrl-1 = <&blsp1_i2c6_sleep>; 3243 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3244 dma-names = "tx", "rx"; 3245 #address-cells = <1>; 3246 #size-cells = <0>; 3247 status = "disabled"; 3248 }; 3249 3250 blsp2_dma: dma-controller@7584000 { 3251 compatible = "qcom,bam-v1.7.0"; 3252 reg = <0x07584000 0x2b000>; 3253 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3254 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3255 clock-names = "bam_clk"; 3256 qcom,controlled-remotely; 3257 #dma-cells = <1>; 3258 qcom,ee = <0>; 3259 }; 3260 3261 blsp2_uart2: serial@75b0000 { 3262 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3263 reg = <0x075b0000 0x1000>; 3264 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3265 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3266 <&gcc GCC_BLSP2_AHB_CLK>; 3267 clock-names = "core", "iface"; 3268 status = "disabled"; 3269 }; 3270 3271 blsp2_uart3: serial@75b1000 { 3272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3273 reg = <0x075b1000 0x1000>; 3274 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3275 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3276 <&gcc GCC_BLSP2_AHB_CLK>; 3277 clock-names = "core", "iface"; 3278 status = "disabled"; 3279 }; 3280 3281 blsp2_i2c1: i2c@75b5000 { 3282 compatible = "qcom,i2c-qup-v2.2.1"; 3283 reg = <0x075b5000 0x1000>; 3284 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3285 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3286 <&gcc GCC_BLSP2_AHB_CLK>; 3287 clock-names = "core", "iface"; 3288 pinctrl-names = "default", "sleep"; 3289 pinctrl-0 = <&blsp2_i2c1_default>; 3290 pinctrl-1 = <&blsp2_i2c1_sleep>; 3291 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3292 dma-names = "tx", "rx"; 3293 #address-cells = <1>; 3294 #size-cells = <0>; 3295 status = "disabled"; 3296 }; 3297 3298 blsp2_i2c2: i2c@75b6000 { 3299 compatible = "qcom,i2c-qup-v2.2.1"; 3300 reg = <0x075b6000 0x1000>; 3301 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3302 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3303 <&gcc GCC_BLSP2_AHB_CLK>; 3304 clock-names = "core", "iface"; 3305 pinctrl-names = "default", "sleep"; 3306 pinctrl-0 = <&blsp2_i2c2_default>; 3307 pinctrl-1 = <&blsp2_i2c2_sleep>; 3308 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3309 dma-names = "tx", "rx"; 3310 #address-cells = <1>; 3311 #size-cells = <0>; 3312 status = "disabled"; 3313 }; 3314 3315 blsp2_i2c3: i2c@75b7000 { 3316 compatible = "qcom,i2c-qup-v2.2.1"; 3317 reg = <0x075b7000 0x1000>; 3318 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3319 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3320 <&gcc GCC_BLSP2_AHB_CLK>; 3321 clock-names = "core", "iface"; 3322 clock-frequency = <400000>; 3323 pinctrl-names = "default", "sleep"; 3324 pinctrl-0 = <&blsp2_i2c3_default>; 3325 pinctrl-1 = <&blsp2_i2c3_sleep>; 3326 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3327 dma-names = "tx", "rx"; 3328 #address-cells = <1>; 3329 #size-cells = <0>; 3330 status = "disabled"; 3331 }; 3332 3333 blsp2_i2c5: i2c@75b9000 { 3334 compatible = "qcom,i2c-qup-v2.2.1"; 3335 reg = <0x75b9000 0x1000>; 3336 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3337 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3338 <&gcc GCC_BLSP2_AHB_CLK>; 3339 clock-names = "core", "iface"; 3340 pinctrl-names = "default"; 3341 pinctrl-0 = <&blsp2_i2c5_default>; 3342 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3343 dma-names = "tx", "rx"; 3344 #address-cells = <1>; 3345 #size-cells = <0>; 3346 status = "disabled"; 3347 }; 3348 3349 blsp2_i2c6: i2c@75ba000 { 3350 compatible = "qcom,i2c-qup-v2.2.1"; 3351 reg = <0x75ba000 0x1000>; 3352 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3353 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3354 <&gcc GCC_BLSP2_AHB_CLK>; 3355 clock-names = "core", "iface"; 3356 pinctrl-names = "default", "sleep"; 3357 pinctrl-0 = <&blsp2_i2c6_default>; 3358 pinctrl-1 = <&blsp2_i2c6_sleep>; 3359 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3360 dma-names = "tx", "rx"; 3361 #address-cells = <1>; 3362 #size-cells = <0>; 3363 status = "disabled"; 3364 }; 3365 3366 blsp2_spi6: spi@75ba000 { 3367 compatible = "qcom,spi-qup-v2.2.1"; 3368 reg = <0x075ba000 0x600>; 3369 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3370 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3371 <&gcc GCC_BLSP2_AHB_CLK>; 3372 clock-names = "core", "iface"; 3373 pinctrl-names = "default", "sleep"; 3374 pinctrl-0 = <&blsp2_spi6_default>; 3375 pinctrl-1 = <&blsp2_spi6_sleep>; 3376 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3377 dma-names = "tx", "rx"; 3378 #address-cells = <1>; 3379 #size-cells = <0>; 3380 status = "disabled"; 3381 }; 3382 3383 usb2: usb@76f8800 { 3384 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3385 reg = <0x076f8800 0x400>; 3386 #address-cells = <1>; 3387 #size-cells = <1>; 3388 ranges; 3389 3390 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 3391 interrupt-names = "hs_phy_irq"; 3392 3393 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3394 <&gcc GCC_USB20_MASTER_CLK>, 3395 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3396 <&gcc GCC_USB20_SLEEP_CLK>, 3397 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3398 clock-names = "cfg_noc", 3399 "core", 3400 "iface", 3401 "sleep", 3402 "mock_utmi"; 3403 3404 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3405 <&gcc GCC_USB20_MASTER_CLK>; 3406 assigned-clock-rates = <19200000>, <60000000>; 3407 3408 power-domains = <&gcc USB30_GDSC>; 3409 qcom,select-utmi-as-pipe-clk; 3410 status = "disabled"; 3411 3412 usb2_dwc3: usb@7600000 { 3413 compatible = "snps,dwc3"; 3414 reg = <0x07600000 0xcc00>; 3415 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3416 phys = <&hsusb_phy2>; 3417 phy-names = "usb2-phy"; 3418 maximum-speed = "high-speed"; 3419 snps,dis_u2_susphy_quirk; 3420 snps,dis_enblslpm_quirk; 3421 }; 3422 }; 3423 3424 slimbam: dma-controller@9184000 { 3425 compatible = "qcom,bam-v1.7.0"; 3426 qcom,controlled-remotely; 3427 reg = <0x09184000 0x32000>; 3428 num-channels = <31>; 3429 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3430 #dma-cells = <1>; 3431 qcom,ee = <1>; 3432 qcom,num-ees = <2>; 3433 }; 3434 3435 slim_msm: slim-ngd@91c0000 { 3436 compatible = "qcom,slim-ngd-v1.5.0"; 3437 reg = <0x091c0000 0x2c000>; 3438 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3439 dmas = <&slimbam 3>, <&slimbam 4>; 3440 dma-names = "rx", "tx"; 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 3444 status = "disabled"; 3445 }; 3446 3447 adsp_pil: remoteproc@9300000 { 3448 compatible = "qcom,msm8996-adsp-pil"; 3449 reg = <0x09300000 0x80000>; 3450 3451 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3452 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3453 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3454 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3455 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3456 interrupt-names = "wdog", "fatal", "ready", 3457 "handover", "stop-ack"; 3458 3459 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3460 clock-names = "xo"; 3461 3462 memory-region = <&adsp_mem>; 3463 3464 qcom,smem-states = <&adsp_smp2p_out 0>; 3465 qcom,smem-state-names = "stop"; 3466 3467 power-domains = <&rpmpd MSM8996_VDDCX>; 3468 power-domain-names = "cx"; 3469 3470 status = "disabled"; 3471 3472 smd-edge { 3473 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3474 3475 label = "lpass"; 3476 mboxes = <&apcs_glb 8>; 3477 qcom,smd-edge = <1>; 3478 qcom,remote-pid = <2>; 3479 3480 apr { 3481 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3482 compatible = "qcom,apr-v2"; 3483 qcom,smd-channels = "apr_audio_svc"; 3484 qcom,domain = <APR_DOMAIN_ADSP>; 3485 #address-cells = <1>; 3486 #size-cells = <0>; 3487 3488 service@3 { 3489 reg = <APR_SVC_ADSP_CORE>; 3490 compatible = "qcom,q6core"; 3491 }; 3492 3493 q6afe: service@4 { 3494 compatible = "qcom,q6afe"; 3495 reg = <APR_SVC_AFE>; 3496 q6afedai: dais { 3497 compatible = "qcom,q6afe-dais"; 3498 #address-cells = <1>; 3499 #size-cells = <0>; 3500 #sound-dai-cells = <1>; 3501 dai@1 { 3502 reg = <1>; 3503 }; 3504 }; 3505 }; 3506 3507 q6asm: service@7 { 3508 compatible = "qcom,q6asm"; 3509 reg = <APR_SVC_ASM>; 3510 q6asmdai: dais { 3511 compatible = "qcom,q6asm-dais"; 3512 #address-cells = <1>; 3513 #size-cells = <0>; 3514 #sound-dai-cells = <1>; 3515 iommus = <&lpass_q6_smmu 1>; 3516 }; 3517 }; 3518 3519 q6adm: service@8 { 3520 compatible = "qcom,q6adm"; 3521 reg = <APR_SVC_ADM>; 3522 q6routing: routing { 3523 compatible = "qcom,q6adm-routing"; 3524 #sound-dai-cells = <0>; 3525 }; 3526 }; 3527 }; 3528 }; 3529 }; 3530 3531 apcs_glb: mailbox@9820000 { 3532 compatible = "qcom,msm8996-apcs-hmss-global"; 3533 reg = <0x09820000 0x1000>; 3534 3535 #mbox-cells = <1>; 3536 #clock-cells = <0>; 3537 }; 3538 3539 timer@9840000 { 3540 #address-cells = <1>; 3541 #size-cells = <1>; 3542 ranges; 3543 compatible = "arm,armv7-timer-mem"; 3544 reg = <0x09840000 0x1000>; 3545 clock-frequency = <19200000>; 3546 3547 frame@9850000 { 3548 frame-number = <0>; 3549 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3551 reg = <0x09850000 0x1000>, 3552 <0x09860000 0x1000>; 3553 }; 3554 3555 frame@9870000 { 3556 frame-number = <1>; 3557 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3558 reg = <0x09870000 0x1000>; 3559 status = "disabled"; 3560 }; 3561 3562 frame@9880000 { 3563 frame-number = <2>; 3564 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3565 reg = <0x09880000 0x1000>; 3566 status = "disabled"; 3567 }; 3568 3569 frame@9890000 { 3570 frame-number = <3>; 3571 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3572 reg = <0x09890000 0x1000>; 3573 status = "disabled"; 3574 }; 3575 3576 frame@98a0000 { 3577 frame-number = <4>; 3578 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3579 reg = <0x098a0000 0x1000>; 3580 status = "disabled"; 3581 }; 3582 3583 frame@98b0000 { 3584 frame-number = <5>; 3585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3586 reg = <0x098b0000 0x1000>; 3587 status = "disabled"; 3588 }; 3589 3590 frame@98c0000 { 3591 frame-number = <6>; 3592 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3593 reg = <0x098c0000 0x1000>; 3594 status = "disabled"; 3595 }; 3596 }; 3597 3598 saw3: syscon@9a10000 { 3599 compatible = "syscon"; 3600 reg = <0x09a10000 0x1000>; 3601 }; 3602 3603 cbf: clock-controller@9a11000 { 3604 compatible = "qcom,msm8996-cbf"; 3605 reg = <0x09a11000 0x10000>; 3606 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3607 #clock-cells = <0>; 3608 #interconnect-cells = <1>; 3609 }; 3610 3611 intc: interrupt-controller@9bc0000 { 3612 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3613 #interrupt-cells = <3>; 3614 interrupt-controller; 3615 #redistributor-regions = <1>; 3616 redistributor-stride = <0x0 0x40000>; 3617 reg = <0x09bc0000 0x10000>, 3618 <0x09c00000 0x100000>; 3619 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3620 }; 3621 }; 3622 3623 sound: sound { 3624 }; 3625 3626 thermal-zones { 3627 cpu0-thermal { 3628 polling-delay-passive = <250>; 3629 polling-delay = <1000>; 3630 3631 thermal-sensors = <&tsens0 3>; 3632 3633 trips { 3634 cpu0_alert0: trip-point0 { 3635 temperature = <75000>; 3636 hysteresis = <2000>; 3637 type = "passive"; 3638 }; 3639 3640 cpu0_crit: cpu-crit { 3641 temperature = <110000>; 3642 hysteresis = <2000>; 3643 type = "critical"; 3644 }; 3645 }; 3646 }; 3647 3648 cpu1-thermal { 3649 polling-delay-passive = <250>; 3650 polling-delay = <1000>; 3651 3652 thermal-sensors = <&tsens0 5>; 3653 3654 trips { 3655 cpu1_alert0: trip-point0 { 3656 temperature = <75000>; 3657 hysteresis = <2000>; 3658 type = "passive"; 3659 }; 3660 3661 cpu1_crit: cpu-crit { 3662 temperature = <110000>; 3663 hysteresis = <2000>; 3664 type = "critical"; 3665 }; 3666 }; 3667 }; 3668 3669 cpu2-thermal { 3670 polling-delay-passive = <250>; 3671 polling-delay = <1000>; 3672 3673 thermal-sensors = <&tsens0 8>; 3674 3675 trips { 3676 cpu2_alert0: trip-point0 { 3677 temperature = <75000>; 3678 hysteresis = <2000>; 3679 type = "passive"; 3680 }; 3681 3682 cpu2_crit: cpu-crit { 3683 temperature = <110000>; 3684 hysteresis = <2000>; 3685 type = "critical"; 3686 }; 3687 }; 3688 }; 3689 3690 cpu3-thermal { 3691 polling-delay-passive = <250>; 3692 polling-delay = <1000>; 3693 3694 thermal-sensors = <&tsens0 10>; 3695 3696 trips { 3697 cpu3_alert0: trip-point0 { 3698 temperature = <75000>; 3699 hysteresis = <2000>; 3700 type = "passive"; 3701 }; 3702 3703 cpu3_crit: cpu-crit { 3704 temperature = <110000>; 3705 hysteresis = <2000>; 3706 type = "critical"; 3707 }; 3708 }; 3709 }; 3710 3711 gpu-top-thermal { 3712 polling-delay-passive = <250>; 3713 polling-delay = <1000>; 3714 3715 thermal-sensors = <&tsens1 6>; 3716 3717 trips { 3718 gpu1_alert0: trip-point0 { 3719 temperature = <90000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 }; 3724 3725 cooling-maps { 3726 map0 { 3727 trip = <&gpu1_alert0>; 3728 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3729 }; 3730 }; 3731 }; 3732 3733 gpu-bottom-thermal { 3734 polling-delay-passive = <250>; 3735 polling-delay = <1000>; 3736 3737 thermal-sensors = <&tsens1 7>; 3738 3739 trips { 3740 gpu2_alert0: trip-point0 { 3741 temperature = <90000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 }; 3746 3747 cooling-maps { 3748 map0 { 3749 trip = <&gpu2_alert0>; 3750 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3751 }; 3752 }; 3753 }; 3754 3755 m4m-thermal { 3756 polling-delay-passive = <250>; 3757 polling-delay = <1000>; 3758 3759 thermal-sensors = <&tsens0 1>; 3760 3761 trips { 3762 m4m_alert0: trip-point0 { 3763 temperature = <90000>; 3764 hysteresis = <2000>; 3765 type = "hot"; 3766 }; 3767 }; 3768 }; 3769 3770 l3-or-venus-thermal { 3771 polling-delay-passive = <250>; 3772 polling-delay = <1000>; 3773 3774 thermal-sensors = <&tsens0 2>; 3775 3776 trips { 3777 l3_or_venus_alert0: trip-point0 { 3778 temperature = <90000>; 3779 hysteresis = <2000>; 3780 type = "hot"; 3781 }; 3782 }; 3783 }; 3784 3785 cluster0-l2-thermal { 3786 polling-delay-passive = <250>; 3787 polling-delay = <1000>; 3788 3789 thermal-sensors = <&tsens0 7>; 3790 3791 trips { 3792 cluster0_l2_alert0: trip-point0 { 3793 temperature = <90000>; 3794 hysteresis = <2000>; 3795 type = "hot"; 3796 }; 3797 }; 3798 }; 3799 3800 cluster1-l2-thermal { 3801 polling-delay-passive = <250>; 3802 polling-delay = <1000>; 3803 3804 thermal-sensors = <&tsens0 12>; 3805 3806 trips { 3807 cluster1_l2_alert0: trip-point0 { 3808 temperature = <90000>; 3809 hysteresis = <2000>; 3810 type = "hot"; 3811 }; 3812 }; 3813 }; 3814 3815 camera-thermal { 3816 polling-delay-passive = <250>; 3817 polling-delay = <1000>; 3818 3819 thermal-sensors = <&tsens1 1>; 3820 3821 trips { 3822 camera_alert0: trip-point0 { 3823 temperature = <90000>; 3824 hysteresis = <2000>; 3825 type = "hot"; 3826 }; 3827 }; 3828 }; 3829 3830 q6-dsp-thermal { 3831 polling-delay-passive = <250>; 3832 polling-delay = <1000>; 3833 3834 thermal-sensors = <&tsens1 2>; 3835 3836 trips { 3837 q6_dsp_alert0: trip-point0 { 3838 temperature = <90000>; 3839 hysteresis = <2000>; 3840 type = "hot"; 3841 }; 3842 }; 3843 }; 3844 3845 mem-thermal { 3846 polling-delay-passive = <250>; 3847 polling-delay = <1000>; 3848 3849 thermal-sensors = <&tsens1 3>; 3850 3851 trips { 3852 mem_alert0: trip-point0 { 3853 temperature = <90000>; 3854 hysteresis = <2000>; 3855 type = "hot"; 3856 }; 3857 }; 3858 }; 3859 3860 modemtx-thermal { 3861 polling-delay-passive = <250>; 3862 polling-delay = <1000>; 3863 3864 thermal-sensors = <&tsens1 4>; 3865 3866 trips { 3867 modemtx_alert0: trip-point0 { 3868 temperature = <90000>; 3869 hysteresis = <2000>; 3870 type = "hot"; 3871 }; 3872 }; 3873 }; 3874 }; 3875 3876 timer { 3877 compatible = "arm,armv8-timer"; 3878 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3879 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3880 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3881 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3882 }; 3883}; 3884