1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,apr.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 clock-output-names = "xo_board"; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <32764>; 33 clock-output-names = "sleep_clk"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 cpu-idle-states = <&CPU_SLEEP_0>; 47 capacity-dmips-mhz = <1024>; 48 clocks = <&kryocc 0>; 49 operating-points-v2 = <&cluster0_opp>; 50 #cooling-cells = <2>; 51 next-level-cache = <&L2_0>; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo"; 61 reg = <0x0 0x1>; 62 enable-method = "psci"; 63 cpu-idle-states = <&CPU_SLEEP_0>; 64 capacity-dmips-mhz = <1024>; 65 clocks = <&kryocc 0>; 66 operating-points-v2 = <&cluster0_opp>; 67 #cooling-cells = <2>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 CPU2: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo"; 74 reg = <0x0 0x100>; 75 enable-method = "psci"; 76 cpu-idle-states = <&CPU_SLEEP_0>; 77 capacity-dmips-mhz = <1024>; 78 clocks = <&kryocc 1>; 79 operating-points-v2 = <&cluster1_opp>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 L2_1: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 }; 86 }; 87 88 CPU3: cpu@101 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x101>; 92 enable-method = "psci"; 93 cpu-idle-states = <&CPU_SLEEP_0>; 94 capacity-dmips-mhz = <1024>; 95 clocks = <&kryocc 1>; 96 operating-points-v2 = <&cluster1_opp>; 97 #cooling-cells = <2>; 98 next-level-cache = <&L2_1>; 99 }; 100 101 cpu-map { 102 cluster0 { 103 core0 { 104 cpu = <&CPU0>; 105 }; 106 107 core1 { 108 cpu = <&CPU1>; 109 }; 110 }; 111 112 cluster1 { 113 core0 { 114 cpu = <&CPU2>; 115 }; 116 117 core1 { 118 cpu = <&CPU3>; 119 }; 120 }; 121 }; 122 123 idle-states { 124 entry-method = "psci"; 125 126 CPU_SLEEP_0: cpu-sleep-0 { 127 compatible = "arm,idle-state"; 128 idle-state-name = "standalone-power-collapse"; 129 arm,psci-suspend-param = <0x00000004>; 130 entry-latency-us = <130>; 131 exit-latency-us = <80>; 132 min-residency-us = <300>; 133 }; 134 }; 135 }; 136 137 cluster0_opp: opp-table-cluster0 { 138 compatible = "operating-points-v2-kryo-cpu"; 139 nvmem-cells = <&speedbin_efuse>; 140 opp-shared; 141 142 /* Nominal fmax for now */ 143 opp-307200000 { 144 opp-hz = /bits/ 64 <307200000>; 145 opp-supported-hw = <0x77>; 146 clock-latency-ns = <200000>; 147 }; 148 opp-422400000 { 149 opp-hz = /bits/ 64 <422400000>; 150 opp-supported-hw = <0x77>; 151 clock-latency-ns = <200000>; 152 }; 153 opp-480000000 { 154 opp-hz = /bits/ 64 <480000000>; 155 opp-supported-hw = <0x77>; 156 clock-latency-ns = <200000>; 157 }; 158 opp-556800000 { 159 opp-hz = /bits/ 64 <556800000>; 160 opp-supported-hw = <0x77>; 161 clock-latency-ns = <200000>; 162 }; 163 opp-652800000 { 164 opp-hz = /bits/ 64 <652800000>; 165 opp-supported-hw = <0x77>; 166 clock-latency-ns = <200000>; 167 }; 168 opp-729600000 { 169 opp-hz = /bits/ 64 <729600000>; 170 opp-supported-hw = <0x77>; 171 clock-latency-ns = <200000>; 172 }; 173 opp-844800000 { 174 opp-hz = /bits/ 64 <844800000>; 175 opp-supported-hw = <0x77>; 176 clock-latency-ns = <200000>; 177 }; 178 opp-960000000 { 179 opp-hz = /bits/ 64 <960000000>; 180 opp-supported-hw = <0x77>; 181 clock-latency-ns = <200000>; 182 }; 183 opp-1036800000 { 184 opp-hz = /bits/ 64 <1036800000>; 185 opp-supported-hw = <0x77>; 186 clock-latency-ns = <200000>; 187 }; 188 opp-1113600000 { 189 opp-hz = /bits/ 64 <1113600000>; 190 opp-supported-hw = <0x77>; 191 clock-latency-ns = <200000>; 192 }; 193 opp-1190400000 { 194 opp-hz = /bits/ 64 <1190400000>; 195 opp-supported-hw = <0x77>; 196 clock-latency-ns = <200000>; 197 }; 198 opp-1228800000 { 199 opp-hz = /bits/ 64 <1228800000>; 200 opp-supported-hw = <0x77>; 201 clock-latency-ns = <200000>; 202 }; 203 opp-1324800000 { 204 opp-hz = /bits/ 64 <1324800000>; 205 opp-supported-hw = <0x77>; 206 clock-latency-ns = <200000>; 207 }; 208 opp-1401600000 { 209 opp-hz = /bits/ 64 <1401600000>; 210 opp-supported-hw = <0x77>; 211 clock-latency-ns = <200000>; 212 }; 213 opp-1478400000 { 214 opp-hz = /bits/ 64 <1478400000>; 215 opp-supported-hw = <0x77>; 216 clock-latency-ns = <200000>; 217 }; 218 opp-1593600000 { 219 opp-hz = /bits/ 64 <1593600000>; 220 opp-supported-hw = <0x77>; 221 clock-latency-ns = <200000>; 222 }; 223 }; 224 225 cluster1_opp: opp-table-cluster1 { 226 compatible = "operating-points-v2-kryo-cpu"; 227 nvmem-cells = <&speedbin_efuse>; 228 opp-shared; 229 230 /* Nominal fmax for now */ 231 opp-307200000 { 232 opp-hz = /bits/ 64 <307200000>; 233 opp-supported-hw = <0x77>; 234 clock-latency-ns = <200000>; 235 }; 236 opp-403200000 { 237 opp-hz = /bits/ 64 <403200000>; 238 opp-supported-hw = <0x77>; 239 clock-latency-ns = <200000>; 240 }; 241 opp-480000000 { 242 opp-hz = /bits/ 64 <480000000>; 243 opp-supported-hw = <0x77>; 244 clock-latency-ns = <200000>; 245 }; 246 opp-556800000 { 247 opp-hz = /bits/ 64 <556800000>; 248 opp-supported-hw = <0x77>; 249 clock-latency-ns = <200000>; 250 }; 251 opp-652800000 { 252 opp-hz = /bits/ 64 <652800000>; 253 opp-supported-hw = <0x77>; 254 clock-latency-ns = <200000>; 255 }; 256 opp-729600000 { 257 opp-hz = /bits/ 64 <729600000>; 258 opp-supported-hw = <0x77>; 259 clock-latency-ns = <200000>; 260 }; 261 opp-806400000 { 262 opp-hz = /bits/ 64 <806400000>; 263 opp-supported-hw = <0x77>; 264 clock-latency-ns = <200000>; 265 }; 266 opp-883200000 { 267 opp-hz = /bits/ 64 <883200000>; 268 opp-supported-hw = <0x77>; 269 clock-latency-ns = <200000>; 270 }; 271 opp-940800000 { 272 opp-hz = /bits/ 64 <940800000>; 273 opp-supported-hw = <0x77>; 274 clock-latency-ns = <200000>; 275 }; 276 opp-1036800000 { 277 opp-hz = /bits/ 64 <1036800000>; 278 opp-supported-hw = <0x77>; 279 clock-latency-ns = <200000>; 280 }; 281 opp-1113600000 { 282 opp-hz = /bits/ 64 <1113600000>; 283 opp-supported-hw = <0x77>; 284 clock-latency-ns = <200000>; 285 }; 286 opp-1190400000 { 287 opp-hz = /bits/ 64 <1190400000>; 288 opp-supported-hw = <0x77>; 289 clock-latency-ns = <200000>; 290 }; 291 opp-1248000000 { 292 opp-hz = /bits/ 64 <1248000000>; 293 opp-supported-hw = <0x77>; 294 clock-latency-ns = <200000>; 295 }; 296 opp-1324800000 { 297 opp-hz = /bits/ 64 <1324800000>; 298 opp-supported-hw = <0x77>; 299 clock-latency-ns = <200000>; 300 }; 301 opp-1401600000 { 302 opp-hz = /bits/ 64 <1401600000>; 303 opp-supported-hw = <0x77>; 304 clock-latency-ns = <200000>; 305 }; 306 opp-1478400000 { 307 opp-hz = /bits/ 64 <1478400000>; 308 opp-supported-hw = <0x77>; 309 clock-latency-ns = <200000>; 310 }; 311 opp-1555200000 { 312 opp-hz = /bits/ 64 <1555200000>; 313 opp-supported-hw = <0x77>; 314 clock-latency-ns = <200000>; 315 }; 316 opp-1632000000 { 317 opp-hz = /bits/ 64 <1632000000>; 318 opp-supported-hw = <0x77>; 319 clock-latency-ns = <200000>; 320 }; 321 opp-1708800000 { 322 opp-hz = /bits/ 64 <1708800000>; 323 opp-supported-hw = <0x77>; 324 clock-latency-ns = <200000>; 325 }; 326 opp-1785600000 { 327 opp-hz = /bits/ 64 <1785600000>; 328 opp-supported-hw = <0x77>; 329 clock-latency-ns = <200000>; 330 }; 331 opp-1824000000 { 332 opp-hz = /bits/ 64 <1824000000>; 333 opp-supported-hw = <0x77>; 334 clock-latency-ns = <200000>; 335 }; 336 opp-1920000000 { 337 opp-hz = /bits/ 64 <1920000000>; 338 opp-supported-hw = <0x77>; 339 clock-latency-ns = <200000>; 340 }; 341 opp-1996800000 { 342 opp-hz = /bits/ 64 <1996800000>; 343 opp-supported-hw = <0x77>; 344 clock-latency-ns = <200000>; 345 }; 346 opp-2073600000 { 347 opp-hz = /bits/ 64 <2073600000>; 348 opp-supported-hw = <0x77>; 349 clock-latency-ns = <200000>; 350 }; 351 opp-2150400000 { 352 opp-hz = /bits/ 64 <2150400000>; 353 opp-supported-hw = <0x77>; 354 clock-latency-ns = <200000>; 355 }; 356 }; 357 358 firmware { 359 scm { 360 compatible = "qcom,scm-msm8996"; 361 qcom,dload-mode = <&tcsr 0x13000>; 362 }; 363 }; 364 365 tcsr_mutex: hwlock { 366 compatible = "qcom,tcsr-mutex"; 367 syscon = <&tcsr_mutex_regs 0 0x1000>; 368 #hwlock-cells = <1>; 369 }; 370 371 memory@80000000 { 372 device_type = "memory"; 373 /* We expect the bootloader to fill in the reg */ 374 reg = <0x0 0x80000000 0x0 0x0>; 375 }; 376 377 psci { 378 compatible = "arm,psci-1.0"; 379 method = "smc"; 380 }; 381 382 reserved-memory { 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 387 hyp_mem: memory@85800000 { 388 reg = <0x0 0x85800000 0x0 0x600000>; 389 no-map; 390 }; 391 392 xbl_mem: memory@85e00000 { 393 reg = <0x0 0x85e00000 0x0 0x200000>; 394 no-map; 395 }; 396 397 smem_mem: smem-mem@86000000 { 398 reg = <0x0 0x86000000 0x0 0x200000>; 399 no-map; 400 }; 401 402 tz_mem: memory@86200000 { 403 reg = <0x0 0x86200000 0x0 0x2600000>; 404 no-map; 405 }; 406 407 rmtfs_mem: rmtfs { 408 compatible = "qcom,rmtfs-mem"; 409 410 size = <0x0 0x200000>; 411 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 412 no-map; 413 414 qcom,client-id = <1>; 415 qcom,vmid = <15>; 416 }; 417 418 mpss_mem: mpss@88800000 { 419 reg = <0x0 0x88800000 0x0 0x6200000>; 420 no-map; 421 }; 422 423 adsp_mem: adsp@8ea00000 { 424 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 425 no-map; 426 }; 427 428 slpi_mem: slpi@90500000 { 429 reg = <0x0 0x90500000 0x0 0xa00000>; 430 no-map; 431 }; 432 433 gpu_mem: gpu@90f00000 { 434 compatible = "shared-dma-pool"; 435 reg = <0x0 0x90f00000 0x0 0x100000>; 436 no-map; 437 }; 438 439 venus_mem: venus@91000000 { 440 reg = <0x0 0x91000000 0x0 0x500000>; 441 no-map; 442 }; 443 444 mba_mem: mba@91500000 { 445 reg = <0x0 0x91500000 0x0 0x200000>; 446 no-map; 447 }; 448 }; 449 450 rpm-glink { 451 compatible = "qcom,glink-rpm"; 452 453 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 454 455 qcom,rpm-msg-ram = <&rpm_msg_ram>; 456 457 mboxes = <&apcs_glb 0>; 458 459 rpm_requests: rpm-requests { 460 compatible = "qcom,rpm-msm8996"; 461 qcom,glink-channels = "rpm_requests"; 462 463 rpmcc: qcom,rpmcc { 464 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 465 #clock-cells = <1>; 466 }; 467 468 rpmpd: power-controller { 469 compatible = "qcom,msm8996-rpmpd"; 470 #power-domain-cells = <1>; 471 operating-points-v2 = <&rpmpd_opp_table>; 472 473 rpmpd_opp_table: opp-table { 474 compatible = "operating-points-v2"; 475 476 rpmpd_opp1: opp1 { 477 opp-level = <1>; 478 }; 479 480 rpmpd_opp2: opp2 { 481 opp-level = <2>; 482 }; 483 484 rpmpd_opp3: opp3 { 485 opp-level = <3>; 486 }; 487 488 rpmpd_opp4: opp4 { 489 opp-level = <4>; 490 }; 491 492 rpmpd_opp5: opp5 { 493 opp-level = <5>; 494 }; 495 496 rpmpd_opp6: opp6 { 497 opp-level = <6>; 498 }; 499 }; 500 }; 501 }; 502 }; 503 504 smem { 505 compatible = "qcom,smem"; 506 memory-region = <&smem_mem>; 507 hwlocks = <&tcsr_mutex 3>; 508 }; 509 510 smp2p-adsp { 511 compatible = "qcom,smp2p"; 512 qcom,smem = <443>, <429>; 513 514 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 515 516 mboxes = <&apcs_glb 10>; 517 518 qcom,local-pid = <0>; 519 qcom,remote-pid = <2>; 520 521 adsp_smp2p_out: master-kernel { 522 qcom,entry-name = "master-kernel"; 523 #qcom,smem-state-cells = <1>; 524 }; 525 526 adsp_smp2p_in: slave-kernel { 527 qcom,entry-name = "slave-kernel"; 528 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 }; 533 534 smp2p-mpss { 535 compatible = "qcom,smp2p"; 536 qcom,smem = <435>, <428>; 537 538 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 539 540 mboxes = <&apcs_glb 14>; 541 542 qcom,local-pid = <0>; 543 qcom,remote-pid = <1>; 544 545 mpss_smp2p_out: master-kernel { 546 qcom,entry-name = "master-kernel"; 547 #qcom,smem-state-cells = <1>; 548 }; 549 550 mpss_smp2p_in: slave-kernel { 551 qcom,entry-name = "slave-kernel"; 552 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 }; 557 558 smp2p-slpi { 559 compatible = "qcom,smp2p"; 560 qcom,smem = <481>, <430>; 561 562 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 563 564 mboxes = <&apcs_glb 26>; 565 566 qcom,local-pid = <0>; 567 qcom,remote-pid = <3>; 568 569 slpi_smp2p_out: master-kernel { 570 qcom,entry-name = "master-kernel"; 571 #qcom,smem-state-cells = <1>; 572 }; 573 574 slpi_smp2p_in: slave-kernel { 575 qcom,entry-name = "slave-kernel"; 576 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 }; 580 }; 581 582 soc: soc { 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges = <0 0 0 0xffffffff>; 586 compatible = "simple-bus"; 587 588 pcie_phy: phy@34000 { 589 compatible = "qcom,msm8996-qmp-pcie-phy"; 590 reg = <0x00034000 0x488>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges; 594 595 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 596 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 597 <&gcc GCC_PCIE_CLKREF_CLK>; 598 clock-names = "aux", "cfg_ahb", "ref"; 599 600 resets = <&gcc GCC_PCIE_PHY_BCR>, 601 <&gcc GCC_PCIE_PHY_COM_BCR>, 602 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 603 reset-names = "phy", "common", "cfg"; 604 status = "disabled"; 605 606 pciephy_0: phy@35000 { 607 reg = <0x00035000 0x130>, 608 <0x00035200 0x200>, 609 <0x00035400 0x1dc>; 610 #phy-cells = <0>; 611 612 #clock-cells = <1>; 613 clock-output-names = "pcie_0_pipe_clk_src"; 614 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 615 clock-names = "pipe0"; 616 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 617 reset-names = "lane0"; 618 }; 619 620 pciephy_1: phy@36000 { 621 reg = <0x00036000 0x130>, 622 <0x00036200 0x200>, 623 <0x00036400 0x1dc>; 624 #phy-cells = <0>; 625 626 clock-output-names = "pcie_1_pipe_clk_src"; 627 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 628 clock-names = "pipe1"; 629 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 630 reset-names = "lane1"; 631 }; 632 633 pciephy_2: phy@37000 { 634 reg = <0x00037000 0x130>, 635 <0x00037200 0x200>, 636 <0x00037400 0x1dc>; 637 #phy-cells = <0>; 638 639 clock-output-names = "pcie_2_pipe_clk_src"; 640 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 641 clock-names = "pipe2"; 642 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 643 reset-names = "lane2"; 644 }; 645 }; 646 647 rpm_msg_ram: sram@68000 { 648 compatible = "qcom,rpm-msg-ram"; 649 reg = <0x00068000 0x6000>; 650 }; 651 652 qfprom@74000 { 653 compatible = "qcom,qfprom"; 654 reg = <0x00074000 0x8ff>; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 658 qusb2p_hstx_trim: hstx_trim@24e { 659 reg = <0x24e 0x2>; 660 bits = <5 4>; 661 }; 662 663 qusb2s_hstx_trim: hstx_trim@24f { 664 reg = <0x24f 0x1>; 665 bits = <1 4>; 666 }; 667 668 speedbin_efuse: speedbin@133 { 669 reg = <0x133 0x1>; 670 bits = <5 3>; 671 }; 672 }; 673 674 rng: rng@83000 { 675 compatible = "qcom,prng-ee"; 676 reg = <0x00083000 0x1000>; 677 clocks = <&gcc GCC_PRNG_AHB_CLK>; 678 clock-names = "core"; 679 }; 680 681 gcc: clock-controller@300000 { 682 compatible = "qcom,gcc-msm8996"; 683 #clock-cells = <1>; 684 #reset-cells = <1>; 685 #power-domain-cells = <1>; 686 reg = <0x00300000 0x90000>; 687 688 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 689 <&rpmcc RPM_SMD_LN_BB_CLK>, 690 <&sleep_clk>; 691 clock-names = "cxo", "cxo2", "sleep_clk"; 692 }; 693 694 tsens0: thermal-sensor@4a9000 { 695 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 696 reg = <0x004a9000 0x1000>, /* TM */ 697 <0x004a8000 0x1000>; /* SROT */ 698 #qcom,sensors = <13>; 699 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "uplow", "critical"; 702 #thermal-sensor-cells = <1>; 703 }; 704 705 tsens1: thermal-sensor@4ad000 { 706 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 707 reg = <0x004ad000 0x1000>, /* TM */ 708 <0x004ac000 0x1000>; /* SROT */ 709 #qcom,sensors = <8>; 710 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-names = "uplow", "critical"; 713 #thermal-sensor-cells = <1>; 714 }; 715 716 cryptobam: dma-controller@644000 { 717 compatible = "qcom,bam-v1.7.0"; 718 reg = <0x00644000 0x24000>; 719 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&gcc GCC_CE1_CLK>; 721 clock-names = "bam_clk"; 722 #dma-cells = <1>; 723 qcom,ee = <0>; 724 qcom,controlled-remotely; 725 }; 726 727 crypto: crypto@67a000 { 728 compatible = "qcom,crypto-v5.4"; 729 reg = <0x0067a000 0x6000>; 730 clocks = <&gcc GCC_CE1_AHB_CLK>, 731 <&gcc GCC_CE1_AXI_CLK>, 732 <&gcc GCC_CE1_CLK>; 733 clock-names = "iface", "bus", "core"; 734 dmas = <&cryptobam 6>, <&cryptobam 7>; 735 dma-names = "rx", "tx"; 736 }; 737 738 tcsr_mutex_regs: syscon@740000 { 739 compatible = "syscon"; 740 reg = <0x00740000 0x40000>; 741 }; 742 743 tcsr: syscon@7a0000 { 744 compatible = "qcom,tcsr-msm8996", "syscon"; 745 reg = <0x007a0000 0x18000>; 746 }; 747 748 mmcc: clock-controller@8c0000 { 749 compatible = "qcom,mmcc-msm8996"; 750 #clock-cells = <1>; 751 #reset-cells = <1>; 752 #power-domain-cells = <1>; 753 reg = <0x008c0000 0x40000>; 754 clocks = <&xo_board>, 755 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 756 <&gcc GPLL0>, 757 <&dsi0_phy 1>, 758 <&dsi0_phy 0>, 759 <0>, 760 <0>, 761 <0>; 762 clock-names = "xo", 763 "gcc_mmss_noc_cfg_ahb_clk", 764 "gpll0", 765 "dsi0pll", 766 "dsi0pllbyte", 767 "dsi1pll", 768 "dsi1pllbyte", 769 "hdmipll"; 770 assigned-clocks = <&mmcc MMPLL9_PLL>, 771 <&mmcc MMPLL1_PLL>, 772 <&mmcc MMPLL3_PLL>, 773 <&mmcc MMPLL4_PLL>, 774 <&mmcc MMPLL5_PLL>; 775 assigned-clock-rates = <624000000>, 776 <810000000>, 777 <980000000>, 778 <960000000>, 779 <825000000>; 780 }; 781 782 mdss: mdss@900000 { 783 compatible = "qcom,mdss"; 784 785 reg = <0x00900000 0x1000>, 786 <0x009b0000 0x1040>, 787 <0x009b8000 0x1040>; 788 reg-names = "mdss_phys", 789 "vbif_phys", 790 "vbif_nrt_phys"; 791 792 power-domains = <&mmcc MDSS_GDSC>; 793 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 794 795 interrupt-controller; 796 #interrupt-cells = <1>; 797 798 clocks = <&mmcc MDSS_AHB_CLK>; 799 clock-names = "iface"; 800 801 #address-cells = <1>; 802 #size-cells = <1>; 803 ranges; 804 805 status = "disabled"; 806 807 mdp: mdp@901000 { 808 compatible = "qcom,mdp5"; 809 reg = <0x00901000 0x90000>; 810 reg-names = "mdp_phys"; 811 812 interrupt-parent = <&mdss>; 813 interrupts = <0>; 814 815 clocks = <&mmcc MDSS_AHB_CLK>, 816 <&mmcc MDSS_AXI_CLK>, 817 <&mmcc MDSS_MDP_CLK>, 818 <&mmcc SMMU_MDP_AXI_CLK>, 819 <&mmcc MDSS_VSYNC_CLK>; 820 clock-names = "iface", 821 "bus", 822 "core", 823 "iommu", 824 "vsync"; 825 826 iommus = <&mdp_smmu 0>; 827 828 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 829 <&mmcc MDSS_VSYNC_CLK>; 830 assigned-clock-rates = <300000000>, 831 <19200000>; 832 833 ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 port@0 { 838 reg = <0>; 839 mdp5_intf3_out: endpoint { 840 remote-endpoint = <&hdmi_in>; 841 }; 842 }; 843 844 port@1 { 845 reg = <1>; 846 mdp5_intf1_out: endpoint { 847 remote-endpoint = <&dsi0_in>; 848 }; 849 }; 850 }; 851 }; 852 853 dsi0: dsi@994000 { 854 compatible = "qcom,mdss-dsi-ctrl"; 855 reg = <0x00994000 0x400>; 856 reg-names = "dsi_ctrl"; 857 858 interrupt-parent = <&mdss>; 859 interrupts = <4>; 860 861 clocks = <&mmcc MDSS_MDP_CLK>, 862 <&mmcc MDSS_BYTE0_CLK>, 863 <&mmcc MDSS_AHB_CLK>, 864 <&mmcc MDSS_AXI_CLK>, 865 <&mmcc MMSS_MISC_AHB_CLK>, 866 <&mmcc MDSS_PCLK0_CLK>, 867 <&mmcc MDSS_ESC0_CLK>; 868 clock-names = "mdp_core", 869 "byte", 870 "iface", 871 "bus", 872 "core_mmss", 873 "pixel", 874 "core"; 875 876 phys = <&dsi0_phy>; 877 phy-names = "dsi"; 878 status = "disabled"; 879 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 ports { 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 port@0 { 888 reg = <0>; 889 dsi0_in: endpoint { 890 remote-endpoint = <&mdp5_intf1_out>; 891 }; 892 }; 893 894 port@1 { 895 reg = <1>; 896 dsi0_out: endpoint { 897 }; 898 }; 899 }; 900 }; 901 902 dsi0_phy: dsi-phy@994400 { 903 compatible = "qcom,dsi-phy-14nm"; 904 reg = <0x00994400 0x100>, 905 <0x00994500 0x300>, 906 <0x00994800 0x188>; 907 reg-names = "dsi_phy", 908 "dsi_phy_lane", 909 "dsi_pll"; 910 911 #clock-cells = <1>; 912 #phy-cells = <0>; 913 914 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 915 clock-names = "iface", "ref"; 916 status = "disabled"; 917 }; 918 919 hdmi: hdmi-tx@9a0000 { 920 compatible = "qcom,hdmi-tx-8996"; 921 reg = <0x009a0000 0x50c>, 922 <0x00070000 0x6158>, 923 <0x009e0000 0xfff>; 924 reg-names = "core_physical", 925 "qfprom_physical", 926 "hdcp_physical"; 927 928 interrupt-parent = <&mdss>; 929 interrupts = <8>; 930 931 clocks = <&mmcc MDSS_MDP_CLK>, 932 <&mmcc MDSS_AHB_CLK>, 933 <&mmcc MDSS_HDMI_CLK>, 934 <&mmcc MDSS_HDMI_AHB_CLK>, 935 <&mmcc MDSS_EXTPCLK_CLK>; 936 clock-names = 937 "mdp_core", 938 "iface", 939 "core", 940 "alt_iface", 941 "extp"; 942 943 phys = <&hdmi_phy>; 944 phy-names = "hdmi_phy"; 945 #sound-dai-cells = <1>; 946 947 status = "disabled"; 948 949 ports { 950 #address-cells = <1>; 951 #size-cells = <0>; 952 953 port@0 { 954 reg = <0>; 955 hdmi_in: endpoint { 956 remote-endpoint = <&mdp5_intf3_out>; 957 }; 958 }; 959 }; 960 }; 961 962 hdmi_phy: hdmi-phy@9a0600 { 963 #phy-cells = <0>; 964 compatible = "qcom,hdmi-phy-8996"; 965 reg = <0x009a0600 0x1c4>, 966 <0x009a0a00 0x124>, 967 <0x009a0c00 0x124>, 968 <0x009a0e00 0x124>, 969 <0x009a1000 0x124>, 970 <0x009a1200 0x0c8>; 971 reg-names = "hdmi_pll", 972 "hdmi_tx_l0", 973 "hdmi_tx_l1", 974 "hdmi_tx_l2", 975 "hdmi_tx_l3", 976 "hdmi_phy"; 977 978 clocks = <&mmcc MDSS_AHB_CLK>, 979 <&gcc GCC_HDMI_CLKREF_CLK>; 980 clock-names = "iface", 981 "ref"; 982 983 status = "disabled"; 984 }; 985 }; 986 987 gpu: gpu@b00000 { 988 compatible = "qcom,adreno-530.2", "qcom,adreno"; 989 990 reg = <0x00b00000 0x3f000>; 991 reg-names = "kgsl_3d0_reg_memory"; 992 993 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 994 995 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 996 <&mmcc GPU_AHB_CLK>, 997 <&mmcc GPU_GX_RBBMTIMER_CLK>, 998 <&gcc GCC_BIMC_GFX_CLK>, 999 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1000 1001 clock-names = "core", 1002 "iface", 1003 "rbbmtimer", 1004 "mem", 1005 "mem_iface"; 1006 1007 power-domains = <&mmcc GPU_GX_GDSC>; 1008 iommus = <&adreno_smmu 0>; 1009 1010 nvmem-cells = <&speedbin_efuse>; 1011 nvmem-cell-names = "speed_bin"; 1012 1013 operating-points-v2 = <&gpu_opp_table>; 1014 1015 status = "disabled"; 1016 1017 #cooling-cells = <2>; 1018 1019 gpu_opp_table: opp-table { 1020 compatible ="operating-points-v2"; 1021 1022 /* 1023 * 624Mhz and 560Mhz are only available on speed 1024 * bin (1 << 0). All the rest are available on 1025 * all bins of the hardware 1026 */ 1027 opp-624000000 { 1028 opp-hz = /bits/ 64 <624000000>; 1029 opp-supported-hw = <0x01>; 1030 }; 1031 opp-560000000 { 1032 opp-hz = /bits/ 64 <560000000>; 1033 opp-supported-hw = <0x01>; 1034 }; 1035 opp-510000000 { 1036 opp-hz = /bits/ 64 <510000000>; 1037 opp-supported-hw = <0xFF>; 1038 }; 1039 opp-401800000 { 1040 opp-hz = /bits/ 64 <401800000>; 1041 opp-supported-hw = <0xFF>; 1042 }; 1043 opp-315000000 { 1044 opp-hz = /bits/ 64 <315000000>; 1045 opp-supported-hw = <0xFF>; 1046 }; 1047 opp-214000000 { 1048 opp-hz = /bits/ 64 <214000000>; 1049 opp-supported-hw = <0xFF>; 1050 }; 1051 opp-133000000 { 1052 opp-hz = /bits/ 64 <133000000>; 1053 opp-supported-hw = <0xFF>; 1054 }; 1055 }; 1056 1057 zap-shader { 1058 memory-region = <&gpu_mem>; 1059 }; 1060 }; 1061 1062 tlmm: pinctrl@1010000 { 1063 compatible = "qcom,msm8996-pinctrl"; 1064 reg = <0x01010000 0x300000>; 1065 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1066 gpio-controller; 1067 gpio-ranges = <&tlmm 0 0 150>; 1068 #gpio-cells = <2>; 1069 interrupt-controller; 1070 #interrupt-cells = <2>; 1071 1072 blsp1_spi1_default: blsp1-spi1-default { 1073 spi { 1074 pins = "gpio0", "gpio1", "gpio3"; 1075 function = "blsp_spi1"; 1076 drive-strength = <12>; 1077 bias-disable; 1078 }; 1079 1080 cs { 1081 pins = "gpio2"; 1082 function = "gpio"; 1083 drive-strength = <16>; 1084 bias-disable; 1085 output-high; 1086 }; 1087 }; 1088 1089 blsp1_spi1_sleep: blsp1-spi1-sleep { 1090 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1091 function = "gpio"; 1092 drive-strength = <2>; 1093 bias-pull-down; 1094 }; 1095 1096 blsp2_uart2_2pins_default: blsp2-uart1-2pins { 1097 pins = "gpio4", "gpio5"; 1098 function = "blsp_uart8"; 1099 drive-strength = <16>; 1100 bias-disable; 1101 }; 1102 1103 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { 1104 pins = "gpio4", "gpio5"; 1105 function = "gpio"; 1106 drive-strength = <2>; 1107 bias-disable; 1108 }; 1109 1110 blsp2_i2c2_default: blsp2-i2c2 { 1111 pins = "gpio6", "gpio7"; 1112 function = "blsp_i2c8"; 1113 drive-strength = <16>; 1114 bias-disable; 1115 }; 1116 1117 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1118 pins = "gpio6", "gpio7"; 1119 function = "gpio"; 1120 drive-strength = <2>; 1121 bias-disable; 1122 }; 1123 1124 cci0_default: cci0-default { 1125 pins = "gpio17", "gpio18"; 1126 function = "cci_i2c"; 1127 drive-strength = <16>; 1128 bias-disable; 1129 }; 1130 1131 camera0_state_on: 1132 camera_rear_default: camera-rear-default { 1133 camera0_mclk: mclk0 { 1134 pins = "gpio13"; 1135 function = "cam_mclk"; 1136 drive-strength = <16>; 1137 bias-disable; 1138 }; 1139 1140 camera0_rst: rst { 1141 pins = "gpio25"; 1142 function = "gpio"; 1143 drive-strength = <16>; 1144 bias-disable; 1145 }; 1146 1147 camera0_pwdn: pwdn { 1148 pins = "gpio26"; 1149 function = "gpio"; 1150 drive-strength = <16>; 1151 bias-disable; 1152 }; 1153 }; 1154 1155 cci1_default: cci1-default { 1156 pins = "gpio19", "gpio20"; 1157 function = "cci_i2c"; 1158 drive-strength = <16>; 1159 bias-disable; 1160 }; 1161 1162 camera1_state_on: 1163 camera_board_default: camera-board-default { 1164 mclk1 { 1165 pins = "gpio14"; 1166 function = "cam_mclk"; 1167 drive-strength = <16>; 1168 bias-disable; 1169 }; 1170 1171 pwdn { 1172 pins = "gpio98"; 1173 function = "gpio"; 1174 drive-strength = <16>; 1175 bias-disable; 1176 }; 1177 1178 rst { 1179 pins = "gpio104"; 1180 function = "gpio"; 1181 drive-strength = <16>; 1182 bias-disable; 1183 }; 1184 }; 1185 1186 camera2_state_on: 1187 camera_front_default: camera-front-default { 1188 camera2_mclk: mclk2 { 1189 pins = "gpio15"; 1190 function = "cam_mclk"; 1191 drive-strength = <16>; 1192 bias-disable; 1193 }; 1194 1195 camera2_rst: rst { 1196 pins = "gpio23"; 1197 function = "gpio"; 1198 drive-strength = <16>; 1199 bias-disable; 1200 }; 1201 1202 pwdn { 1203 pins = "gpio133"; 1204 function = "gpio"; 1205 drive-strength = <16>; 1206 bias-disable; 1207 }; 1208 }; 1209 1210 pcie0_state_on: pcie0-state-on { 1211 perst { 1212 pins = "gpio35"; 1213 function = "gpio"; 1214 drive-strength = <2>; 1215 bias-pull-down; 1216 }; 1217 1218 clkreq { 1219 pins = "gpio36"; 1220 function = "pci_e0"; 1221 drive-strength = <2>; 1222 bias-pull-up; 1223 }; 1224 1225 wake { 1226 pins = "gpio37"; 1227 function = "gpio"; 1228 drive-strength = <2>; 1229 bias-pull-up; 1230 }; 1231 }; 1232 1233 pcie0_state_off: pcie0-state-off { 1234 perst { 1235 pins = "gpio35"; 1236 function = "gpio"; 1237 drive-strength = <2>; 1238 bias-pull-down; 1239 }; 1240 1241 clkreq { 1242 pins = "gpio36"; 1243 function = "gpio"; 1244 drive-strength = <2>; 1245 bias-disable; 1246 }; 1247 1248 wake { 1249 pins = "gpio37"; 1250 function = "gpio"; 1251 drive-strength = <2>; 1252 bias-disable; 1253 }; 1254 }; 1255 1256 blsp1_uart2_default: blsp1-uart2-default { 1257 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1258 function = "blsp_uart2"; 1259 drive-strength = <16>; 1260 bias-disable; 1261 }; 1262 1263 blsp1_uart2_sleep: blsp1-uart2-sleep { 1264 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1265 function = "gpio"; 1266 drive-strength = <2>; 1267 bias-disable; 1268 }; 1269 1270 blsp1_i2c3_default: blsp1-i2c2-default { 1271 pins = "gpio47", "gpio48"; 1272 function = "blsp_i2c3"; 1273 drive-strength = <16>; 1274 bias-disable; 1275 }; 1276 1277 blsp1_i2c3_sleep: blsp1-i2c2-sleep { 1278 pins = "gpio47", "gpio48"; 1279 function = "gpio"; 1280 drive-strength = <2>; 1281 bias-disable; 1282 }; 1283 1284 blsp2_uart3_4pins_default: blsp2-uart2-4pins { 1285 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1286 function = "blsp_uart9"; 1287 drive-strength = <16>; 1288 bias-disable; 1289 }; 1290 1291 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { 1292 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1293 function = "blsp_uart9"; 1294 drive-strength = <2>; 1295 bias-disable; 1296 }; 1297 1298 blsp2_i2c3_default: blsp2-i2c3 { 1299 pins = "gpio51", "gpio52"; 1300 function = "blsp_i2c9"; 1301 drive-strength = <16>; 1302 bias-disable; 1303 }; 1304 1305 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1306 pins = "gpio51", "gpio52"; 1307 function = "gpio"; 1308 drive-strength = <2>; 1309 bias-disable; 1310 }; 1311 1312 wcd_intr_default: wcd-intr-default{ 1313 pins = "gpio54"; 1314 function = "gpio"; 1315 drive-strength = <2>; 1316 bias-pull-down; 1317 input-enable; 1318 }; 1319 1320 blsp2_i2c1_default: blsp2-i2c1 { 1321 pins = "gpio55", "gpio56"; 1322 function = "blsp_i2c7"; 1323 drive-strength = <16>; 1324 bias-disable; 1325 }; 1326 1327 blsp2_i2c1_sleep: blsp2-i2c0-sleep { 1328 pins = "gpio55", "gpio56"; 1329 function = "gpio"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 1334 blsp2_i2c5_default: blsp2-i2c5 { 1335 pins = "gpio60", "gpio61"; 1336 function = "blsp_i2c11"; 1337 drive-strength = <2>; 1338 bias-disable; 1339 }; 1340 1341 /* Sleep state for BLSP2_I2C5 is missing.. */ 1342 1343 cdc_reset_active: cdc-reset-active { 1344 pins = "gpio64"; 1345 function = "gpio"; 1346 drive-strength = <16>; 1347 bias-pull-down; 1348 output-high; 1349 }; 1350 1351 cdc_reset_sleep: cdc-reset-sleep { 1352 pins = "gpio64"; 1353 function = "gpio"; 1354 drive-strength = <16>; 1355 bias-disable; 1356 output-low; 1357 }; 1358 1359 blsp2_spi6_default: blsp2-spi5-default { 1360 spi { 1361 pins = "gpio85", "gpio86", "gpio88"; 1362 function = "blsp_spi12"; 1363 drive-strength = <12>; 1364 bias-disable; 1365 }; 1366 1367 cs { 1368 pins = "gpio87"; 1369 function = "gpio"; 1370 drive-strength = <16>; 1371 bias-disable; 1372 output-high; 1373 }; 1374 }; 1375 1376 blsp2_spi6_sleep: blsp2-spi5-sleep { 1377 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1378 function = "gpio"; 1379 drive-strength = <2>; 1380 bias-pull-down; 1381 }; 1382 1383 blsp2_i2c6_default: blsp2-i2c6 { 1384 pins = "gpio87", "gpio88"; 1385 function = "blsp_i2c12"; 1386 drive-strength = <16>; 1387 bias-disable; 1388 }; 1389 1390 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1391 pins = "gpio87", "gpio88"; 1392 function = "gpio"; 1393 drive-strength = <2>; 1394 bias-disable; 1395 }; 1396 1397 pcie1_state_on: pcie1-state-on { 1398 perst { 1399 pins = "gpio130"; 1400 function = "gpio"; 1401 drive-strength = <2>; 1402 bias-pull-down; 1403 }; 1404 1405 clkreq { 1406 pins = "gpio131"; 1407 function = "pci_e1"; 1408 drive-strength = <2>; 1409 bias-pull-up; 1410 }; 1411 1412 wake { 1413 pins = "gpio132"; 1414 function = "gpio"; 1415 drive-strength = <2>; 1416 bias-pull-down; 1417 }; 1418 }; 1419 1420 pcie1_state_off: pcie1-state-off { 1421 /* Perst is missing? */ 1422 clkreq { 1423 pins = "gpio131"; 1424 function = "gpio"; 1425 drive-strength = <2>; 1426 bias-disable; 1427 }; 1428 1429 wake { 1430 pins = "gpio132"; 1431 function = "gpio"; 1432 drive-strength = <2>; 1433 bias-disable; 1434 }; 1435 }; 1436 1437 pcie2_state_on: pcie2-state-on { 1438 perst { 1439 pins = "gpio114"; 1440 function = "gpio"; 1441 drive-strength = <2>; 1442 bias-pull-down; 1443 }; 1444 1445 clkreq { 1446 pins = "gpio115"; 1447 function = "pci_e2"; 1448 drive-strength = <2>; 1449 bias-pull-up; 1450 }; 1451 1452 wake { 1453 pins = "gpio116"; 1454 function = "gpio"; 1455 drive-strength = <2>; 1456 bias-pull-down; 1457 }; 1458 }; 1459 1460 pcie2_state_off: pcie2-state-off { 1461 /* Perst is missing? */ 1462 clkreq { 1463 pins = "gpio115"; 1464 function = "gpio"; 1465 drive-strength = <2>; 1466 bias-disable; 1467 }; 1468 1469 wake { 1470 pins = "gpio116"; 1471 function = "gpio"; 1472 drive-strength = <2>; 1473 bias-disable; 1474 }; 1475 }; 1476 1477 sdc1_state_on: sdc1-state-on { 1478 clk { 1479 pins = "sdc1_clk"; 1480 bias-disable; 1481 drive-strength = <16>; 1482 }; 1483 1484 cmd { 1485 pins = "sdc1_cmd"; 1486 bias-pull-up; 1487 drive-strength = <10>; 1488 }; 1489 1490 data { 1491 pins = "sdc1_data"; 1492 bias-pull-up; 1493 drive-strength = <10>; 1494 }; 1495 1496 rclk { 1497 pins = "sdc1_rclk"; 1498 bias-pull-down; 1499 }; 1500 }; 1501 1502 sdc1_state_off: sdc1-state-off { 1503 clk { 1504 pins = "sdc1_clk"; 1505 bias-disable; 1506 drive-strength = <2>; 1507 }; 1508 1509 cmd { 1510 pins = "sdc1_cmd"; 1511 bias-pull-up; 1512 drive-strength = <2>; 1513 }; 1514 1515 data { 1516 pins = "sdc1_data"; 1517 bias-pull-up; 1518 drive-strength = <2>; 1519 }; 1520 1521 rclk { 1522 pins = "sdc1_rclk"; 1523 bias-pull-down; 1524 }; 1525 }; 1526 1527 sdc2_state_on: sdc2-clk-on { 1528 clk { 1529 pins = "sdc2_clk"; 1530 bias-disable; 1531 drive-strength = <16>; 1532 }; 1533 1534 cmd { 1535 pins = "sdc2_cmd"; 1536 bias-pull-up; 1537 drive-strength = <10>; 1538 }; 1539 1540 data { 1541 pins = "sdc2_data"; 1542 bias-pull-up; 1543 drive-strength = <10>; 1544 }; 1545 }; 1546 1547 sdc2_state_off: sdc2-clk-off { 1548 clk { 1549 pins = "sdc2_clk"; 1550 bias-disable; 1551 drive-strength = <2>; 1552 }; 1553 1554 cmd { 1555 pins = "sdc2_cmd"; 1556 bias-pull-up; 1557 drive-strength = <2>; 1558 }; 1559 1560 data { 1561 pins = "sdc2_data"; 1562 bias-pull-up; 1563 drive-strength = <2>; 1564 }; 1565 }; 1566 }; 1567 1568 sram@290000 { 1569 compatible = "qcom,rpm-stats"; 1570 reg = <0x00290000 0x10000>; 1571 }; 1572 1573 spmi_bus: spmi@400f000 { 1574 compatible = "qcom,spmi-pmic-arb"; 1575 reg = <0x0400f000 0x1000>, 1576 <0x04400000 0x800000>, 1577 <0x04c00000 0x800000>, 1578 <0x05800000 0x200000>, 1579 <0x0400a000 0x002100>; 1580 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1581 interrupt-names = "periph_irq"; 1582 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1583 qcom,ee = <0>; 1584 qcom,channel = <0>; 1585 #address-cells = <2>; 1586 #size-cells = <0>; 1587 interrupt-controller; 1588 #interrupt-cells = <4>; 1589 }; 1590 1591 agnoc@0 { 1592 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1593 compatible = "simple-pm-bus"; 1594 #address-cells = <1>; 1595 #size-cells = <1>; 1596 ranges; 1597 1598 pcie0: pcie@600000 { 1599 compatible = "qcom,pcie-msm8996"; 1600 status = "disabled"; 1601 power-domains = <&gcc PCIE0_GDSC>; 1602 bus-range = <0x00 0xff>; 1603 num-lanes = <1>; 1604 1605 reg = <0x00600000 0x2000>, 1606 <0x0c000000 0xf1d>, 1607 <0x0c000f20 0xa8>, 1608 <0x0c100000 0x100000>; 1609 reg-names = "parf", "dbi", "elbi","config"; 1610 1611 phys = <&pciephy_0>; 1612 phy-names = "pciephy"; 1613 1614 #address-cells = <3>; 1615 #size-cells = <2>; 1616 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1617 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1618 1619 device_type = "pci"; 1620 1621 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1622 interrupt-names = "msi"; 1623 #interrupt-cells = <1>; 1624 interrupt-map-mask = <0 0 0 0x7>; 1625 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1626 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1627 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1628 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1629 1630 pinctrl-names = "default", "sleep"; 1631 pinctrl-0 = <&pcie0_state_on>; 1632 pinctrl-1 = <&pcie0_state_off>; 1633 1634 linux,pci-domain = <0>; 1635 1636 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1637 <&gcc GCC_PCIE_0_AUX_CLK>, 1638 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1639 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1640 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1641 1642 clock-names = "pipe", 1643 "aux", 1644 "cfg", 1645 "bus_master", 1646 "bus_slave"; 1647 1648 }; 1649 1650 pcie1: pcie@608000 { 1651 compatible = "qcom,pcie-msm8996"; 1652 power-domains = <&gcc PCIE1_GDSC>; 1653 bus-range = <0x00 0xff>; 1654 num-lanes = <1>; 1655 1656 status = "disabled"; 1657 1658 reg = <0x00608000 0x2000>, 1659 <0x0d000000 0xf1d>, 1660 <0x0d000f20 0xa8>, 1661 <0x0d100000 0x100000>; 1662 1663 reg-names = "parf", "dbi", "elbi","config"; 1664 1665 phys = <&pciephy_1>; 1666 phy-names = "pciephy"; 1667 1668 #address-cells = <3>; 1669 #size-cells = <2>; 1670 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1671 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1672 1673 device_type = "pci"; 1674 1675 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1676 interrupt-names = "msi"; 1677 #interrupt-cells = <1>; 1678 interrupt-map-mask = <0 0 0 0x7>; 1679 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1680 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1681 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1682 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1683 1684 pinctrl-names = "default", "sleep"; 1685 pinctrl-0 = <&pcie1_state_on>; 1686 pinctrl-1 = <&pcie1_state_off>; 1687 1688 linux,pci-domain = <1>; 1689 1690 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1691 <&gcc GCC_PCIE_1_AUX_CLK>, 1692 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1693 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1694 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1695 1696 clock-names = "pipe", 1697 "aux", 1698 "cfg", 1699 "bus_master", 1700 "bus_slave"; 1701 }; 1702 1703 pcie2: pcie@610000 { 1704 compatible = "qcom,pcie-msm8996"; 1705 power-domains = <&gcc PCIE2_GDSC>; 1706 bus-range = <0x00 0xff>; 1707 num-lanes = <1>; 1708 status = "disabled"; 1709 reg = <0x00610000 0x2000>, 1710 <0x0e000000 0xf1d>, 1711 <0x0e000f20 0xa8>, 1712 <0x0e100000 0x100000>; 1713 1714 reg-names = "parf", "dbi", "elbi","config"; 1715 1716 phys = <&pciephy_2>; 1717 phy-names = "pciephy"; 1718 1719 #address-cells = <3>; 1720 #size-cells = <2>; 1721 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1722 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1723 1724 device_type = "pci"; 1725 1726 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "msi"; 1728 #interrupt-cells = <1>; 1729 interrupt-map-mask = <0 0 0 0x7>; 1730 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1731 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1732 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1733 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1734 1735 pinctrl-names = "default", "sleep"; 1736 pinctrl-0 = <&pcie2_state_on>; 1737 pinctrl-1 = <&pcie2_state_off>; 1738 1739 linux,pci-domain = <2>; 1740 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1741 <&gcc GCC_PCIE_2_AUX_CLK>, 1742 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1743 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1744 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1745 1746 clock-names = "pipe", 1747 "aux", 1748 "cfg", 1749 "bus_master", 1750 "bus_slave"; 1751 }; 1752 }; 1753 1754 ufshc: ufshc@624000 { 1755 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1756 "jedec,ufs-2.0"; 1757 reg = <0x00624000 0x2500>; 1758 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1759 1760 phys = <&ufsphy_lane>; 1761 phy-names = "ufsphy"; 1762 1763 power-domains = <&gcc UFS_GDSC>; 1764 1765 clock-names = 1766 "core_clk_src", 1767 "core_clk", 1768 "bus_clk", 1769 "bus_aggr_clk", 1770 "iface_clk", 1771 "core_clk_unipro_src", 1772 "core_clk_unipro", 1773 "core_clk_ice", 1774 "ref_clk", 1775 "tx_lane0_sync_clk", 1776 "rx_lane0_sync_clk"; 1777 clocks = 1778 <&gcc UFS_AXI_CLK_SRC>, 1779 <&gcc GCC_UFS_AXI_CLK>, 1780 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 1781 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 1782 <&gcc GCC_UFS_AHB_CLK>, 1783 <&gcc UFS_ICE_CORE_CLK_SRC>, 1784 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1785 <&gcc GCC_UFS_ICE_CORE_CLK>, 1786 <&rpmcc RPM_SMD_LN_BB_CLK>, 1787 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1788 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 1789 freq-table-hz = 1790 <100000000 200000000>, 1791 <0 0>, 1792 <0 0>, 1793 <0 0>, 1794 <0 0>, 1795 <150000000 300000000>, 1796 <0 0>, 1797 <0 0>, 1798 <0 0>, 1799 <0 0>, 1800 <0 0>; 1801 1802 lanes-per-direction = <1>; 1803 #reset-cells = <1>; 1804 status = "disabled"; 1805 1806 ufs_variant { 1807 compatible = "qcom,ufs_variant"; 1808 }; 1809 }; 1810 1811 ufsphy: phy@627000 { 1812 compatible = "qcom,msm8996-qmp-ufs-phy"; 1813 reg = <0x00627000 0x1c4>; 1814 #address-cells = <1>; 1815 #size-cells = <1>; 1816 ranges; 1817 1818 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 1819 clock-names = "ref"; 1820 1821 resets = <&ufshc 0>; 1822 reset-names = "ufsphy"; 1823 status = "disabled"; 1824 1825 ufsphy_lane: phy@627400 { 1826 reg = <0x627400 0x12c>, 1827 <0x627600 0x200>, 1828 <0x627c00 0x1b4>; 1829 #phy-cells = <0>; 1830 }; 1831 }; 1832 1833 camss: camss@a00000 { 1834 compatible = "qcom,msm8996-camss"; 1835 reg = <0x00a34000 0x1000>, 1836 <0x00a00030 0x4>, 1837 <0x00a35000 0x1000>, 1838 <0x00a00038 0x4>, 1839 <0x00a36000 0x1000>, 1840 <0x00a00040 0x4>, 1841 <0x00a30000 0x100>, 1842 <0x00a30400 0x100>, 1843 <0x00a30800 0x100>, 1844 <0x00a30c00 0x100>, 1845 <0x00a31000 0x500>, 1846 <0x00a00020 0x10>, 1847 <0x00a10000 0x1000>, 1848 <0x00a14000 0x1000>; 1849 reg-names = "csiphy0", 1850 "csiphy0_clk_mux", 1851 "csiphy1", 1852 "csiphy1_clk_mux", 1853 "csiphy2", 1854 "csiphy2_clk_mux", 1855 "csid0", 1856 "csid1", 1857 "csid2", 1858 "csid3", 1859 "ispif", 1860 "csi_clk_mux", 1861 "vfe0", 1862 "vfe1"; 1863 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1864 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1865 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1866 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1867 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1868 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1869 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1870 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1871 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1872 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1873 interrupt-names = "csiphy0", 1874 "csiphy1", 1875 "csiphy2", 1876 "csid0", 1877 "csid1", 1878 "csid2", 1879 "csid3", 1880 "ispif", 1881 "vfe0", 1882 "vfe1"; 1883 power-domains = <&mmcc VFE0_GDSC>, 1884 <&mmcc VFE1_GDSC>; 1885 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1886 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1887 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1888 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1889 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1890 <&mmcc CAMSS_CSI0_AHB_CLK>, 1891 <&mmcc CAMSS_CSI0_CLK>, 1892 <&mmcc CAMSS_CSI0PHY_CLK>, 1893 <&mmcc CAMSS_CSI0PIX_CLK>, 1894 <&mmcc CAMSS_CSI0RDI_CLK>, 1895 <&mmcc CAMSS_CSI1_AHB_CLK>, 1896 <&mmcc CAMSS_CSI1_CLK>, 1897 <&mmcc CAMSS_CSI1PHY_CLK>, 1898 <&mmcc CAMSS_CSI1PIX_CLK>, 1899 <&mmcc CAMSS_CSI1RDI_CLK>, 1900 <&mmcc CAMSS_CSI2_AHB_CLK>, 1901 <&mmcc CAMSS_CSI2_CLK>, 1902 <&mmcc CAMSS_CSI2PHY_CLK>, 1903 <&mmcc CAMSS_CSI2PIX_CLK>, 1904 <&mmcc CAMSS_CSI2RDI_CLK>, 1905 <&mmcc CAMSS_CSI3_AHB_CLK>, 1906 <&mmcc CAMSS_CSI3_CLK>, 1907 <&mmcc CAMSS_CSI3PHY_CLK>, 1908 <&mmcc CAMSS_CSI3PIX_CLK>, 1909 <&mmcc CAMSS_CSI3RDI_CLK>, 1910 <&mmcc CAMSS_AHB_CLK>, 1911 <&mmcc CAMSS_VFE0_CLK>, 1912 <&mmcc CAMSS_CSI_VFE0_CLK>, 1913 <&mmcc CAMSS_VFE0_AHB_CLK>, 1914 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1915 <&mmcc CAMSS_VFE1_CLK>, 1916 <&mmcc CAMSS_CSI_VFE1_CLK>, 1917 <&mmcc CAMSS_VFE1_AHB_CLK>, 1918 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1919 <&mmcc CAMSS_VFE_AHB_CLK>, 1920 <&mmcc CAMSS_VFE_AXI_CLK>; 1921 clock-names = "top_ahb", 1922 "ispif_ahb", 1923 "csiphy0_timer", 1924 "csiphy1_timer", 1925 "csiphy2_timer", 1926 "csi0_ahb", 1927 "csi0", 1928 "csi0_phy", 1929 "csi0_pix", 1930 "csi0_rdi", 1931 "csi1_ahb", 1932 "csi1", 1933 "csi1_phy", 1934 "csi1_pix", 1935 "csi1_rdi", 1936 "csi2_ahb", 1937 "csi2", 1938 "csi2_phy", 1939 "csi2_pix", 1940 "csi2_rdi", 1941 "csi3_ahb", 1942 "csi3", 1943 "csi3_phy", 1944 "csi3_pix", 1945 "csi3_rdi", 1946 "ahb", 1947 "vfe0", 1948 "csi_vfe0", 1949 "vfe0_ahb", 1950 "vfe0_stream", 1951 "vfe1", 1952 "csi_vfe1", 1953 "vfe1_ahb", 1954 "vfe1_stream", 1955 "vfe_ahb", 1956 "vfe_axi"; 1957 iommus = <&vfe_smmu 0>, 1958 <&vfe_smmu 1>, 1959 <&vfe_smmu 2>, 1960 <&vfe_smmu 3>; 1961 status = "disabled"; 1962 ports { 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 }; 1966 }; 1967 1968 cci: cci@a0c000 { 1969 compatible = "qcom,msm8996-cci"; 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 reg = <0xa0c000 0x1000>; 1973 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1974 power-domains = <&mmcc CAMSS_GDSC>; 1975 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1976 <&mmcc CAMSS_CCI_AHB_CLK>, 1977 <&mmcc CAMSS_CCI_CLK>, 1978 <&mmcc CAMSS_AHB_CLK>; 1979 clock-names = "camss_top_ahb", 1980 "cci_ahb", 1981 "cci", 1982 "camss_ahb"; 1983 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1984 <&mmcc CAMSS_CCI_CLK>; 1985 assigned-clock-rates = <80000000>, <37500000>; 1986 pinctrl-names = "default"; 1987 pinctrl-0 = <&cci0_default &cci1_default>; 1988 status = "disabled"; 1989 1990 cci_i2c0: i2c-bus@0 { 1991 reg = <0>; 1992 clock-frequency = <400000>; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 }; 1996 1997 cci_i2c1: i2c-bus@1 { 1998 reg = <1>; 1999 clock-frequency = <400000>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 }; 2003 }; 2004 2005 adreno_smmu: iommu@b40000 { 2006 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2007 reg = <0x00b40000 0x10000>; 2008 2009 #global-interrupts = <1>; 2010 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2013 #iommu-cells = <1>; 2014 2015 clocks = <&mmcc GPU_AHB_CLK>, 2016 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 2017 clock-names = "iface", "bus"; 2018 2019 power-domains = <&mmcc GPU_GDSC>; 2020 }; 2021 2022 venus: video-codec@c00000 { 2023 compatible = "qcom,msm8996-venus"; 2024 reg = <0x00c00000 0xff000>; 2025 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2026 power-domains = <&mmcc VENUS_GDSC>; 2027 clocks = <&mmcc VIDEO_CORE_CLK>, 2028 <&mmcc VIDEO_AHB_CLK>, 2029 <&mmcc VIDEO_AXI_CLK>, 2030 <&mmcc VIDEO_MAXI_CLK>; 2031 clock-names = "core", "iface", "bus", "mbus"; 2032 iommus = <&venus_smmu 0x00>, 2033 <&venus_smmu 0x01>, 2034 <&venus_smmu 0x0a>, 2035 <&venus_smmu 0x07>, 2036 <&venus_smmu 0x0e>, 2037 <&venus_smmu 0x0f>, 2038 <&venus_smmu 0x08>, 2039 <&venus_smmu 0x09>, 2040 <&venus_smmu 0x0b>, 2041 <&venus_smmu 0x0c>, 2042 <&venus_smmu 0x0d>, 2043 <&venus_smmu 0x10>, 2044 <&venus_smmu 0x11>, 2045 <&venus_smmu 0x21>, 2046 <&venus_smmu 0x28>, 2047 <&venus_smmu 0x29>, 2048 <&venus_smmu 0x2b>, 2049 <&venus_smmu 0x2c>, 2050 <&venus_smmu 0x2d>, 2051 <&venus_smmu 0x31>; 2052 memory-region = <&venus_mem>; 2053 status = "disabled"; 2054 2055 video-decoder { 2056 compatible = "venus-decoder"; 2057 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2058 clock-names = "core"; 2059 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2060 }; 2061 2062 video-encoder { 2063 compatible = "venus-encoder"; 2064 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2065 clock-names = "core"; 2066 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2067 }; 2068 }; 2069 2070 mdp_smmu: iommu@d00000 { 2071 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2072 reg = <0x00d00000 0x10000>; 2073 2074 #global-interrupts = <1>; 2075 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2078 #iommu-cells = <1>; 2079 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 2080 <&mmcc SMMU_MDP_AXI_CLK>; 2081 clock-names = "iface", "bus"; 2082 2083 power-domains = <&mmcc MDSS_GDSC>; 2084 }; 2085 2086 venus_smmu: iommu@d40000 { 2087 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2088 reg = <0x00d40000 0x20000>; 2089 #global-interrupts = <1>; 2090 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2098 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2099 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 2100 <&mmcc SMMU_VIDEO_AXI_CLK>; 2101 clock-names = "iface", "bus"; 2102 #iommu-cells = <1>; 2103 status = "okay"; 2104 }; 2105 2106 vfe_smmu: iommu@da0000 { 2107 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2108 reg = <0x00da0000 0x10000>; 2109 2110 #global-interrupts = <1>; 2111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2114 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2115 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 2116 <&mmcc SMMU_VFE_AXI_CLK>; 2117 clock-names = "iface", 2118 "bus"; 2119 #iommu-cells = <1>; 2120 }; 2121 2122 lpass_q6_smmu: iommu@1600000 { 2123 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2124 reg = <0x01600000 0x20000>; 2125 #iommu-cells = <1>; 2126 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2127 2128 #global-interrupts = <1>; 2129 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2142 2143 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 2144 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 2145 clock-names = "iface", "bus"; 2146 }; 2147 2148 slpi_pil: remoteproc@1c00000 { 2149 compatible = "qcom,msm8996-slpi-pil"; 2150 reg = <0x01c00000 0x4000>; 2151 2152 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2153 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2154 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2155 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2156 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2157 interrupt-names = "wdog", 2158 "fatal", 2159 "ready", 2160 "handover", 2161 "stop-ack"; 2162 2163 clocks = <&xo_board>, 2164 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2165 clock-names = "xo", "aggre2"; 2166 2167 memory-region = <&slpi_mem>; 2168 2169 qcom,smem-states = <&slpi_smp2p_out 0>; 2170 qcom,smem-state-names = "stop"; 2171 2172 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2173 power-domain-names = "ssc_cx"; 2174 2175 status = "disabled"; 2176 2177 smd-edge { 2178 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2179 2180 label = "dsps"; 2181 mboxes = <&apcs_glb 25>; 2182 qcom,smd-edge = <3>; 2183 qcom,remote-pid = <3>; 2184 }; 2185 }; 2186 2187 mss_pil: remoteproc@2080000 { 2188 compatible = "qcom,msm8996-mss-pil"; 2189 reg = <0x2080000 0x100>, 2190 <0x2180000 0x020>; 2191 reg-names = "qdsp6", "rmb"; 2192 2193 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2194 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2195 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2196 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2197 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2198 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2199 interrupt-names = "wdog", "fatal", "ready", 2200 "handover", "stop-ack", 2201 "shutdown-ack"; 2202 2203 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2204 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2205 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2206 <&xo_board>, 2207 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2208 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2209 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2210 <&rpmcc RPM_SMD_PCNOC_CLK>, 2211 <&rpmcc RPM_SMD_QDSS_CLK>; 2212 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2213 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2214 2215 resets = <&gcc GCC_MSS_RESTART>; 2216 reset-names = "mss_restart"; 2217 2218 power-domains = <&rpmpd MSM8996_VDDCX>, 2219 <&rpmpd MSM8996_VDDMX>; 2220 power-domain-names = "cx", "mx"; 2221 2222 qcom,smem-states = <&mpss_smp2p_out 0>; 2223 qcom,smem-state-names = "stop"; 2224 2225 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2226 2227 status = "disabled"; 2228 2229 mba { 2230 memory-region = <&mba_mem>; 2231 }; 2232 2233 mpss { 2234 memory-region = <&mpss_mem>; 2235 }; 2236 2237 smd-edge { 2238 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2239 2240 label = "mpss"; 2241 mboxes = <&apcs_glb 12>; 2242 qcom,smd-edge = <0>; 2243 qcom,remote-pid = <1>; 2244 }; 2245 }; 2246 2247 stm@3002000 { 2248 compatible = "arm,coresight-stm", "arm,primecell"; 2249 reg = <0x3002000 0x1000>, 2250 <0x8280000 0x180000>; 2251 reg-names = "stm-base", "stm-stimulus-base"; 2252 2253 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2254 clock-names = "apb_pclk", "atclk"; 2255 2256 out-ports { 2257 port { 2258 stm_out: endpoint { 2259 remote-endpoint = 2260 <&funnel0_in>; 2261 }; 2262 }; 2263 }; 2264 }; 2265 2266 tpiu@3020000 { 2267 compatible = "arm,coresight-tpiu", "arm,primecell"; 2268 reg = <0x3020000 0x1000>; 2269 2270 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2271 clock-names = "apb_pclk", "atclk"; 2272 2273 in-ports { 2274 port { 2275 tpiu_in: endpoint { 2276 remote-endpoint = 2277 <&replicator_out1>; 2278 }; 2279 }; 2280 }; 2281 }; 2282 2283 funnel@3021000 { 2284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2285 reg = <0x3021000 0x1000>; 2286 2287 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2288 clock-names = "apb_pclk", "atclk"; 2289 2290 in-ports { 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 2294 port@7 { 2295 reg = <7>; 2296 funnel0_in: endpoint { 2297 remote-endpoint = 2298 <&stm_out>; 2299 }; 2300 }; 2301 }; 2302 2303 out-ports { 2304 port { 2305 funnel0_out: endpoint { 2306 remote-endpoint = 2307 <&merge_funnel_in0>; 2308 }; 2309 }; 2310 }; 2311 }; 2312 2313 funnel@3022000 { 2314 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2315 reg = <0x3022000 0x1000>; 2316 2317 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2318 clock-names = "apb_pclk", "atclk"; 2319 2320 in-ports { 2321 #address-cells = <1>; 2322 #size-cells = <0>; 2323 2324 port@6 { 2325 reg = <6>; 2326 funnel1_in: endpoint { 2327 remote-endpoint = 2328 <&apss_merge_funnel_out>; 2329 }; 2330 }; 2331 }; 2332 2333 out-ports { 2334 port { 2335 funnel1_out: endpoint { 2336 remote-endpoint = 2337 <&merge_funnel_in1>; 2338 }; 2339 }; 2340 }; 2341 }; 2342 2343 funnel@3023000 { 2344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2345 reg = <0x3023000 0x1000>; 2346 2347 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2348 clock-names = "apb_pclk", "atclk"; 2349 2350 2351 out-ports { 2352 port { 2353 funnel2_out: endpoint { 2354 remote-endpoint = 2355 <&merge_funnel_in2>; 2356 }; 2357 }; 2358 }; 2359 }; 2360 2361 funnel@3025000 { 2362 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2363 reg = <0x3025000 0x1000>; 2364 2365 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2366 clock-names = "apb_pclk", "atclk"; 2367 2368 in-ports { 2369 #address-cells = <1>; 2370 #size-cells = <0>; 2371 2372 port@0 { 2373 reg = <0>; 2374 merge_funnel_in0: endpoint { 2375 remote-endpoint = 2376 <&funnel0_out>; 2377 }; 2378 }; 2379 2380 port@1 { 2381 reg = <1>; 2382 merge_funnel_in1: endpoint { 2383 remote-endpoint = 2384 <&funnel1_out>; 2385 }; 2386 }; 2387 2388 port@2 { 2389 reg = <2>; 2390 merge_funnel_in2: endpoint { 2391 remote-endpoint = 2392 <&funnel2_out>; 2393 }; 2394 }; 2395 }; 2396 2397 out-ports { 2398 port { 2399 merge_funnel_out: endpoint { 2400 remote-endpoint = 2401 <&etf_in>; 2402 }; 2403 }; 2404 }; 2405 }; 2406 2407 replicator@3026000 { 2408 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2409 reg = <0x3026000 0x1000>; 2410 2411 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2412 clock-names = "apb_pclk", "atclk"; 2413 2414 in-ports { 2415 port { 2416 replicator_in: endpoint { 2417 remote-endpoint = 2418 <&etf_out>; 2419 }; 2420 }; 2421 }; 2422 2423 out-ports { 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 2427 port@0 { 2428 reg = <0>; 2429 replicator_out0: endpoint { 2430 remote-endpoint = 2431 <&etr_in>; 2432 }; 2433 }; 2434 2435 port@1 { 2436 reg = <1>; 2437 replicator_out1: endpoint { 2438 remote-endpoint = 2439 <&tpiu_in>; 2440 }; 2441 }; 2442 }; 2443 }; 2444 2445 etf@3027000 { 2446 compatible = "arm,coresight-tmc", "arm,primecell"; 2447 reg = <0x3027000 0x1000>; 2448 2449 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2450 clock-names = "apb_pclk", "atclk"; 2451 2452 in-ports { 2453 port { 2454 etf_in: endpoint { 2455 remote-endpoint = 2456 <&merge_funnel_out>; 2457 }; 2458 }; 2459 }; 2460 2461 out-ports { 2462 port { 2463 etf_out: endpoint { 2464 remote-endpoint = 2465 <&replicator_in>; 2466 }; 2467 }; 2468 }; 2469 }; 2470 2471 etr@3028000 { 2472 compatible = "arm,coresight-tmc", "arm,primecell"; 2473 reg = <0x3028000 0x1000>; 2474 2475 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2476 clock-names = "apb_pclk", "atclk"; 2477 arm,scatter-gather; 2478 2479 in-ports { 2480 port { 2481 etr_in: endpoint { 2482 remote-endpoint = 2483 <&replicator_out0>; 2484 }; 2485 }; 2486 }; 2487 }; 2488 2489 debug@3810000 { 2490 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2491 reg = <0x3810000 0x1000>; 2492 2493 clocks = <&rpmcc RPM_QDSS_CLK>; 2494 clock-names = "apb_pclk"; 2495 2496 cpu = <&CPU0>; 2497 }; 2498 2499 etm@3840000 { 2500 compatible = "arm,coresight-etm4x", "arm,primecell"; 2501 reg = <0x3840000 0x1000>; 2502 2503 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2504 clock-names = "apb_pclk", "atclk"; 2505 2506 cpu = <&CPU0>; 2507 2508 out-ports { 2509 port { 2510 etm0_out: endpoint { 2511 remote-endpoint = 2512 <&apss_funnel0_in0>; 2513 }; 2514 }; 2515 }; 2516 }; 2517 2518 debug@3910000 { 2519 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2520 reg = <0x3910000 0x1000>; 2521 2522 clocks = <&rpmcc RPM_QDSS_CLK>; 2523 clock-names = "apb_pclk"; 2524 2525 cpu = <&CPU1>; 2526 }; 2527 2528 etm@3940000 { 2529 compatible = "arm,coresight-etm4x", "arm,primecell"; 2530 reg = <0x3940000 0x1000>; 2531 2532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2533 clock-names = "apb_pclk", "atclk"; 2534 2535 cpu = <&CPU1>; 2536 2537 out-ports { 2538 port { 2539 etm1_out: endpoint { 2540 remote-endpoint = 2541 <&apss_funnel0_in1>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 funnel@39b0000 { /* APSS Funnel 0 */ 2548 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2549 reg = <0x39b0000 0x1000>; 2550 2551 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2552 clock-names = "apb_pclk", "atclk"; 2553 2554 in-ports { 2555 #address-cells = <1>; 2556 #size-cells = <0>; 2557 2558 port@0 { 2559 reg = <0>; 2560 apss_funnel0_in0: endpoint { 2561 remote-endpoint = <&etm0_out>; 2562 }; 2563 }; 2564 2565 port@1 { 2566 reg = <1>; 2567 apss_funnel0_in1: endpoint { 2568 remote-endpoint = <&etm1_out>; 2569 }; 2570 }; 2571 }; 2572 2573 out-ports { 2574 port { 2575 apss_funnel0_out: endpoint { 2576 remote-endpoint = 2577 <&apss_merge_funnel_in0>; 2578 }; 2579 }; 2580 }; 2581 }; 2582 2583 debug@3a10000 { 2584 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2585 reg = <0x3a10000 0x1000>; 2586 2587 clocks = <&rpmcc RPM_QDSS_CLK>; 2588 clock-names = "apb_pclk"; 2589 2590 cpu = <&CPU2>; 2591 }; 2592 2593 etm@3a40000 { 2594 compatible = "arm,coresight-etm4x", "arm,primecell"; 2595 reg = <0x3a40000 0x1000>; 2596 2597 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2598 clock-names = "apb_pclk", "atclk"; 2599 2600 cpu = <&CPU2>; 2601 2602 out-ports { 2603 port { 2604 etm2_out: endpoint { 2605 remote-endpoint = 2606 <&apss_funnel1_in0>; 2607 }; 2608 }; 2609 }; 2610 }; 2611 2612 debug@3b10000 { 2613 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2614 reg = <0x3b10000 0x1000>; 2615 2616 clocks = <&rpmcc RPM_QDSS_CLK>; 2617 clock-names = "apb_pclk"; 2618 2619 cpu = <&CPU3>; 2620 }; 2621 2622 etm@3b40000 { 2623 compatible = "arm,coresight-etm4x", "arm,primecell"; 2624 reg = <0x3b40000 0x1000>; 2625 2626 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2627 clock-names = "apb_pclk", "atclk"; 2628 2629 cpu = <&CPU3>; 2630 2631 out-ports { 2632 port { 2633 etm3_out: endpoint { 2634 remote-endpoint = 2635 <&apss_funnel1_in1>; 2636 }; 2637 }; 2638 }; 2639 }; 2640 2641 funnel@3bb0000 { /* APSS Funnel 1 */ 2642 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2643 reg = <0x3bb0000 0x1000>; 2644 2645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2646 clock-names = "apb_pclk", "atclk"; 2647 2648 in-ports { 2649 #address-cells = <1>; 2650 #size-cells = <0>; 2651 2652 port@0 { 2653 reg = <0>; 2654 apss_funnel1_in0: endpoint { 2655 remote-endpoint = <&etm2_out>; 2656 }; 2657 }; 2658 2659 port@1 { 2660 reg = <1>; 2661 apss_funnel1_in1: endpoint { 2662 remote-endpoint = <&etm3_out>; 2663 }; 2664 }; 2665 }; 2666 2667 out-ports { 2668 port { 2669 apss_funnel1_out: endpoint { 2670 remote-endpoint = 2671 <&apss_merge_funnel_in1>; 2672 }; 2673 }; 2674 }; 2675 }; 2676 2677 funnel@3bc0000 { 2678 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2679 reg = <0x3bc0000 0x1000>; 2680 2681 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2682 clock-names = "apb_pclk", "atclk"; 2683 2684 in-ports { 2685 #address-cells = <1>; 2686 #size-cells = <0>; 2687 2688 port@0 { 2689 reg = <0>; 2690 apss_merge_funnel_in0: endpoint { 2691 remote-endpoint = 2692 <&apss_funnel0_out>; 2693 }; 2694 }; 2695 2696 port@1 { 2697 reg = <1>; 2698 apss_merge_funnel_in1: endpoint { 2699 remote-endpoint = 2700 <&apss_funnel1_out>; 2701 }; 2702 }; 2703 }; 2704 2705 out-ports { 2706 port { 2707 apss_merge_funnel_out: endpoint { 2708 remote-endpoint = 2709 <&funnel1_in>; 2710 }; 2711 }; 2712 }; 2713 }; 2714 2715 kryocc: clock-controller@6400000 { 2716 compatible = "qcom,msm8996-apcc"; 2717 reg = <0x06400000 0x90000>; 2718 2719 clock-names = "xo"; 2720 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 2721 2722 #clock-cells = <1>; 2723 }; 2724 2725 usb3: usb@6af8800 { 2726 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2727 reg = <0x06af8800 0x400>; 2728 #address-cells = <1>; 2729 #size-cells = <1>; 2730 ranges; 2731 2732 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2734 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2735 2736 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2737 <&gcc GCC_USB30_MASTER_CLK>, 2738 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2739 <&gcc GCC_USB30_SLEEP_CLK>, 2740 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2741 clock-names = "cfg_noc", 2742 "core", 2743 "iface", 2744 "sleep", 2745 "mock_utmi"; 2746 2747 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2748 <&gcc GCC_USB30_MASTER_CLK>; 2749 assigned-clock-rates = <19200000>, <120000000>; 2750 2751 power-domains = <&gcc USB30_GDSC>; 2752 status = "disabled"; 2753 2754 usb3_dwc3: usb@6a00000 { 2755 compatible = "snps,dwc3"; 2756 reg = <0x06a00000 0xcc00>; 2757 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 2758 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 2759 phy-names = "usb2-phy", "usb3-phy"; 2760 snps,dis_u2_susphy_quirk; 2761 snps,dis_enblslpm_quirk; 2762 }; 2763 }; 2764 2765 usb3phy: phy@7410000 { 2766 compatible = "qcom,msm8996-qmp-usb3-phy"; 2767 reg = <0x07410000 0x1c4>; 2768 #address-cells = <1>; 2769 #size-cells = <1>; 2770 ranges; 2771 2772 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2773 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2774 <&gcc GCC_USB3_CLKREF_CLK>; 2775 clock-names = "aux", "cfg_ahb", "ref"; 2776 2777 resets = <&gcc GCC_USB3_PHY_BCR>, 2778 <&gcc GCC_USB3PHY_PHY_BCR>; 2779 reset-names = "phy", "common"; 2780 status = "disabled"; 2781 2782 ssusb_phy_0: phy@7410200 { 2783 reg = <0x07410200 0x200>, 2784 <0x07410400 0x130>, 2785 <0x07410600 0x1a8>; 2786 #phy-cells = <0>; 2787 2788 #clock-cells = <1>; 2789 clock-output-names = "usb3_phy_pipe_clk_src"; 2790 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2791 clock-names = "pipe0"; 2792 }; 2793 }; 2794 2795 hsusb_phy1: phy@7411000 { 2796 compatible = "qcom,msm8996-qusb2-phy"; 2797 reg = <0x07411000 0x180>; 2798 #phy-cells = <0>; 2799 2800 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2801 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2802 clock-names = "cfg_ahb", "ref"; 2803 2804 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2805 nvmem-cells = <&qusb2p_hstx_trim>; 2806 status = "disabled"; 2807 }; 2808 2809 hsusb_phy2: phy@7412000 { 2810 compatible = "qcom,msm8996-qusb2-phy"; 2811 reg = <0x07412000 0x180>; 2812 #phy-cells = <0>; 2813 2814 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2815 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 2816 clock-names = "cfg_ahb", "ref"; 2817 2818 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2819 nvmem-cells = <&qusb2s_hstx_trim>; 2820 status = "disabled"; 2821 }; 2822 2823 sdhc1: sdhci@7464900 { 2824 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 2825 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 2826 reg-names = "hc_mem", "core_mem"; 2827 2828 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2829 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2830 interrupt-names = "hc_irq", "pwr_irq"; 2831 2832 clock-names = "iface", "core", "xo"; 2833 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2834 <&gcc GCC_SDCC1_APPS_CLK>, 2835 <&rpmcc RPM_SMD_BB_CLK1>; 2836 resets = <&gcc GCC_SDCC1_BCR>; 2837 2838 pinctrl-names = "default", "sleep"; 2839 pinctrl-0 = <&sdc1_state_on>; 2840 pinctrl-1 = <&sdc1_state_off>; 2841 2842 bus-width = <8>; 2843 non-removable; 2844 status = "disabled"; 2845 }; 2846 2847 sdhc2: sdhci@74a4900 { 2848 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 2849 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 2850 reg-names = "hc_mem", "core_mem"; 2851 2852 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2854 interrupt-names = "hc_irq", "pwr_irq"; 2855 2856 clock-names = "iface", "core", "xo"; 2857 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2858 <&gcc GCC_SDCC2_APPS_CLK>, 2859 <&rpmcc RPM_SMD_BB_CLK1>; 2860 resets = <&gcc GCC_SDCC2_BCR>; 2861 2862 pinctrl-names = "default", "sleep"; 2863 pinctrl-0 = <&sdc2_state_on>; 2864 pinctrl-1 = <&sdc2_state_off>; 2865 2866 bus-width = <4>; 2867 status = "disabled"; 2868 }; 2869 2870 blsp1_dma: dma-controller@7544000 { 2871 compatible = "qcom,bam-v1.7.0"; 2872 reg = <0x07544000 0x2b000>; 2873 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2874 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2875 clock-names = "bam_clk"; 2876 qcom,controlled-remotely; 2877 #dma-cells = <1>; 2878 qcom,ee = <0>; 2879 }; 2880 2881 blsp1_uart2: serial@7570000 { 2882 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2883 reg = <0x07570000 0x1000>; 2884 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2885 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 2886 <&gcc GCC_BLSP1_AHB_CLK>; 2887 clock-names = "core", "iface"; 2888 pinctrl-names = "default", "sleep"; 2889 pinctrl-0 = <&blsp1_uart2_default>; 2890 pinctrl-1 = <&blsp1_uart2_sleep>; 2891 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 2892 dma-names = "tx", "rx"; 2893 status = "disabled"; 2894 }; 2895 2896 blsp1_spi1: spi@7575000 { 2897 compatible = "qcom,spi-qup-v2.2.1"; 2898 reg = <0x07575000 0x600>; 2899 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2900 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2901 <&gcc GCC_BLSP1_AHB_CLK>; 2902 clock-names = "core", "iface"; 2903 pinctrl-names = "default", "sleep"; 2904 pinctrl-0 = <&blsp1_spi1_default>; 2905 pinctrl-1 = <&blsp1_spi1_sleep>; 2906 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2907 dma-names = "tx", "rx"; 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 status = "disabled"; 2911 }; 2912 2913 blsp1_i2c3: i2c@7577000 { 2914 compatible = "qcom,i2c-qup-v2.2.1"; 2915 reg = <0x07577000 0x1000>; 2916 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2917 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2918 <&gcc GCC_BLSP1_AHB_CLK>; 2919 clock-names = "core", "iface"; 2920 pinctrl-names = "default", "sleep"; 2921 pinctrl-0 = <&blsp1_i2c3_default>; 2922 pinctrl-1 = <&blsp1_i2c3_sleep>; 2923 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2924 dma-names = "tx", "rx"; 2925 #address-cells = <1>; 2926 #size-cells = <0>; 2927 status = "disabled"; 2928 }; 2929 2930 blsp2_dma: dma-controller@7584000 { 2931 compatible = "qcom,bam-v1.7.0"; 2932 reg = <0x07584000 0x2b000>; 2933 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2934 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2935 clock-names = "bam_clk"; 2936 qcom,controlled-remotely; 2937 #dma-cells = <1>; 2938 qcom,ee = <0>; 2939 }; 2940 2941 blsp2_uart2: serial@75b0000 { 2942 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2943 reg = <0x075b0000 0x1000>; 2944 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2945 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2946 <&gcc GCC_BLSP2_AHB_CLK>; 2947 clock-names = "core", "iface"; 2948 status = "disabled"; 2949 }; 2950 2951 blsp2_uart3: serial@75b1000 { 2952 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2953 reg = <0x075b1000 0x1000>; 2954 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2955 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 2956 <&gcc GCC_BLSP2_AHB_CLK>; 2957 clock-names = "core", "iface"; 2958 status = "disabled"; 2959 }; 2960 2961 blsp2_i2c1: i2c@75b5000 { 2962 compatible = "qcom,i2c-qup-v2.2.1"; 2963 reg = <0x075b5000 0x1000>; 2964 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2965 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2966 <&gcc GCC_BLSP2_AHB_CLK>; 2967 clock-names = "core", "iface"; 2968 pinctrl-names = "default", "sleep"; 2969 pinctrl-0 = <&blsp2_i2c1_default>; 2970 pinctrl-1 = <&blsp2_i2c1_sleep>; 2971 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2972 dma-names = "tx", "rx"; 2973 #address-cells = <1>; 2974 #size-cells = <0>; 2975 status = "disabled"; 2976 }; 2977 2978 blsp2_i2c2: i2c@75b6000 { 2979 compatible = "qcom,i2c-qup-v2.2.1"; 2980 reg = <0x075b6000 0x1000>; 2981 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2982 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2983 <&gcc GCC_BLSP2_AHB_CLK>; 2984 clock-names = "core", "iface"; 2985 pinctrl-names = "default", "sleep"; 2986 pinctrl-0 = <&blsp2_i2c2_default>; 2987 pinctrl-1 = <&blsp2_i2c2_sleep>; 2988 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2989 dma-names = "tx", "rx"; 2990 #address-cells = <1>; 2991 #size-cells = <0>; 2992 status = "disabled"; 2993 }; 2994 2995 blsp2_i2c3: i2c@75b7000 { 2996 compatible = "qcom,i2c-qup-v2.2.1"; 2997 reg = <0x075b7000 0x1000>; 2998 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2999 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3000 <&gcc GCC_BLSP2_AHB_CLK>; 3001 clock-names = "core", "iface"; 3002 clock-frequency = <400000>; 3003 pinctrl-names = "default", "sleep"; 3004 pinctrl-0 = <&blsp2_i2c3_default>; 3005 pinctrl-1 = <&blsp2_i2c3_sleep>; 3006 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3007 dma-names = "tx", "rx"; 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 status = "disabled"; 3011 }; 3012 3013 blsp2_i2c5: i2c@75b9000 { 3014 compatible = "qcom,i2c-qup-v2.2.1"; 3015 reg = <0x75b9000 0x1000>; 3016 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3017 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3018 <&gcc GCC_BLSP2_AHB_CLK>; 3019 clock-names = "core", "iface"; 3020 pinctrl-names = "default"; 3021 pinctrl-0 = <&blsp2_i2c5_default>; 3022 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3023 dma-names = "tx", "rx"; 3024 #address-cells = <1>; 3025 #size-cells = <0>; 3026 status = "disabled"; 3027 }; 3028 3029 blsp2_i2c6: i2c@75ba000 { 3030 compatible = "qcom,i2c-qup-v2.2.1"; 3031 reg = <0x75ba000 0x1000>; 3032 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3033 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3034 <&gcc GCC_BLSP2_AHB_CLK>; 3035 clock-names = "core", "iface"; 3036 pinctrl-names = "default", "sleep"; 3037 pinctrl-0 = <&blsp2_i2c6_default>; 3038 pinctrl-1 = <&blsp2_i2c6_sleep>; 3039 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3040 dma-names = "tx", "rx"; 3041 #address-cells = <1>; 3042 #size-cells = <0>; 3043 status = "disabled"; 3044 }; 3045 3046 blsp2_spi6: spi@75ba000{ 3047 compatible = "qcom,spi-qup-v2.2.1"; 3048 reg = <0x075ba000 0x600>; 3049 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3050 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3051 <&gcc GCC_BLSP2_AHB_CLK>; 3052 clock-names = "core", "iface"; 3053 pinctrl-names = "default", "sleep"; 3054 pinctrl-0 = <&blsp2_spi6_default>; 3055 pinctrl-1 = <&blsp2_spi6_sleep>; 3056 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3057 dma-names = "tx", "rx"; 3058 #address-cells = <1>; 3059 #size-cells = <0>; 3060 status = "disabled"; 3061 }; 3062 3063 usb2: usb@76f8800 { 3064 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3065 reg = <0x076f8800 0x400>; 3066 #address-cells = <1>; 3067 #size-cells = <1>; 3068 ranges; 3069 3070 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3071 <&gcc GCC_USB20_MASTER_CLK>, 3072 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3073 <&gcc GCC_USB20_SLEEP_CLK>, 3074 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3075 clock-names = "cfg_noc", 3076 "core", 3077 "iface", 3078 "sleep", 3079 "mock_utmi"; 3080 3081 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3082 <&gcc GCC_USB20_MASTER_CLK>; 3083 assigned-clock-rates = <19200000>, <60000000>; 3084 3085 power-domains = <&gcc USB30_GDSC>; 3086 qcom,select-utmi-as-pipe-clk; 3087 status = "disabled"; 3088 3089 usb2_dwc3: usb@7600000 { 3090 compatible = "snps,dwc3"; 3091 reg = <0x07600000 0xcc00>; 3092 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3093 phys = <&hsusb_phy2>; 3094 phy-names = "usb2-phy"; 3095 maximum-speed = "high-speed"; 3096 snps,dis_u2_susphy_quirk; 3097 snps,dis_enblslpm_quirk; 3098 }; 3099 }; 3100 3101 slimbam: dma-controller@9184000 { 3102 compatible = "qcom,bam-v1.7.0"; 3103 qcom,controlled-remotely; 3104 reg = <0x09184000 0x32000>; 3105 num-channels = <31>; 3106 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3107 #dma-cells = <1>; 3108 qcom,ee = <1>; 3109 qcom,num-ees = <2>; 3110 }; 3111 3112 slim_msm: slim@91c0000 { 3113 compatible = "qcom,slim-ngd-v1.5.0"; 3114 reg = <0x091c0000 0x2C000>; 3115 reg-names = "ctrl"; 3116 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3117 dmas = <&slimbam 3>, <&slimbam 4>, 3118 <&slimbam 5>, <&slimbam 6>; 3119 dma-names = "rx", "tx", "tx2", "rx2"; 3120 #address-cells = <1>; 3121 #size-cells = <0>; 3122 ngd@1 { 3123 reg = <1>; 3124 #address-cells = <1>; 3125 #size-cells = <1>; 3126 3127 tasha_ifd: tas-ifd { 3128 compatible = "slim217,1a0"; 3129 reg = <0 0>; 3130 }; 3131 3132 wcd9335: codec@1{ 3133 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3134 pinctrl-names = "default"; 3135 3136 compatible = "slim217,1a0"; 3137 reg = <1 0>; 3138 3139 interrupt-parent = <&tlmm>; 3140 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3141 <53 IRQ_TYPE_LEVEL_HIGH>; 3142 interrupt-names = "intr1", "intr2"; 3143 interrupt-controller; 3144 #interrupt-cells = <1>; 3145 reset-gpios = <&tlmm 64 0>; 3146 3147 slim-ifc-dev = <&tasha_ifd>; 3148 3149 #sound-dai-cells = <1>; 3150 }; 3151 }; 3152 }; 3153 3154 adsp_pil: remoteproc@9300000 { 3155 compatible = "qcom,msm8996-adsp-pil"; 3156 reg = <0x09300000 0x80000>; 3157 3158 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3159 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3160 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3161 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3162 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3163 interrupt-names = "wdog", "fatal", "ready", 3164 "handover", "stop-ack"; 3165 3166 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3167 clock-names = "xo"; 3168 3169 memory-region = <&adsp_mem>; 3170 3171 qcom,smem-states = <&adsp_smp2p_out 0>; 3172 qcom,smem-state-names = "stop"; 3173 3174 power-domains = <&rpmpd MSM8996_VDDCX>; 3175 power-domain-names = "cx"; 3176 3177 status = "disabled"; 3178 3179 smd-edge { 3180 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3181 3182 label = "lpass"; 3183 mboxes = <&apcs_glb 8>; 3184 qcom,smd-edge = <1>; 3185 qcom,remote-pid = <2>; 3186 #address-cells = <1>; 3187 #size-cells = <0>; 3188 apr { 3189 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3190 compatible = "qcom,apr-v2"; 3191 qcom,smd-channels = "apr_audio_svc"; 3192 qcom,domain = <APR_DOMAIN_ADSP>; 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 q6core { 3197 reg = <APR_SVC_ADSP_CORE>; 3198 compatible = "qcom,q6core"; 3199 }; 3200 3201 q6afe: q6afe { 3202 compatible = "qcom,q6afe"; 3203 reg = <APR_SVC_AFE>; 3204 q6afedai: dais { 3205 compatible = "qcom,q6afe-dais"; 3206 #address-cells = <1>; 3207 #size-cells = <0>; 3208 #sound-dai-cells = <1>; 3209 hdmi@1 { 3210 reg = <1>; 3211 }; 3212 }; 3213 }; 3214 3215 q6asm: q6asm { 3216 compatible = "qcom,q6asm"; 3217 reg = <APR_SVC_ASM>; 3218 q6asmdai: dais { 3219 compatible = "qcom,q6asm-dais"; 3220 #address-cells = <1>; 3221 #size-cells = <0>; 3222 #sound-dai-cells = <1>; 3223 iommus = <&lpass_q6_smmu 1>; 3224 }; 3225 }; 3226 3227 q6adm: q6adm { 3228 compatible = "qcom,q6adm"; 3229 reg = <APR_SVC_ADM>; 3230 q6routing: routing { 3231 compatible = "qcom,q6adm-routing"; 3232 #sound-dai-cells = <0>; 3233 }; 3234 }; 3235 }; 3236 3237 }; 3238 }; 3239 3240 apcs_glb: mailbox@9820000 { 3241 compatible = "qcom,msm8996-apcs-hmss-global"; 3242 reg = <0x09820000 0x1000>; 3243 3244 #mbox-cells = <1>; 3245 }; 3246 3247 timer@9840000 { 3248 #address-cells = <1>; 3249 #size-cells = <1>; 3250 ranges; 3251 compatible = "arm,armv7-timer-mem"; 3252 reg = <0x09840000 0x1000>; 3253 clock-frequency = <19200000>; 3254 3255 frame@9850000 { 3256 frame-number = <0>; 3257 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3259 reg = <0x09850000 0x1000>, 3260 <0x09860000 0x1000>; 3261 }; 3262 3263 frame@9870000 { 3264 frame-number = <1>; 3265 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3266 reg = <0x09870000 0x1000>; 3267 status = "disabled"; 3268 }; 3269 3270 frame@9880000 { 3271 frame-number = <2>; 3272 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3273 reg = <0x09880000 0x1000>; 3274 status = "disabled"; 3275 }; 3276 3277 frame@9890000 { 3278 frame-number = <3>; 3279 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3280 reg = <0x09890000 0x1000>; 3281 status = "disabled"; 3282 }; 3283 3284 frame@98a0000 { 3285 frame-number = <4>; 3286 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3287 reg = <0x098a0000 0x1000>; 3288 status = "disabled"; 3289 }; 3290 3291 frame@98b0000 { 3292 frame-number = <5>; 3293 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3294 reg = <0x098b0000 0x1000>; 3295 status = "disabled"; 3296 }; 3297 3298 frame@98c0000 { 3299 frame-number = <6>; 3300 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3301 reg = <0x098c0000 0x1000>; 3302 status = "disabled"; 3303 }; 3304 }; 3305 3306 saw3: syscon@9a10000 { 3307 compatible = "syscon"; 3308 reg = <0x09a10000 0x1000>; 3309 }; 3310 3311 intc: interrupt-controller@9bc0000 { 3312 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3313 #interrupt-cells = <3>; 3314 interrupt-controller; 3315 #redistributor-regions = <1>; 3316 redistributor-stride = <0x0 0x40000>; 3317 reg = <0x09bc0000 0x10000>, 3318 <0x09c00000 0x100000>; 3319 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3320 }; 3321 }; 3322 3323 sound: sound { 3324 }; 3325 3326 thermal-zones { 3327 cpu0-thermal { 3328 polling-delay-passive = <250>; 3329 polling-delay = <1000>; 3330 3331 thermal-sensors = <&tsens0 3>; 3332 3333 trips { 3334 cpu0_alert0: trip-point0 { 3335 temperature = <75000>; 3336 hysteresis = <2000>; 3337 type = "passive"; 3338 }; 3339 3340 cpu0_crit: cpu_crit { 3341 temperature = <110000>; 3342 hysteresis = <2000>; 3343 type = "critical"; 3344 }; 3345 }; 3346 }; 3347 3348 cpu1-thermal { 3349 polling-delay-passive = <250>; 3350 polling-delay = <1000>; 3351 3352 thermal-sensors = <&tsens0 5>; 3353 3354 trips { 3355 cpu1_alert0: trip-point0 { 3356 temperature = <75000>; 3357 hysteresis = <2000>; 3358 type = "passive"; 3359 }; 3360 3361 cpu1_crit: cpu_crit { 3362 temperature = <110000>; 3363 hysteresis = <2000>; 3364 type = "critical"; 3365 }; 3366 }; 3367 }; 3368 3369 cpu2-thermal { 3370 polling-delay-passive = <250>; 3371 polling-delay = <1000>; 3372 3373 thermal-sensors = <&tsens0 8>; 3374 3375 trips { 3376 cpu2_alert0: trip-point0 { 3377 temperature = <75000>; 3378 hysteresis = <2000>; 3379 type = "passive"; 3380 }; 3381 3382 cpu2_crit: cpu_crit { 3383 temperature = <110000>; 3384 hysteresis = <2000>; 3385 type = "critical"; 3386 }; 3387 }; 3388 }; 3389 3390 cpu3-thermal { 3391 polling-delay-passive = <250>; 3392 polling-delay = <1000>; 3393 3394 thermal-sensors = <&tsens0 10>; 3395 3396 trips { 3397 cpu3_alert0: trip-point0 { 3398 temperature = <75000>; 3399 hysteresis = <2000>; 3400 type = "passive"; 3401 }; 3402 3403 cpu3_crit: cpu_crit { 3404 temperature = <110000>; 3405 hysteresis = <2000>; 3406 type = "critical"; 3407 }; 3408 }; 3409 }; 3410 3411 gpu-top-thermal { 3412 polling-delay-passive = <250>; 3413 polling-delay = <1000>; 3414 3415 thermal-sensors = <&tsens1 6>; 3416 3417 trips { 3418 gpu1_alert0: trip-point0 { 3419 temperature = <90000>; 3420 hysteresis = <2000>; 3421 type = "passive"; 3422 }; 3423 }; 3424 3425 cooling-maps { 3426 map0 { 3427 trip = <&gpu1_alert0>; 3428 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3429 }; 3430 }; 3431 }; 3432 3433 gpu-bottom-thermal { 3434 polling-delay-passive = <250>; 3435 polling-delay = <1000>; 3436 3437 thermal-sensors = <&tsens1 7>; 3438 3439 trips { 3440 gpu2_alert0: trip-point0 { 3441 temperature = <90000>; 3442 hysteresis = <2000>; 3443 type = "passive"; 3444 }; 3445 }; 3446 3447 cooling-maps { 3448 map0 { 3449 trip = <&gpu2_alert0>; 3450 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3451 }; 3452 }; 3453 }; 3454 3455 m4m-thermal { 3456 polling-delay-passive = <250>; 3457 polling-delay = <1000>; 3458 3459 thermal-sensors = <&tsens0 1>; 3460 3461 trips { 3462 m4m_alert0: trip-point0 { 3463 temperature = <90000>; 3464 hysteresis = <2000>; 3465 type = "hot"; 3466 }; 3467 }; 3468 }; 3469 3470 l3-or-venus-thermal { 3471 polling-delay-passive = <250>; 3472 polling-delay = <1000>; 3473 3474 thermal-sensors = <&tsens0 2>; 3475 3476 trips { 3477 l3_or_venus_alert0: trip-point0 { 3478 temperature = <90000>; 3479 hysteresis = <2000>; 3480 type = "hot"; 3481 }; 3482 }; 3483 }; 3484 3485 cluster0-l2-thermal { 3486 polling-delay-passive = <250>; 3487 polling-delay = <1000>; 3488 3489 thermal-sensors = <&tsens0 7>; 3490 3491 trips { 3492 cluster0_l2_alert0: trip-point0 { 3493 temperature = <90000>; 3494 hysteresis = <2000>; 3495 type = "hot"; 3496 }; 3497 }; 3498 }; 3499 3500 cluster1-l2-thermal { 3501 polling-delay-passive = <250>; 3502 polling-delay = <1000>; 3503 3504 thermal-sensors = <&tsens0 12>; 3505 3506 trips { 3507 cluster1_l2_alert0: trip-point0 { 3508 temperature = <90000>; 3509 hysteresis = <2000>; 3510 type = "hot"; 3511 }; 3512 }; 3513 }; 3514 3515 camera-thermal { 3516 polling-delay-passive = <250>; 3517 polling-delay = <1000>; 3518 3519 thermal-sensors = <&tsens1 1>; 3520 3521 trips { 3522 camera_alert0: trip-point0 { 3523 temperature = <90000>; 3524 hysteresis = <2000>; 3525 type = "hot"; 3526 }; 3527 }; 3528 }; 3529 3530 q6-dsp-thermal { 3531 polling-delay-passive = <250>; 3532 polling-delay = <1000>; 3533 3534 thermal-sensors = <&tsens1 2>; 3535 3536 trips { 3537 q6_dsp_alert0: trip-point0 { 3538 temperature = <90000>; 3539 hysteresis = <2000>; 3540 type = "hot"; 3541 }; 3542 }; 3543 }; 3544 3545 mem-thermal { 3546 polling-delay-passive = <250>; 3547 polling-delay = <1000>; 3548 3549 thermal-sensors = <&tsens1 3>; 3550 3551 trips { 3552 mem_alert0: trip-point0 { 3553 temperature = <90000>; 3554 hysteresis = <2000>; 3555 type = "hot"; 3556 }; 3557 }; 3558 }; 3559 3560 modemtx-thermal { 3561 polling-delay-passive = <250>; 3562 polling-delay = <1000>; 3563 3564 thermal-sensors = <&tsens1 4>; 3565 3566 trips { 3567 modemtx_alert0: trip-point0 { 3568 temperature = <90000>; 3569 hysteresis = <2000>; 3570 type = "hot"; 3571 }; 3572 }; 3573 }; 3574 }; 3575 3576 timer { 3577 compatible = "arm,armv8-timer"; 3578 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3579 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3580 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3581 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3582 }; 3583}; 3584