xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision 2f0754f2) 
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x77>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x77>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x77>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x77>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x77>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x77>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x77>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x77>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x77>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x77>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x77>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x77>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x77>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1401600000 {
209			opp-hz = /bits/ 64 <1401600000>;
210			opp-supported-hw = <0x77>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1478400000 {
214			opp-hz = /bits/ 64 <1478400000>;
215			opp-supported-hw = <0x77>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1593600000 {
219			opp-hz = /bits/ 64 <1593600000>;
220			opp-supported-hw = <0x77>;
221			clock-latency-ns = <200000>;
222		};
223	};
224
225	cluster1_opp: opp_table1 {
226		compatible = "operating-points-v2-kryo-cpu";
227		nvmem-cells = <&speedbin_efuse>;
228		opp-shared;
229
230		/* Nominal fmax for now */
231		opp-307200000 {
232			opp-hz = /bits/ 64 <307200000>;
233			opp-supported-hw = <0x77>;
234			clock-latency-ns = <200000>;
235		};
236		opp-403200000 {
237			opp-hz = /bits/ 64 <403200000>;
238			opp-supported-hw = <0x77>;
239			clock-latency-ns = <200000>;
240		};
241		opp-480000000 {
242			opp-hz = /bits/ 64 <480000000>;
243			opp-supported-hw = <0x77>;
244			clock-latency-ns = <200000>;
245		};
246		opp-556800000 {
247			opp-hz = /bits/ 64 <556800000>;
248			opp-supported-hw = <0x77>;
249			clock-latency-ns = <200000>;
250		};
251		opp-652800000 {
252			opp-hz = /bits/ 64 <652800000>;
253			opp-supported-hw = <0x77>;
254			clock-latency-ns = <200000>;
255		};
256		opp-729600000 {
257			opp-hz = /bits/ 64 <729600000>;
258			opp-supported-hw = <0x77>;
259			clock-latency-ns = <200000>;
260		};
261		opp-806400000 {
262			opp-hz = /bits/ 64 <806400000>;
263			opp-supported-hw = <0x77>;
264			clock-latency-ns = <200000>;
265		};
266		opp-883200000 {
267			opp-hz = /bits/ 64 <883200000>;
268			opp-supported-hw = <0x77>;
269			clock-latency-ns = <200000>;
270		};
271		opp-940800000 {
272			opp-hz = /bits/ 64 <940800000>;
273			opp-supported-hw = <0x77>;
274			clock-latency-ns = <200000>;
275		};
276		opp-1036800000 {
277			opp-hz = /bits/ 64 <1036800000>;
278			opp-supported-hw = <0x77>;
279			clock-latency-ns = <200000>;
280		};
281		opp-1113600000 {
282			opp-hz = /bits/ 64 <1113600000>;
283			opp-supported-hw = <0x77>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1190400000 {
287			opp-hz = /bits/ 64 <1190400000>;
288			opp-supported-hw = <0x77>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1248000000 {
292			opp-hz = /bits/ 64 <1248000000>;
293			opp-supported-hw = <0x77>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1324800000 {
297			opp-hz = /bits/ 64 <1324800000>;
298			opp-supported-hw = <0x77>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1401600000 {
302			opp-hz = /bits/ 64 <1401600000>;
303			opp-supported-hw = <0x77>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1478400000 {
307			opp-hz = /bits/ 64 <1478400000>;
308			opp-supported-hw = <0x77>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1555200000 {
312			opp-hz = /bits/ 64 <1555200000>;
313			opp-supported-hw = <0x77>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1632000000 {
317			opp-hz = /bits/ 64 <1632000000>;
318			opp-supported-hw = <0x77>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1708800000 {
322			opp-hz = /bits/ 64 <1708800000>;
323			opp-supported-hw = <0x77>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1785600000 {
327			opp-hz = /bits/ 64 <1785600000>;
328			opp-supported-hw = <0x77>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1824000000 {
332			opp-hz = /bits/ 64 <1824000000>;
333			opp-supported-hw = <0x77>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1920000000 {
337			opp-hz = /bits/ 64 <1920000000>;
338			opp-supported-hw = <0x77>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1996800000 {
342			opp-hz = /bits/ 64 <1996800000>;
343			opp-supported-hw = <0x77>;
344			clock-latency-ns = <200000>;
345		};
346		opp-2073600000 {
347			opp-hz = /bits/ 64 <2073600000>;
348			opp-supported-hw = <0x77>;
349			clock-latency-ns = <200000>;
350		};
351		opp-2150400000 {
352			opp-hz = /bits/ 64 <2150400000>;
353			opp-supported-hw = <0x77>;
354			clock-latency-ns = <200000>;
355		};
356	};
357
358	firmware {
359		scm {
360			compatible = "qcom,scm-msm8996";
361			qcom,dload-mode = <&tcsr 0x13000>;
362		};
363	};
364
365	tcsr_mutex: hwlock {
366		compatible = "qcom,tcsr-mutex";
367		syscon = <&tcsr_mutex_regs 0 0x1000>;
368		#hwlock-cells = <1>;
369	};
370
371	memory@80000000 {
372		device_type = "memory";
373		/* We expect the bootloader to fill in the reg */
374		reg = <0x0 0x80000000 0x0 0x0>;
375	};
376
377	psci {
378		compatible = "arm,psci-1.0";
379		method = "smc";
380	};
381
382	reserved-memory {
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges;
386
387		mba_region: mba@91500000 {
388			reg = <0x0 0x91500000 0x0 0x200000>;
389			no-map;
390		};
391
392		slpi_region: slpi@90b00000 {
393			reg = <0x0 0x90b00000 0x0 0xa00000>;
394			no-map;
395		};
396
397		venus_region: venus@90400000 {
398			reg = <0x0 0x90400000 0x0 0x700000>;
399			no-map;
400		};
401
402		adsp_region: adsp@8ea00000 {
403			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
404			no-map;
405		};
406
407		mpss_region: mpss@88800000 {
408			reg = <0x0 0x88800000 0x0 0x6200000>;
409			no-map;
410		};
411
412		smem_mem: smem-mem@86000000 {
413			reg = <0x0 0x86000000 0x0 0x200000>;
414			no-map;
415		};
416
417		memory@85800000 {
418			reg = <0x0 0x85800000 0x0 0x800000>;
419			no-map;
420		};
421
422		memory@86200000 {
423			reg = <0x0 0x86200000 0x0 0x2600000>;
424			no-map;
425		};
426
427		rmtfs@86700000 {
428			compatible = "qcom,rmtfs-mem";
429
430			size = <0x0 0x200000>;
431			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432			no-map;
433
434			qcom,client-id = <1>;
435			qcom,vmid = <15>;
436		};
437
438		zap_shader_region: gpu@8f200000 {
439			compatible = "shared-dma-pool";
440			reg = <0x0 0x90b00000 0x0 0xa00000>;
441			no-map;
442		};
443	};
444
445	rpm-glink {
446		compatible = "qcom,glink-rpm";
447
448		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
449
450		qcom,rpm-msg-ram = <&rpm_msg_ram>;
451
452		mboxes = <&apcs_glb 0>;
453
454		rpm_requests: rpm-requests {
455			compatible = "qcom,rpm-msm8996";
456			qcom,glink-channels = "rpm_requests";
457
458			rpmcc: qcom,rpmcc {
459				compatible = "qcom,rpmcc-msm8996";
460				#clock-cells = <1>;
461			};
462
463			rpmpd: power-controller {
464				compatible = "qcom,msm8996-rpmpd";
465				#power-domain-cells = <1>;
466				operating-points-v2 = <&rpmpd_opp_table>;
467
468				rpmpd_opp_table: opp-table {
469					compatible = "operating-points-v2";
470
471					rpmpd_opp1: opp1 {
472						opp-level = <1>;
473					};
474
475					rpmpd_opp2: opp2 {
476						opp-level = <2>;
477					};
478
479					rpmpd_opp3: opp3 {
480						opp-level = <3>;
481					};
482
483					rpmpd_opp4: opp4 {
484						opp-level = <4>;
485					};
486
487					rpmpd_opp5: opp5 {
488						opp-level = <5>;
489					};
490
491					rpmpd_opp6: opp6 {
492						opp-level = <6>;
493					};
494				};
495			};
496		};
497	};
498
499	smem {
500		compatible = "qcom,smem";
501		memory-region = <&smem_mem>;
502		hwlocks = <&tcsr_mutex 3>;
503	};
504
505	smp2p-adsp {
506		compatible = "qcom,smp2p";
507		qcom,smem = <443>, <429>;
508
509		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
510
511		mboxes = <&apcs_glb 10>;
512
513		qcom,local-pid = <0>;
514		qcom,remote-pid = <2>;
515
516		smp2p_adsp_out: master-kernel {
517			qcom,entry-name = "master-kernel";
518			#qcom,smem-state-cells = <1>;
519		};
520
521		smp2p_adsp_in: slave-kernel {
522			qcom,entry-name = "slave-kernel";
523
524			interrupt-controller;
525			#interrupt-cells = <2>;
526		};
527	};
528
529	smp2p-modem {
530		compatible = "qcom,smp2p";
531		qcom,smem = <435>, <428>;
532
533		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
534
535		mboxes = <&apcs_glb 14>;
536
537		qcom,local-pid = <0>;
538		qcom,remote-pid = <1>;
539
540		modem_smp2p_out: master-kernel {
541			qcom,entry-name = "master-kernel";
542			#qcom,smem-state-cells = <1>;
543		};
544
545		modem_smp2p_in: slave-kernel {
546			qcom,entry-name = "slave-kernel";
547
548			interrupt-controller;
549			#interrupt-cells = <2>;
550		};
551	};
552
553	smp2p-slpi {
554		compatible = "qcom,smp2p";
555		qcom,smem = <481>, <430>;
556
557		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
558
559		mboxes = <&apcs_glb 26>;
560
561		qcom,local-pid = <0>;
562		qcom,remote-pid = <3>;
563
564		smp2p_slpi_in: slave-kernel {
565			qcom,entry-name = "slave-kernel";
566			interrupt-controller;
567			#interrupt-cells = <2>;
568		};
569
570		smp2p_slpi_out: master-kernel {
571			qcom,entry-name = "master-kernel";
572			#qcom,smem-state-cells = <1>;
573		};
574	};
575
576	soc: soc {
577		#address-cells = <1>;
578		#size-cells = <1>;
579		ranges = <0 0 0 0xffffffff>;
580		compatible = "simple-bus";
581
582		pcie_phy: phy@34000 {
583			compatible = "qcom,msm8996-qmp-pcie-phy";
584			reg = <0x00034000 0x488>;
585			#address-cells = <1>;
586			#size-cells = <1>;
587			ranges;
588
589			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
590				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
591				<&gcc GCC_PCIE_CLKREF_CLK>;
592			clock-names = "aux", "cfg_ahb", "ref";
593
594			resets = <&gcc GCC_PCIE_PHY_BCR>,
595				<&gcc GCC_PCIE_PHY_COM_BCR>,
596				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
597			reset-names = "phy", "common", "cfg";
598			status = "disabled";
599
600			pciephy_0: phy@35000 {
601				reg = <0x00035000 0x130>,
602				      <0x00035200 0x200>,
603				      <0x00035400 0x1dc>;
604				#phy-cells = <0>;
605
606				#clock-cells = <1>;
607				clock-output-names = "pcie_0_pipe_clk_src";
608				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609				clock-names = "pipe0";
610				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611				reset-names = "lane0";
612			};
613
614			pciephy_1: phy@36000 {
615				reg = <0x00036000 0x130>,
616				      <0x00036200 0x200>,
617				      <0x00036400 0x1dc>;
618				#phy-cells = <0>;
619
620				clock-output-names = "pcie_1_pipe_clk_src";
621				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622				clock-names = "pipe1";
623				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624				reset-names = "lane1";
625			};
626
627			pciephy_2: phy@37000 {
628				reg = <0x00037000 0x130>,
629				      <0x00037200 0x200>,
630				      <0x00037400 0x1dc>;
631				#phy-cells = <0>;
632
633				clock-output-names = "pcie_2_pipe_clk_src";
634				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635				clock-names = "pipe2";
636				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637				reset-names = "lane2";
638			};
639		};
640
641		rpm_msg_ram: sram@68000 {
642			compatible = "qcom,rpm-msg-ram";
643			reg = <0x00068000 0x6000>;
644		};
645
646		qfprom@74000 {
647			compatible = "qcom,qfprom";
648			reg = <0x00074000 0x8ff>;
649			#address-cells = <1>;
650			#size-cells = <1>;
651
652			qusb2p_hstx_trim: hstx_trim@24e {
653				reg = <0x24e 0x2>;
654				bits = <5 4>;
655			};
656
657			qusb2s_hstx_trim: hstx_trim@24f {
658				reg = <0x24f 0x1>;
659				bits = <1 4>;
660			};
661
662			speedbin_efuse: speedbin@133 {
663				reg = <0x133 0x1>;
664				bits = <5 3>;
665			};
666		};
667
668		rng: rng@83000 {
669			compatible = "qcom,prng-ee";
670			reg = <0x00083000 0x1000>;
671			clocks = <&gcc GCC_PRNG_AHB_CLK>;
672			clock-names = "core";
673		};
674
675		gcc: clock-controller@300000 {
676			compatible = "qcom,gcc-msm8996";
677			#clock-cells = <1>;
678			#reset-cells = <1>;
679			#power-domain-cells = <1>;
680			reg = <0x00300000 0x90000>;
681
682			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683			clock-names = "cxo2";
684		};
685
686		tsens0: thermal-sensor@4a9000 {
687			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688			reg = <0x004a9000 0x1000>, /* TM */
689			      <0x004a8000 0x1000>; /* SROT */
690			#qcom,sensors = <13>;
691			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693			interrupt-names = "uplow", "critical";
694			#thermal-sensor-cells = <1>;
695		};
696
697		tsens1: thermal-sensor@4ad000 {
698			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699			reg = <0x004ad000 0x1000>, /* TM */
700			      <0x004ac000 0x1000>; /* SROT */
701			#qcom,sensors = <8>;
702			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "uplow", "critical";
705			#thermal-sensor-cells = <1>;
706		};
707
708		cryptobam: dma@644000 {
709			compatible = "qcom,bam-v1.7.0";
710			reg = <0x00644000 0x24000>;
711			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
712			clocks = <&gcc GCC_CE1_CLK>;
713			clock-names = "bam_clk";
714			#dma-cells = <1>;
715			qcom,ee = <0>;
716			qcom,controlled-remotely = <1>;
717		};
718
719		crypto: crypto@67a000 {
720			compatible = "qcom,crypto-v5.4";
721			reg = <0x0067a000 0x6000>;
722			clocks = <&gcc GCC_CE1_AHB_CLK>,
723				 <&gcc GCC_CE1_AXI_CLK>,
724				 <&gcc GCC_CE1_CLK>;
725			clock-names = "iface", "bus", "core";
726			dmas = <&cryptobam 6>, <&cryptobam 7>;
727			dma-names = "rx", "tx";
728		};
729
730		tcsr_mutex_regs: syscon@740000 {
731			compatible = "syscon";
732			reg = <0x00740000 0x40000>;
733		};
734
735		tcsr: syscon@7a0000 {
736			compatible = "qcom,tcsr-msm8996", "syscon";
737			reg = <0x007a0000 0x18000>;
738		};
739
740		mmcc: clock-controller@8c0000 {
741			compatible = "qcom,mmcc-msm8996";
742			#clock-cells = <1>;
743			#reset-cells = <1>;
744			#power-domain-cells = <1>;
745			reg = <0x008c0000 0x40000>;
746			assigned-clocks = <&mmcc MMPLL9_PLL>,
747					  <&mmcc MMPLL1_PLL>,
748					  <&mmcc MMPLL3_PLL>,
749					  <&mmcc MMPLL4_PLL>,
750					  <&mmcc MMPLL5_PLL>;
751			assigned-clock-rates = <624000000>,
752					       <810000000>,
753					       <980000000>,
754					       <960000000>,
755					       <825000000>;
756		};
757
758		mdss: mdss@900000 {
759			compatible = "qcom,mdss";
760
761			reg = <0x00900000 0x1000>,
762			      <0x009b0000 0x1040>,
763			      <0x009b8000 0x1040>;
764			reg-names = "mdss_phys",
765				    "vbif_phys",
766				    "vbif_nrt_phys";
767
768			power-domains = <&mmcc MDSS_GDSC>;
769			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
770
771			interrupt-controller;
772			#interrupt-cells = <1>;
773
774			clocks = <&mmcc MDSS_AHB_CLK>;
775			clock-names = "iface";
776
777			#address-cells = <1>;
778			#size-cells = <1>;
779			ranges;
780
781			status = "disabled";
782
783			mdp: mdp@901000 {
784				compatible = "qcom,mdp5";
785				reg = <0x00901000 0x90000>;
786				reg-names = "mdp_phys";
787
788				interrupt-parent = <&mdss>;
789				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
790
791				clocks = <&mmcc MDSS_AHB_CLK>,
792					 <&mmcc MDSS_AXI_CLK>,
793					 <&mmcc MDSS_MDP_CLK>,
794					 <&mmcc SMMU_MDP_AXI_CLK>,
795					 <&mmcc MDSS_VSYNC_CLK>;
796				clock-names = "iface",
797					      "bus",
798					      "core",
799					      "iommu",
800					      "vsync";
801
802				iommus = <&mdp_smmu 0>;
803
804				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
805					 <&mmcc MDSS_VSYNC_CLK>;
806				assigned-clock-rates = <300000000>,
807					 <19200000>;
808
809				ports {
810					#address-cells = <1>;
811					#size-cells = <0>;
812
813					port@0 {
814						reg = <0>;
815						mdp5_intf3_out: endpoint {
816							remote-endpoint = <&hdmi_in>;
817						};
818					};
819
820					port@1 {
821						reg = <1>;
822						mdp5_intf1_out: endpoint {
823							remote-endpoint = <&dsi0_in>;
824						};
825					};
826				};
827			};
828
829			dsi0: dsi@994000 {
830				compatible = "qcom,mdss-dsi-ctrl";
831				reg = <0x00994000 0x400>;
832				reg-names = "dsi_ctrl";
833
834				interrupt-parent = <&mdss>;
835				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
836
837				clocks = <&mmcc MDSS_MDP_CLK>,
838					 <&mmcc MDSS_BYTE0_CLK>,
839					 <&mmcc MDSS_AHB_CLK>,
840					 <&mmcc MDSS_AXI_CLK>,
841					 <&mmcc MMSS_MISC_AHB_CLK>,
842					 <&mmcc MDSS_PCLK0_CLK>,
843					 <&mmcc MDSS_ESC0_CLK>;
844				clock-names = "mdp_core",
845					      "byte",
846					      "iface",
847					      "bus",
848					      "core_mmss",
849					      "pixel",
850					      "core";
851
852				phys = <&dsi0_phy>;
853				phy-names = "dsi";
854				status = "disabled";
855
856				#address-cells = <1>;
857				#size-cells = <0>;
858
859				ports {
860					#address-cells = <1>;
861					#size-cells = <0>;
862
863					port@0 {
864						reg = <0>;
865						dsi0_in: endpoint {
866							remote-endpoint = <&mdp5_intf1_out>;
867						};
868					};
869
870					port@1 {
871						reg = <1>;
872						dsi0_out: endpoint {
873						};
874					};
875				};
876			};
877
878			dsi0_phy: dsi-phy@994400 {
879				compatible = "qcom,dsi-phy-14nm";
880				reg = <0x00994400 0x100>,
881				      <0x00994500 0x300>,
882				      <0x00994800 0x188>;
883				reg-names = "dsi_phy",
884					    "dsi_phy_lane",
885					    "dsi_pll";
886
887				#clock-cells = <1>;
888				#phy-cells = <0>;
889
890				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
891				clock-names = "iface", "ref";
892				status = "disabled";
893			};
894
895			hdmi: hdmi-tx@9a0000 {
896				compatible = "qcom,hdmi-tx-8996";
897				reg =	<0x009a0000 0x50c>,
898					<0x00070000 0x6158>,
899					<0x009e0000 0xfff>;
900				reg-names = "core_physical",
901					    "qfprom_physical",
902					    "hdcp_physical";
903
904				interrupt-parent = <&mdss>;
905				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
906
907				clocks = <&mmcc MDSS_MDP_CLK>,
908					 <&mmcc MDSS_AHB_CLK>,
909					 <&mmcc MDSS_HDMI_CLK>,
910					 <&mmcc MDSS_HDMI_AHB_CLK>,
911					 <&mmcc MDSS_EXTPCLK_CLK>;
912				clock-names =
913					"mdp_core",
914					"iface",
915					"core",
916					"alt_iface",
917					"extp";
918
919				phys = <&hdmi_phy>;
920				phy-names = "hdmi_phy";
921				#sound-dai-cells = <1>;
922
923				status = "disabled";
924
925				ports {
926					#address-cells = <1>;
927					#size-cells = <0>;
928
929					port@0 {
930						reg = <0>;
931						hdmi_in: endpoint {
932							remote-endpoint = <&mdp5_intf3_out>;
933						};
934					};
935				};
936			};
937
938			hdmi_phy: hdmi-phy@9a0600 {
939				#phy-cells = <0>;
940				compatible = "qcom,hdmi-phy-8996";
941				reg = <0x009a0600 0x1c4>,
942				      <0x009a0a00 0x124>,
943				      <0x009a0c00 0x124>,
944				      <0x009a0e00 0x124>,
945				      <0x009a1000 0x124>,
946				      <0x009a1200 0x0c8>;
947				reg-names = "hdmi_pll",
948					    "hdmi_tx_l0",
949					    "hdmi_tx_l1",
950					    "hdmi_tx_l2",
951					    "hdmi_tx_l3",
952					    "hdmi_phy";
953
954				clocks = <&mmcc MDSS_AHB_CLK>,
955					 <&gcc GCC_HDMI_CLKREF_CLK>;
956				clock-names = "iface",
957					      "ref";
958
959				status = "disabled";
960			};
961		};
962
963		gpu: gpu@b00000 {
964			compatible = "qcom,adreno-530.2", "qcom,adreno";
965
966			reg = <0x00b00000 0x3f000>;
967			reg-names = "kgsl_3d0_reg_memory";
968
969			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
970
971			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
972				<&mmcc GPU_AHB_CLK>,
973				<&mmcc GPU_GX_RBBMTIMER_CLK>,
974				<&gcc GCC_BIMC_GFX_CLK>,
975				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
976
977			clock-names = "core",
978				"iface",
979				"rbbmtimer",
980				"mem",
981				"mem_iface";
982
983			power-domains = <&mmcc GPU_GX_GDSC>;
984			iommus = <&adreno_smmu 0>;
985
986			nvmem-cells = <&speedbin_efuse>;
987			nvmem-cell-names = "speed_bin";
988
989			operating-points-v2 = <&gpu_opp_table>;
990
991			status = "disabled";
992
993			#cooling-cells = <2>;
994
995			gpu_opp_table: opp-table {
996				compatible  ="operating-points-v2";
997
998				/*
999				 * 624Mhz and 560Mhz are only available on speed
1000				 * bin (1 << 0). All the rest are available on
1001				 * all bins of the hardware
1002				 */
1003				opp-624000000 {
1004					opp-hz = /bits/ 64 <624000000>;
1005					opp-supported-hw = <0x01>;
1006				};
1007				opp-560000000 {
1008					opp-hz = /bits/ 64 <560000000>;
1009					opp-supported-hw = <0x01>;
1010				};
1011				opp-510000000 {
1012					opp-hz = /bits/ 64 <510000000>;
1013					opp-supported-hw = <0xFF>;
1014				};
1015				opp-401800000 {
1016					opp-hz = /bits/ 64 <401800000>;
1017					opp-supported-hw = <0xFF>;
1018				};
1019				opp-315000000 {
1020					opp-hz = /bits/ 64 <315000000>;
1021					opp-supported-hw = <0xFF>;
1022				};
1023				opp-214000000 {
1024					opp-hz = /bits/ 64 <214000000>;
1025					opp-supported-hw = <0xFF>;
1026				};
1027				opp-133000000 {
1028					opp-hz = /bits/ 64 <133000000>;
1029					opp-supported-hw = <0xFF>;
1030				};
1031			};
1032
1033			zap-shader {
1034				memory-region = <&zap_shader_region>;
1035			};
1036		};
1037
1038		tlmm: pinctrl@1010000 {
1039			compatible = "qcom,msm8996-pinctrl";
1040			reg = <0x01010000 0x300000>;
1041			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1042			gpio-controller;
1043			gpio-ranges = <&tlmm 0 0 150>;
1044			#gpio-cells = <2>;
1045			interrupt-controller;
1046			#interrupt-cells = <2>;
1047
1048			blsp1_spi1_default: blsp1-spi1-default {
1049				spi {
1050					pins = "gpio0", "gpio1", "gpio3";
1051					function = "blsp_spi1";
1052					drive-strength = <12>;
1053					bias-disable;
1054				};
1055
1056				cs {
1057					pins = "gpio2";
1058					function = "gpio";
1059					drive-strength = <16>;
1060					bias-disable;
1061					output-high;
1062				};
1063			};
1064
1065			blsp1_spi1_sleep: blsp1-spi1-sleep {
1066				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1067				function = "gpio";
1068				drive-strength = <2>;
1069				bias-pull-down;
1070			};
1071
1072			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1073				pins = "gpio4", "gpio5";
1074				function = "blsp_uart8";
1075				drive-strength = <16>;
1076				bias-disable;
1077			};
1078
1079			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1080				pins = "gpio4", "gpio5";
1081				function = "gpio";
1082				drive-strength = <2>;
1083				bias-disable;
1084			};
1085
1086			blsp2_i2c2_default: blsp2-i2c2 {
1087				pins = "gpio6", "gpio7";
1088				function = "blsp_i2c8";
1089				drive-strength = <16>;
1090				bias-disable;
1091			};
1092
1093			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1094				pins = "gpio6", "gpio7";
1095				function = "gpio";
1096				drive-strength = <2>;
1097				bias-disable;
1098			};
1099
1100			cci0_default: cci0-default {
1101				pins = "gpio17", "gpio18";
1102				function = "cci_i2c";
1103				drive-strength = <16>;
1104				bias-disable;
1105			};
1106
1107			camera0_state_on:
1108			camera_rear_default: camera-rear-default {
1109				camera0_mclk: mclk0 {
1110					pins = "gpio13";
1111					function = "cam_mclk";
1112					drive-strength = <16>;
1113					bias-disable;
1114				};
1115
1116				camera0_rst: rst {
1117					pins = "gpio25";
1118					function = "gpio";
1119					drive-strength = <16>;
1120					bias-disable;
1121				};
1122
1123				camera0_pwdn: pwdn {
1124					pins = "gpio26";
1125					function = "gpio";
1126					drive-strength = <16>;
1127					bias-disable;
1128				};
1129			};
1130
1131			cci1_default: cci1-default {
1132				pins = "gpio19", "gpio20";
1133				function = "cci_i2c";
1134				drive-strength = <16>;
1135				bias-disable;
1136			};
1137
1138			camera1_state_on:
1139			camera_board_default: camera-board-default {
1140				mclk1 {
1141					pins = "gpio14";
1142					function = "cam_mclk";
1143					drive-strength = <16>;
1144					bias-disable;
1145				};
1146
1147				pwdn {
1148					pins = "gpio98";
1149					function = "gpio";
1150					drive-strength = <16>;
1151					bias-disable;
1152				};
1153
1154				rst {
1155					pins = "gpio104";
1156					function = "gpio";
1157					drive-strength = <16>;
1158					bias-disable;
1159				};
1160			};
1161
1162			camera2_state_on:
1163			camera_front_default: camera-front-default {
1164				camera2_mclk: mclk2 {
1165					pins = "gpio15";
1166					function = "cam_mclk";
1167					drive-strength = <16>;
1168					bias-disable;
1169				};
1170
1171				camera2_rst: rst {
1172					pins = "gpio23";
1173					function = "gpio";
1174					drive-strength = <16>;
1175					bias-disable;
1176				};
1177
1178				pwdn {
1179					pins = "gpio133";
1180					function = "gpio";
1181					drive-strength = <16>;
1182					bias-disable;
1183				};
1184			};
1185
1186			pcie0_state_on: pcie0-state-on {
1187				perst {
1188					pins = "gpio35";
1189					function = "gpio";
1190					drive-strength = <2>;
1191					bias-pull-down;
1192				};
1193
1194				clkreq {
1195					pins = "gpio36";
1196					function = "pci_e0";
1197					drive-strength = <2>;
1198					bias-pull-up;
1199				};
1200
1201				wake {
1202					pins = "gpio37";
1203					function = "gpio";
1204					drive-strength = <2>;
1205					bias-pull-up;
1206				};
1207			};
1208
1209			pcie0_state_off: pcie0-state-off {
1210				perst {
1211					pins = "gpio35";
1212					function = "gpio";
1213					drive-strength = <2>;
1214					bias-pull-down;
1215				};
1216
1217				clkreq {
1218					pins = "gpio36";
1219					function = "gpio";
1220					drive-strength = <2>;
1221					bias-disable;
1222				};
1223
1224				wake {
1225					pins = "gpio37";
1226					function = "gpio";
1227					drive-strength = <2>;
1228					bias-disable;
1229				};
1230			};
1231
1232			blsp1_uart2_default: blsp1-uart2-default {
1233				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1234				function = "blsp_uart2";
1235				drive-strength = <16>;
1236				bias-disable;
1237			};
1238
1239			blsp1_uart2_sleep: blsp1-uart2-sleep {
1240				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1241				function = "gpio";
1242				drive-strength = <2>;
1243				bias-disable;
1244			};
1245
1246			blsp1_i2c3_default: blsp1-i2c2-default {
1247				pins = "gpio47", "gpio48";
1248				function = "blsp_i2c3";
1249				drive-strength = <16>;
1250				bias-disable = <0>;
1251			};
1252
1253			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1254				pins = "gpio47", "gpio48";
1255				function = "gpio";
1256				drive-strength = <2>;
1257				bias-disable = <0>;
1258			};
1259
1260			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1261				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1262				function = "blsp_uart9";
1263				drive-strength = <16>;
1264				bias-disable;
1265			};
1266
1267			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1268				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1269				function = "blsp_uart9";
1270				drive-strength = <2>;
1271				bias-disable;
1272			};
1273
1274			blsp2_i2c3_default: blsp2-i2c3 {
1275				pins = "gpio51", "gpio52";
1276				function = "blsp_i2c9";
1277				drive-strength = <16>;
1278				bias-disable;
1279			};
1280
1281			blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1282				pins = "gpio51", "gpio52";
1283				function = "gpio";
1284				drive-strength = <2>;
1285				bias-disable;
1286			};
1287
1288			wcd_intr_default: wcd-intr-default{
1289				pins = "gpio54";
1290				function = "gpio";
1291				drive-strength = <2>;
1292				bias-pull-down;
1293				input-enable;
1294			};
1295
1296			blsp2_i2c1_default: blsp2-i2c1 {
1297				pins = "gpio55", "gpio56";
1298				function = "blsp_i2c7";
1299				drive-strength = <16>;
1300				bias-disable;
1301			};
1302
1303			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1304				pins = "gpio55", "gpio56";
1305				function = "gpio";
1306				drive-strength = <2>;
1307				bias-disable;
1308			};
1309
1310			blsp2_i2c5_default: blsp2-i2c5 {
1311				pins = "gpio60", "gpio61";
1312				function = "blsp_i2c11";
1313				drive-strength = <2>;
1314				bias-disable;
1315			};
1316
1317			/* Sleep state for BLSP2_I2C5 is missing.. */
1318
1319			cdc_reset_active: cdc-reset-active {
1320				pins = "gpio64";
1321				function = "gpio";
1322				drive-strength = <16>;
1323				bias-pull-down;
1324				output-high;
1325			};
1326
1327			cdc_reset_sleep: cdc-reset-sleep {
1328				pins = "gpio64";
1329				function = "gpio";
1330				drive-strength = <16>;
1331				bias-disable;
1332				output-low;
1333			};
1334
1335			blsp2_spi6_default: blsp2-spi5-default {
1336				spi {
1337					pins = "gpio85", "gpio86", "gpio88";
1338					function = "blsp_spi12";
1339					drive-strength = <12>;
1340					bias-disable;
1341				};
1342
1343				cs {
1344					pins = "gpio87";
1345					function = "gpio";
1346					drive-strength = <16>;
1347					bias-disable;
1348					output-high;
1349				};
1350			};
1351
1352			blsp2_spi6_sleep: blsp2-spi5-sleep {
1353				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1354				function = "gpio";
1355				drive-strength = <2>;
1356				bias-pull-down;
1357			};
1358
1359			blsp2_i2c6_default: blsp2-i2c6 {
1360				pins = "gpio87", "gpio88";
1361				function = "blsp_i2c12";
1362				drive-strength = <16>;
1363				bias-disable;
1364			};
1365
1366			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1367				pins = "gpio87", "gpio88";
1368				function = "gpio";
1369				drive-strength = <2>;
1370				bias-disable;
1371			};
1372
1373			pcie1_state_on: pcie1-state-on {
1374				perst {
1375					pins = "gpio130";
1376					function = "gpio";
1377					drive-strength = <2>;
1378					bias-pull-down;
1379				};
1380
1381				clkreq {
1382					pins = "gpio131";
1383					function = "pci_e1";
1384					drive-strength = <2>;
1385					bias-pull-up;
1386				};
1387
1388				wake {
1389					pins = "gpio132";
1390					function = "gpio";
1391					drive-strength = <2>;
1392					bias-pull-down;
1393				};
1394			};
1395
1396			pcie1_state_off: pcie1-state-off {
1397				/* Perst is missing? */
1398				clkreq {
1399					pins = "gpio131";
1400					function = "gpio";
1401					drive-strength = <2>;
1402					bias-disable;
1403				};
1404
1405				wake {
1406					pins = "gpio132";
1407					function = "gpio";
1408					drive-strength = <2>;
1409					bias-disable;
1410				};
1411			};
1412
1413			pcie2_state_on: pcie2-state-on {
1414				perst {
1415					pins = "gpio114";
1416					function = "gpio";
1417					drive-strength = <2>;
1418					bias-pull-down;
1419				};
1420
1421				clkreq {
1422					pins = "gpio115";
1423					function = "pci_e2";
1424					drive-strength = <2>;
1425					bias-pull-up;
1426				};
1427
1428				wake {
1429					pins = "gpio116";
1430					function = "gpio";
1431					drive-strength = <2>;
1432					bias-pull-down;
1433				};
1434			};
1435
1436			pcie2_state_off: pcie2-state-off {
1437				/* Perst is missing? */
1438				clkreq {
1439					pins = "gpio115";
1440					function = "gpio";
1441					drive-strength = <2>;
1442					bias-disable;
1443				};
1444
1445				wake {
1446					pins = "gpio116";
1447					function = "gpio";
1448					drive-strength = <2>;
1449					bias-disable;
1450				};
1451			};
1452
1453			sdc1_state_on: sdc1-state-on {
1454				clk {
1455					pins = "sdc1_clk";
1456					bias-disable;
1457					drive-strength = <16>;
1458				};
1459
1460				cmd {
1461					pins = "sdc1_cmd";
1462					bias-pull-up;
1463					drive-strength = <10>;
1464				};
1465
1466				data {
1467					pins = "sdc1_data";
1468					bias-pull-up;
1469					drive-strength = <10>;
1470				};
1471
1472				rclk {
1473					pins = "sdc1_rclk";
1474					bias-pull-down;
1475				};
1476			};
1477
1478			sdc1_state_off: sdc1-state-off {
1479				clk {
1480					pins = "sdc1_clk";
1481					bias-disable;
1482					drive-strength = <2>;
1483				};
1484
1485				cmd {
1486					pins = "sdc1_cmd";
1487					bias-pull-up;
1488					drive-strength = <2>;
1489				};
1490
1491				data {
1492					pins = "sdc1_data";
1493					bias-pull-up;
1494					drive-strength = <2>;
1495				};
1496
1497				rclk {
1498					pins = "sdc1_rclk";
1499					bias-pull-down;
1500				};
1501			};
1502
1503			sdc2_state_on: sdc2-clk-on {
1504				clk {
1505					pins = "sdc2_clk";
1506					bias-disable;
1507					drive-strength = <16>;
1508				};
1509
1510				cmd {
1511					pins = "sdc2_cmd";
1512					bias-pull-up;
1513					drive-strength = <10>;
1514				};
1515
1516				data {
1517					pins = "sdc2_data";
1518					bias-pull-up;
1519					drive-strength = <10>;
1520				};
1521			};
1522
1523			sdc2_state_off: sdc2-clk-off {
1524				clk {
1525					pins = "sdc2_clk";
1526					bias-disable;
1527					drive-strength = <2>;
1528				};
1529
1530				cmd {
1531					pins = "sdc2_cmd";
1532					bias-pull-up;
1533					drive-strength = <2>;
1534				};
1535
1536				data {
1537					pins = "sdc2_data";
1538					bias-pull-up;
1539					drive-strength = <2>;
1540				};
1541			};
1542		};
1543
1544		sram@290000 {
1545			compatible = "qcom,rpm-stats";
1546			reg = <0x00290000 0x10000>;
1547		};
1548
1549		spmi_bus: qcom,spmi@400f000 {
1550			compatible = "qcom,spmi-pmic-arb";
1551			reg = <0x0400f000 0x1000>,
1552			      <0x04400000 0x800000>,
1553			      <0x04c00000 0x800000>,
1554			      <0x05800000 0x200000>,
1555			      <0x0400a000 0x002100>;
1556			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1557			interrupt-names = "periph_irq";
1558			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1559			qcom,ee = <0>;
1560			qcom,channel = <0>;
1561			#address-cells = <2>;
1562			#size-cells = <0>;
1563			interrupt-controller;
1564			#interrupt-cells = <4>;
1565		};
1566
1567		agnoc@0 {
1568			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1569			compatible = "simple-pm-bus";
1570			#address-cells = <1>;
1571			#size-cells = <1>;
1572			ranges;
1573
1574			pcie0: pcie@600000 {
1575				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1576				status = "disabled";
1577				power-domains = <&gcc PCIE0_GDSC>;
1578				bus-range = <0x00 0xff>;
1579				num-lanes = <1>;
1580
1581				reg = <0x00600000 0x2000>,
1582				      <0x0c000000 0xf1d>,
1583				      <0x0c000f20 0xa8>,
1584				      <0x0c100000 0x100000>;
1585				reg-names = "parf", "dbi", "elbi","config";
1586
1587				phys = <&pciephy_0>;
1588				phy-names = "pciephy";
1589
1590				#address-cells = <3>;
1591				#size-cells = <2>;
1592				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1593					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1594
1595				device_type = "pci";
1596
1597				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1598				interrupt-names = "msi";
1599				#interrupt-cells = <1>;
1600				interrupt-map-mask = <0 0 0 0x7>;
1601				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1602						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1603						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1604						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1605
1606				pinctrl-names = "default", "sleep";
1607				pinctrl-0 = <&pcie0_state_on>;
1608				pinctrl-1 = <&pcie0_state_off>;
1609
1610				linux,pci-domain = <0>;
1611
1612				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1613					<&gcc GCC_PCIE_0_AUX_CLK>,
1614					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1615					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1616					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1617
1618				clock-names =  "pipe",
1619						"aux",
1620						"cfg",
1621						"bus_master",
1622						"bus_slave";
1623
1624			};
1625
1626			pcie1: pcie@608000 {
1627				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1628				power-domains = <&gcc PCIE1_GDSC>;
1629				bus-range = <0x00 0xff>;
1630				num-lanes = <1>;
1631
1632				status  = "disabled";
1633
1634				reg = <0x00608000 0x2000>,
1635				      <0x0d000000 0xf1d>,
1636				      <0x0d000f20 0xa8>,
1637				      <0x0d100000 0x100000>;
1638
1639				reg-names = "parf", "dbi", "elbi","config";
1640
1641				phys = <&pciephy_1>;
1642				phy-names = "pciephy";
1643
1644				#address-cells = <3>;
1645				#size-cells = <2>;
1646				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1647					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1648
1649				device_type = "pci";
1650
1651				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1652				interrupt-names = "msi";
1653				#interrupt-cells = <1>;
1654				interrupt-map-mask = <0 0 0 0x7>;
1655				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1656						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1657						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1658						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1659
1660				pinctrl-names = "default", "sleep";
1661				pinctrl-0 = <&pcie1_state_on>;
1662				pinctrl-1 = <&pcie1_state_off>;
1663
1664				linux,pci-domain = <1>;
1665
1666				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1667					<&gcc GCC_PCIE_1_AUX_CLK>,
1668					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1669					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1670					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1671
1672				clock-names =  "pipe",
1673						"aux",
1674						"cfg",
1675						"bus_master",
1676						"bus_slave";
1677			};
1678
1679			pcie2: pcie@610000 {
1680				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1681				power-domains = <&gcc PCIE2_GDSC>;
1682				bus-range = <0x00 0xff>;
1683				num-lanes = <1>;
1684				status = "disabled";
1685				reg = <0x00610000 0x2000>,
1686				      <0x0e000000 0xf1d>,
1687				      <0x0e000f20 0xa8>,
1688				      <0x0e100000 0x100000>;
1689
1690				reg-names = "parf", "dbi", "elbi","config";
1691
1692				phys = <&pciephy_2>;
1693				phy-names = "pciephy";
1694
1695				#address-cells = <3>;
1696				#size-cells = <2>;
1697				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1698					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1699
1700				device_type = "pci";
1701
1702				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1703				interrupt-names = "msi";
1704				#interrupt-cells = <1>;
1705				interrupt-map-mask = <0 0 0 0x7>;
1706				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1707						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1708						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1709						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1710
1711				pinctrl-names = "default", "sleep";
1712				pinctrl-0 = <&pcie2_state_on>;
1713				pinctrl-1 = <&pcie2_state_off>;
1714
1715				linux,pci-domain = <2>;
1716				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1717					<&gcc GCC_PCIE_2_AUX_CLK>,
1718					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1719					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1720					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1721
1722				clock-names =  "pipe",
1723						"aux",
1724						"cfg",
1725						"bus_master",
1726						"bus_slave";
1727			};
1728		};
1729
1730		ufshc: ufshc@624000 {
1731			compatible = "qcom,ufshc";
1732			reg = <0x00624000 0x2500>;
1733			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1734
1735			phys = <&ufsphy_lane>;
1736			phy-names = "ufsphy";
1737
1738			power-domains = <&gcc UFS_GDSC>;
1739
1740			clock-names =
1741				"core_clk_src",
1742				"core_clk",
1743				"bus_clk",
1744				"bus_aggr_clk",
1745				"iface_clk",
1746				"core_clk_unipro_src",
1747				"core_clk_unipro",
1748				"core_clk_ice",
1749				"ref_clk",
1750				"tx_lane0_sync_clk",
1751				"rx_lane0_sync_clk";
1752			clocks =
1753				<&gcc UFS_AXI_CLK_SRC>,
1754				<&gcc GCC_UFS_AXI_CLK>,
1755				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1756				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1757				<&gcc GCC_UFS_AHB_CLK>,
1758				<&gcc UFS_ICE_CORE_CLK_SRC>,
1759				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1760				<&gcc GCC_UFS_ICE_CORE_CLK>,
1761				<&rpmcc RPM_SMD_LN_BB_CLK>,
1762				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1763				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1764			freq-table-hz =
1765				<100000000 200000000>,
1766				<0 0>,
1767				<0 0>,
1768				<0 0>,
1769				<0 0>,
1770				<150000000 300000000>,
1771				<0 0>,
1772				<0 0>,
1773				<0 0>,
1774				<0 0>,
1775				<0 0>;
1776
1777			lanes-per-direction = <1>;
1778			#reset-cells = <1>;
1779			status = "disabled";
1780
1781			ufs_variant {
1782				compatible = "qcom,ufs_variant";
1783			};
1784		};
1785
1786		ufsphy: phy@627000 {
1787			compatible = "qcom,msm8996-qmp-ufs-phy";
1788			reg = <0x00627000 0x1c4>;
1789			#address-cells = <1>;
1790			#size-cells = <1>;
1791			ranges;
1792
1793			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1794			clock-names = "ref";
1795
1796			resets = <&ufshc 0>;
1797			reset-names = "ufsphy";
1798			status = "disabled";
1799
1800			ufsphy_lane: phy@627400 {
1801				reg = <0x627400 0x12c>,
1802				      <0x627600 0x200>,
1803				      <0x627c00 0x1b4>;
1804				#phy-cells = <0>;
1805			};
1806		};
1807
1808		camss: camss@a00000 {
1809			compatible = "qcom,msm8996-camss";
1810			reg = <0x00a34000 0x1000>,
1811			      <0x00a00030 0x4>,
1812			      <0x00a35000 0x1000>,
1813			      <0x00a00038 0x4>,
1814			      <0x00a36000 0x1000>,
1815			      <0x00a00040 0x4>,
1816			      <0x00a30000 0x100>,
1817			      <0x00a30400 0x100>,
1818			      <0x00a30800 0x100>,
1819			      <0x00a30c00 0x100>,
1820			      <0x00a31000 0x500>,
1821			      <0x00a00020 0x10>,
1822			      <0x00a10000 0x1000>,
1823			      <0x00a14000 0x1000>;
1824			reg-names = "csiphy0",
1825				"csiphy0_clk_mux",
1826				"csiphy1",
1827				"csiphy1_clk_mux",
1828				"csiphy2",
1829				"csiphy2_clk_mux",
1830				"csid0",
1831				"csid1",
1832				"csid2",
1833				"csid3",
1834				"ispif",
1835				"csi_clk_mux",
1836				"vfe0",
1837				"vfe1";
1838			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1839				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1840				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1841				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1842				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1843				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1844				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1845				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1846				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1847				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1848			interrupt-names = "csiphy0",
1849				"csiphy1",
1850				"csiphy2",
1851				"csid0",
1852				"csid1",
1853				"csid2",
1854				"csid3",
1855				"ispif",
1856				"vfe0",
1857				"vfe1";
1858			power-domains = <&mmcc VFE0_GDSC>,
1859					<&mmcc VFE1_GDSC>;
1860			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1861				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1862				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1863				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1864				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1865				<&mmcc CAMSS_CSI0_AHB_CLK>,
1866				<&mmcc CAMSS_CSI0_CLK>,
1867				<&mmcc CAMSS_CSI0PHY_CLK>,
1868				<&mmcc CAMSS_CSI0PIX_CLK>,
1869				<&mmcc CAMSS_CSI0RDI_CLK>,
1870				<&mmcc CAMSS_CSI1_AHB_CLK>,
1871				<&mmcc CAMSS_CSI1_CLK>,
1872				<&mmcc CAMSS_CSI1PHY_CLK>,
1873				<&mmcc CAMSS_CSI1PIX_CLK>,
1874				<&mmcc CAMSS_CSI1RDI_CLK>,
1875				<&mmcc CAMSS_CSI2_AHB_CLK>,
1876				<&mmcc CAMSS_CSI2_CLK>,
1877				<&mmcc CAMSS_CSI2PHY_CLK>,
1878				<&mmcc CAMSS_CSI2PIX_CLK>,
1879				<&mmcc CAMSS_CSI2RDI_CLK>,
1880				<&mmcc CAMSS_CSI3_AHB_CLK>,
1881				<&mmcc CAMSS_CSI3_CLK>,
1882				<&mmcc CAMSS_CSI3PHY_CLK>,
1883				<&mmcc CAMSS_CSI3PIX_CLK>,
1884				<&mmcc CAMSS_CSI3RDI_CLK>,
1885				<&mmcc CAMSS_AHB_CLK>,
1886				<&mmcc CAMSS_VFE0_CLK>,
1887				<&mmcc CAMSS_CSI_VFE0_CLK>,
1888				<&mmcc CAMSS_VFE0_AHB_CLK>,
1889				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1890				<&mmcc CAMSS_VFE1_CLK>,
1891				<&mmcc CAMSS_CSI_VFE1_CLK>,
1892				<&mmcc CAMSS_VFE1_AHB_CLK>,
1893				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1894				<&mmcc CAMSS_VFE_AHB_CLK>,
1895				<&mmcc CAMSS_VFE_AXI_CLK>;
1896			clock-names = "top_ahb",
1897				"ispif_ahb",
1898				"csiphy0_timer",
1899				"csiphy1_timer",
1900				"csiphy2_timer",
1901				"csi0_ahb",
1902				"csi0",
1903				"csi0_phy",
1904				"csi0_pix",
1905				"csi0_rdi",
1906				"csi1_ahb",
1907				"csi1",
1908				"csi1_phy",
1909				"csi1_pix",
1910				"csi1_rdi",
1911				"csi2_ahb",
1912				"csi2",
1913				"csi2_phy",
1914				"csi2_pix",
1915				"csi2_rdi",
1916				"csi3_ahb",
1917				"csi3",
1918				"csi3_phy",
1919				"csi3_pix",
1920				"csi3_rdi",
1921				"ahb",
1922				"vfe0",
1923				"csi_vfe0",
1924				"vfe0_ahb",
1925				"vfe0_stream",
1926				"vfe1",
1927				"csi_vfe1",
1928				"vfe1_ahb",
1929				"vfe1_stream",
1930				"vfe_ahb",
1931				"vfe_axi";
1932			iommus = <&vfe_smmu 0>,
1933				 <&vfe_smmu 1>,
1934				 <&vfe_smmu 2>,
1935				 <&vfe_smmu 3>;
1936			status = "disabled";
1937			ports {
1938				#address-cells = <1>;
1939				#size-cells = <0>;
1940			};
1941		};
1942
1943		cci: cci@a0c000 {
1944			compatible = "qcom,msm8996-cci";
1945			#address-cells = <1>;
1946			#size-cells = <0>;
1947			reg = <0xa0c000 0x1000>;
1948			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1949			power-domains = <&mmcc CAMSS_GDSC>;
1950			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1951				 <&mmcc CAMSS_CCI_AHB_CLK>,
1952				 <&mmcc CAMSS_CCI_CLK>,
1953				 <&mmcc CAMSS_AHB_CLK>;
1954			clock-names = "camss_top_ahb",
1955				      "cci_ahb",
1956				      "cci",
1957				      "camss_ahb";
1958			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1959					  <&mmcc CAMSS_CCI_CLK>;
1960			assigned-clock-rates = <80000000>, <37500000>;
1961			pinctrl-names = "default";
1962			pinctrl-0 = <&cci0_default &cci1_default>;
1963			status = "disabled";
1964
1965			cci_i2c0: i2c-bus@0 {
1966				reg = <0>;
1967				clock-frequency = <400000>;
1968				#address-cells = <1>;
1969				#size-cells = <0>;
1970			};
1971
1972			cci_i2c1: i2c-bus@1 {
1973				reg = <1>;
1974				clock-frequency = <400000>;
1975				#address-cells = <1>;
1976				#size-cells = <0>;
1977			};
1978		};
1979
1980		adreno_smmu: iommu@b40000 {
1981			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1982			reg = <0x00b40000 0x10000>;
1983
1984			#global-interrupts = <1>;
1985			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1986				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1987				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1988			#iommu-cells = <1>;
1989
1990			clocks = <&mmcc GPU_AHB_CLK>,
1991				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1992			clock-names = "iface", "bus";
1993
1994			power-domains = <&mmcc GPU_GDSC>;
1995		};
1996
1997		venus: video-codec@c00000 {
1998			compatible = "qcom,msm8996-venus";
1999			reg = <0x00c00000 0xff000>;
2000			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2001			power-domains = <&mmcc VENUS_GDSC>;
2002			clocks = <&mmcc VIDEO_CORE_CLK>,
2003				 <&mmcc VIDEO_AHB_CLK>,
2004				 <&mmcc VIDEO_AXI_CLK>,
2005				 <&mmcc VIDEO_MAXI_CLK>;
2006			clock-names = "core", "iface", "bus", "mbus";
2007			iommus = <&venus_smmu 0x00>,
2008				 <&venus_smmu 0x01>,
2009				 <&venus_smmu 0x0a>,
2010				 <&venus_smmu 0x07>,
2011				 <&venus_smmu 0x0e>,
2012				 <&venus_smmu 0x0f>,
2013				 <&venus_smmu 0x08>,
2014				 <&venus_smmu 0x09>,
2015				 <&venus_smmu 0x0b>,
2016				 <&venus_smmu 0x0c>,
2017				 <&venus_smmu 0x0d>,
2018				 <&venus_smmu 0x10>,
2019				 <&venus_smmu 0x11>,
2020				 <&venus_smmu 0x21>,
2021				 <&venus_smmu 0x28>,
2022				 <&venus_smmu 0x29>,
2023				 <&venus_smmu 0x2b>,
2024				 <&venus_smmu 0x2c>,
2025				 <&venus_smmu 0x2d>,
2026				 <&venus_smmu 0x31>;
2027			memory-region = <&venus_region>;
2028			status = "disabled";
2029
2030			video-decoder {
2031				compatible = "venus-decoder";
2032				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2033				clock-names = "core";
2034				power-domains = <&mmcc VENUS_CORE0_GDSC>;
2035			};
2036
2037			video-encoder {
2038				compatible = "venus-encoder";
2039				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2040				clock-names = "core";
2041				power-domains = <&mmcc VENUS_CORE1_GDSC>;
2042			};
2043		};
2044
2045		mdp_smmu: iommu@d00000 {
2046			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2047			reg = <0x00d00000 0x10000>;
2048
2049			#global-interrupts = <1>;
2050			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2051				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2052				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2053			#iommu-cells = <1>;
2054			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2055				 <&mmcc SMMU_MDP_AXI_CLK>;
2056			clock-names = "iface", "bus";
2057
2058			power-domains = <&mmcc MDSS_GDSC>;
2059		};
2060
2061		venus_smmu: iommu@d40000 {
2062			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2063			reg = <0x00d40000 0x20000>;
2064			#global-interrupts = <1>;
2065			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2066				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2067				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2068				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2069				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2070				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2071				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2072				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2073			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2074			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2075				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2076			clock-names = "iface", "bus";
2077			#iommu-cells = <1>;
2078			status = "okay";
2079		};
2080
2081		vfe_smmu: iommu@da0000 {
2082			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2083			reg = <0x00da0000 0x10000>;
2084
2085			#global-interrupts = <1>;
2086			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2087				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2088				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2089			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2090			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2091				 <&mmcc SMMU_VFE_AXI_CLK>;
2092			clock-names = "iface",
2093				      "bus";
2094			#iommu-cells = <1>;
2095		};
2096
2097		lpass_q6_smmu: iommu@1600000 {
2098			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2099			reg = <0x01600000 0x20000>;
2100			#iommu-cells = <1>;
2101			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2102
2103			#global-interrupts = <1>;
2104			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2105		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2106		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2107		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2108		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2109		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2110		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2111		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2112		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2113		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2114		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2115		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2116		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2117
2118			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2119				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2120			clock-names = "iface", "bus";
2121		};
2122
2123		stm@3002000 {
2124			compatible = "arm,coresight-stm", "arm,primecell";
2125			reg = <0x3002000 0x1000>,
2126			      <0x8280000 0x180000>;
2127			reg-names = "stm-base", "stm-stimulus-base";
2128
2129			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2130			clock-names = "apb_pclk", "atclk";
2131
2132			out-ports {
2133				port {
2134					stm_out: endpoint {
2135						remote-endpoint =
2136						  <&funnel0_in>;
2137					};
2138				};
2139			};
2140		};
2141
2142		tpiu@3020000 {
2143			compatible = "arm,coresight-tpiu", "arm,primecell";
2144			reg = <0x3020000 0x1000>;
2145
2146			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2147			clock-names = "apb_pclk", "atclk";
2148
2149			in-ports {
2150				port {
2151					tpiu_in: endpoint {
2152						remote-endpoint =
2153						  <&replicator_out1>;
2154					};
2155				};
2156			};
2157		};
2158
2159		funnel@3021000 {
2160			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2161			reg = <0x3021000 0x1000>;
2162
2163			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2164			clock-names = "apb_pclk", "atclk";
2165
2166			in-ports {
2167				#address-cells = <1>;
2168				#size-cells = <0>;
2169
2170				port@7 {
2171					reg = <7>;
2172					funnel0_in: endpoint {
2173						remote-endpoint =
2174						  <&stm_out>;
2175					};
2176				};
2177			};
2178
2179			out-ports {
2180				port {
2181					funnel0_out: endpoint {
2182						remote-endpoint =
2183						  <&merge_funnel_in0>;
2184					};
2185				};
2186			};
2187		};
2188
2189		funnel@3022000 {
2190			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2191			reg = <0x3022000 0x1000>;
2192
2193			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2194			clock-names = "apb_pclk", "atclk";
2195
2196			in-ports {
2197				#address-cells = <1>;
2198				#size-cells = <0>;
2199
2200				port@6 {
2201					reg = <6>;
2202					funnel1_in: endpoint {
2203						remote-endpoint =
2204						  <&apss_merge_funnel_out>;
2205					};
2206				};
2207			};
2208
2209			out-ports {
2210				port {
2211					funnel1_out: endpoint {
2212						remote-endpoint =
2213						  <&merge_funnel_in1>;
2214					};
2215				};
2216			};
2217		};
2218
2219		funnel@3023000 {
2220			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2221			reg = <0x3023000 0x1000>;
2222
2223			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2224			clock-names = "apb_pclk", "atclk";
2225
2226
2227			out-ports {
2228				port {
2229					funnel2_out: endpoint {
2230						remote-endpoint =
2231						  <&merge_funnel_in2>;
2232					};
2233				};
2234			};
2235		};
2236
2237		funnel@3025000 {
2238			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2239			reg = <0x3025000 0x1000>;
2240
2241			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2242			clock-names = "apb_pclk", "atclk";
2243
2244			in-ports {
2245				#address-cells = <1>;
2246				#size-cells = <0>;
2247
2248				port@0 {
2249					reg = <0>;
2250					merge_funnel_in0: endpoint {
2251						remote-endpoint =
2252						  <&funnel0_out>;
2253					};
2254				};
2255
2256				port@1 {
2257					reg = <1>;
2258					merge_funnel_in1: endpoint {
2259						remote-endpoint =
2260						  <&funnel1_out>;
2261					};
2262				};
2263
2264				port@2 {
2265					reg = <2>;
2266					merge_funnel_in2: endpoint {
2267						remote-endpoint =
2268						  <&funnel2_out>;
2269					};
2270				};
2271			};
2272
2273			out-ports {
2274				port {
2275					merge_funnel_out: endpoint {
2276						remote-endpoint =
2277						  <&etf_in>;
2278					};
2279				};
2280			};
2281		};
2282
2283		replicator@3026000 {
2284			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2285			reg = <0x3026000 0x1000>;
2286
2287			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2288			clock-names = "apb_pclk", "atclk";
2289
2290			in-ports {
2291				port {
2292					replicator_in: endpoint {
2293						remote-endpoint =
2294						  <&etf_out>;
2295					};
2296				};
2297			};
2298
2299			out-ports {
2300				#address-cells = <1>;
2301				#size-cells = <0>;
2302
2303				port@0 {
2304					reg = <0>;
2305					replicator_out0: endpoint {
2306						remote-endpoint =
2307						  <&etr_in>;
2308					};
2309				};
2310
2311				port@1 {
2312					reg = <1>;
2313					replicator_out1: endpoint {
2314						remote-endpoint =
2315						  <&tpiu_in>;
2316					};
2317				};
2318			};
2319		};
2320
2321		etf@3027000 {
2322			compatible = "arm,coresight-tmc", "arm,primecell";
2323			reg = <0x3027000 0x1000>;
2324
2325			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2326			clock-names = "apb_pclk", "atclk";
2327
2328			in-ports {
2329				port {
2330					etf_in: endpoint {
2331						remote-endpoint =
2332						  <&merge_funnel_out>;
2333					};
2334				};
2335			};
2336
2337			out-ports {
2338				port {
2339					etf_out: endpoint {
2340						remote-endpoint =
2341						  <&replicator_in>;
2342					};
2343				};
2344			};
2345		};
2346
2347		etr@3028000 {
2348			compatible = "arm,coresight-tmc", "arm,primecell";
2349			reg = <0x3028000 0x1000>;
2350
2351			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2352			clock-names = "apb_pclk", "atclk";
2353			arm,scatter-gather;
2354
2355			in-ports {
2356				port {
2357					etr_in: endpoint {
2358						remote-endpoint =
2359						  <&replicator_out0>;
2360					};
2361				};
2362			};
2363		};
2364
2365		debug@3810000 {
2366			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2367			reg = <0x3810000 0x1000>;
2368
2369			clocks = <&rpmcc RPM_QDSS_CLK>;
2370			clock-names = "apb_pclk";
2371
2372			cpu = <&CPU0>;
2373		};
2374
2375		etm@3840000 {
2376			compatible = "arm,coresight-etm4x", "arm,primecell";
2377			reg = <0x3840000 0x1000>;
2378
2379			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2380			clock-names = "apb_pclk", "atclk";
2381
2382			cpu = <&CPU0>;
2383
2384			out-ports {
2385				port {
2386					etm0_out: endpoint {
2387						remote-endpoint =
2388						  <&apss_funnel0_in0>;
2389					};
2390				};
2391			};
2392		};
2393
2394		debug@3910000 {
2395			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2396			reg = <0x3910000 0x1000>;
2397
2398			clocks = <&rpmcc RPM_QDSS_CLK>;
2399			clock-names = "apb_pclk";
2400
2401			cpu = <&CPU1>;
2402		};
2403
2404		etm@3940000 {
2405			compatible = "arm,coresight-etm4x", "arm,primecell";
2406			reg = <0x3940000 0x1000>;
2407
2408			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2409			clock-names = "apb_pclk", "atclk";
2410
2411			cpu = <&CPU1>;
2412
2413			out-ports {
2414				port {
2415					etm1_out: endpoint {
2416						remote-endpoint =
2417						  <&apss_funnel0_in1>;
2418					};
2419				};
2420			};
2421		};
2422
2423		funnel@39b0000 { /* APSS Funnel 0 */
2424			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2425			reg = <0x39b0000 0x1000>;
2426
2427			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2428			clock-names = "apb_pclk", "atclk";
2429
2430			in-ports {
2431				#address-cells = <1>;
2432				#size-cells = <0>;
2433
2434				port@0 {
2435					reg = <0>;
2436					apss_funnel0_in0: endpoint {
2437						remote-endpoint = <&etm0_out>;
2438					};
2439				};
2440
2441				port@1 {
2442					reg = <1>;
2443					apss_funnel0_in1: endpoint {
2444						remote-endpoint = <&etm1_out>;
2445					};
2446				};
2447			};
2448
2449			out-ports {
2450				port {
2451					apss_funnel0_out: endpoint {
2452						remote-endpoint =
2453						  <&apss_merge_funnel_in0>;
2454					};
2455				};
2456			};
2457		};
2458
2459		debug@3a10000 {
2460			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2461			reg = <0x3a10000 0x1000>;
2462
2463			clocks = <&rpmcc RPM_QDSS_CLK>;
2464			clock-names = "apb_pclk";
2465
2466			cpu = <&CPU2>;
2467		};
2468
2469		etm@3a40000 {
2470			compatible = "arm,coresight-etm4x", "arm,primecell";
2471			reg = <0x3a40000 0x1000>;
2472
2473			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2474			clock-names = "apb_pclk", "atclk";
2475
2476			cpu = <&CPU2>;
2477
2478			out-ports {
2479				port {
2480					etm2_out: endpoint {
2481						remote-endpoint =
2482						  <&apss_funnel1_in0>;
2483					};
2484				};
2485			};
2486		};
2487
2488		debug@3b10000 {
2489			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2490			reg = <0x3b10000 0x1000>;
2491
2492			clocks = <&rpmcc RPM_QDSS_CLK>;
2493			clock-names = "apb_pclk";
2494
2495			cpu = <&CPU3>;
2496		};
2497
2498		etm@3b40000 {
2499			compatible = "arm,coresight-etm4x", "arm,primecell";
2500			reg = <0x3b40000 0x1000>;
2501
2502			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2503			clock-names = "apb_pclk", "atclk";
2504
2505			cpu = <&CPU3>;
2506
2507			out-ports {
2508				port {
2509					etm3_out: endpoint {
2510						remote-endpoint =
2511						  <&apss_funnel1_in1>;
2512					};
2513				};
2514			};
2515		};
2516
2517		funnel@3bb0000 { /* APSS Funnel 1 */
2518			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2519			reg = <0x3bb0000 0x1000>;
2520
2521			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2522			clock-names = "apb_pclk", "atclk";
2523
2524			in-ports {
2525				#address-cells = <1>;
2526				#size-cells = <0>;
2527
2528				port@0 {
2529					reg = <0>;
2530					apss_funnel1_in0: endpoint {
2531						remote-endpoint = <&etm2_out>;
2532					};
2533				};
2534
2535				port@1 {
2536					reg = <1>;
2537					apss_funnel1_in1: endpoint {
2538						remote-endpoint = <&etm3_out>;
2539					};
2540				};
2541			};
2542
2543			out-ports {
2544				port {
2545					apss_funnel1_out: endpoint {
2546						remote-endpoint =
2547						  <&apss_merge_funnel_in1>;
2548					};
2549				};
2550			};
2551		};
2552
2553		funnel@3bc0000 {
2554			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2555			reg = <0x3bc0000 0x1000>;
2556
2557			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2558			clock-names = "apb_pclk", "atclk";
2559
2560			in-ports {
2561				#address-cells = <1>;
2562				#size-cells = <0>;
2563
2564				port@0 {
2565					reg = <0>;
2566					apss_merge_funnel_in0: endpoint {
2567						remote-endpoint =
2568						  <&apss_funnel0_out>;
2569					};
2570				};
2571
2572				port@1 {
2573					reg = <1>;
2574					apss_merge_funnel_in1: endpoint {
2575						remote-endpoint =
2576						  <&apss_funnel1_out>;
2577					};
2578				};
2579			};
2580
2581			out-ports {
2582				port {
2583					apss_merge_funnel_out: endpoint {
2584						remote-endpoint =
2585						  <&funnel1_in>;
2586					};
2587				};
2588			};
2589		};
2590
2591		kryocc: clock-controller@6400000 {
2592			compatible = "qcom,msm8996-apcc";
2593			reg = <0x06400000 0x90000>;
2594
2595			clock-names = "xo";
2596			clocks = <&xo_board>;
2597
2598			#clock-cells = <1>;
2599		};
2600
2601		usb3: usb@6af8800 {
2602			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2603			reg = <0x06af8800 0x400>;
2604			#address-cells = <1>;
2605			#size-cells = <1>;
2606			ranges;
2607
2608			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2609				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2610			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2611
2612			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2613				<&gcc GCC_USB30_MASTER_CLK>,
2614				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2615				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2616				<&gcc GCC_USB30_SLEEP_CLK>,
2617				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2618
2619			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2620					  <&gcc GCC_USB30_MASTER_CLK>;
2621			assigned-clock-rates = <19200000>, <120000000>;
2622
2623			power-domains = <&gcc USB30_GDSC>;
2624			status = "disabled";
2625
2626			usb3_dwc3: dwc3@6a00000 {
2627				compatible = "snps,dwc3";
2628				reg = <0x06a00000 0xcc00>;
2629				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2630				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2631				phy-names = "usb2-phy", "usb3-phy";
2632				snps,dis_u2_susphy_quirk;
2633				snps,dis_enblslpm_quirk;
2634			};
2635		};
2636
2637		usb3phy: phy@7410000 {
2638			compatible = "qcom,msm8996-qmp-usb3-phy";
2639			reg = <0x07410000 0x1c4>;
2640			#address-cells = <1>;
2641			#size-cells = <1>;
2642			ranges;
2643
2644			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2645				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2646				<&gcc GCC_USB3_CLKREF_CLK>;
2647			clock-names = "aux", "cfg_ahb", "ref";
2648
2649			resets = <&gcc GCC_USB3_PHY_BCR>,
2650				<&gcc GCC_USB3PHY_PHY_BCR>;
2651			reset-names = "phy", "common";
2652			status = "disabled";
2653
2654			ssusb_phy_0: phy@7410200 {
2655				reg = <0x07410200 0x200>,
2656				      <0x07410400 0x130>,
2657				      <0x07410600 0x1a8>;
2658				#phy-cells = <0>;
2659
2660				#clock-cells = <1>;
2661				clock-output-names = "usb3_phy_pipe_clk_src";
2662				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2663				clock-names = "pipe0";
2664			};
2665		};
2666
2667		hsusb_phy1: phy@7411000 {
2668			compatible = "qcom,msm8996-qusb2-phy";
2669			reg = <0x07411000 0x180>;
2670			#phy-cells = <0>;
2671
2672			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2673				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2674			clock-names = "cfg_ahb", "ref";
2675
2676			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2677			nvmem-cells = <&qusb2p_hstx_trim>;
2678			status = "disabled";
2679		};
2680
2681		hsusb_phy2: phy@7412000 {
2682			compatible = "qcom,msm8996-qusb2-phy";
2683			reg = <0x07412000 0x180>;
2684			#phy-cells = <0>;
2685
2686			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2687				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2688			clock-names = "cfg_ahb", "ref";
2689
2690			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2691			nvmem-cells = <&qusb2s_hstx_trim>;
2692			status = "disabled";
2693		};
2694
2695		sdhc1: sdhci@7464900 {
2696			compatible = "qcom,sdhci-msm-v4";
2697			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2698			reg-names = "hc_mem", "core_mem";
2699
2700			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2701					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2702			interrupt-names = "hc_irq", "pwr_irq";
2703
2704			clock-names = "iface", "core", "xo";
2705			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2706				<&gcc GCC_SDCC1_APPS_CLK>,
2707				<&xo_board>;
2708
2709			pinctrl-names = "default", "sleep";
2710			pinctrl-0 = <&sdc1_state_on>;
2711			pinctrl-1 = <&sdc1_state_off>;
2712
2713			bus-width = <8>;
2714			non-removable;
2715			status = "disabled";
2716		};
2717
2718		sdhc2: sdhci@74a4900 {
2719			compatible = "qcom,sdhci-msm-v4";
2720			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2721			reg-names = "hc_mem", "core_mem";
2722
2723			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2724				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2725			interrupt-names = "hc_irq", "pwr_irq";
2726
2727			clock-names = "iface", "core", "xo";
2728			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2729				<&gcc GCC_SDCC2_APPS_CLK>,
2730				<&xo_board>;
2731
2732			pinctrl-names = "default", "sleep";
2733			pinctrl-0 = <&sdc2_state_on>;
2734			pinctrl-1 = <&sdc2_state_off>;
2735
2736			bus-width = <4>;
2737			status = "disabled";
2738		 };
2739
2740		blsp1_dma: dma-controller@7544000 {
2741			compatible = "qcom,bam-v1.7.0";
2742			reg = <0x07544000 0x2b000>;
2743			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2744			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2745			clock-names = "bam_clk";
2746			qcom,controlled-remotely;
2747			#dma-cells = <1>;
2748			qcom,ee = <0>;
2749		};
2750
2751		blsp1_uart2: serial@7570000 {
2752			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2753			reg = <0x07570000 0x1000>;
2754			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2755			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2756				 <&gcc GCC_BLSP1_AHB_CLK>;
2757			clock-names = "core", "iface";
2758			pinctrl-names = "default", "sleep";
2759			pinctrl-0 = <&blsp1_uart2_default>;
2760			pinctrl-1 = <&blsp1_uart2_sleep>;
2761			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2762			dma-names = "tx", "rx";
2763			status = "disabled";
2764		};
2765
2766		blsp1_spi1: spi@7575000 {
2767			compatible = "qcom,spi-qup-v2.2.1";
2768			reg = <0x07575000 0x600>;
2769			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2770			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2771				 <&gcc GCC_BLSP1_AHB_CLK>;
2772			clock-names = "core", "iface";
2773			pinctrl-names = "default", "sleep";
2774			pinctrl-0 = <&blsp1_spi1_default>;
2775			pinctrl-1 = <&blsp1_spi1_sleep>;
2776			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2777			dma-names = "tx", "rx";
2778			#address-cells = <1>;
2779			#size-cells = <0>;
2780			status = "disabled";
2781		};
2782
2783		blsp1_i2c3: i2c@7577000 {
2784			compatible = "qcom,i2c-qup-v2.2.1";
2785			reg = <0x07577000 0x1000>;
2786			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2787			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2788				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2789			clock-names = "iface", "core";
2790			pinctrl-names = "default", "sleep";
2791			pinctrl-0 = <&blsp1_i2c3_default>;
2792			pinctrl-1 = <&blsp1_i2c3_sleep>;
2793			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2794			dma-names = "tx", "rx";
2795			#address-cells = <1>;
2796			#size-cells = <0>;
2797			status = "disabled";
2798		};
2799
2800		blsp2_dma: dma-controller@7584000 {
2801			compatible = "qcom,bam-v1.7.0";
2802			reg = <0x07584000 0x2b000>;
2803			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2804			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2805			clock-names = "bam_clk";
2806			qcom,controlled-remotely;
2807			#dma-cells = <1>;
2808			qcom,ee = <0>;
2809		};
2810
2811		blsp2_uart2: serial@75b0000 {
2812			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2813			reg = <0x075b0000 0x1000>;
2814			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2815			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2816				 <&gcc GCC_BLSP2_AHB_CLK>;
2817			clock-names = "core", "iface";
2818			status = "disabled";
2819		};
2820
2821		blsp2_uart3: serial@75b1000 {
2822			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2823			reg = <0x075b1000 0x1000>;
2824			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2825			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2826				 <&gcc GCC_BLSP2_AHB_CLK>;
2827			clock-names = "core", "iface";
2828			status = "disabled";
2829		};
2830
2831		blsp2_i2c1: i2c@75b5000 {
2832			compatible = "qcom,i2c-qup-v2.2.1";
2833			reg = <0x075b5000 0x1000>;
2834			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2835			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2836				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2837			clock-names = "iface", "core";
2838			pinctrl-names = "default", "sleep";
2839			pinctrl-0 = <&blsp2_i2c1_default>;
2840			pinctrl-1 = <&blsp2_i2c1_sleep>;
2841			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2842			dma-names = "tx", "rx";
2843			#address-cells = <1>;
2844			#size-cells = <0>;
2845			status = "disabled";
2846		};
2847
2848		blsp2_i2c2: i2c@75b6000 {
2849			compatible = "qcom,i2c-qup-v2.2.1";
2850			reg = <0x075b6000 0x1000>;
2851			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2852			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2853				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2854			clock-names = "iface", "core";
2855			pinctrl-names = "default", "sleep";
2856			pinctrl-0 = <&blsp2_i2c2_default>;
2857			pinctrl-1 = <&blsp2_i2c2_sleep>;
2858			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2859			dma-names = "tx", "rx";
2860			#address-cells = <1>;
2861			#size-cells = <0>;
2862			status = "disabled";
2863		};
2864
2865		blsp2_i2c3: i2c@75b7000 {
2866			compatible = "qcom,i2c-qup-v2.2.1";
2867			reg = <0x075b7000 0x1000>;
2868			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2869			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2870				<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
2871			clock-names = "iface", "core";
2872			clock-frequency = <400000>;
2873			pinctrl-names = "default", "sleep";
2874			pinctrl-0 = <&blsp2_i2c3_default>;
2875			pinctrl-1 = <&blsp2_i2c3_sleep>;
2876			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2877			dma-names = "tx", "rx";
2878			#address-cells = <1>;
2879			#size-cells = <0>;
2880			status = "disabled";
2881		};
2882
2883		blsp2_i2c5: i2c@75b9000 {
2884			compatible = "qcom,i2c-qup-v2.2.1";
2885			reg = <0x75b9000 0x1000>;
2886			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2887			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2888				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2889			clock-names = "iface", "core";
2890			pinctrl-names = "default";
2891			pinctrl-0 = <&blsp2_i2c5_default>;
2892			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2893			dma-names = "tx", "rx";
2894			#address-cells = <1>;
2895			#size-cells = <0>;
2896			status = "disabled";
2897		};
2898
2899		blsp2_i2c6: i2c@75ba000 {
2900			compatible = "qcom,i2c-qup-v2.2.1";
2901			reg = <0x75ba000 0x1000>;
2902			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2903			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2904				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2905			clock-names = "iface", "core";
2906			pinctrl-names = "default", "sleep";
2907			pinctrl-0 = <&blsp2_i2c6_default>;
2908			pinctrl-1 = <&blsp2_i2c6_sleep>;
2909			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2910			dma-names = "tx", "rx";
2911			#address-cells = <1>;
2912			#size-cells = <0>;
2913			status = "disabled";
2914		};
2915
2916		blsp2_spi6: spi@75ba000{
2917			compatible = "qcom,spi-qup-v2.2.1";
2918			reg = <0x075ba000 0x600>;
2919			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2920			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2921				 <&gcc GCC_BLSP2_AHB_CLK>;
2922			clock-names = "core", "iface";
2923			pinctrl-names = "default", "sleep";
2924			pinctrl-0 = <&blsp2_spi6_default>;
2925			pinctrl-1 = <&blsp2_spi6_sleep>;
2926			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2927			dma-names = "tx", "rx";
2928			#address-cells = <1>;
2929			#size-cells = <0>;
2930			status = "disabled";
2931		};
2932
2933		usb2: usb@76f8800 {
2934			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2935			reg = <0x076f8800 0x400>;
2936			#address-cells = <1>;
2937			#size-cells = <1>;
2938			ranges;
2939
2940			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2941				<&gcc GCC_USB20_MASTER_CLK>,
2942				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2943				<&gcc GCC_USB20_SLEEP_CLK>,
2944				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2945
2946			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2947					  <&gcc GCC_USB20_MASTER_CLK>;
2948			assigned-clock-rates = <19200000>, <60000000>;
2949
2950			power-domains = <&gcc USB30_GDSC>;
2951			qcom,select-utmi-as-pipe-clk;
2952			status = "disabled";
2953
2954			dwc3@7600000 {
2955				compatible = "snps,dwc3";
2956				reg = <0x07600000 0xcc00>;
2957				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2958				phys = <&hsusb_phy2>;
2959				phy-names = "usb2-phy";
2960				maximum-speed = "high-speed";
2961				snps,dis_u2_susphy_quirk;
2962				snps,dis_enblslpm_quirk;
2963			};
2964		};
2965
2966		slimbam: dma-controller@9184000 {
2967			compatible = "qcom,bam-v1.7.0";
2968			qcom,controlled-remotely;
2969			reg = <0x09184000 0x32000>;
2970			num-channels  = <31>;
2971			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2972			#dma-cells = <1>;
2973			qcom,ee = <1>;
2974			qcom,num-ees = <2>;
2975		};
2976
2977		slim_msm: slim@91c0000 {
2978			compatible = "qcom,slim-ngd-v1.5.0";
2979			reg = <0x091c0000 0x2C000>;
2980			reg-names = "ctrl";
2981			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2982			dmas =	<&slimbam 3>, <&slimbam 4>,
2983				<&slimbam 5>, <&slimbam 6>;
2984			dma-names = "rx", "tx", "tx2", "rx2";
2985			#address-cells = <1>;
2986			#size-cells = <0>;
2987			ngd@1 {
2988				reg = <1>;
2989				#address-cells = <1>;
2990				#size-cells = <1>;
2991
2992				tasha_ifd: tas-ifd {
2993					compatible = "slim217,1a0";
2994					reg  = <0 0>;
2995				};
2996
2997				wcd9335: codec@1{
2998					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2999					pinctrl-names = "default";
3000
3001					compatible = "slim217,1a0";
3002					reg  = <1 0>;
3003
3004					interrupt-parent = <&tlmm>;
3005					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3006						     <53 IRQ_TYPE_LEVEL_HIGH>;
3007					interrupt-names  = "intr1", "intr2";
3008					interrupt-controller;
3009					#interrupt-cells = <1>;
3010					reset-gpios = <&tlmm 64 0>;
3011
3012					slim-ifc-dev  = <&tasha_ifd>;
3013
3014					#sound-dai-cells = <1>;
3015				};
3016			};
3017		};
3018
3019		adsp_pil: remoteproc@9300000 {
3020			compatible = "qcom,msm8996-adsp-pil";
3021			reg = <0x09300000 0x80000>;
3022
3023			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3024					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3025					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3026					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3027					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3028			interrupt-names = "wdog", "fatal", "ready",
3029					  "handover", "stop-ack";
3030
3031			clocks = <&xo_board>;
3032			clock-names = "xo";
3033
3034			memory-region = <&adsp_region>;
3035
3036			qcom,smem-states = <&smp2p_adsp_out 0>;
3037			qcom,smem-state-names = "stop";
3038
3039			power-domains = <&rpmpd MSM8996_VDDCX>;
3040			power-domain-names = "cx";
3041
3042			status = "disabled";
3043
3044			smd-edge {
3045				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3046
3047				label = "lpass";
3048				mboxes = <&apcs_glb 8>;
3049				qcom,smd-edge = <1>;
3050				qcom,remote-pid = <2>;
3051				#address-cells = <1>;
3052				#size-cells = <0>;
3053				apr {
3054					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3055					compatible = "qcom,apr-v2";
3056					qcom,smd-channels = "apr_audio_svc";
3057					qcom,apr-domain = <APR_DOMAIN_ADSP>;
3058					#address-cells = <1>;
3059					#size-cells = <0>;
3060
3061					q6core {
3062						reg = <APR_SVC_ADSP_CORE>;
3063						compatible = "qcom,q6core";
3064					};
3065
3066					q6afe: q6afe {
3067						compatible = "qcom,q6afe";
3068						reg = <APR_SVC_AFE>;
3069						q6afedai: dais {
3070							compatible = "qcom,q6afe-dais";
3071							#address-cells = <1>;
3072							#size-cells = <0>;
3073							#sound-dai-cells = <1>;
3074							hdmi@1 {
3075								reg = <1>;
3076							};
3077						};
3078					};
3079
3080					q6asm: q6asm {
3081						compatible = "qcom,q6asm";
3082						reg = <APR_SVC_ASM>;
3083						q6asmdai: dais {
3084							compatible = "qcom,q6asm-dais";
3085							#address-cells = <1>;
3086							#size-cells = <0>;
3087							#sound-dai-cells = <1>;
3088							iommus = <&lpass_q6_smmu 1>;
3089						};
3090					};
3091
3092					q6adm: q6adm {
3093						compatible = "qcom,q6adm";
3094						reg = <APR_SVC_ADM>;
3095						q6routing: routing {
3096							compatible = "qcom,q6adm-routing";
3097							#sound-dai-cells = <0>;
3098						};
3099					};
3100				};
3101
3102			};
3103		};
3104
3105		apcs_glb: mailbox@9820000 {
3106			compatible = "qcom,msm8996-apcs-hmss-global";
3107			reg = <0x09820000 0x1000>;
3108
3109			#mbox-cells = <1>;
3110		};
3111
3112		timer@9840000 {
3113			#address-cells = <1>;
3114			#size-cells = <1>;
3115			ranges;
3116			compatible = "arm,armv7-timer-mem";
3117			reg = <0x09840000 0x1000>;
3118			clock-frequency = <19200000>;
3119
3120			frame@9850000 {
3121				frame-number = <0>;
3122				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3123					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3124				reg = <0x09850000 0x1000>,
3125				      <0x09860000 0x1000>;
3126			};
3127
3128			frame@9870000 {
3129				frame-number = <1>;
3130				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3131				reg = <0x09870000 0x1000>;
3132				status = "disabled";
3133			};
3134
3135			frame@9880000 {
3136				frame-number = <2>;
3137				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3138				reg = <0x09880000 0x1000>;
3139				status = "disabled";
3140			};
3141
3142			frame@9890000 {
3143				frame-number = <3>;
3144				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3145				reg = <0x09890000 0x1000>;
3146				status = "disabled";
3147			};
3148
3149			frame@98a0000 {
3150				frame-number = <4>;
3151				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3152				reg = <0x098a0000 0x1000>;
3153				status = "disabled";
3154			};
3155
3156			frame@98b0000 {
3157				frame-number = <5>;
3158				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3159				reg = <0x098b0000 0x1000>;
3160				status = "disabled";
3161			};
3162
3163			frame@98c0000 {
3164				frame-number = <6>;
3165				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3166				reg = <0x098c0000 0x1000>;
3167				status = "disabled";
3168			};
3169		};
3170
3171		saw3: syscon@9a10000 {
3172			compatible = "syscon";
3173			reg = <0x09a10000 0x1000>;
3174		};
3175
3176		intc: interrupt-controller@9bc0000 {
3177			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3178			#interrupt-cells = <3>;
3179			interrupt-controller;
3180			#redistributor-regions = <1>;
3181			redistributor-stride = <0x0 0x40000>;
3182			reg = <0x09bc0000 0x10000>,
3183			      <0x09c00000 0x100000>;
3184			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3185		};
3186	};
3187
3188	sound: sound {
3189	};
3190
3191	thermal-zones {
3192		cpu0-thermal {
3193			polling-delay-passive = <250>;
3194			polling-delay = <1000>;
3195
3196			thermal-sensors = <&tsens0 3>;
3197
3198			trips {
3199				cpu0_alert0: trip-point0 {
3200					temperature = <75000>;
3201					hysteresis = <2000>;
3202					type = "passive";
3203				};
3204
3205				cpu0_crit: cpu_crit {
3206					temperature = <110000>;
3207					hysteresis = <2000>;
3208					type = "critical";
3209				};
3210			};
3211		};
3212
3213		cpu1-thermal {
3214			polling-delay-passive = <250>;
3215			polling-delay = <1000>;
3216
3217			thermal-sensors = <&tsens0 5>;
3218
3219			trips {
3220				cpu1_alert0: trip-point0 {
3221					temperature = <75000>;
3222					hysteresis = <2000>;
3223					type = "passive";
3224				};
3225
3226				cpu1_crit: cpu_crit {
3227					temperature = <110000>;
3228					hysteresis = <2000>;
3229					type = "critical";
3230				};
3231			};
3232		};
3233
3234		cpu2-thermal {
3235			polling-delay-passive = <250>;
3236			polling-delay = <1000>;
3237
3238			thermal-sensors = <&tsens0 8>;
3239
3240			trips {
3241				cpu2_alert0: trip-point0 {
3242					temperature = <75000>;
3243					hysteresis = <2000>;
3244					type = "passive";
3245				};
3246
3247				cpu2_crit: cpu_crit {
3248					temperature = <110000>;
3249					hysteresis = <2000>;
3250					type = "critical";
3251				};
3252			};
3253		};
3254
3255		cpu3-thermal {
3256			polling-delay-passive = <250>;
3257			polling-delay = <1000>;
3258
3259			thermal-sensors = <&tsens0 10>;
3260
3261			trips {
3262				cpu3_alert0: trip-point0 {
3263					temperature = <75000>;
3264					hysteresis = <2000>;
3265					type = "passive";
3266				};
3267
3268				cpu3_crit: cpu_crit {
3269					temperature = <110000>;
3270					hysteresis = <2000>;
3271					type = "critical";
3272				};
3273			};
3274		};
3275
3276		gpu-thermal-top {
3277			polling-delay-passive = <250>;
3278			polling-delay = <1000>;
3279
3280			thermal-sensors = <&tsens1 6>;
3281
3282			trips {
3283				gpu1_alert0: trip-point0 {
3284					temperature = <90000>;
3285					hysteresis = <2000>;
3286					type = "passive";
3287				};
3288			};
3289
3290			cooling-maps {
3291				map0 {
3292					trip = <&gpu1_alert0>;
3293					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3294				};
3295			};
3296		};
3297
3298		gpu-thermal-bottom {
3299			polling-delay-passive = <250>;
3300			polling-delay = <1000>;
3301
3302			thermal-sensors = <&tsens1 7>;
3303
3304			trips {
3305				gpu2_alert0: trip-point0 {
3306					temperature = <90000>;
3307					hysteresis = <2000>;
3308					type = "passive";
3309				};
3310			};
3311
3312			cooling-maps {
3313				map0 {
3314					trip = <&gpu2_alert0>;
3315					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3316				};
3317			};
3318		};
3319
3320		m4m-thermal {
3321			polling-delay-passive = <250>;
3322			polling-delay = <1000>;
3323
3324			thermal-sensors = <&tsens0 1>;
3325
3326			trips {
3327				m4m_alert0: trip-point0 {
3328					temperature = <90000>;
3329					hysteresis = <2000>;
3330					type = "hot";
3331				};
3332			};
3333		};
3334
3335		l3-or-venus-thermal {
3336			polling-delay-passive = <250>;
3337			polling-delay = <1000>;
3338
3339			thermal-sensors = <&tsens0 2>;
3340
3341			trips {
3342				l3_or_venus_alert0: trip-point0 {
3343					temperature = <90000>;
3344					hysteresis = <2000>;
3345					type = "hot";
3346				};
3347			};
3348		};
3349
3350		cluster0-l2-thermal {
3351			polling-delay-passive = <250>;
3352			polling-delay = <1000>;
3353
3354			thermal-sensors = <&tsens0 7>;
3355
3356			trips {
3357				cluster0_l2_alert0: trip-point0 {
3358					temperature = <90000>;
3359					hysteresis = <2000>;
3360					type = "hot";
3361				};
3362			};
3363		};
3364
3365		cluster1-l2-thermal {
3366			polling-delay-passive = <250>;
3367			polling-delay = <1000>;
3368
3369			thermal-sensors = <&tsens0 12>;
3370
3371			trips {
3372				cluster1_l2_alert0: trip-point0 {
3373					temperature = <90000>;
3374					hysteresis = <2000>;
3375					type = "hot";
3376				};
3377			};
3378		};
3379
3380		camera-thermal {
3381			polling-delay-passive = <250>;
3382			polling-delay = <1000>;
3383
3384			thermal-sensors = <&tsens1 1>;
3385
3386			trips {
3387				camera_alert0: trip-point0 {
3388					temperature = <90000>;
3389					hysteresis = <2000>;
3390					type = "hot";
3391				};
3392			};
3393		};
3394
3395		q6-dsp-thermal {
3396			polling-delay-passive = <250>;
3397			polling-delay = <1000>;
3398
3399			thermal-sensors = <&tsens1 2>;
3400
3401			trips {
3402				q6_dsp_alert0: trip-point0 {
3403					temperature = <90000>;
3404					hysteresis = <2000>;
3405					type = "hot";
3406				};
3407			};
3408		};
3409
3410		mem-thermal {
3411			polling-delay-passive = <250>;
3412			polling-delay = <1000>;
3413
3414			thermal-sensors = <&tsens1 3>;
3415
3416			trips {
3417				mem_alert0: trip-point0 {
3418					temperature = <90000>;
3419					hysteresis = <2000>;
3420					type = "hot";
3421				};
3422			};
3423		};
3424
3425		modemtx-thermal {
3426			polling-delay-passive = <250>;
3427			polling-delay = <1000>;
3428
3429			thermal-sensors = <&tsens1 4>;
3430
3431			trips {
3432				modemtx_alert0: trip-point0 {
3433					temperature = <90000>;
3434					hysteresis = <2000>;
3435					type = "hot";
3436				};
3437			};
3438		};
3439	};
3440
3441	timer {
3442		compatible = "arm,armv8-timer";
3443		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3444			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3445			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3446			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3447	};
3448};
3449