1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16 17/ { 18 model = "Qualcomm Technologies, Inc. MSM8996"; 19 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 memory { 28 device_type = "memory"; 29 /* We expect the bootloader to fill in the reg */ 30 reg = <0 0 0 0>; 31 }; 32 33 reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 mba_region: mba@91500000 { 39 reg = <0x0 0x91500000 0x0 0x200000>; 40 no-map; 41 }; 42 43 slpi_region: slpi@90b00000 { 44 reg = <0x0 0x90b00000 0x0 0xa00000>; 45 no-map; 46 }; 47 48 venus_region: venus@90400000 { 49 reg = <0x0 0x90400000 0x0 0x700000>; 50 no-map; 51 }; 52 53 adsp_region: adsp@8ea00000 { 54 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 55 no-map; 56 }; 57 58 mpss_region: mpss@88800000 { 59 reg = <0x0 0x88800000 0x0 0x6200000>; 60 no-map; 61 }; 62 63 smem_mem: smem-mem@86000000 { 64 reg = <0x0 0x86000000 0x0 0x200000>; 65 no-map; 66 }; 67 68 memory@85800000 { 69 reg = <0x0 0x85800000 0x0 0x800000>; 70 no-map; 71 }; 72 73 memory@86200000 { 74 reg = <0x0 0x86200000 0x0 0x2600000>; 75 no-map; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <2>; 81 #size-cells = <0>; 82 83 CPU0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "qcom,kryo"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_0>; 89 L2_0: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 }; 93 }; 94 95 CPU1: cpu@1 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo"; 98 reg = <0x0 0x1>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 }; 102 103 CPU2: cpu@100 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_1>; 109 L2_1: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 }; 113 }; 114 115 CPU3: cpu@101 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x101>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_1>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&CPU0>; 127 }; 128 129 core1 { 130 cpu = <&CPU1>; 131 }; 132 }; 133 134 cluster1 { 135 core0 { 136 cpu = <&CPU2>; 137 }; 138 139 core1 { 140 cpu = <&CPU3>; 141 }; 142 }; 143 }; 144 }; 145 146 thermal-zones { 147 cpu-thermal0 { 148 polling-delay-passive = <250>; 149 polling-delay = <1000>; 150 151 thermal-sensors = <&tsens0 3>; 152 153 trips { 154 cpu_alert0: trip0 { 155 temperature = <75000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 160 cpu_crit0: trip1 { 161 temperature = <110000>; 162 hysteresis = <2000>; 163 type = "critical"; 164 }; 165 }; 166 }; 167 168 cpu-thermal1 { 169 polling-delay-passive = <250>; 170 polling-delay = <1000>; 171 172 thermal-sensors = <&tsens0 5>; 173 174 trips { 175 cpu_alert1: trip0 { 176 temperature = <75000>; 177 hysteresis = <2000>; 178 type = "passive"; 179 }; 180 181 cpu_crit1: trip1 { 182 temperature = <110000>; 183 hysteresis = <2000>; 184 type = "critical"; 185 }; 186 }; 187 }; 188 189 cpu-thermal2 { 190 polling-delay-passive = <250>; 191 polling-delay = <1000>; 192 193 thermal-sensors = <&tsens0 8>; 194 195 trips { 196 cpu_alert2: trip0 { 197 temperature = <75000>; 198 hysteresis = <2000>; 199 type = "passive"; 200 }; 201 202 cpu_crit2: trip1 { 203 temperature = <110000>; 204 hysteresis = <2000>; 205 type = "critical"; 206 }; 207 }; 208 }; 209 210 cpu-thermal3 { 211 polling-delay-passive = <250>; 212 polling-delay = <1000>; 213 214 thermal-sensors = <&tsens0 10>; 215 216 trips { 217 cpu_alert3: trip0 { 218 temperature = <75000>; 219 hysteresis = <2000>; 220 type = "passive"; 221 }; 222 223 cpu_crit3: trip1 { 224 temperature = <110000>; 225 hysteresis = <2000>; 226 type = "critical"; 227 }; 228 }; 229 }; 230 }; 231 232 timer { 233 compatible = "arm,armv8-timer"; 234 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 238 }; 239 240 clocks { 241 xo_board: xo_board { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <19200000>; 245 clock-output-names = "xo_board"; 246 }; 247 248 sleep_clk: sleep_clk { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <32764>; 252 clock-output-names = "sleep_clk"; 253 }; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 firmware { 262 scm { 263 compatible = "qcom,scm-msm8996"; 264 }; 265 }; 266 267 tcsr_mutex: hwlock { 268 compatible = "qcom,tcsr-mutex"; 269 syscon = <&tcsr_mutex_regs 0 0x1000>; 270 #hwlock-cells = <1>; 271 }; 272 273 smem { 274 compatible = "qcom,smem"; 275 memory-region = <&smem_mem>; 276 hwlocks = <&tcsr_mutex 3>; 277 }; 278 279 soc: soc { 280 #address-cells = <1>; 281 #size-cells = <1>; 282 ranges = <0 0 0 0xffffffff>; 283 compatible = "simple-bus"; 284 285 tcsr_mutex_regs: syscon@740000 { 286 compatible = "syscon"; 287 reg = <0x740000 0x20000>; 288 }; 289 290 intc: interrupt-controller@9bc0000 { 291 compatible = "arm,gic-v3"; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 #redistributor-regions = <1>; 295 redistributor-stride = <0x0 0x40000>; 296 reg = <0x09bc0000 0x10000>, 297 <0x09c00000 0x100000>; 298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 apcs: syscon@9820000 { 302 compatible = "syscon"; 303 reg = <0x9820000 0x1000>; 304 }; 305 306 gcc: clock-controller@300000 { 307 compatible = "qcom,gcc-msm8996"; 308 #clock-cells = <1>; 309 #reset-cells = <1>; 310 #power-domain-cells = <1>; 311 reg = <0x300000 0x90000>; 312 }; 313 314 blsp1_spi0: spi@07575000 { 315 compatible = "qcom,spi-qup-v2.2.1"; 316 reg = <0x07575000 0x600>; 317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 319 <&gcc GCC_BLSP1_AHB_CLK>; 320 clock-names = "core", "iface"; 321 pinctrl-names = "default", "sleep"; 322 pinctrl-0 = <&blsp1_spi0_default>; 323 pinctrl-1 = <&blsp1_spi0_sleep>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "disabled"; 327 }; 328 329 blsp2_i2c0: i2c@075b5000 { 330 compatible = "qcom,i2c-qup-v2.2.1"; 331 reg = <0x075b5000 0x1000>; 332 interrupts = <GIC_SPI 101 0>; 333 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 334 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 335 clock-names = "iface", "core"; 336 pinctrl-names = "default", "sleep"; 337 pinctrl-0 = <&blsp2_i2c0_default>; 338 pinctrl-1 = <&blsp2_i2c0_sleep>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 tsens0: thermal-sensor@4a8000 { 345 compatible = "qcom,msm8996-tsens"; 346 reg = <0x4a8000 0x2000>; 347 #thermal-sensor-cells = <1>; 348 }; 349 350 blsp2_uart1: serial@75b0000 { 351 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 352 reg = <0x75b0000 0x1000>; 353 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 355 <&gcc GCC_BLSP2_AHB_CLK>; 356 clock-names = "core", "iface"; 357 status = "disabled"; 358 }; 359 360 blsp2_i2c1: i2c@075b6000 { 361 compatible = "qcom,i2c-qup-v2.2.1"; 362 reg = <0x075b6000 0x1000>; 363 interrupts = <GIC_SPI 102 0>; 364 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 365 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 366 clock-names = "iface", "core"; 367 pinctrl-names = "default", "sleep"; 368 pinctrl-0 = <&blsp2_i2c1_default>; 369 pinctrl-1 = <&blsp2_i2c1_sleep>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 blsp2_uart2: serial@75b1000 { 376 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 377 reg = <0x075b1000 0x1000>; 378 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 380 <&gcc GCC_BLSP2_AHB_CLK>; 381 clock-names = "core", "iface"; 382 status = "disabled"; 383 }; 384 385 blsp1_i2c2: i2c@07577000 { 386 compatible = "qcom,i2c-qup-v2.2.1"; 387 reg = <0x07577000 0x1000>; 388 interrupts = <GIC_SPI 97 0>; 389 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 390 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 391 clock-names = "iface", "core"; 392 pinctrl-names = "default", "sleep"; 393 pinctrl-0 = <&blsp1_i2c2_default>; 394 pinctrl-1 = <&blsp1_i2c2_sleep>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 blsp2_spi5: spi@075ba000{ 401 compatible = "qcom,spi-qup-v2.2.1"; 402 reg = <0x075ba000 0x600>; 403 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 405 <&gcc GCC_BLSP2_AHB_CLK>; 406 clock-names = "core", "iface"; 407 pinctrl-names = "default", "sleep"; 408 pinctrl-0 = <&blsp2_spi5_default>; 409 pinctrl-1 = <&blsp2_spi5_sleep>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 sdhc2: sdhci@74a4900 { 416 status = "disabled"; 417 compatible = "qcom,sdhci-msm-v4"; 418 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 419 reg-names = "hc_mem", "core_mem"; 420 421 interrupts = <0 125 0>, <0 221 0>; 422 interrupt-names = "hc_irq", "pwr_irq"; 423 424 clock-names = "iface", "core", "xo"; 425 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 426 <&gcc GCC_SDCC2_APPS_CLK>, 427 <&xo_board>; 428 bus-width = <4>; 429 }; 430 431 msmgpio: pinctrl@1010000 { 432 compatible = "qcom,msm8996-pinctrl"; 433 reg = <0x01010000 0x300000>; 434 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 }; 440 441 timer@09840000 { 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges; 445 compatible = "arm,armv7-timer-mem"; 446 reg = <0x09840000 0x1000>; 447 clock-frequency = <19200000>; 448 449 frame@9850000 { 450 frame-number = <0>; 451 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 453 reg = <0x09850000 0x1000>, 454 <0x09860000 0x1000>; 455 }; 456 457 frame@9870000 { 458 frame-number = <1>; 459 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 460 reg = <0x09870000 0x1000>; 461 status = "disabled"; 462 }; 463 464 frame@9880000 { 465 frame-number = <2>; 466 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 467 reg = <0x09880000 0x1000>; 468 status = "disabled"; 469 }; 470 471 frame@9890000 { 472 frame-number = <3>; 473 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 474 reg = <0x09890000 0x1000>; 475 status = "disabled"; 476 }; 477 478 frame@98a0000 { 479 frame-number = <4>; 480 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 481 reg = <0x098a0000 0x1000>; 482 status = "disabled"; 483 }; 484 485 frame@98b0000 { 486 frame-number = <5>; 487 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 488 reg = <0x098b0000 0x1000>; 489 status = "disabled"; 490 }; 491 492 frame@98c0000 { 493 frame-number = <6>; 494 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 495 reg = <0x098c0000 0x1000>; 496 status = "disabled"; 497 }; 498 }; 499 500 spmi_bus: qcom,spmi@400f000 { 501 compatible = "qcom,spmi-pmic-arb"; 502 reg = <0x400f000 0x1000>, 503 <0x4400000 0x800000>, 504 <0x4c00000 0x800000>, 505 <0x5800000 0x200000>, 506 <0x400a000 0x002100>; 507 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 508 interrupt-names = "periph_irq"; 509 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 510 qcom,ee = <0>; 511 qcom,channel = <0>; 512 #address-cells = <2>; 513 #size-cells = <0>; 514 interrupt-controller; 515 #interrupt-cells = <4>; 516 }; 517 518 mmcc: clock-controller@8c0000 { 519 compatible = "qcom,mmcc-msm8996"; 520 #clock-cells = <1>; 521 #reset-cells = <1>; 522 #power-domain-cells = <1>; 523 reg = <0x8c0000 0x40000>; 524 assigned-clocks = <&mmcc MMPLL9_PLL>, 525 <&mmcc MMPLL1_PLL>, 526 <&mmcc MMPLL3_PLL>, 527 <&mmcc MMPLL4_PLL>, 528 <&mmcc MMPLL5_PLL>; 529 assigned-clock-rates = <624000000>, 530 <810000000>, 531 <980000000>, 532 <960000000>, 533 <825000000>; 534 }; 535 }; 536 537 adsp-smp2p { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <443>, <429>; 540 541 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 542 543 qcom,ipc = <&apcs 16 10>; 544 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <2>; 547 548 adsp_smp2p_out: master-kernel { 549 qcom,entry-name = "master-kernel"; 550 #qcom,state-cells = <1>; 551 }; 552 553 adsp_smp2p_in: slave-kernel { 554 qcom,entry-name = "slave-kernel"; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 }; 560}; 561#include "msm8996-pins.dtsi" 562