1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16#include <dt-bindings/clock/qcom,rpmcc.h> 17#include <dt-bindings/soc/qcom,apr.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 memory { 28 device_type = "memory"; 29 /* We expect the bootloader to fill in the reg */ 30 reg = <0 0 0 0>; 31 }; 32 33 reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 mba_region: mba@91500000 { 39 reg = <0x0 0x91500000 0x0 0x200000>; 40 no-map; 41 }; 42 43 slpi_region: slpi@90b00000 { 44 reg = <0x0 0x90b00000 0x0 0xa00000>; 45 no-map; 46 }; 47 48 venus_region: venus@90400000 { 49 reg = <0x0 0x90400000 0x0 0x700000>; 50 no-map; 51 }; 52 53 adsp_region: adsp@8ea00000 { 54 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 55 no-map; 56 }; 57 58 mpss_region: mpss@88800000 { 59 reg = <0x0 0x88800000 0x0 0x6200000>; 60 no-map; 61 }; 62 63 smem_mem: smem-mem@86000000 { 64 reg = <0x0 0x86000000 0x0 0x200000>; 65 no-map; 66 }; 67 68 memory@85800000 { 69 reg = <0x0 0x85800000 0x0 0x800000>; 70 no-map; 71 }; 72 73 memory@86200000 { 74 reg = <0x0 0x86200000 0x0 0x2600000>; 75 no-map; 76 }; 77 78 rmtfs@86700000 { 79 compatible = "qcom,rmtfs-mem"; 80 81 size = <0x0 0x200000>; 82 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 83 no-map; 84 85 qcom,client-id = <1>; 86 qcom,vmid = <15>; 87 }; 88 89 zap_shader_region: gpu@8f200000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x0 0x90b00000 0x0 0xa00000>; 92 no-map; 93 }; 94 }; 95 96 cpus { 97 #address-cells = <2>; 98 #size-cells = <0>; 99 100 CPU0: cpu@0 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo"; 103 reg = <0x0 0x0>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_0>; 106 L2_0: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 }; 110 }; 111 112 CPU1: cpu@1 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo"; 115 reg = <0x0 0x1>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_0>; 118 }; 119 120 CPU2: cpu@100 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_1>; 126 L2_1: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 }; 130 }; 131 132 CPU3: cpu@101 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo"; 135 reg = <0x0 0x101>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_1>; 138 }; 139 140 cpu-map { 141 cluster0 { 142 core0 { 143 cpu = <&CPU0>; 144 }; 145 146 core1 { 147 cpu = <&CPU1>; 148 }; 149 }; 150 151 cluster1 { 152 core0 { 153 cpu = <&CPU2>; 154 }; 155 156 core1 { 157 cpu = <&CPU3>; 158 }; 159 }; 160 }; 161 }; 162 163 thermal-zones { 164 cpu0-thermal { 165 polling-delay-passive = <250>; 166 polling-delay = <1000>; 167 168 thermal-sensors = <&tsens0 3>; 169 170 trips { 171 cpu0_alert0: trip-point@0 { 172 temperature = <75000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 cpu0_crit: cpu_crit { 178 temperature = <110000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 cpu1-thermal { 186 polling-delay-passive = <250>; 187 polling-delay = <1000>; 188 189 thermal-sensors = <&tsens0 5>; 190 191 trips { 192 cpu1_alert0: trip-point@0 { 193 temperature = <75000>; 194 hysteresis = <2000>; 195 type = "passive"; 196 }; 197 198 cpu1_crit: cpu_crit { 199 temperature = <110000>; 200 hysteresis = <2000>; 201 type = "critical"; 202 }; 203 }; 204 }; 205 206 cpu2-thermal { 207 polling-delay-passive = <250>; 208 polling-delay = <1000>; 209 210 thermal-sensors = <&tsens0 8>; 211 212 trips { 213 cpu2_alert0: trip-point@0 { 214 temperature = <75000>; 215 hysteresis = <2000>; 216 type = "passive"; 217 }; 218 219 cpu2_crit: cpu_crit { 220 temperature = <110000>; 221 hysteresis = <2000>; 222 type = "critical"; 223 }; 224 }; 225 }; 226 227 cpu3-thermal { 228 polling-delay-passive = <250>; 229 polling-delay = <1000>; 230 231 thermal-sensors = <&tsens0 10>; 232 233 trips { 234 cpu3_alert0: trip-point@0 { 235 temperature = <75000>; 236 hysteresis = <2000>; 237 type = "passive"; 238 }; 239 240 cpu3_crit: cpu_crit { 241 temperature = <110000>; 242 hysteresis = <2000>; 243 type = "critical"; 244 }; 245 }; 246 }; 247 248 gpu-thermal-top { 249 polling-delay-passive = <250>; 250 polling-delay = <1000>; 251 252 thermal-sensors = <&tsens1 6>; 253 254 trips { 255 gpu1_alert0: trip-point@0 { 256 temperature = <90000>; 257 hysteresis = <2000>; 258 type = "hot"; 259 }; 260 }; 261 }; 262 263 gpu-thermal-bottom { 264 polling-delay-passive = <250>; 265 polling-delay = <1000>; 266 267 thermal-sensors = <&tsens1 7>; 268 269 trips { 270 gpu2_alert0: trip-point@0 { 271 temperature = <90000>; 272 hysteresis = <2000>; 273 type = "hot"; 274 }; 275 }; 276 }; 277 278 m4m-thermal { 279 polling-delay-passive = <250>; 280 polling-delay = <1000>; 281 282 thermal-sensors = <&tsens0 1>; 283 284 trips { 285 m4m_alert0: trip-point@0 { 286 temperature = <90000>; 287 hysteresis = <2000>; 288 type = "hot"; 289 }; 290 }; 291 }; 292 293 l3-or-venus-thermal { 294 polling-delay-passive = <250>; 295 polling-delay = <1000>; 296 297 thermal-sensors = <&tsens0 2>; 298 299 trips { 300 l3_or_venus_alert0: trip-point@0 { 301 temperature = <90000>; 302 hysteresis = <2000>; 303 type = "hot"; 304 }; 305 }; 306 }; 307 308 cluster0-l2-thermal { 309 polling-delay-passive = <250>; 310 polling-delay = <1000>; 311 312 thermal-sensors = <&tsens0 7>; 313 314 trips { 315 cluster0_l2_alert0: trip-point@0 { 316 temperature = <90000>; 317 hysteresis = <2000>; 318 type = "hot"; 319 }; 320 }; 321 }; 322 323 cluster1-l2-thermal { 324 polling-delay-passive = <250>; 325 polling-delay = <1000>; 326 327 thermal-sensors = <&tsens0 12>; 328 329 trips { 330 cluster1_l2_alert0: trip-point@0 { 331 temperature = <90000>; 332 hysteresis = <2000>; 333 type = "hot"; 334 }; 335 }; 336 }; 337 338 camera-thermal { 339 polling-delay-passive = <250>; 340 polling-delay = <1000>; 341 342 thermal-sensors = <&tsens1 1>; 343 344 trips { 345 camera_alert0: trip-point@0 { 346 temperature = <90000>; 347 hysteresis = <2000>; 348 type = "hot"; 349 }; 350 }; 351 }; 352 353 q6-dsp-thermal { 354 polling-delay-passive = <250>; 355 polling-delay = <1000>; 356 357 thermal-sensors = <&tsens1 2>; 358 359 trips { 360 q6_dsp_alert0: trip-point@0 { 361 temperature = <90000>; 362 hysteresis = <2000>; 363 type = "hot"; 364 }; 365 }; 366 }; 367 368 mem-thermal { 369 polling-delay-passive = <250>; 370 polling-delay = <1000>; 371 372 thermal-sensors = <&tsens1 3>; 373 374 trips { 375 mem_alert0: trip-point@0 { 376 temperature = <90000>; 377 hysteresis = <2000>; 378 type = "hot"; 379 }; 380 }; 381 }; 382 383 modemtx-thermal { 384 polling-delay-passive = <250>; 385 polling-delay = <1000>; 386 387 thermal-sensors = <&tsens1 4>; 388 389 trips { 390 modemtx_alert0: trip-point@0 { 391 temperature = <90000>; 392 hysteresis = <2000>; 393 type = "hot"; 394 }; 395 }; 396 }; 397 }; 398 399 timer { 400 compatible = "arm,armv8-timer"; 401 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 402 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 403 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 404 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 405 }; 406 407 clocks { 408 xo_board: xo_board { 409 compatible = "fixed-clock"; 410 #clock-cells = <0>; 411 clock-frequency = <19200000>; 412 clock-output-names = "xo_board"; 413 }; 414 415 sleep_clk: sleep_clk { 416 compatible = "fixed-clock"; 417 #clock-cells = <0>; 418 clock-frequency = <32764>; 419 clock-output-names = "sleep_clk"; 420 }; 421 }; 422 423 psci { 424 compatible = "arm,psci-1.0"; 425 method = "smc"; 426 }; 427 428 firmware { 429 scm { 430 compatible = "qcom,scm-msm8996"; 431 432 qcom,dload-mode = <&tcsr 0x13000>; 433 }; 434 }; 435 436 tcsr_mutex: hwlock { 437 compatible = "qcom,tcsr-mutex"; 438 syscon = <&tcsr_mutex_regs 0 0x1000>; 439 #hwlock-cells = <1>; 440 }; 441 442 smem { 443 compatible = "qcom,smem"; 444 memory-region = <&smem_mem>; 445 hwlocks = <&tcsr_mutex 3>; 446 }; 447 448 rpm-glink { 449 compatible = "qcom,glink-rpm"; 450 451 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 452 453 qcom,rpm-msg-ram = <&rpm_msg_ram>; 454 455 mboxes = <&apcs_glb 0>; 456 457 rpm_requests { 458 compatible = "qcom,rpm-msm8996"; 459 qcom,glink-channels = "rpm_requests"; 460 461 rpmcc: qcom,rpmcc { 462 compatible = "qcom,rpmcc-msm8996"; 463 #clock-cells = <1>; 464 }; 465 466 rpmpd: power-controller { 467 compatible = "qcom,msm8996-rpmpd"; 468 #power-domain-cells = <1>; 469 operating-points-v2 = <&rpmpd_opp_table>; 470 471 rpmpd_opp_table: opp-table { 472 compatible = "operating-points-v2"; 473 474 rpmpd_opp1: opp1 { 475 opp-level = <1>; 476 }; 477 478 rpmpd_opp2: opp2 { 479 opp-level = <2>; 480 }; 481 482 rpmpd_opp3: opp3 { 483 opp-level = <3>; 484 }; 485 486 rpmpd_opp4: opp4 { 487 opp-level = <4>; 488 }; 489 490 rpmpd_opp5: opp5 { 491 opp-level = <5>; 492 }; 493 494 rpmpd_opp6: opp6 { 495 opp-level = <6>; 496 }; 497 }; 498 }; 499 500 pm8994-regulators { 501 compatible = "qcom,rpm-pm8994-regulators"; 502 503 pm8994_s1: s1 {}; 504 pm8994_s2: s2 {}; 505 pm8994_s3: s3 {}; 506 pm8994_s4: s4 {}; 507 pm8994_s5: s5 {}; 508 pm8994_s6: s6 {}; 509 pm8994_s7: s7 {}; 510 pm8994_s8: s8 {}; 511 pm8994_s9: s9 {}; 512 pm8994_s10: s10 {}; 513 pm8994_s11: s11 {}; 514 pm8994_s12: s12 {}; 515 516 pm8994_l1: l1 {}; 517 pm8994_l2: l2 {}; 518 pm8994_l3: l3 {}; 519 pm8994_l4: l4 {}; 520 pm8994_l5: l5 {}; 521 pm8994_l6: l6 {}; 522 pm8994_l7: l7 {}; 523 pm8994_l8: l8 {}; 524 pm8994_l9: l9 {}; 525 pm8994_l10: l10 {}; 526 pm8994_l11: l11 {}; 527 pm8994_l12: l12 {}; 528 pm8994_l13: l13 {}; 529 pm8994_l14: l14 {}; 530 pm8994_l15: l15 {}; 531 pm8994_l16: l16 {}; 532 pm8994_l17: l17 {}; 533 pm8994_l18: l18 {}; 534 pm8994_l19: l19 {}; 535 pm8994_l20: l20 {}; 536 pm8994_l21: l21 {}; 537 pm8994_l22: l22 {}; 538 pm8994_l23: l23 {}; 539 pm8994_l24: l24 {}; 540 pm8994_l25: l25 {}; 541 pm8994_l26: l26 {}; 542 pm8994_l27: l27 {}; 543 pm8994_l28: l28 {}; 544 pm8994_l29: l29 {}; 545 pm8994_l30: l30 {}; 546 pm8994_l31: l31 {}; 547 pm8994_l32: l32 {}; 548 }; 549 550 }; 551 }; 552 553 soc: soc { 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges = <0 0 0 0xffffffff>; 557 compatible = "simple-bus"; 558 559 rpm_msg_ram: memory@68000 { 560 compatible = "qcom,rpm-msg-ram"; 561 reg = <0x68000 0x6000>; 562 }; 563 564 rng: rng@83000 { 565 compatible = "qcom,prng-ee"; 566 reg = <0x00083000 0x1000>; 567 clocks = <&gcc GCC_PRNG_AHB_CLK>; 568 clock-names = "core"; 569 }; 570 571 tcsr_mutex_regs: syscon@740000 { 572 compatible = "syscon"; 573 reg = <0x740000 0x20000>; 574 }; 575 576 tsens0: thermal-sensor@4a9000 { 577 compatible = "qcom,msm8996-tsens"; 578 reg = <0x4a9000 0x1000>, /* TM */ 579 <0x4a8000 0x1000>; /* SROT */ 580 #qcom,sensors = <13>; 581 #thermal-sensor-cells = <1>; 582 }; 583 584 tsens1: thermal-sensor@4ad000 { 585 compatible = "qcom,msm8996-tsens"; 586 reg = <0x4ad000 0x1000>, /* TM */ 587 <0x4ac000 0x1000>; /* SROT */ 588 #qcom,sensors = <8>; 589 #thermal-sensor-cells = <1>; 590 }; 591 592 tcsr: syscon@7a0000 { 593 compatible = "qcom,tcsr-msm8996", "syscon"; 594 reg = <0x7a0000 0x18000>; 595 }; 596 597 intc: interrupt-controller@9bc0000 { 598 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 599 #interrupt-cells = <3>; 600 interrupt-controller; 601 #redistributor-regions = <1>; 602 redistributor-stride = <0x0 0x40000>; 603 reg = <0x09bc0000 0x10000>, 604 <0x09c00000 0x100000>; 605 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 606 }; 607 608 apcs_glb: mailbox@9820000 { 609 compatible = "qcom,msm8996-apcs-hmss-global"; 610 reg = <0x9820000 0x1000>; 611 612 #mbox-cells = <1>; 613 }; 614 615 gcc: clock-controller@300000 { 616 compatible = "qcom,gcc-msm8996"; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 #power-domain-cells = <1>; 620 reg = <0x300000 0x90000>; 621 }; 622 623 kryocc: clock-controller@6400000 { 624 compatible = "qcom,apcc-msm8996"; 625 reg = <0x6400000 0x90000>; 626 #clock-cells = <1>; 627 }; 628 629 blsp1_uart1: serial@7570000 { 630 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 631 reg = <0x07570000 0x1000>; 632 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 634 <&gcc GCC_BLSP1_AHB_CLK>; 635 clock-names = "core", "iface"; 636 status = "disabled"; 637 }; 638 639 blsp1_spi0: spi@7575000 { 640 compatible = "qcom,spi-qup-v2.2.1"; 641 reg = <0x07575000 0x600>; 642 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 644 <&gcc GCC_BLSP1_AHB_CLK>; 645 clock-names = "core", "iface"; 646 pinctrl-names = "default", "sleep"; 647 pinctrl-0 = <&blsp1_spi0_default>; 648 pinctrl-1 = <&blsp1_spi0_sleep>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 status = "disabled"; 652 }; 653 654 blsp2_i2c0: i2c@75b5000 { 655 compatible = "qcom,i2c-qup-v2.2.1"; 656 reg = <0x075b5000 0x1000>; 657 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 659 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 660 clock-names = "iface", "core"; 661 pinctrl-names = "default", "sleep"; 662 pinctrl-0 = <&blsp2_i2c0_default>; 663 pinctrl-1 = <&blsp2_i2c0_sleep>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 status = "disabled"; 667 }; 668 669 blsp2_uart1: serial@75b0000 { 670 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 671 reg = <0x75b0000 0x1000>; 672 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 674 <&gcc GCC_BLSP2_AHB_CLK>; 675 clock-names = "core", "iface"; 676 status = "disabled"; 677 }; 678 679 blsp2_i2c1: i2c@75b6000 { 680 compatible = "qcom,i2c-qup-v2.2.1"; 681 reg = <0x075b6000 0x1000>; 682 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 684 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 685 clock-names = "iface", "core"; 686 pinctrl-names = "default", "sleep"; 687 pinctrl-0 = <&blsp2_i2c1_default>; 688 pinctrl-1 = <&blsp2_i2c1_sleep>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 blsp2_uart2: serial@75b1000 { 695 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 696 reg = <0x075b1000 0x1000>; 697 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 699 <&gcc GCC_BLSP2_AHB_CLK>; 700 clock-names = "core", "iface"; 701 status = "disabled"; 702 }; 703 704 blsp1_i2c2: i2c@7577000 { 705 compatible = "qcom,i2c-qup-v2.2.1"; 706 reg = <0x07577000 0x1000>; 707 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 709 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 710 clock-names = "iface", "core"; 711 pinctrl-names = "default", "sleep"; 712 pinctrl-0 = <&blsp1_i2c2_default>; 713 pinctrl-1 = <&blsp1_i2c2_sleep>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 blsp2_spi5: spi@75ba000{ 720 compatible = "qcom,spi-qup-v2.2.1"; 721 reg = <0x075ba000 0x600>; 722 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 724 <&gcc GCC_BLSP2_AHB_CLK>; 725 clock-names = "core", "iface"; 726 pinctrl-names = "default", "sleep"; 727 pinctrl-0 = <&blsp2_spi5_default>; 728 pinctrl-1 = <&blsp2_spi5_sleep>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 sdhc2: sdhci@74a4900 { 735 status = "disabled"; 736 compatible = "qcom,sdhci-msm-v4"; 737 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 738 reg-names = "hc_mem", "core_mem"; 739 740 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 741 <0 221 IRQ_TYPE_LEVEL_HIGH>; 742 interrupt-names = "hc_irq", "pwr_irq"; 743 744 clock-names = "iface", "core", "xo"; 745 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 746 <&gcc GCC_SDCC2_APPS_CLK>, 747 <&xo_board>; 748 bus-width = <4>; 749 }; 750 751 msmgpio: pinctrl@1010000 { 752 compatible = "qcom,msm8996-pinctrl"; 753 reg = <0x01010000 0x300000>; 754 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 755 gpio-controller; 756 #gpio-cells = <2>; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 761 timer@9840000 { 762 #address-cells = <1>; 763 #size-cells = <1>; 764 ranges; 765 compatible = "arm,armv7-timer-mem"; 766 reg = <0x09840000 0x1000>; 767 clock-frequency = <19200000>; 768 769 frame@9850000 { 770 frame-number = <0>; 771 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 773 reg = <0x09850000 0x1000>, 774 <0x09860000 0x1000>; 775 }; 776 777 frame@9870000 { 778 frame-number = <1>; 779 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 780 reg = <0x09870000 0x1000>; 781 status = "disabled"; 782 }; 783 784 frame@9880000 { 785 frame-number = <2>; 786 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 787 reg = <0x09880000 0x1000>; 788 status = "disabled"; 789 }; 790 791 frame@9890000 { 792 frame-number = <3>; 793 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 794 reg = <0x09890000 0x1000>; 795 status = "disabled"; 796 }; 797 798 frame@98a0000 { 799 frame-number = <4>; 800 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 801 reg = <0x098a0000 0x1000>; 802 status = "disabled"; 803 }; 804 805 frame@98b0000 { 806 frame-number = <5>; 807 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 808 reg = <0x098b0000 0x1000>; 809 status = "disabled"; 810 }; 811 812 frame@98c0000 { 813 frame-number = <6>; 814 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 815 reg = <0x098c0000 0x1000>; 816 status = "disabled"; 817 }; 818 }; 819 820 spmi_bus: qcom,spmi@400f000 { 821 compatible = "qcom,spmi-pmic-arb"; 822 reg = <0x400f000 0x1000>, 823 <0x4400000 0x800000>, 824 <0x4c00000 0x800000>, 825 <0x5800000 0x200000>, 826 <0x400a000 0x002100>; 827 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 828 interrupt-names = "periph_irq"; 829 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 830 qcom,ee = <0>; 831 qcom,channel = <0>; 832 #address-cells = <2>; 833 #size-cells = <0>; 834 interrupt-controller; 835 #interrupt-cells = <4>; 836 }; 837 838 ufsphy: phy@627000 { 839 compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; 840 reg = <0x627000 0xda8>; 841 reg-names = "phy_mem"; 842 #phy-cells = <0>; 843 844 vdda-phy-supply = <&pm8994_l28>; 845 vdda-pll-supply = <&pm8994_l12>; 846 847 vdda-phy-max-microamp = <18380>; 848 vdda-pll-max-microamp = <9440>; 849 850 vddp-ref-clk-supply = <&pm8994_l25>; 851 vddp-ref-clk-max-microamp = <100>; 852 vddp-ref-clk-always-on; 853 854 clock-names = "ref_clk_src", "ref_clk"; 855 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 856 <&gcc GCC_UFS_CLKREF_CLK>; 857 status = "disabled"; 858 }; 859 860 ufshc@624000 { 861 compatible = "qcom,ufshc"; 862 reg = <0x624000 0x2500>; 863 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 864 865 phys = <&ufsphy>; 866 phy-names = "ufsphy"; 867 868 vcc-supply = <&pm8994_l20>; 869 vccq-supply = <&pm8994_l25>; 870 vccq2-supply = <&pm8994_s4>; 871 872 vcc-max-microamp = <600000>; 873 vccq-max-microamp = <450000>; 874 vccq2-max-microamp = <450000>; 875 876 power-domains = <&gcc UFS_GDSC>; 877 878 clock-names = 879 "core_clk_src", 880 "core_clk", 881 "bus_clk", 882 "bus_aggr_clk", 883 "iface_clk", 884 "core_clk_unipro_src", 885 "core_clk_unipro", 886 "core_clk_ice", 887 "ref_clk", 888 "tx_lane0_sync_clk", 889 "rx_lane0_sync_clk"; 890 clocks = 891 <&gcc UFS_AXI_CLK_SRC>, 892 <&gcc GCC_UFS_AXI_CLK>, 893 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 894 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 895 <&gcc GCC_UFS_AHB_CLK>, 896 <&gcc UFS_ICE_CORE_CLK_SRC>, 897 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 898 <&gcc GCC_UFS_ICE_CORE_CLK>, 899 <&rpmcc RPM_SMD_LN_BB_CLK>, 900 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 901 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 902 freq-table-hz = 903 <100000000 200000000>, 904 <0 0>, 905 <0 0>, 906 <0 0>, 907 <0 0>, 908 <150000000 300000000>, 909 <0 0>, 910 <0 0>, 911 <0 0>, 912 <0 0>, 913 <0 0>; 914 915 lanes-per-direction = <1>; 916 status = "disabled"; 917 918 ufs_variant { 919 compatible = "qcom,ufs_variant"; 920 }; 921 }; 922 923 mmcc: clock-controller@8c0000 { 924 compatible = "qcom,mmcc-msm8996"; 925 #clock-cells = <1>; 926 #reset-cells = <1>; 927 #power-domain-cells = <1>; 928 reg = <0x8c0000 0x40000>; 929 assigned-clocks = <&mmcc MMPLL9_PLL>, 930 <&mmcc MMPLL1_PLL>, 931 <&mmcc MMPLL3_PLL>, 932 <&mmcc MMPLL4_PLL>, 933 <&mmcc MMPLL5_PLL>; 934 assigned-clock-rates = <624000000>, 935 <810000000>, 936 <980000000>, 937 <960000000>, 938 <825000000>; 939 }; 940 941 qfprom@74000 { 942 compatible = "qcom,qfprom"; 943 reg = <0x74000 0x8ff>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 947 qusb2p_hstx_trim: hstx_trim@24e { 948 reg = <0x24e 0x2>; 949 bits = <5 4>; 950 }; 951 952 qusb2s_hstx_trim: hstx_trim@24f { 953 reg = <0x24f 0x1>; 954 bits = <1 4>; 955 }; 956 957 gpu_speed_bin: gpu_speed_bin@133 { 958 reg = <0x133 0x1>; 959 bits = <5 3>; 960 }; 961 }; 962 963 phy@34000 { 964 compatible = "qcom,msm8996-qmp-pcie-phy"; 965 reg = <0x34000 0x488>; 966 #clock-cells = <1>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 ranges; 970 971 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 972 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 973 <&gcc GCC_PCIE_CLKREF_CLK>; 974 clock-names = "aux", "cfg_ahb", "ref"; 975 976 vdda-phy-supply = <&pm8994_l28>; 977 vdda-pll-supply = <&pm8994_l12>; 978 979 resets = <&gcc GCC_PCIE_PHY_BCR>, 980 <&gcc GCC_PCIE_PHY_COM_BCR>, 981 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 982 reset-names = "phy", "common", "cfg"; 983 status = "disabled"; 984 985 pciephy_0: lane@35000 { 986 reg = <0x035000 0x130>, 987 <0x035200 0x200>, 988 <0x035400 0x1dc>; 989 #phy-cells = <0>; 990 991 clock-output-names = "pcie_0_pipe_clk_src"; 992 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 993 clock-names = "pipe0"; 994 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 995 reset-names = "lane0"; 996 }; 997 998 pciephy_1: lane@36000 { 999 reg = <0x036000 0x130>, 1000 <0x036200 0x200>, 1001 <0x036400 0x1dc>; 1002 #phy-cells = <0>; 1003 1004 clock-output-names = "pcie_1_pipe_clk_src"; 1005 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1006 clock-names = "pipe1"; 1007 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1008 reset-names = "lane1"; 1009 }; 1010 1011 pciephy_2: lane@37000 { 1012 reg = <0x037000 0x130>, 1013 <0x037200 0x200>, 1014 <0x037400 0x1dc>; 1015 #phy-cells = <0>; 1016 1017 clock-output-names = "pcie_2_pipe_clk_src"; 1018 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1019 clock-names = "pipe2"; 1020 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1021 reset-names = "lane2"; 1022 }; 1023 }; 1024 1025 phy@7410000 { 1026 compatible = "qcom,msm8996-qmp-usb3-phy"; 1027 reg = <0x7410000 0x1c4>; 1028 #clock-cells = <1>; 1029 #address-cells = <1>; 1030 #size-cells = <1>; 1031 ranges; 1032 1033 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1034 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1035 <&gcc GCC_USB3_CLKREF_CLK>; 1036 clock-names = "aux", "cfg_ahb", "ref"; 1037 1038 vdda-phy-supply = <&pm8994_l28>; 1039 vdda-pll-supply = <&pm8994_l12>; 1040 1041 resets = <&gcc GCC_USB3_PHY_BCR>, 1042 <&gcc GCC_USB3PHY_PHY_BCR>; 1043 reset-names = "phy", "common"; 1044 status = "disabled"; 1045 1046 ssusb_phy_0: lane@7410200 { 1047 reg = <0x7410200 0x200>, 1048 <0x7410400 0x130>, 1049 <0x7410600 0x1a8>; 1050 #phy-cells = <0>; 1051 1052 clock-output-names = "usb3_phy_pipe_clk_src"; 1053 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1054 clock-names = "pipe0"; 1055 }; 1056 }; 1057 1058 hsusb_phy1: phy@7411000 { 1059 compatible = "qcom,msm8996-qusb2-phy"; 1060 reg = <0x7411000 0x180>; 1061 #phy-cells = <0>; 1062 1063 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1064 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1065 clock-names = "cfg_ahb", "ref"; 1066 1067 vdda-pll-supply = <&pm8994_l12>; 1068 vdda-phy-dpdm-supply = <&pm8994_l24>; 1069 1070 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1071 nvmem-cells = <&qusb2p_hstx_trim>; 1072 status = "disabled"; 1073 }; 1074 1075 hsusb_phy2: phy@7412000 { 1076 compatible = "qcom,msm8996-qusb2-phy"; 1077 reg = <0x7412000 0x180>; 1078 #phy-cells = <0>; 1079 1080 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1081 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1082 clock-names = "cfg_ahb", "ref"; 1083 1084 vdda-pll-supply = <&pm8994_l12>; 1085 vdda-phy-dpdm-supply = <&pm8994_l24>; 1086 1087 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1088 nvmem-cells = <&qusb2s_hstx_trim>; 1089 status = "disabled"; 1090 }; 1091 1092 usb2: usb@76f8800 { 1093 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1094 reg = <0x76f8800 0x400>; 1095 #address-cells = <1>; 1096 #size-cells = <1>; 1097 ranges; 1098 1099 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1100 <&gcc GCC_USB20_MASTER_CLK>, 1101 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1102 <&gcc GCC_USB20_SLEEP_CLK>, 1103 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1104 1105 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1106 <&gcc GCC_USB20_MASTER_CLK>; 1107 assigned-clock-rates = <19200000>, <60000000>; 1108 1109 power-domains = <&gcc USB30_GDSC>; 1110 status = "disabled"; 1111 1112 dwc3@7600000 { 1113 compatible = "snps,dwc3"; 1114 reg = <0x7600000 0xcc00>; 1115 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 1116 phys = <&hsusb_phy2>; 1117 phy-names = "usb2-phy"; 1118 }; 1119 }; 1120 1121 usb3: usb@6af8800 { 1122 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1123 reg = <0x6af8800 0x400>; 1124 #address-cells = <1>; 1125 #size-cells = <1>; 1126 ranges; 1127 1128 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1129 <&gcc GCC_USB30_MASTER_CLK>, 1130 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1131 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1132 <&gcc GCC_USB30_SLEEP_CLK>, 1133 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1134 1135 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1136 <&gcc GCC_USB30_MASTER_CLK>; 1137 assigned-clock-rates = <19200000>, <120000000>; 1138 1139 power-domains = <&gcc USB30_GDSC>; 1140 status = "disabled"; 1141 1142 dwc3@6a00000 { 1143 compatible = "snps,dwc3"; 1144 reg = <0x6a00000 0xcc00>; 1145 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1146 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1147 phy-names = "usb2-phy", "usb3-phy"; 1148 }; 1149 }; 1150 1151 vfe_smmu: arm,smmu@da0000 { 1152 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1153 reg = <0xda0000 0x10000>; 1154 1155 #global-interrupts = <1>; 1156 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1160 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1161 <&mmcc SMMU_VFE_AXI_CLK>; 1162 clock-names = "iface", 1163 "bus"; 1164 #iommu-cells = <1>; 1165 status = "disabled"; 1166 }; 1167 1168 camss: camss@a00000 { 1169 compatible = "qcom,msm8996-camss"; 1170 reg = <0xa34000 0x1000>, 1171 <0xa00030 0x4>, 1172 <0xa35000 0x1000>, 1173 <0xa00038 0x4>, 1174 <0xa36000 0x1000>, 1175 <0xa00040 0x4>, 1176 <0xa30000 0x100>, 1177 <0xa30400 0x100>, 1178 <0xa30800 0x100>, 1179 <0xa30c00 0x100>, 1180 <0xa31000 0x500>, 1181 <0xa00020 0x10>, 1182 <0xa10000 0x1000>, 1183 <0xa14000 0x1000>; 1184 reg-names = "csiphy0", 1185 "csiphy0_clk_mux", 1186 "csiphy1", 1187 "csiphy1_clk_mux", 1188 "csiphy2", 1189 "csiphy2_clk_mux", 1190 "csid0", 1191 "csid1", 1192 "csid2", 1193 "csid3", 1194 "ispif", 1195 "csi_clk_mux", 1196 "vfe0", 1197 "vfe1"; 1198 interrupts = <GIC_SPI 78 0>, 1199 <GIC_SPI 79 0>, 1200 <GIC_SPI 80 0>, 1201 <GIC_SPI 296 0>, 1202 <GIC_SPI 297 0>, 1203 <GIC_SPI 298 0>, 1204 <GIC_SPI 299 0>, 1205 <GIC_SPI 309 0>, 1206 <GIC_SPI 314 0>, 1207 <GIC_SPI 315 0>; 1208 interrupt-names = "csiphy0", 1209 "csiphy1", 1210 "csiphy2", 1211 "csid0", 1212 "csid1", 1213 "csid2", 1214 "csid3", 1215 "ispif", 1216 "vfe0", 1217 "vfe1"; 1218 power-domains = <&mmcc VFE0_GDSC>; 1219 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1220 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1221 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1222 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1223 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1224 <&mmcc CAMSS_CSI0_AHB_CLK>, 1225 <&mmcc CAMSS_CSI0_CLK>, 1226 <&mmcc CAMSS_CSI0PHY_CLK>, 1227 <&mmcc CAMSS_CSI0PIX_CLK>, 1228 <&mmcc CAMSS_CSI0RDI_CLK>, 1229 <&mmcc CAMSS_CSI1_AHB_CLK>, 1230 <&mmcc CAMSS_CSI1_CLK>, 1231 <&mmcc CAMSS_CSI1PHY_CLK>, 1232 <&mmcc CAMSS_CSI1PIX_CLK>, 1233 <&mmcc CAMSS_CSI1RDI_CLK>, 1234 <&mmcc CAMSS_CSI2_AHB_CLK>, 1235 <&mmcc CAMSS_CSI2_CLK>, 1236 <&mmcc CAMSS_CSI2PHY_CLK>, 1237 <&mmcc CAMSS_CSI2PIX_CLK>, 1238 <&mmcc CAMSS_CSI2RDI_CLK>, 1239 <&mmcc CAMSS_CSI3_AHB_CLK>, 1240 <&mmcc CAMSS_CSI3_CLK>, 1241 <&mmcc CAMSS_CSI3PHY_CLK>, 1242 <&mmcc CAMSS_CSI3PIX_CLK>, 1243 <&mmcc CAMSS_CSI3RDI_CLK>, 1244 <&mmcc CAMSS_AHB_CLK>, 1245 <&mmcc CAMSS_VFE0_CLK>, 1246 <&mmcc CAMSS_CSI_VFE0_CLK>, 1247 <&mmcc CAMSS_VFE0_AHB_CLK>, 1248 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1249 <&mmcc CAMSS_VFE1_CLK>, 1250 <&mmcc CAMSS_CSI_VFE1_CLK>, 1251 <&mmcc CAMSS_VFE1_AHB_CLK>, 1252 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1253 <&mmcc CAMSS_VFE_AHB_CLK>, 1254 <&mmcc CAMSS_VFE_AXI_CLK>; 1255 clock-names = "top_ahb", 1256 "ispif_ahb", 1257 "csiphy0_timer", 1258 "csiphy1_timer", 1259 "csiphy2_timer", 1260 "csi0_ahb", 1261 "csi0", 1262 "csi0_phy", 1263 "csi0_pix", 1264 "csi0_rdi", 1265 "csi1_ahb", 1266 "csi1", 1267 "csi1_phy", 1268 "csi1_pix", 1269 "csi1_rdi", 1270 "csi2_ahb", 1271 "csi2", 1272 "csi2_phy", 1273 "csi2_pix", 1274 "csi2_rdi", 1275 "csi3_ahb", 1276 "csi3", 1277 "csi3_phy", 1278 "csi3_pix", 1279 "csi3_rdi", 1280 "ahb", 1281 "vfe0", 1282 "csi_vfe0", 1283 "vfe0_ahb", 1284 "vfe0_stream", 1285 "vfe1", 1286 "csi_vfe1", 1287 "vfe1_ahb", 1288 "vfe1_stream", 1289 "vfe_ahb", 1290 "vfe_axi"; 1291 vdda-supply = <&pm8994_l2>; 1292 iommus = <&vfe_smmu 0>, 1293 <&vfe_smmu 1>, 1294 <&vfe_smmu 2>, 1295 <&vfe_smmu 3>; 1296 status = "disabled"; 1297 ports { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 }; 1301 }; 1302 1303 adreno_smmu: arm,smmu@b40000 { 1304 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1305 reg = <0xb40000 0x10000>; 1306 1307 #global-interrupts = <1>; 1308 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1311 #iommu-cells = <1>; 1312 1313 clocks = <&mmcc GPU_AHB_CLK>, 1314 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1315 clock-names = "iface", "bus"; 1316 1317 power-domains = <&mmcc GPU_GDSC>; 1318 1319 status = "disabled"; 1320 }; 1321 1322 mdp_smmu: arm,smmu@d00000 { 1323 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1324 reg = <0xd00000 0x10000>; 1325 1326 #global-interrupts = <1>; 1327 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1330 #iommu-cells = <1>; 1331 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1332 <&mmcc SMMU_MDP_AXI_CLK>; 1333 clock-names = "iface", "bus"; 1334 1335 power-domains = <&mmcc MDSS_GDSC>; 1336 1337 status = "disabled"; 1338 }; 1339 1340 lpass_q6_smmu: arm,smmu-lpass_q6@1600000 { 1341 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1342 reg = <0x1600000 0x20000>; 1343 #iommu-cells = <1>; 1344 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1345 1346 #global-interrupts = <1>; 1347 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1360 1361 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1362 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1363 clock-names = "iface", "bus"; 1364 status = "disabled"; 1365 }; 1366 1367 agnoc@0 { 1368 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1369 compatible = "simple-pm-bus"; 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 ranges; 1373 1374 pcie0: pcie@600000 { 1375 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1376 status = "disabled"; 1377 power-domains = <&gcc PCIE0_GDSC>; 1378 bus-range = <0x00 0xff>; 1379 num-lanes = <1>; 1380 1381 reg = <0x00600000 0x2000>, 1382 <0x0c000000 0xf1d>, 1383 <0x0c000f20 0xa8>, 1384 <0x0c100000 0x100000>; 1385 reg-names = "parf", "dbi", "elbi","config"; 1386 1387 phys = <&pciephy_0>; 1388 phy-names = "pciephy"; 1389 1390 #address-cells = <3>; 1391 #size-cells = <2>; 1392 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1393 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1394 1395 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1396 interrupt-names = "msi"; 1397 #interrupt-cells = <1>; 1398 interrupt-map-mask = <0 0 0 0x7>; 1399 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1400 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1401 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1402 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1403 1404 pinctrl-names = "default", "sleep"; 1405 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 1406 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 1407 1408 1409 vdda-supply = <&pm8994_l28>; 1410 1411 linux,pci-domain = <0>; 1412 1413 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1414 <&gcc GCC_PCIE_0_AUX_CLK>, 1415 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1416 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1417 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1418 1419 clock-names = "pipe", 1420 "aux", 1421 "cfg", 1422 "bus_master", 1423 "bus_slave"; 1424 1425 }; 1426 1427 pcie1: pcie@608000 { 1428 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1429 power-domains = <&gcc PCIE1_GDSC>; 1430 bus-range = <0x00 0xff>; 1431 num-lanes = <1>; 1432 1433 status = "disabled"; 1434 1435 reg = <0x00608000 0x2000>, 1436 <0x0d000000 0xf1d>, 1437 <0x0d000f20 0xa8>, 1438 <0x0d100000 0x100000>; 1439 1440 reg-names = "parf", "dbi", "elbi","config"; 1441 1442 phys = <&pciephy_1>; 1443 phy-names = "pciephy"; 1444 1445 #address-cells = <3>; 1446 #size-cells = <2>; 1447 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1448 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1449 1450 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1451 interrupt-names = "msi"; 1452 #interrupt-cells = <1>; 1453 interrupt-map-mask = <0 0 0 0x7>; 1454 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1455 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1456 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1457 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1458 1459 pinctrl-names = "default", "sleep"; 1460 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 1461 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 1462 1463 1464 vdda-supply = <&pm8994_l28>; 1465 linux,pci-domain = <1>; 1466 1467 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1468 <&gcc GCC_PCIE_1_AUX_CLK>, 1469 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1470 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1471 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1472 1473 clock-names = "pipe", 1474 "aux", 1475 "cfg", 1476 "bus_master", 1477 "bus_slave"; 1478 }; 1479 1480 pcie2: pcie@610000 { 1481 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1482 power-domains = <&gcc PCIE2_GDSC>; 1483 bus-range = <0x00 0xff>; 1484 num-lanes = <1>; 1485 status = "disabled"; 1486 reg = <0x00610000 0x2000>, 1487 <0x0e000000 0xf1d>, 1488 <0x0e000f20 0xa8>, 1489 <0x0e100000 0x100000>; 1490 1491 reg-names = "parf", "dbi", "elbi","config"; 1492 1493 phys = <&pciephy_2>; 1494 phy-names = "pciephy"; 1495 1496 #address-cells = <3>; 1497 #size-cells = <2>; 1498 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1499 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1500 1501 device_type = "pci"; 1502 1503 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1504 interrupt-names = "msi"; 1505 #interrupt-cells = <1>; 1506 interrupt-map-mask = <0 0 0 0x7>; 1507 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1508 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1509 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1510 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1511 1512 pinctrl-names = "default", "sleep"; 1513 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 1514 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 1515 1516 vdda-supply = <&pm8994_l28>; 1517 1518 linux,pci-domain = <2>; 1519 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1520 <&gcc GCC_PCIE_2_AUX_CLK>, 1521 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1522 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1523 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1524 1525 clock-names = "pipe", 1526 "aux", 1527 "cfg", 1528 "bus_master", 1529 "bus_slave"; 1530 }; 1531 }; 1532 1533 slimbam:dma@9184000 1534 { 1535 compatible = "qcom,bam-v1.7.0"; 1536 qcom,controlled-remotely; 1537 reg = <0x9184000 0x32000>; 1538 num-channels = <31>; 1539 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 1540 #dma-cells = <1>; 1541 qcom,ee = <1>; 1542 qcom,num-ees = <2>; 1543 }; 1544 1545 slim_msm: slim@91c0000 { 1546 compatible = "qcom,slim-ngd-v1.5.0"; 1547 reg = <0x91c0000 0x2C000>; 1548 reg-names = "ctrl"; 1549 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 1550 dmas = <&slimbam 3>, <&slimbam 4>, 1551 <&slimbam 5>, <&slimbam 6>; 1552 dma-names = "rx", "tx", "tx2", "rx2"; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 ngd@1 { 1556 reg = <1>; 1557 #address-cells = <1>; 1558 #size-cells = <1>; 1559 1560 tasha_ifd: tas-ifd { 1561 compatible = "slim217,1a0"; 1562 reg = <0 0>; 1563 }; 1564 1565 wcd9335: codec@1{ 1566 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 1567 pinctrl-names = "default"; 1568 1569 compatible = "slim217,1a0"; 1570 reg = <1 0>; 1571 1572 interrupt-parent = <&msmgpio>; 1573 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 1574 <53 IRQ_TYPE_LEVEL_HIGH>; 1575 interrupt-names = "intr1", "intr2"; 1576 interrupt-controller; 1577 #interrupt-cells = <1>; 1578 reset-gpios = <&msmgpio 64 0>; 1579 1580 slim-ifc-dev = <&tasha_ifd>; 1581 1582 vdd-buck-supply = <&pm8994_s4>; 1583 vdd-buck-sido-supply = <&pm8994_s4>; 1584 vdd-tx-supply = <&pm8994_s4>; 1585 vdd-rx-supply = <&pm8994_s4>; 1586 vdd-io-supply = <&pm8994_s4>; 1587 1588 #sound-dai-cells = <1>; 1589 }; 1590 }; 1591 }; 1592 1593 gpu@b00000 { 1594 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1595 #stream-id-cells = <16>; 1596 1597 reg = <0xb00000 0x3f000>; 1598 reg-names = "kgsl_3d0_reg_memory"; 1599 1600 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1601 1602 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1603 <&mmcc GPU_AHB_CLK>, 1604 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1605 <&gcc GCC_BIMC_GFX_CLK>, 1606 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1607 1608 clock-names = "core", 1609 "iface", 1610 "rbbmtimer", 1611 "mem", 1612 "mem_iface"; 1613 1614 power-domains = <&mmcc GPU_GDSC>; 1615 iommus = <&adreno_smmu 0>; 1616 1617 nvmem-cells = <&gpu_speed_bin>; 1618 nvmem-cell-names = "speed_bin"; 1619 1620 qcom,gpu-quirk-two-pass-use-wfi; 1621 qcom,gpu-quirk-fault-detect-mask; 1622 1623 operating-points-v2 = <&gpu_opp_table>; 1624 1625 gpu_opp_table: opp-table { 1626 compatible ="operating-points-v2"; 1627 1628 /* 1629 * 624Mhz and 560Mhz are only available on speed 1630 * bin (1 << 0). All the rest are available on 1631 * all bins of the hardware 1632 */ 1633 opp-624000000 { 1634 opp-hz = /bits/ 64 <624000000>; 1635 opp-supported-hw = <0x01>; 1636 }; 1637 opp-560000000 { 1638 opp-hz = /bits/ 64 <560000000>; 1639 opp-supported-hw = <0x01>; 1640 }; 1641 opp-510000000 { 1642 opp-hz = /bits/ 64 <510000000>; 1643 opp-supported-hw = <0xFF>; 1644 }; 1645 opp-401800000 { 1646 opp-hz = /bits/ 64 <401800000>; 1647 opp-supported-hw = <0xFF>; 1648 }; 1649 opp-315000000 { 1650 opp-hz = /bits/ 64 <315000000>; 1651 opp-supported-hw = <0xFF>; 1652 }; 1653 opp-214000000 { 1654 opp-hz = /bits/ 64 <214000000>; 1655 opp-supported-hw = <0xFF>; 1656 }; 1657 opp-133000000 { 1658 opp-hz = /bits/ 64 <133000000>; 1659 opp-supported-hw = <0xFF>; 1660 }; 1661 }; 1662 1663 zap-shader { 1664 memory-region = <&zap_shader_region>; 1665 }; 1666 }; 1667 1668 mdss: mdss@900000 { 1669 compatible = "qcom,mdss"; 1670 1671 reg = <0x900000 0x1000>, 1672 <0x9b0000 0x1040>, 1673 <0x9b8000 0x1040>; 1674 reg-names = "mdss_phys", 1675 "vbif_phys", 1676 "vbif_nrt_phys"; 1677 1678 power-domains = <&mmcc MDSS_GDSC>; 1679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1680 1681 interrupt-controller; 1682 #interrupt-cells = <1>; 1683 1684 clocks = <&mmcc MDSS_AHB_CLK>; 1685 clock-names = "iface_clk"; 1686 1687 #address-cells = <1>; 1688 #size-cells = <1>; 1689 ranges; 1690 1691 mdp: mdp@901000 { 1692 compatible = "qcom,mdp5"; 1693 reg = <0x901000 0x90000>; 1694 reg-names = "mdp_phys"; 1695 1696 interrupt-parent = <&mdss>; 1697 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1698 1699 clocks = <&mmcc MDSS_AHB_CLK>, 1700 <&mmcc MDSS_AXI_CLK>, 1701 <&mmcc MDSS_MDP_CLK>, 1702 <&mmcc SMMU_MDP_AXI_CLK>, 1703 <&mmcc MDSS_VSYNC_CLK>; 1704 clock-names = "iface_clk", 1705 "bus_clk", 1706 "core_clk", 1707 "iommu_clk", 1708 "vsync_clk"; 1709 1710 iommus = <&mdp_smmu 0>; 1711 1712 ports { 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 port@0 { 1717 reg = <0>; 1718 mdp5_intf3_out: endpoint { 1719 remote-endpoint = <&hdmi_in>; 1720 }; 1721 }; 1722 }; 1723 }; 1724 1725 hdmi: hdmi-tx@9a0000 { 1726 compatible = "qcom,hdmi-tx-8996"; 1727 reg = <0x009a0000 0x50c>, 1728 <0x00070000 0x6158>, 1729 <0x009e0000 0xfff>; 1730 reg-names = "core_physical", 1731 "qfprom_physical", 1732 "hdcp_physical"; 1733 1734 interrupt-parent = <&mdss>; 1735 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1736 1737 clocks = <&mmcc MDSS_MDP_CLK>, 1738 <&mmcc MDSS_AHB_CLK>, 1739 <&mmcc MDSS_HDMI_CLK>, 1740 <&mmcc MDSS_HDMI_AHB_CLK>, 1741 <&mmcc MDSS_EXTPCLK_CLK>; 1742 clock-names = 1743 "mdp_core_clk", 1744 "iface_clk", 1745 "core_clk", 1746 "alt_iface_clk", 1747 "extp_clk"; 1748 1749 phys = <&hdmi_phy>; 1750 phy-names = "hdmi_phy"; 1751 #sound-dai-cells = <1>; 1752 1753 ports { 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 port@0 { 1758 reg = <0>; 1759 hdmi_in: endpoint { 1760 remote-endpoint = <&mdp5_intf3_out>; 1761 }; 1762 }; 1763 }; 1764 }; 1765 1766 hdmi_phy: hdmi-phy@9a0600 { 1767 #phy-cells = <0>; 1768 compatible = "qcom,hdmi-phy-8996"; 1769 reg = <0x9a0600 0x1c4>, 1770 <0x9a0a00 0x124>, 1771 <0x9a0c00 0x124>, 1772 <0x9a0e00 0x124>, 1773 <0x9a1000 0x124>, 1774 <0x9a1200 0x0c8>; 1775 reg-names = "hdmi_pll", 1776 "hdmi_tx_l0", 1777 "hdmi_tx_l1", 1778 "hdmi_tx_l2", 1779 "hdmi_tx_l3", 1780 "hdmi_phy"; 1781 1782 clocks = <&mmcc MDSS_AHB_CLK>, 1783 <&gcc GCC_HDMI_CLKREF_CLK>; 1784 clock-names = "iface_clk", 1785 "ref_clk"; 1786 }; 1787 }; 1788 }; 1789 1790 sound: sound { 1791 }; 1792 1793 adsp-pil { 1794 compatible = "qcom,msm8996-adsp-pil"; 1795 1796 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 1797 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1798 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1799 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1800 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1801 interrupt-names = "wdog", "fatal", "ready", 1802 "handover", "stop-ack"; 1803 1804 clocks = <&xo_board>; 1805 clock-names = "xo"; 1806 1807 memory-region = <&adsp_region>; 1808 1809 qcom,smem-states = <&adsp_smp2p_out 0>; 1810 qcom,smem-state-names = "stop"; 1811 1812 smd-edge { 1813 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1814 1815 label = "lpass"; 1816 mboxes = <&apcs_glb 8>; 1817 qcom,smd-edge = <1>; 1818 qcom,remote-pid = <2>; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 apr { 1822 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 1823 compatible = "qcom,apr-v2"; 1824 qcom,smd-channels = "apr_audio_svc"; 1825 reg = <APR_DOMAIN_ADSP>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 q6core { 1830 reg = <APR_SVC_ADSP_CORE>; 1831 compatible = "qcom,q6core"; 1832 }; 1833 1834 q6afe: q6afe { 1835 compatible = "qcom,q6afe"; 1836 reg = <APR_SVC_AFE>; 1837 q6afedai: dais { 1838 compatible = "qcom,q6afe-dais"; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 #sound-dai-cells = <1>; 1842 hdmi@1 { 1843 reg = <1>; 1844 }; 1845 }; 1846 }; 1847 1848 q6asm: q6asm { 1849 compatible = "qcom,q6asm"; 1850 reg = <APR_SVC_ASM>; 1851 q6asmdai: dais { 1852 compatible = "qcom,q6asm-dais"; 1853 #sound-dai-cells = <1>; 1854 iommus = <&lpass_q6_smmu 1>; 1855 }; 1856 }; 1857 1858 q6adm: q6adm { 1859 compatible = "qcom,q6adm"; 1860 reg = <APR_SVC_ADM>; 1861 q6routing: routing { 1862 compatible = "qcom,q6adm-routing"; 1863 #sound-dai-cells = <0>; 1864 }; 1865 }; 1866 }; 1867 1868 }; 1869 }; 1870 1871 adsp-smp2p { 1872 compatible = "qcom,smp2p"; 1873 qcom,smem = <443>, <429>; 1874 1875 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 1876 1877 mboxes = <&apcs_glb 10>; 1878 1879 qcom,local-pid = <0>; 1880 qcom,remote-pid = <2>; 1881 1882 adsp_smp2p_out: master-kernel { 1883 qcom,entry-name = "master-kernel"; 1884 #qcom,smem-state-cells = <1>; 1885 }; 1886 1887 adsp_smp2p_in: slave-kernel { 1888 qcom,entry-name = "slave-kernel"; 1889 1890 interrupt-controller; 1891 #interrupt-cells = <2>; 1892 }; 1893 }; 1894 1895 modem-smp2p { 1896 compatible = "qcom,smp2p"; 1897 qcom,smem = <435>, <428>; 1898 1899 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1900 1901 mboxes = <&apcs_glb 14>; 1902 1903 qcom,local-pid = <0>; 1904 qcom,remote-pid = <1>; 1905 1906 modem_smp2p_out: master-kernel { 1907 qcom,entry-name = "master-kernel"; 1908 #qcom,smem-state-cells = <1>; 1909 }; 1910 1911 modem_smp2p_in: slave-kernel { 1912 qcom,entry-name = "slave-kernel"; 1913 1914 interrupt-controller; 1915 #interrupt-cells = <2>; 1916 }; 1917 }; 1918 1919 smp2p-slpi { 1920 compatible = "qcom,smp2p"; 1921 qcom,smem = <481>, <430>; 1922 1923 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 1924 1925 mboxes = <&apcs_glb 26>; 1926 1927 qcom,local-pid = <0>; 1928 qcom,remote-pid = <3>; 1929 1930 slpi_smp2p_in: slave-kernel { 1931 qcom,entry-name = "slave-kernel"; 1932 interrupt-controller; 1933 #interrupt-cells = <2>; 1934 }; 1935 1936 slpi_smp2p_out: master-kernel { 1937 qcom,entry-name = "master-kernel"; 1938 #qcom,smem-state-cells = <1>; 1939 }; 1940 }; 1941 1942}; 1943#include "msm8996-pins.dtsi" 1944