1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8994.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8994.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc1 = &sdhc1; 21 mmc2 = &sdhc2; 22 }; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x1>; 62 enable-method = "psci"; 63 next-level-cache = <&L2_0>; 64 }; 65 66 CPU2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 next-level-cache = <&L2_0>; 80 }; 81 82 CPU4: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a57"; 85 reg = <0x0 0x100>; 86 enable-method = "psci"; 87 next-level-cache = <&L2_1>; 88 L2_1: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 }; 92 }; 93 94 CPU5: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x0 0x101>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_1>; 100 }; 101 102 CPU6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a57"; 105 reg = <0x0 0x102>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_1>; 108 }; 109 110 CPU7: cpu@103 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a57"; 113 reg = <0x0 0x103>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_1>; 116 }; 117 118 cpu-map { 119 cluster0 { 120 core0 { 121 cpu = <&CPU0>; 122 }; 123 124 core1 { 125 cpu = <&CPU1>; 126 }; 127 128 core2 { 129 cpu = <&CPU2>; 130 }; 131 132 core3 { 133 cpu = <&CPU3>; 134 }; 135 }; 136 137 cluster1 { 138 core0 { 139 cpu = <&CPU4>; 140 }; 141 142 core1 { 143 cpu = <&CPU5>; 144 }; 145 146 cpu6_map: core2 { 147 cpu = <&CPU6>; 148 }; 149 150 cpu7_map: core3 { 151 cpu = <&CPU7>; 152 }; 153 }; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-msm8994", "qcom,scm"; 160 }; 161 }; 162 163 memory@80000000 { 164 device_type = "memory"; 165 /* We expect the bootloader to fill in the reg */ 166 reg = <0 0x80000000 0 0>; 167 }; 168 169 pmu { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 psci { 175 compatible = "arm,psci-0.2"; 176 method = "hvc"; 177 }; 178 179 reserved-memory { 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 dfps_data_mem: dfps_data_mem@3400000 { 185 reg = <0 0x03400000 0 0x1000>; 186 no-map; 187 }; 188 189 cont_splash_mem: memory@3401000 { 190 reg = <0 0x03401000 0 0x2200000>; 191 no-map; 192 }; 193 194 smem_mem: smem_region@6a00000 { 195 reg = <0 0x06a00000 0 0x200000>; 196 no-map; 197 }; 198 199 mpss_mem: memory@7000000 { 200 reg = <0 0x07000000 0 0x5a00000>; 201 no-map; 202 }; 203 204 peripheral_region: memory@ca00000 { 205 reg = <0 0x0ca00000 0 0x1f00000>; 206 no-map; 207 }; 208 209 rmtfs_mem: memory@c6400000 { 210 compatible = "qcom,rmtfs-mem"; 211 reg = <0 0xc6400000 0 0x180000>; 212 no-map; 213 214 qcom,client-id = <1>; 215 }; 216 217 mba_mem: memory@c6700000 { 218 reg = <0 0xc6700000 0 0x100000>; 219 no-map; 220 }; 221 222 audio_mem: memory@c7000000 { 223 reg = <0 0xc7000000 0 0x800000>; 224 no-map; 225 }; 226 227 adsp_mem: memory@c9400000 { 228 reg = <0 0xc9400000 0 0x3f00000>; 229 no-map; 230 }; 231 232 reserved@6c00000 { 233 reg = <0 0x06c00000 0 0x400000>; 234 no-map; 235 }; 236 }; 237 238 smd { 239 compatible = "qcom,smd"; 240 rpm { 241 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 242 qcom,ipc = <&apcs 8 0>; 243 qcom,smd-edge = <15>; 244 qcom,remote-pid = <6>; 245 246 rpm_requests: rpm-requests { 247 compatible = "qcom,rpm-msm8994"; 248 qcom,smd-channels = "rpm_requests"; 249 250 rpmcc: clock-controller { 251 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; 252 #clock-cells = <1>; 253 }; 254 255 rpmpd: power-controller { 256 compatible = "qcom,msm8994-rpmpd"; 257 #power-domain-cells = <1>; 258 operating-points-v2 = <&rpmpd_opp_table>; 259 260 rpmpd_opp_table: opp-table { 261 compatible = "operating-points-v2"; 262 263 rpmpd_opp_ret: opp1 { 264 opp-level = <1>; 265 }; 266 rpmpd_opp_svs_krait: opp2 { 267 opp-level = <2>; 268 }; 269 rpmpd_opp_svs_soc: opp3 { 270 opp-level = <3>; 271 }; 272 rpmpd_opp_nom: opp4 { 273 opp-level = <4>; 274 }; 275 rpmpd_opp_turbo: opp5 { 276 opp-level = <5>; 277 }; 278 rpmpd_opp_super_turbo: opp6 { 279 opp-level = <6>; 280 }; 281 }; 282 }; 283 }; 284 }; 285 }; 286 287 smem { 288 compatible = "qcom,smem"; 289 memory-region = <&smem_mem>; 290 qcom,rpm-msg-ram = <&rpm_msg_ram>; 291 hwlocks = <&tcsr_mutex 3>; 292 }; 293 294 smp2p-lpass { 295 compatible = "qcom,smp2p"; 296 qcom,smem = <443>, <429>; 297 298 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 299 300 qcom,ipc = <&apcs 8 10>; 301 302 qcom,local-pid = <0>; 303 qcom,remote-pid = <2>; 304 305 adsp_smp2p_out: master-kernel { 306 qcom,entry-name = "master-kernel"; 307 #qcom,smem-state-cells = <1>; 308 }; 309 310 adsp_smp2p_in: slave-kernel { 311 qcom,entry-name = "slave-kernel"; 312 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 }; 317 318 smp2p-modem { 319 compatible = "qcom,smp2p"; 320 qcom,smem = <435>, <428>; 321 322 interrupt-parent = <&intc>; 323 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 324 325 qcom,ipc = <&apcs 8 14>; 326 327 qcom,local-pid = <0>; 328 qcom,remote-pid = <1>; 329 330 modem_smp2p_out: master-kernel { 331 qcom,entry-name = "master-kernel"; 332 #qcom,smem-state-cells = <1>; 333 }; 334 335 modem_smp2p_in: slave-kernel { 336 qcom,entry-name = "slave-kernel"; 337 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 }; 342 343 soc: soc { 344 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges = <0 0 0 0xffffffff>; 348 compatible = "simple-bus"; 349 350 intc: interrupt-controller@f9000000 { 351 compatible = "qcom,msm-qgic2"; 352 interrupt-controller; 353 #interrupt-cells = <3>; 354 reg = <0xf9000000 0x1000>, 355 <0xf9002000 0x1000>; 356 }; 357 358 apcs: mailbox@f900d000 { 359 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 360 reg = <0xf900d000 0x2000>; 361 #mbox-cells = <1>; 362 }; 363 364 watchdog@f9017000 { 365 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; 366 reg = <0xf9017000 0x1000>; 367 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 369 clocks = <&sleep_clk>; 370 timeout-sec = <10>; 371 }; 372 373 timer@f9020000 { 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges; 377 compatible = "arm,armv7-timer-mem"; 378 reg = <0xf9020000 0x1000>; 379 380 frame@f9021000 { 381 frame-number = <0>; 382 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 384 reg = <0xf9021000 0x1000>, 385 <0xf9022000 0x1000>; 386 }; 387 388 frame@f9023000 { 389 frame-number = <1>; 390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0xf9023000 0x1000>; 392 status = "disabled"; 393 }; 394 395 frame@f9024000 { 396 frame-number = <2>; 397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0xf9024000 0x1000>; 399 status = "disabled"; 400 }; 401 402 frame@f9025000 { 403 frame-number = <3>; 404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 405 reg = <0xf9025000 0x1000>; 406 status = "disabled"; 407 }; 408 409 frame@f9026000 { 410 frame-number = <4>; 411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0xf9026000 0x1000>; 413 status = "disabled"; 414 }; 415 416 frame@f9027000 { 417 frame-number = <5>; 418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0xf9027000 0x1000>; 420 status = "disabled"; 421 }; 422 423 frame@f9028000 { 424 frame-number = <6>; 425 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 426 reg = <0xf9028000 0x1000>; 427 status = "disabled"; 428 }; 429 }; 430 431 usb3: usb@f92f8800 { 432 compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; 433 reg = <0xf92f8800 0x400>; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges; 437 438 clocks = <&gcc GCC_USB30_MASTER_CLK>, 439 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 440 <&gcc GCC_USB30_SLEEP_CLK>, 441 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 442 clock-names = "core", 443 "iface", 444 "sleep", 445 "mock_utmi"; 446 447 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 448 <&gcc GCC_USB30_MASTER_CLK>; 449 assigned-clock-rates = <19200000>, <120000000>; 450 451 power-domains = <&gcc USB30_GDSC>; 452 qcom,select-utmi-as-pipe-clk; 453 454 usb@f9200000 { 455 compatible = "snps,dwc3"; 456 reg = <0xf9200000 0xcc00>; 457 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 458 snps,dis_u2_susphy_quirk; 459 snps,dis_enblslpm_quirk; 460 maximum-speed = "high-speed"; 461 dr_mode = "peripheral"; 462 }; 463 }; 464 465 sdhc1: mmc@f9824900 { 466 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 467 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 468 reg-names = "hc", "core"; 469 470 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "hc_irq", "pwr_irq"; 473 474 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 475 <&gcc GCC_SDCC1_APPS_CLK>, 476 <&xo_board>; 477 clock-names = "iface", "core", "xo"; 478 479 pinctrl-names = "default", "sleep"; 480 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 481 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 482 483 bus-width = <8>; 484 non-removable; 485 status = "disabled"; 486 }; 487 488 sdhc2: mmc@f98a4900 { 489 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 490 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 491 reg-names = "hc", "core"; 492 493 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "hc_irq", "pwr_irq"; 496 497 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 498 <&gcc GCC_SDCC2_APPS_CLK>, 499 <&xo_board>; 500 clock-names = "iface", "core", "xo"; 501 502 pinctrl-names = "default", "sleep"; 503 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 504 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 505 506 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; 507 bus-width = <4>; 508 status = "disabled"; 509 }; 510 511 blsp1_dma: dma-controller@f9904000 { 512 compatible = "qcom,bam-v1.7.0"; 513 reg = <0xf9904000 0x19000>; 514 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 516 clock-names = "bam_clk"; 517 #dma-cells = <1>; 518 qcom,ee = <0>; 519 qcom,controlled-remotely; 520 num-channels = <24>; 521 qcom,num-ees = <4>; 522 }; 523 524 blsp1_uart2: serial@f991e000 { 525 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 526 reg = <0xf991e000 0x1000>; 527 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 528 clock-names = "core", "iface"; 529 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 530 <&gcc GCC_BLSP1_AHB_CLK>; 531 pinctrl-names = "default", "sleep"; 532 pinctrl-0 = <&blsp1_uart2_default>; 533 pinctrl-1 = <&blsp1_uart2_sleep>; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c1: i2c@f9923000 { 538 compatible = "qcom,i2c-qup-v2.2.1"; 539 reg = <0xf9923000 0x500>; 540 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 542 <&gcc GCC_BLSP1_AHB_CLK>; 543 clock-names = "core", "iface"; 544 clock-frequency = <400000>; 545 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 546 dma-names = "tx", "rx"; 547 pinctrl-names = "default", "sleep"; 548 pinctrl-0 = <&i2c1_default>; 549 pinctrl-1 = <&i2c1_sleep>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 }; 554 555 blsp1_spi1: spi@f9923000 { 556 compatible = "qcom,spi-qup-v2.2.1"; 557 reg = <0xf9923000 0x500>; 558 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 560 <&gcc GCC_BLSP1_AHB_CLK>; 561 clock-names = "core", "iface"; 562 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 563 dma-names = "tx", "rx"; 564 pinctrl-names = "default", "sleep"; 565 pinctrl-0 = <&blsp1_spi1_default>; 566 pinctrl-1 = <&blsp1_spi1_sleep>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 blsp1_i2c2: i2c@f9924000 { 573 compatible = "qcom,i2c-qup-v2.2.1"; 574 reg = <0xf9924000 0x500>; 575 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 577 <&gcc GCC_BLSP1_AHB_CLK>; 578 clock-names = "core", "iface"; 579 clock-frequency = <400000>; 580 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 581 dma-names = "tx", "rx"; 582 pinctrl-names = "default", "sleep"; 583 pinctrl-0 = <&i2c2_default>; 584 pinctrl-1 = <&i2c2_sleep>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 /* I2C3 doesn't exist */ 591 592 blsp1_i2c4: i2c@f9926000 { 593 compatible = "qcom,i2c-qup-v2.2.1"; 594 reg = <0xf9926000 0x500>; 595 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 597 <&gcc GCC_BLSP1_AHB_CLK>; 598 clock-names = "core", "iface"; 599 clock-frequency = <400000>; 600 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; 601 dma-names = "tx", "rx"; 602 pinctrl-names = "default", "sleep"; 603 pinctrl-0 = <&i2c4_default>; 604 pinctrl-1 = <&i2c4_sleep>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 blsp1_i2c5: i2c@f9927000 { 611 compatible = "qcom,i2c-qup-v2.2.1"; 612 reg = <0xf9927000 0x500>; 613 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 615 <&gcc GCC_BLSP1_AHB_CLK>; 616 clock-names = "core", "iface"; 617 clock-frequency = <400000>; 618 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 619 dma-names = "tx", "rx"; 620 pinctrl-names = "default", "sleep"; 621 pinctrl-0 = <&i2c5_default>; 622 pinctrl-1 = <&i2c5_sleep>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 blsp1_i2c6: i2c@f9928000 { 629 compatible = "qcom,i2c-qup-v2.2.1"; 630 reg = <0xf9928000 0x500>; 631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 633 <&gcc GCC_BLSP1_AHB_CLK>; 634 clock-names = "core", "iface"; 635 clock-frequency = <400000>; 636 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 637 dma-names = "tx", "rx"; 638 pinctrl-names = "default", "sleep"; 639 pinctrl-0 = <&i2c6_default>; 640 pinctrl-1 = <&i2c6_sleep>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 status = "disabled"; 644 }; 645 646 blsp2_dma: dma-controller@f9944000 { 647 compatible = "qcom,bam-v1.7.0"; 648 reg = <0xf9944000 0x19000>; 649 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 651 clock-names = "bam_clk"; 652 #dma-cells = <1>; 653 qcom,ee = <0>; 654 qcom,controlled-remotely; 655 num-channels = <24>; 656 qcom,num-ees = <4>; 657 }; 658 659 blsp2_uart2: serial@f995e000 { 660 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 661 reg = <0xf995e000 0x1000>; 662 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 663 clock-names = "core", "iface"; 664 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 665 <&gcc GCC_BLSP2_AHB_CLK>; 666 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 667 dma-names = "tx", "rx"; 668 pinctrl-names = "default", "sleep"; 669 pinctrl-0 = <&blsp2_uart2_default>; 670 pinctrl-1 = <&blsp2_uart2_sleep>; 671 status = "disabled"; 672 }; 673 674 blsp2_i2c1: i2c@f9963000 { 675 compatible = "qcom,i2c-qup-v2.2.1"; 676 reg = <0xf9963000 0x500>; 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 679 <&gcc GCC_BLSP2_AHB_CLK>; 680 clock-names = "core", "iface"; 681 clock-frequency = <400000>; 682 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 683 dma-names = "tx", "rx"; 684 pinctrl-names = "default", "sleep"; 685 pinctrl-0 = <&i2c7_default>; 686 pinctrl-1 = <&i2c7_sleep>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 blsp2_spi4: spi@f9966000 { 693 compatible = "qcom,spi-qup-v2.2.1"; 694 reg = <0xf9966000 0x500>; 695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 697 <&gcc GCC_BLSP2_AHB_CLK>; 698 clock-names = "core", "iface"; 699 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; 700 dma-names = "tx", "rx"; 701 pinctrl-names = "default", "sleep"; 702 pinctrl-0 = <&blsp2_spi10_default>; 703 pinctrl-1 = <&blsp2_spi10_sleep>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 status = "disabled"; 707 }; 708 709 blsp2_i2c5: i2c@f9967000 { 710 compatible = "qcom,i2c-qup-v2.2.1"; 711 reg = <0xf9967000 0x500>; 712 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 714 <&gcc GCC_BLSP2_AHB_CLK>; 715 clock-names = "core", "iface"; 716 clock-frequency = <355000>; 717 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 718 dma-names = "tx", "rx"; 719 pinctrl-names = "default", "sleep"; 720 pinctrl-0 = <&i2c11_default>; 721 pinctrl-1 = <&i2c11_sleep>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 status = "disabled"; 725 }; 726 727 gcc: clock-controller@fc400000 { 728 compatible = "qcom,gcc-msm8994"; 729 #clock-cells = <1>; 730 #reset-cells = <1>; 731 #power-domain-cells = <1>; 732 reg = <0xfc400000 0x2000>; 733 734 clock-names = "xo", "sleep"; 735 clocks = <&xo_board>, <&sleep_clk>; 736 }; 737 738 rpm_msg_ram: sram@fc428000 { 739 compatible = "qcom,rpm-msg-ram"; 740 reg = <0xfc428000 0x4000>; 741 }; 742 743 restart@fc4ab000 { 744 compatible = "qcom,pshold"; 745 reg = <0xfc4ab000 0x4>; 746 }; 747 748 spmi_bus: spmi@fc4c0000 { 749 compatible = "qcom,spmi-pmic-arb"; 750 reg = <0xfc4cf000 0x1000>, 751 <0xfc4cb000 0x1000>, 752 <0xfc4ca000 0x1000>; 753 reg-names = "core", "intr", "cnfg"; 754 interrupt-names = "periph_irq"; 755 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 756 qcom,ee = <0>; 757 qcom,channel = <0>; 758 #address-cells = <2>; 759 #size-cells = <0>; 760 interrupt-controller; 761 #interrupt-cells = <4>; 762 }; 763 764 tcsr_mutex: hwlock@fd484000 { 765 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; 766 reg = <0xfd484000 0x1000>; 767 #hwlock-cells = <1>; 768 }; 769 770 tlmm: pinctrl@fd510000 { 771 compatible = "qcom,msm8994-pinctrl"; 772 reg = <0xfd510000 0x4000>; 773 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 774 gpio-controller; 775 gpio-ranges = <&tlmm 0 0 146>; 776 #gpio-cells = <2>; 777 interrupt-controller; 778 #interrupt-cells = <2>; 779 780 blsp1_uart2_default: blsp1-uart2-default-state { 781 pins = "gpio4", "gpio5"; 782 function = "blsp_uart2"; 783 drive-strength = <16>; 784 bias-disable; 785 }; 786 787 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 788 pins = "gpio4", "gpio5"; 789 function = "gpio"; 790 drive-strength = <2>; 791 bias-pull-down; 792 }; 793 794 blsp2_uart2_default: blsp2-uart2-default-state { 795 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 796 function = "blsp_uart8"; 797 drive-strength = <16>; 798 bias-disable; 799 }; 800 801 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 802 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 803 function = "gpio"; 804 drive-strength = <2>; 805 bias-disable; 806 }; 807 808 i2c1_default: i2c1-default-state { 809 pins = "gpio2", "gpio3"; 810 function = "blsp_i2c1"; 811 drive-strength = <2>; 812 bias-disable; 813 }; 814 815 i2c1_sleep: i2c1-sleep-state { 816 pins = "gpio2", "gpio3"; 817 function = "gpio"; 818 drive-strength = <2>; 819 bias-disable; 820 }; 821 822 i2c2_default: i2c2-default-state { 823 pins = "gpio6", "gpio7"; 824 function = "blsp_i2c2"; 825 drive-strength = <2>; 826 bias-disable; 827 }; 828 829 i2c2_sleep: i2c2-sleep-state { 830 pins = "gpio6", "gpio7"; 831 function = "gpio"; 832 drive-strength = <2>; 833 bias-disable; 834 }; 835 836 i2c4_default: i2c4-default-state { 837 pins = "gpio19", "gpio20"; 838 function = "blsp_i2c4"; 839 drive-strength = <2>; 840 bias-disable; 841 }; 842 843 i2c4_sleep: i2c4-sleep-state { 844 pins = "gpio19", "gpio20"; 845 function = "gpio"; 846 drive-strength = <2>; 847 bias-pull-down; 848 }; 849 850 i2c5_default: i2c5-default-state { 851 pins = "gpio23", "gpio24"; 852 function = "blsp_i2c5"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c5_sleep: i2c5-sleep-state { 858 pins = "gpio23", "gpio24"; 859 function = "gpio"; 860 drive-strength = <2>; 861 bias-disable; 862 }; 863 864 i2c6_default: i2c6-default-state { 865 pins = "gpio28", "gpio27"; 866 function = "blsp_i2c6"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c6_sleep: i2c6-sleep-state { 872 pins = "gpio28", "gpio27"; 873 function = "gpio"; 874 drive-strength = <2>; 875 bias-disable; 876 }; 877 878 i2c7_default: i2c7-default-state { 879 pins = "gpio44", "gpio43"; 880 function = "blsp_i2c7"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c7_sleep: i2c7-sleep-state { 886 pins = "gpio44", "gpio43"; 887 function = "gpio"; 888 drive-strength = <2>; 889 bias-disable; 890 }; 891 892 blsp2_spi10_default: blsp2-spi10-default-state { 893 default-pins { 894 pins = "gpio53", "gpio54", "gpio55"; 895 function = "blsp_spi10"; 896 drive-strength = <10>; 897 bias-pull-down; 898 }; 899 900 cs-pins { 901 pins = "gpio67"; 902 function = "gpio"; 903 drive-strength = <2>; 904 bias-disable; 905 }; 906 }; 907 908 blsp2_spi10_sleep: blsp2-spi10-sleep-state { 909 pins = "gpio53", "gpio54", "gpio55"; 910 function = "gpio"; 911 drive-strength = <2>; 912 bias-disable; 913 }; 914 915 i2c11_default: i2c11-default-state { 916 pins = "gpio83", "gpio84"; 917 function = "blsp_i2c11"; 918 drive-strength = <2>; 919 bias-disable; 920 }; 921 922 i2c11_sleep: i2c11-sleep-state { 923 pins = "gpio83", "gpio84"; 924 function = "gpio"; 925 drive-strength = <2>; 926 bias-disable; 927 }; 928 929 blsp1_spi1_default: blsp1-spi1-default-state { 930 default-pins { 931 pins = "gpio0", "gpio1", "gpio3"; 932 function = "blsp_spi1"; 933 drive-strength = <10>; 934 bias-pull-down; 935 }; 936 937 cs-pins { 938 pins = "gpio8"; 939 function = "gpio"; 940 drive-strength = <2>; 941 bias-disable; 942 }; 943 }; 944 945 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 946 pins = "gpio0", "gpio1", "gpio3"; 947 function = "gpio"; 948 drive-strength = <2>; 949 bias-disable; 950 }; 951 952 sdc1_clk_on: clk-on-state { 953 pins = "sdc1_clk"; 954 bias-disable; 955 drive-strength = <16>; 956 }; 957 958 sdc1_clk_off: clk-off-state { 959 pins = "sdc1_clk"; 960 bias-disable; 961 drive-strength = <2>; 962 }; 963 964 sdc1_cmd_on: cmd-on-state { 965 pins = "sdc1_cmd"; 966 bias-pull-up; 967 drive-strength = <8>; 968 }; 969 970 sdc1_cmd_off: cmd-off-state { 971 pins = "sdc1_cmd"; 972 bias-pull-up; 973 drive-strength = <2>; 974 }; 975 976 sdc1_data_on: data-on-state { 977 pins = "sdc1_data"; 978 bias-pull-up; 979 drive-strength = <8>; 980 }; 981 982 sdc1_data_off: data-off-state { 983 pins = "sdc1_data"; 984 bias-pull-up; 985 drive-strength = <2>; 986 }; 987 988 sdc1_rclk_on: rclk-on-state { 989 pins = "sdc1_rclk"; 990 bias-pull-down; 991 }; 992 993 sdc1_rclk_off: rclk-off-state { 994 pins = "sdc1_rclk"; 995 bias-pull-down; 996 }; 997 998 sdc2_clk_on: sdc2-clk-on-state { 999 pins = "sdc2_clk"; 1000 bias-disable; 1001 drive-strength = <10>; 1002 }; 1003 1004 sdc2_clk_off: sdc2-clk-off-state { 1005 pins = "sdc2_clk"; 1006 bias-disable; 1007 drive-strength = <2>; 1008 }; 1009 1010 sdc2_cmd_on: sdc2-cmd-on-state { 1011 pins = "sdc2_cmd"; 1012 bias-pull-up; 1013 drive-strength = <10>; 1014 }; 1015 1016 sdc2_cmd_off: sdc2-cmd-off-state { 1017 pins = "sdc2_cmd"; 1018 bias-pull-up; 1019 drive-strength = <2>; 1020 }; 1021 1022 sdc2_data_on: sdc2-data-on-state { 1023 pins = "sdc2_data"; 1024 bias-pull-up; 1025 drive-strength = <10>; 1026 }; 1027 1028 sdc2_data_off: sdc2-data-off-state { 1029 pins = "sdc2_data"; 1030 bias-pull-up; 1031 drive-strength = <2>; 1032 }; 1033 }; 1034 1035 mmcc: clock-controller@fd8c0000 { 1036 compatible = "qcom,mmcc-msm8994"; 1037 reg = <0xfd8c0000 0x5200>; 1038 #clock-cells = <1>; 1039 #reset-cells = <1>; 1040 #power-domain-cells = <1>; 1041 1042 clock-names = "xo", 1043 "gpll0", 1044 "mmssnoc_ahb", 1045 "oxili_gfx3d_clk_src", 1046 "dsi0pll", 1047 "dsi0pllbyte", 1048 "dsi1pll", 1049 "dsi1pllbyte", 1050 "hdmipll"; 1051 clocks = <&xo_board>, 1052 <&gcc GPLL0_OUT_MMSSCC>, 1053 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, 1054 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1055 <0>, 1056 <0>, 1057 <0>, 1058 <0>, 1059 <0>; 1060 1061 assigned-clocks = <&mmcc MMPLL0_PLL>, 1062 <&mmcc MMPLL1_PLL>, 1063 <&mmcc MMPLL3_PLL>, 1064 <&mmcc MMPLL4_PLL>, 1065 <&mmcc MMPLL5_PLL>; 1066 assigned-clock-rates = <800000000>, 1067 <1167000000>, 1068 <1020000000>, 1069 <960000000>, 1070 <600000000>; 1071 }; 1072 1073 ocmem: sram@fdd00000 { 1074 compatible = "qcom,msm8974-ocmem"; 1075 reg = <0xfdd00000 0x2000>, 1076 <0xfec00000 0x200000>; 1077 reg-names = "ctrl", "mem"; 1078 ranges = <0 0xfec00000 0x200000>; 1079 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1080 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1081 clock-names = "core", "iface"; 1082 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 1086 gmu_sram: gmu-sram@0 { 1087 reg = <0x0 0x180000>; 1088 }; 1089 }; 1090 }; 1091 1092 timer: timer { 1093 compatible = "arm,armv8-timer"; 1094 interrupts = <GIC_PPI 2 0xff08>, 1095 <GIC_PPI 3 0xff08>, 1096 <GIC_PPI 4 0xff08>, 1097 <GIC_PPI 1 0xff08>; 1098 }; 1099 1100 vph_pwr: vph-pwr-regulator { 1101 compatible = "regulator-fixed"; 1102 regulator-name = "vph_pwr"; 1103 1104 regulator-min-microvolt = <3600000>; 1105 regulator-max-microvolt = <3600000>; 1106 1107 regulator-always-on; 1108 }; 1109}; 1110 1111