1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8994.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8994.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 mmc1 = &sdhc1; 19 mmc2 = &sdhc2; 20 }; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32768>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 cache-level = <2>; 53 }; 54 }; 55 56 CPU1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x0 0x1>; 60 enable-method = "psci"; 61 next-level-cache = <&L2_0>; 62 }; 63 64 CPU2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x3>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_0>; 78 }; 79 80 CPU4: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a57"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 next-level-cache = <&L2_1>; 86 L2_1: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 }; 90 }; 91 92 CPU5: cpu@101 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a57"; 95 reg = <0x0 0x101>; 96 enable-method = "psci"; 97 next-level-cache = <&L2_1>; 98 }; 99 100 CPU6: cpu@102 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a57"; 103 reg = <0x0 0x101>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_1>; 106 }; 107 108 CPU7: cpu@103 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a57"; 111 reg = <0x0 0x101>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_1>; 114 }; 115 116 cpu-map { 117 cluster0 { 118 core0 { 119 cpu = <&CPU0>; 120 }; 121 122 core1 { 123 cpu = <&CPU1>; 124 }; 125 126 core2 { 127 cpu = <&CPU2>; 128 }; 129 130 core3 { 131 cpu = <&CPU3>; 132 }; 133 }; 134 135 cluster1 { 136 core0 { 137 cpu = <&CPU4>; 138 }; 139 140 core1 { 141 cpu = <&CPU5>; 142 }; 143 144 cpu6_map: core2 { 145 cpu = <&CPU6>; 146 }; 147 148 cpu7_map: core3 { 149 cpu = <&CPU7>; 150 }; 151 }; 152 }; 153 }; 154 155 firmware { 156 scm { 157 compatible = "qcom,scm-msm8994", "qcom,scm"; 158 }; 159 }; 160 161 memory@80000000 { 162 device_type = "memory"; 163 /* We expect the bootloader to fill in the reg */ 164 reg = <0 0x80000000 0 0>; 165 }; 166 167 tcsr_mutex: hwlock { 168 compatible = "qcom,tcsr-mutex"; 169 syscon = <&tcsr_mutex_regs 0 0x80>; 170 #hwlock-cells = <1>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 176 }; 177 178 psci { 179 compatible = "arm,psci-0.2"; 180 method = "hvc"; 181 }; 182 183 reserved-memory { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges; 187 188 dfps_data_mem: dfps_data_mem@3400000 { 189 reg = <0 0x03400000 0 0x1000>; 190 no-map; 191 }; 192 193 cont_splash_mem: memory@3401000 { 194 reg = <0 0x03401000 0 0x2200000>; 195 no-map; 196 }; 197 198 smem_mem: smem_region@6a00000 { 199 reg = <0 0x06a00000 0 0x200000>; 200 no-map; 201 }; 202 203 mpss_mem: memory@7000000 { 204 reg = <0 0x07000000 0 0x5a00000>; 205 no-map; 206 }; 207 208 peripheral_region: memory@ca00000 { 209 reg = <0 0x0ca00000 0 0x1f00000>; 210 no-map; 211 }; 212 213 rmtfs_mem: memory@c6400000 { 214 compatible = "qcom,rmtfs-mem"; 215 reg = <0 0xc6400000 0 0x180000>; 216 no-map; 217 218 qcom,client-id = <1>; 219 }; 220 221 mba_mem: memory@c6700000 { 222 reg = <0 0xc6700000 0 0x100000>; 223 no-map; 224 }; 225 226 audio_mem: memory@c7000000 { 227 reg = <0 0xc7000000 0 0x800000>; 228 no-map; 229 }; 230 231 adsp_mem: memory@c9400000 { 232 reg = <0 0xc9400000 0 0x3f00000>; 233 no-map; 234 }; 235 }; 236 237 smd { 238 compatible = "qcom,smd"; 239 rpm { 240 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 241 qcom,ipc = <&apcs 8 0>; 242 qcom,smd-edge = <15>; 243 qcom,remote-pid = <6>; 244 245 rpm_requests: rpm-requests { 246 compatible = "qcom,rpm-msm8994"; 247 qcom,smd-channels = "rpm_requests"; 248 249 rpmcc: rpmcc { 250 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; 251 #clock-cells = <1>; 252 }; 253 254 rpmpd: power-controller { 255 compatible = "qcom,msm8994-rpmpd"; 256 #power-domain-cells = <1>; 257 operating-points-v2 = <&rpmpd_opp_table>; 258 259 rpmpd_opp_table: opp-table { 260 compatible = "operating-points-v2"; 261 262 rpmpd_opp_ret: opp1 { 263 opp-level = <1>; 264 }; 265 rpmpd_opp_svs_krait: opp2 { 266 opp-level = <2>; 267 }; 268 rpmpd_opp_svs_soc: opp3 { 269 opp-level = <3>; 270 }; 271 rpmpd_opp_nom: opp4 { 272 opp-level = <4>; 273 }; 274 rpmpd_opp_turbo: opp5 { 275 opp-level = <5>; 276 }; 277 rpmpd_opp_super_turbo: opp6 { 278 opp-level = <6>; 279 }; 280 }; 281 }; 282 }; 283 }; 284 }; 285 286 smem { 287 compatible = "qcom,smem"; 288 memory-region = <&smem_mem>; 289 qcom,rpm-msg-ram = <&rpm_msg_ram>; 290 hwlocks = <&tcsr_mutex 3>; 291 }; 292 293 smp2p-lpass { 294 compatible = "qcom,smp2p"; 295 qcom,smem = <443>, <429>; 296 297 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 298 299 qcom,ipc = <&apcs 8 10>; 300 301 qcom,local-pid = <0>; 302 qcom,remote-pid = <2>; 303 304 adsp_smp2p_out: master-kernel { 305 qcom,entry-name = "master-kernel"; 306 #qcom,smem-state-cells = <1>; 307 }; 308 309 adsp_smp2p_in: slave-kernel { 310 qcom,entry-name = "slave-kernel"; 311 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 }; 316 317 smp2p-modem { 318 compatible = "qcom,smp2p"; 319 qcom,smem = <435>, <428>; 320 321 interrupt-parent = <&intc>; 322 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 323 324 qcom,ipc = <&apcs 8 14>; 325 326 qcom,local-pid = <0>; 327 qcom,remote-pid = <1>; 328 329 modem_smp2p_out: master-kernel { 330 qcom,entry-name = "master-kernel"; 331 #qcom,smem-state-cells = <1>; 332 }; 333 334 modem_smp2p_in: slave-kernel { 335 qcom,entry-name = "slave-kernel"; 336 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 }; 341 342 soc: soc { 343 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0 0 0 0xffffffff>; 347 compatible = "simple-bus"; 348 349 intc: interrupt-controller@f9000000 { 350 compatible = "qcom,msm-qgic2"; 351 interrupt-controller; 352 #interrupt-cells = <3>; 353 reg = <0xf9000000 0x1000>, 354 <0xf9002000 0x1000>; 355 }; 356 357 apcs: mailbox@f900d000 { 358 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 359 reg = <0xf900d000 0x2000>; 360 #mbox-cells = <1>; 361 }; 362 363 watchdog@f9017000 { 364 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; 365 reg = <0xf9017000 0x1000>; 366 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 368 clocks = <&sleep_clk>; 369 timeout-sec = <10>; 370 }; 371 372 timer@f9020000 { 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges; 376 compatible = "arm,armv7-timer-mem"; 377 reg = <0xf9020000 0x1000>; 378 379 frame@f9021000 { 380 frame-number = <0>; 381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 383 reg = <0xf9021000 0x1000>, 384 <0xf9022000 0x1000>; 385 }; 386 387 frame@f9023000 { 388 frame-number = <1>; 389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 390 reg = <0xf9023000 0x1000>; 391 status = "disabled"; 392 }; 393 394 frame@f9024000 { 395 frame-number = <2>; 396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 397 reg = <0xf9024000 0x1000>; 398 status = "disabled"; 399 }; 400 401 frame@f9025000 { 402 frame-number = <3>; 403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 404 reg = <0xf9025000 0x1000>; 405 status = "disabled"; 406 }; 407 408 frame@f9026000 { 409 frame-number = <4>; 410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 411 reg = <0xf9026000 0x1000>; 412 status = "disabled"; 413 }; 414 415 frame@f9027000 { 416 frame-number = <5>; 417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 418 reg = <0xf9027000 0x1000>; 419 status = "disabled"; 420 }; 421 422 frame@f9028000 { 423 frame-number = <6>; 424 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 425 reg = <0xf9028000 0x1000>; 426 status = "disabled"; 427 }; 428 }; 429 430 usb3: usb@f92f8800 { 431 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 432 reg = <0xf92f8800 0x400>; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges; 436 437 clocks = <&gcc GCC_USB30_MASTER_CLK>, 438 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 439 <&gcc GCC_USB30_SLEEP_CLK>, 440 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 441 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; 442 443 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 444 <&gcc GCC_USB30_MASTER_CLK>; 445 assigned-clock-rates = <19200000>, <120000000>; 446 447 power-domains = <&gcc USB30_GDSC>; 448 qcom,select-utmi-as-pipe-clk; 449 450 usb@f9200000 { 451 compatible = "snps,dwc3"; 452 reg = <0xf9200000 0xcc00>; 453 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 454 snps,dis_u2_susphy_quirk; 455 snps,dis_enblslpm_quirk; 456 maximum-speed = "high-speed"; 457 dr_mode = "peripheral"; 458 }; 459 }; 460 461 sdhc1: sdhci@f9824900 { 462 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 463 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 464 reg-names = "hc_mem", "core_mem"; 465 466 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "hc_irq", "pwr_irq"; 469 470 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 471 <&gcc GCC_SDCC1_AHB_CLK>, 472 <&xo_board>; 473 clock-names = "core", "iface", "xo"; 474 475 pinctrl-names = "default", "sleep"; 476 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 477 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 478 479 bus-width = <8>; 480 non-removable; 481 status = "disabled"; 482 }; 483 484 sdhc2: sdhci@f98a4900 { 485 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 486 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 487 reg-names = "hc_mem", "core_mem"; 488 489 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "hc_irq", "pwr_irq"; 492 493 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 494 <&gcc GCC_SDCC2_AHB_CLK>, 495 <&xo_board>; 496 clock-names = "core", "iface", "xo"; 497 498 pinctrl-names = "default", "sleep"; 499 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 500 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 501 502 cd-gpios = <&tlmm 100 0>; 503 bus-width = <4>; 504 status = "disabled"; 505 }; 506 507 blsp1_dma: dma-controller@f9904000 { 508 compatible = "qcom,bam-v1.7.0"; 509 reg = <0xf9904000 0x19000>; 510 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 512 clock-names = "bam_clk"; 513 #dma-cells = <1>; 514 qcom,ee = <0>; 515 qcom,controlled-remotely; 516 num-channels = <24>; 517 qcom,num-ees = <4>; 518 }; 519 520 blsp1_uart2: serial@f991e000 { 521 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 522 reg = <0xf991e000 0x1000>; 523 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 524 clock-names = "core", "iface"; 525 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 526 <&gcc GCC_BLSP1_AHB_CLK>; 527 pinctrl-names = "default", "sleep"; 528 pinctrl-0 = <&blsp1_uart2_default>; 529 pinctrl-1 = <&blsp1_uart2_sleep>; 530 status = "disabled"; 531 }; 532 533 blsp1_i2c1: i2c@f9923000 { 534 compatible = "qcom,i2c-qup-v2.2.1"; 535 reg = <0xf9923000 0x500>; 536 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 538 <&gcc GCC_BLSP1_AHB_CLK>; 539 clock-names = "core", "iface"; 540 clock-frequency = <400000>; 541 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 542 dma-names = "tx", "rx"; 543 pinctrl-names = "default", "sleep"; 544 pinctrl-0 = <&i2c1_default>; 545 pinctrl-1 = <&i2c1_sleep>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 blsp1_spi1: spi@f9923000 { 552 compatible = "qcom,spi-qup-v2.2.1"; 553 reg = <0xf9923000 0x500>; 554 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 556 <&gcc GCC_BLSP1_AHB_CLK>; 557 clock-names = "core", "iface"; 558 spi-max-frequency = <19200000>; 559 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 560 dma-names = "tx", "rx"; 561 pinctrl-names = "default", "sleep"; 562 pinctrl-0 = <&blsp1_spi1_default>; 563 pinctrl-1 = <&blsp1_spi1_sleep>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 569 blsp1_i2c2: i2c@f9924000 { 570 compatible = "qcom,i2c-qup-v2.2.1"; 571 reg = <0xf9924000 0x500>; 572 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 574 <&gcc GCC_BLSP1_AHB_CLK>; 575 clock-names = "core", "iface"; 576 clock-frequency = <400000>; 577 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 578 dma-names = "tx", "rx"; 579 pinctrl-names = "default", "sleep"; 580 pinctrl-0 = <&i2c2_default>; 581 pinctrl-1 = <&i2c2_sleep>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 /* I2C3 doesn't exist */ 588 589 blsp1_i2c4: i2c@f9926000 { 590 compatible = "qcom,i2c-qup-v2.2.1"; 591 reg = <0xf9926000 0x500>; 592 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 594 <&gcc GCC_BLSP1_AHB_CLK>; 595 clock-names = "core", "iface"; 596 clock-frequency = <400000>; 597 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; 598 dma-names = "tx", "rx"; 599 pinctrl-names = "default", "sleep"; 600 pinctrl-0 = <&i2c4_default>; 601 pinctrl-1 = <&i2c4_sleep>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 blsp1_i2c5: i2c@f9927000 { 608 compatible = "qcom,i2c-qup-v2.2.1"; 609 reg = <0xf9927000 0x500>; 610 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 612 <&gcc GCC_BLSP1_AHB_CLK>; 613 clock-names = "core", "iface"; 614 clock-frequency = <400000>; 615 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 616 dma-names = "tx", "rx"; 617 pinctrl-names = "default", "sleep"; 618 pinctrl-0 = <&i2c5_default>; 619 pinctrl-1 = <&i2c5_sleep>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 blsp1_i2c6: i2c@f9928000 { 626 compatible = "qcom,i2c-qup-v2.2.1"; 627 reg = <0xf9928000 0x500>; 628 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 630 <&gcc GCC_BLSP1_AHB_CLK>; 631 clock-names = "core", "iface"; 632 clock-frequency = <400000>; 633 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 634 dma-names = "tx", "rx"; 635 pinctrl-names = "default", "sleep"; 636 pinctrl-0 = <&i2c6_default>; 637 pinctrl-1 = <&i2c6_sleep>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 blsp2_dma: dma-controller@f9944000 { 644 compatible = "qcom,bam-v1.7.0"; 645 reg = <0xf9944000 0x19000>; 646 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 648 clock-names = "bam_clk"; 649 #dma-cells = <1>; 650 qcom,ee = <0>; 651 qcom,controlled-remotely; 652 num-channels = <24>; 653 qcom,num-ees = <4>; 654 }; 655 656 blsp2_uart2: serial@f995e000 { 657 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 658 reg = <0xf995e000 0x1000>; 659 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 660 clock-names = "core", "iface"; 661 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 662 <&gcc GCC_BLSP2_AHB_CLK>; 663 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 664 dma-names = "tx", "rx"; 665 pinctrl-names = "default", "sleep"; 666 pinctrl-0 = <&blsp2_uart2_default>; 667 pinctrl-1 = <&blsp2_uart2_sleep>; 668 status = "disabled"; 669 }; 670 671 blsp2_i2c1: i2c@f9963000 { 672 compatible = "qcom,i2c-qup-v2.2.1"; 673 reg = <0xf9963000 0x500>; 674 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 676 <&gcc GCC_BLSP2_AHB_CLK>; 677 clock-names = "core", "iface"; 678 clock-frequency = <400000>; 679 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 680 dma-names = "tx", "rx"; 681 pinctrl-names = "default", "sleep"; 682 pinctrl-0 = <&i2c7_default>; 683 pinctrl-1 = <&i2c7_sleep>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 blsp2_spi4: spi@f9966000 { 690 compatible = "qcom,spi-qup-v2.2.1"; 691 reg = <0xf9966000 0x500>; 692 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 694 <&gcc GCC_BLSP2_AHB_CLK>; 695 clock-names = "core", "iface"; 696 spi-max-frequency = <19200000>; 697 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; 698 dma-names = "tx", "rx"; 699 pinctrl-names = "default", "sleep"; 700 pinctrl-0 = <&blsp2_spi10_default>; 701 pinctrl-1 = <&blsp2_spi10_sleep>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 blsp2_i2c5: i2c@f9967000 { 708 compatible = "qcom,i2c-qup-v2.2.1"; 709 reg = <0xf9967000 0x500>; 710 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 712 <&gcc GCC_BLSP2_AHB_CLK>; 713 clock-names = "core", "iface"; 714 clock-frequency = <355000>; 715 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 716 dma-names = "tx", "rx"; 717 pinctrl-names = "default", "sleep"; 718 pinctrl-0 = <&i2c11_default>; 719 pinctrl-1 = <&i2c11_sleep>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 gcc: clock-controller@fc400000 { 726 compatible = "qcom,gcc-msm8994"; 727 #clock-cells = <1>; 728 #reset-cells = <1>; 729 #power-domain-cells = <1>; 730 reg = <0xfc400000 0x2000>; 731 732 clock-names = "xo", "sleep"; 733 clocks = <&xo_board>, <&sleep_clk>; 734 }; 735 736 rpm_msg_ram: sram@fc428000 { 737 compatible = "qcom,rpm-msg-ram"; 738 reg = <0xfc428000 0x4000>; 739 }; 740 741 restart@fc4ab000 { 742 compatible = "qcom,pshold"; 743 reg = <0xfc4ab000 0x4>; 744 }; 745 746 spmi_bus: spmi@fc4c0000 { 747 compatible = "qcom,spmi-pmic-arb"; 748 reg = <0xfc4cf000 0x1000>, 749 <0xfc4cb000 0x1000>, 750 <0xfc4ca000 0x1000>; 751 reg-names = "core", "intr", "cnfg"; 752 interrupt-names = "periph_irq"; 753 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 754 qcom,ee = <0>; 755 qcom,channel = <0>; 756 #address-cells = <2>; 757 #size-cells = <0>; 758 interrupt-controller; 759 #interrupt-cells = <4>; 760 }; 761 762 tcsr_mutex_regs: syscon@fd484000 { 763 compatible = "syscon"; 764 reg = <0xfd484000 0x2000>; 765 }; 766 767 tlmm: pinctrl@fd510000 { 768 compatible = "qcom,msm8994-pinctrl"; 769 reg = <0xfd510000 0x4000>; 770 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 771 gpio-controller; 772 gpio-ranges = <&tlmm 0 0 146>; 773 #gpio-cells = <2>; 774 interrupt-controller; 775 #interrupt-cells = <2>; 776 777 blsp1_uart2_default: blsp1-uart2-default { 778 function = "blsp_uart2"; 779 pins = "gpio4", "gpio5"; 780 drive-strength = <16>; 781 bias-disable; 782 }; 783 784 blsp1_uart2_sleep: blsp1-uart2-sleep { 785 function = "gpio"; 786 pins = "gpio4", "gpio5"; 787 drive-strength = <2>; 788 bias-pull-down; 789 }; 790 791 blsp2_uart2_default: blsp2-uart2-default { 792 function = "blsp_uart8"; 793 pins = "gpio45", "gpio46", 794 "gpio47", "gpio48"; 795 drive-strength = <16>; 796 bias-disable; 797 }; 798 799 blsp2_uart2_sleep: blsp2-uart2-sleep { 800 function = "gpio"; 801 pins = "gpio45", "gpio46", 802 "gpio47", "gpio48"; 803 drive-strength = <2>; 804 bias-disable; 805 }; 806 807 i2c1_default: i2c1-default { 808 function = "blsp_i2c1"; 809 pins = "gpio2", "gpio3"; 810 drive-strength = <2>; 811 bias-disable; 812 }; 813 814 i2c1_sleep: i2c1-sleep { 815 function = "gpio"; 816 pins = "gpio2", "gpio3"; 817 drive-strength = <2>; 818 bias-disable; 819 }; 820 821 i2c2_default: i2c2-default { 822 function = "blsp_i2c2"; 823 pins = "gpio6", "gpio7"; 824 drive-strength = <2>; 825 bias-disable; 826 }; 827 828 i2c2_sleep: i2c2-sleep { 829 function = "gpio"; 830 pins = "gpio6", "gpio7"; 831 drive-strength = <2>; 832 bias-disable; 833 }; 834 835 i2c4_default: i2c4-default { 836 function = "blsp_i2c4"; 837 pins = "gpio19", "gpio20"; 838 drive-strength = <2>; 839 bias-disable; 840 }; 841 842 i2c4_sleep: i2c4-sleep { 843 function = "gpio"; 844 pins = "gpio19", "gpio20"; 845 drive-strength = <2>; 846 bias-pull-down; 847 input-enable; 848 }; 849 850 i2c5_default: i2c5-default { 851 function = "blsp_i2c5"; 852 pins = "gpio23", "gpio24"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c5_sleep: i2c5-sleep { 858 function = "gpio"; 859 pins = "gpio23", "gpio24"; 860 drive-strength = <2>; 861 bias-disable; 862 }; 863 864 i2c6_default: i2c6-default { 865 function = "blsp_i2c6"; 866 pins = "gpio28", "gpio27"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c6_sleep: i2c6-sleep { 872 function = "gpio"; 873 pins = "gpio28", "gpio27"; 874 drive-strength = <2>; 875 bias-disable; 876 }; 877 878 i2c7_default: i2c7-default { 879 function = "blsp_i2c7"; 880 pins = "gpio44", "gpio43"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c7_sleep: i2c7-sleep { 886 function = "gpio"; 887 pins = "gpio44", "gpio43"; 888 drive-strength = <2>; 889 bias-disable; 890 }; 891 892 blsp2_spi10_default: blsp2-spi10-default { 893 default { 894 function = "blsp_spi10"; 895 pins = "gpio53", "gpio54", "gpio55"; 896 drive-strength = <10>; 897 bias-pull-down; 898 }; 899 cs { 900 function = "gpio"; 901 pins = "gpio55"; 902 drive-strength = <2>; 903 bias-disable; 904 }; 905 }; 906 907 blsp2_spi10_sleep: blsp2-spi10-sleep { 908 pins = "gpio53", "gpio54", "gpio55"; 909 drive-strength = <2>; 910 bias-disable; 911 }; 912 913 i2c11_default: i2c11-default { 914 function = "blsp_i2c11"; 915 pins = "gpio83", "gpio84"; 916 drive-strength = <2>; 917 bias-disable; 918 }; 919 920 i2c11_sleep: i2c11-sleep { 921 function = "gpio"; 922 pins = "gpio83", "gpio84"; 923 drive-strength = <2>; 924 bias-disable; 925 }; 926 927 blsp1_spi1_default: blsp1-spi1-default { 928 default { 929 function = "blsp_spi1"; 930 pins = "gpio0", "gpio1", "gpio3"; 931 drive-strength = <10>; 932 bias-pull-down; 933 }; 934 cs { 935 function = "gpio"; 936 pins = "gpio8"; 937 drive-strength = <2>; 938 bias-disable; 939 }; 940 }; 941 942 blsp1_spi1_sleep: blsp1-spi1-sleep { 943 pins = "gpio0", "gpio1", "gpio3"; 944 drive-strength = <2>; 945 bias-disable; 946 }; 947 948 sdc1_clk_on: clk-on { 949 pins = "sdc1_clk"; 950 bias-disable; 951 drive-strength = <16>; 952 }; 953 954 sdc1_clk_off: clk-off { 955 pins = "sdc1_clk"; 956 bias-disable; 957 drive-strength = <2>; 958 }; 959 960 sdc1_cmd_on: cmd-on { 961 pins = "sdc1_cmd"; 962 bias-pull-up; 963 drive-strength = <8>; 964 }; 965 966 sdc1_cmd_off: cmd-off { 967 pins = "sdc1_cmd"; 968 bias-pull-up; 969 drive-strength = <2>; 970 }; 971 972 sdc1_data_on: data-on { 973 pins = "sdc1_data"; 974 bias-pull-up; 975 drive-strength = <8>; 976 }; 977 978 sdc1_data_off: data-off { 979 pins = "sdc1_data"; 980 bias-pull-up; 981 drive-strength = <2>; 982 }; 983 984 sdc1_rclk_on: rclk-on { 985 pins = "sdc1_rclk"; 986 bias-pull-down; 987 }; 988 989 sdc1_rclk_off: rclk-off { 990 pins = "sdc1_rclk"; 991 bias-pull-down; 992 }; 993 994 sdc2_clk_on: sdc2-clk-on { 995 pins = "sdc2_clk"; 996 bias-disable; 997 drive-strength = <10>; 998 }; 999 1000 sdc2_clk_off: sdc2-clk-off { 1001 pins = "sdc2_clk"; 1002 bias-disable; 1003 drive-strength = <2>; 1004 }; 1005 1006 sdc2_cmd_on: sdc2-cmd-on { 1007 pins = "sdc2_cmd"; 1008 bias-pull-up; 1009 drive-strength = <10>; 1010 }; 1011 1012 sdc2_cmd_off: sdc2-cmd-off { 1013 pins = "sdc2_cmd"; 1014 bias-pull-up; 1015 drive-strength = <2>; 1016 }; 1017 1018 sdc2_data_on: sdc2-data-on { 1019 pins = "sdc2_data"; 1020 bias-pull-up; 1021 drive-strength = <10>; 1022 }; 1023 1024 sdc2_data_off: sdc2-data-off { 1025 pins = "sdc2_data"; 1026 bias-pull-up; 1027 drive-strength = <2>; 1028 }; 1029 }; 1030 1031 mmcc: clock-controller@fd8c0000 { 1032 compatible = "qcom,mmcc-msm8994"; 1033 reg = <0xfd8c0000 0x5200>; 1034 #clock-cells = <1>; 1035 #reset-cells = <1>; 1036 #power-domain-cells = <1>; 1037 1038 clock-names = "xo", 1039 "gpll0", 1040 "mmssnoc_ahb", 1041 "oxili_gfx3d_clk_src", 1042 "dsi0pll", 1043 "dsi0pllbyte", 1044 "dsi1pll", 1045 "dsi1pllbyte", 1046 "hdmipll"; 1047 clocks = <&xo_board>, 1048 <&gcc GPLL0_OUT_MMSSCC>, 1049 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, 1050 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1051 <0>, 1052 <0>, 1053 <0>, 1054 <0>, 1055 <0>; 1056 1057 assigned-clocks = <&mmcc MMPLL0_PLL>, 1058 <&mmcc MMPLL1_PLL>, 1059 <&mmcc MMPLL3_PLL>, 1060 <&mmcc MMPLL4_PLL>, 1061 <&mmcc MMPLL5_PLL>; 1062 assigned-clock-rates = <800000000>, 1063 <1167000000>, 1064 <1020000000>, 1065 <960000000>, 1066 <600000000>; 1067 }; 1068 1069 ocmem: ocmem@fdd00000 { 1070 compatible = "qcom,msm8974-ocmem"; 1071 reg = <0xfdd00000 0x2000>, 1072 <0xfec00000 0x200000>; 1073 reg-names = "ctrl", "mem"; 1074 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1075 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1076 clock-names = "core", "iface"; 1077 1078 #address-cells = <1>; 1079 #size-cells = <1>; 1080 1081 gmu_sram: gmu-sram@0 { 1082 reg = <0x0 0x180000>; 1083 }; 1084 }; 1085 }; 1086 1087 timer: timer { 1088 compatible = "arm,armv8-timer"; 1089 interrupts = <GIC_PPI 2 0xff08>, 1090 <GIC_PPI 3 0xff08>, 1091 <GIC_PPI 4 0xff08>, 1092 <GIC_PPI 1 0xff08>; 1093 }; 1094 1095 vph_pwr: vph-pwr-regulator { 1096 compatible = "regulator-fixed"; 1097 regulator-name = "vph_pwr"; 1098 1099 regulator-min-microvolt = <3600000>; 1100 regulator-max-microvolt = <3600000>; 1101 1102 regulator-always-on; 1103 }; 1104}; 1105 1106