1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8994.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8994.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc1 = &sdhc1; 21 mmc2 = &sdhc2; 22 }; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 enable-method = "psci"; 64 next-level-cache = <&L2_0>; 65 }; 66 67 CPU2: cpu@2 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x0 0x2>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x0 0x3>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 }; 82 83 CPU4: cpu@100 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a57"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_1>; 89 L2_1: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 CPU5: cpu@101 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a57"; 99 reg = <0x0 0x101>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_1>; 102 }; 103 104 CPU6: cpu@102 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a57"; 107 reg = <0x0 0x102>; 108 enable-method = "psci"; 109 next-level-cache = <&L2_1>; 110 }; 111 112 CPU7: cpu@103 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a57"; 115 reg = <0x0 0x103>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_1>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&CPU0>; 124 }; 125 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 130 core2 { 131 cpu = <&CPU2>; 132 }; 133 134 core3 { 135 cpu = <&CPU3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&CPU4>; 142 }; 143 144 core1 { 145 cpu = <&CPU5>; 146 }; 147 148 cpu6_map: core2 { 149 cpu = <&CPU6>; 150 }; 151 152 cpu7_map: core3 { 153 cpu = <&CPU7>; 154 }; 155 }; 156 }; 157 }; 158 159 firmware { 160 scm { 161 compatible = "qcom,scm-msm8994", "qcom,scm"; 162 }; 163 }; 164 165 memory@80000000 { 166 device_type = "memory"; 167 /* We expect the bootloader to fill in the reg */ 168 reg = <0 0x80000000 0 0>; 169 }; 170 171 pmu { 172 compatible = "arm,cortex-a53-pmu"; 173 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 174 }; 175 176 psci { 177 compatible = "arm,psci-0.2"; 178 method = "hvc"; 179 }; 180 181 reserved-memory { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges; 185 186 dfps_data_mem: dfps_data_mem@3400000 { 187 reg = <0 0x03400000 0 0x1000>; 188 no-map; 189 }; 190 191 cont_splash_mem: memory@3401000 { 192 reg = <0 0x03401000 0 0x2200000>; 193 no-map; 194 }; 195 196 smem_mem: smem_region@6a00000 { 197 reg = <0 0x06a00000 0 0x200000>; 198 no-map; 199 }; 200 201 mpss_mem: memory@7000000 { 202 reg = <0 0x07000000 0 0x5a00000>; 203 no-map; 204 }; 205 206 peripheral_region: memory@ca00000 { 207 reg = <0 0x0ca00000 0 0x1f00000>; 208 no-map; 209 }; 210 211 rmtfs_mem: memory@c6400000 { 212 compatible = "qcom,rmtfs-mem"; 213 reg = <0 0xc6400000 0 0x180000>; 214 no-map; 215 216 qcom,client-id = <1>; 217 }; 218 219 mba_mem: memory@c6700000 { 220 reg = <0 0xc6700000 0 0x100000>; 221 no-map; 222 }; 223 224 audio_mem: memory@c7000000 { 225 reg = <0 0xc7000000 0 0x800000>; 226 no-map; 227 }; 228 229 adsp_mem: memory@c9400000 { 230 reg = <0 0xc9400000 0 0x3f00000>; 231 no-map; 232 }; 233 234 reserved@6c00000 { 235 reg = <0 0x06c00000 0 0x400000>; 236 no-map; 237 }; 238 }; 239 240 smd { 241 compatible = "qcom,smd"; 242 rpm { 243 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 244 qcom,ipc = <&apcs 8 0>; 245 qcom,smd-edge = <15>; 246 qcom,remote-pid = <6>; 247 248 rpm_requests: rpm-requests { 249 compatible = "qcom,rpm-msm8994"; 250 qcom,smd-channels = "rpm_requests"; 251 252 rpmcc: clock-controller { 253 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; 254 #clock-cells = <1>; 255 }; 256 257 rpmpd: power-controller { 258 compatible = "qcom,msm8994-rpmpd"; 259 #power-domain-cells = <1>; 260 operating-points-v2 = <&rpmpd_opp_table>; 261 262 rpmpd_opp_table: opp-table { 263 compatible = "operating-points-v2"; 264 265 rpmpd_opp_ret: opp1 { 266 opp-level = <1>; 267 }; 268 rpmpd_opp_svs_krait: opp2 { 269 opp-level = <2>; 270 }; 271 rpmpd_opp_svs_soc: opp3 { 272 opp-level = <3>; 273 }; 274 rpmpd_opp_nom: opp4 { 275 opp-level = <4>; 276 }; 277 rpmpd_opp_turbo: opp5 { 278 opp-level = <5>; 279 }; 280 rpmpd_opp_super_turbo: opp6 { 281 opp-level = <6>; 282 }; 283 }; 284 }; 285 }; 286 }; 287 }; 288 289 smem { 290 compatible = "qcom,smem"; 291 memory-region = <&smem_mem>; 292 qcom,rpm-msg-ram = <&rpm_msg_ram>; 293 hwlocks = <&tcsr_mutex 3>; 294 }; 295 296 smp2p-lpass { 297 compatible = "qcom,smp2p"; 298 qcom,smem = <443>, <429>; 299 300 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 301 302 qcom,ipc = <&apcs 8 10>; 303 304 qcom,local-pid = <0>; 305 qcom,remote-pid = <2>; 306 307 adsp_smp2p_out: master-kernel { 308 qcom,entry-name = "master-kernel"; 309 #qcom,smem-state-cells = <1>; 310 }; 311 312 adsp_smp2p_in: slave-kernel { 313 qcom,entry-name = "slave-kernel"; 314 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-modem { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <435>, <428>; 323 324 interrupt-parent = <&intc>; 325 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 326 327 qcom,ipc = <&apcs 8 14>; 328 329 qcom,local-pid = <0>; 330 qcom,remote-pid = <1>; 331 332 modem_smp2p_out: master-kernel { 333 qcom,entry-name = "master-kernel"; 334 #qcom,smem-state-cells = <1>; 335 }; 336 337 modem_smp2p_in: slave-kernel { 338 qcom,entry-name = "slave-kernel"; 339 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 }; 343 }; 344 345 soc: soc@0 { 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges = <0 0 0 0xffffffff>; 349 compatible = "simple-bus"; 350 351 intc: interrupt-controller@f9000000 { 352 compatible = "qcom,msm-qgic2"; 353 interrupt-controller; 354 #interrupt-cells = <3>; 355 reg = <0xf9000000 0x1000>, 356 <0xf9002000 0x1000>; 357 }; 358 359 apcs: mailbox@f900d000 { 360 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 361 reg = <0xf900d000 0x2000>; 362 #mbox-cells = <1>; 363 }; 364 365 watchdog@f9017000 { 366 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; 367 reg = <0xf9017000 0x1000>; 368 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 369 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 370 clocks = <&sleep_clk>; 371 timeout-sec = <10>; 372 }; 373 374 timer@f9020000 { 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges; 378 compatible = "arm,armv7-timer-mem"; 379 reg = <0xf9020000 0x1000>; 380 381 frame@f9021000 { 382 frame-number = <0>; 383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 385 reg = <0xf9021000 0x1000>, 386 <0xf9022000 0x1000>; 387 }; 388 389 frame@f9023000 { 390 frame-number = <1>; 391 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 392 reg = <0xf9023000 0x1000>; 393 status = "disabled"; 394 }; 395 396 frame@f9024000 { 397 frame-number = <2>; 398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 399 reg = <0xf9024000 0x1000>; 400 status = "disabled"; 401 }; 402 403 frame@f9025000 { 404 frame-number = <3>; 405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 406 reg = <0xf9025000 0x1000>; 407 status = "disabled"; 408 }; 409 410 frame@f9026000 { 411 frame-number = <4>; 412 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 413 reg = <0xf9026000 0x1000>; 414 status = "disabled"; 415 }; 416 417 frame@f9027000 { 418 frame-number = <5>; 419 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 420 reg = <0xf9027000 0x1000>; 421 status = "disabled"; 422 }; 423 424 frame@f9028000 { 425 frame-number = <6>; 426 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 427 reg = <0xf9028000 0x1000>; 428 status = "disabled"; 429 }; 430 }; 431 432 usb3: usb@f92f8800 { 433 compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; 434 reg = <0xf92f8800 0x400>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges; 438 439 clocks = <&gcc GCC_USB30_MASTER_CLK>, 440 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 441 <&gcc GCC_USB30_SLEEP_CLK>, 442 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 443 clock-names = "core", 444 "iface", 445 "sleep", 446 "mock_utmi"; 447 448 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 449 <&gcc GCC_USB30_MASTER_CLK>; 450 assigned-clock-rates = <19200000>, <120000000>; 451 452 power-domains = <&gcc USB30_GDSC>; 453 qcom,select-utmi-as-pipe-clk; 454 455 usb@f9200000 { 456 compatible = "snps,dwc3"; 457 reg = <0xf9200000 0xcc00>; 458 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 459 snps,dis_u2_susphy_quirk; 460 snps,dis_enblslpm_quirk; 461 maximum-speed = "high-speed"; 462 dr_mode = "peripheral"; 463 }; 464 }; 465 466 sdhc1: mmc@f9824900 { 467 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 468 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 469 reg-names = "hc", "core"; 470 471 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 473 interrupt-names = "hc_irq", "pwr_irq"; 474 475 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 476 <&gcc GCC_SDCC1_APPS_CLK>, 477 <&xo_board>; 478 clock-names = "iface", "core", "xo"; 479 480 pinctrl-names = "default", "sleep"; 481 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 482 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 483 484 bus-width = <8>; 485 non-removable; 486 status = "disabled"; 487 }; 488 489 sdhc2: mmc@f98a4900 { 490 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 491 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 492 reg-names = "hc", "core"; 493 494 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "hc_irq", "pwr_irq"; 497 498 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 499 <&gcc GCC_SDCC2_APPS_CLK>, 500 <&xo_board>; 501 clock-names = "iface", "core", "xo"; 502 503 pinctrl-names = "default", "sleep"; 504 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 505 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 506 507 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; 508 bus-width = <4>; 509 status = "disabled"; 510 }; 511 512 blsp1_dma: dma-controller@f9904000 { 513 compatible = "qcom,bam-v1.7.0"; 514 reg = <0xf9904000 0x19000>; 515 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 517 clock-names = "bam_clk"; 518 #dma-cells = <1>; 519 qcom,ee = <0>; 520 qcom,controlled-remotely; 521 num-channels = <24>; 522 qcom,num-ees = <4>; 523 }; 524 525 blsp1_uart2: serial@f991e000 { 526 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 527 reg = <0xf991e000 0x1000>; 528 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 529 clock-names = "core", "iface"; 530 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 531 <&gcc GCC_BLSP1_AHB_CLK>; 532 pinctrl-names = "default", "sleep"; 533 pinctrl-0 = <&blsp1_uart2_default>; 534 pinctrl-1 = <&blsp1_uart2_sleep>; 535 status = "disabled"; 536 }; 537 538 blsp1_i2c1: i2c@f9923000 { 539 compatible = "qcom,i2c-qup-v2.2.1"; 540 reg = <0xf9923000 0x500>; 541 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 543 <&gcc GCC_BLSP1_AHB_CLK>; 544 clock-names = "core", "iface"; 545 clock-frequency = <400000>; 546 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 547 dma-names = "tx", "rx"; 548 pinctrl-names = "default", "sleep"; 549 pinctrl-0 = <&i2c1_default>; 550 pinctrl-1 = <&i2c1_sleep>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 blsp1_spi1: spi@f9923000 { 557 compatible = "qcom,spi-qup-v2.2.1"; 558 reg = <0xf9923000 0x500>; 559 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 561 <&gcc GCC_BLSP1_AHB_CLK>; 562 clock-names = "core", "iface"; 563 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 564 dma-names = "tx", "rx"; 565 pinctrl-names = "default", "sleep"; 566 pinctrl-0 = <&blsp1_spi1_default>; 567 pinctrl-1 = <&blsp1_spi1_sleep>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 blsp1_i2c2: i2c@f9924000 { 574 compatible = "qcom,i2c-qup-v2.2.1"; 575 reg = <0xf9924000 0x500>; 576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 578 <&gcc GCC_BLSP1_AHB_CLK>; 579 clock-names = "core", "iface"; 580 clock-frequency = <400000>; 581 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 582 dma-names = "tx", "rx"; 583 pinctrl-names = "default", "sleep"; 584 pinctrl-0 = <&i2c2_default>; 585 pinctrl-1 = <&i2c2_sleep>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 /* I2C3 doesn't exist */ 592 593 blsp1_i2c4: i2c@f9926000 { 594 compatible = "qcom,i2c-qup-v2.2.1"; 595 reg = <0xf9926000 0x500>; 596 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 598 <&gcc GCC_BLSP1_AHB_CLK>; 599 clock-names = "core", "iface"; 600 clock-frequency = <400000>; 601 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; 602 dma-names = "tx", "rx"; 603 pinctrl-names = "default", "sleep"; 604 pinctrl-0 = <&i2c4_default>; 605 pinctrl-1 = <&i2c4_sleep>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 blsp1_i2c5: i2c@f9927000 { 612 compatible = "qcom,i2c-qup-v2.2.1"; 613 reg = <0xf9927000 0x500>; 614 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 616 <&gcc GCC_BLSP1_AHB_CLK>; 617 clock-names = "core", "iface"; 618 clock-frequency = <400000>; 619 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 620 dma-names = "tx", "rx"; 621 pinctrl-names = "default", "sleep"; 622 pinctrl-0 = <&i2c5_default>; 623 pinctrl-1 = <&i2c5_sleep>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 blsp1_i2c6: i2c@f9928000 { 630 compatible = "qcom,i2c-qup-v2.2.1"; 631 reg = <0xf9928000 0x500>; 632 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 634 <&gcc GCC_BLSP1_AHB_CLK>; 635 clock-names = "core", "iface"; 636 clock-frequency = <400000>; 637 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 638 dma-names = "tx", "rx"; 639 pinctrl-names = "default", "sleep"; 640 pinctrl-0 = <&i2c6_default>; 641 pinctrl-1 = <&i2c6_sleep>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 blsp2_dma: dma-controller@f9944000 { 648 compatible = "qcom,bam-v1.7.0"; 649 reg = <0xf9944000 0x19000>; 650 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 652 clock-names = "bam_clk"; 653 #dma-cells = <1>; 654 qcom,ee = <0>; 655 qcom,controlled-remotely; 656 num-channels = <24>; 657 qcom,num-ees = <4>; 658 }; 659 660 blsp2_uart2: serial@f995e000 { 661 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 662 reg = <0xf995e000 0x1000>; 663 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 664 clock-names = "core", "iface"; 665 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 666 <&gcc GCC_BLSP2_AHB_CLK>; 667 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 668 dma-names = "tx", "rx"; 669 pinctrl-names = "default", "sleep"; 670 pinctrl-0 = <&blsp2_uart2_default>; 671 pinctrl-1 = <&blsp2_uart2_sleep>; 672 status = "disabled"; 673 }; 674 675 blsp2_i2c1: i2c@f9963000 { 676 compatible = "qcom,i2c-qup-v2.2.1"; 677 reg = <0xf9963000 0x500>; 678 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 680 <&gcc GCC_BLSP2_AHB_CLK>; 681 clock-names = "core", "iface"; 682 clock-frequency = <400000>; 683 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 684 dma-names = "tx", "rx"; 685 pinctrl-names = "default", "sleep"; 686 pinctrl-0 = <&i2c7_default>; 687 pinctrl-1 = <&i2c7_sleep>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 blsp2_spi4: spi@f9966000 { 694 compatible = "qcom,spi-qup-v2.2.1"; 695 reg = <0xf9966000 0x500>; 696 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 698 <&gcc GCC_BLSP2_AHB_CLK>; 699 clock-names = "core", "iface"; 700 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; 701 dma-names = "tx", "rx"; 702 pinctrl-names = "default", "sleep"; 703 pinctrl-0 = <&blsp2_spi10_default>; 704 pinctrl-1 = <&blsp2_spi10_sleep>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 status = "disabled"; 708 }; 709 710 blsp2_i2c5: i2c@f9967000 { 711 compatible = "qcom,i2c-qup-v2.2.1"; 712 reg = <0xf9967000 0x500>; 713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 715 <&gcc GCC_BLSP2_AHB_CLK>; 716 clock-names = "core", "iface"; 717 clock-frequency = <355000>; 718 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 719 dma-names = "tx", "rx"; 720 pinctrl-names = "default", "sleep"; 721 pinctrl-0 = <&i2c11_default>; 722 pinctrl-1 = <&i2c11_sleep>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 }; 727 728 gcc: clock-controller@fc400000 { 729 compatible = "qcom,gcc-msm8994"; 730 #clock-cells = <1>; 731 #reset-cells = <1>; 732 #power-domain-cells = <1>; 733 reg = <0xfc400000 0x2000>; 734 735 clock-names = "xo", "sleep"; 736 clocks = <&xo_board>, <&sleep_clk>; 737 }; 738 739 rpm_msg_ram: sram@fc428000 { 740 compatible = "qcom,rpm-msg-ram"; 741 reg = <0xfc428000 0x4000>; 742 }; 743 744 restart@fc4ab000 { 745 compatible = "qcom,pshold"; 746 reg = <0xfc4ab000 0x4>; 747 }; 748 749 spmi_bus: spmi@fc4cf000 { 750 compatible = "qcom,spmi-pmic-arb"; 751 reg = <0xfc4cf000 0x1000>, 752 <0xfc4cb000 0x1000>, 753 <0xfc4ca000 0x1000>; 754 reg-names = "core", "intr", "cnfg"; 755 interrupt-names = "periph_irq"; 756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 757 qcom,ee = <0>; 758 qcom,channel = <0>; 759 #address-cells = <2>; 760 #size-cells = <0>; 761 interrupt-controller; 762 #interrupt-cells = <4>; 763 }; 764 765 tcsr_mutex: hwlock@fd484000 { 766 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; 767 reg = <0xfd484000 0x1000>; 768 #hwlock-cells = <1>; 769 }; 770 771 tlmm: pinctrl@fd510000 { 772 compatible = "qcom,msm8994-pinctrl"; 773 reg = <0xfd510000 0x4000>; 774 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 775 gpio-controller; 776 gpio-ranges = <&tlmm 0 0 146>; 777 #gpio-cells = <2>; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 781 blsp1_uart2_default: blsp1-uart2-default-state { 782 pins = "gpio4", "gpio5"; 783 function = "blsp_uart2"; 784 drive-strength = <16>; 785 bias-disable; 786 }; 787 788 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 789 pins = "gpio4", "gpio5"; 790 function = "gpio"; 791 drive-strength = <2>; 792 bias-pull-down; 793 }; 794 795 blsp2_uart2_default: blsp2-uart2-default-state { 796 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 797 function = "blsp_uart8"; 798 drive-strength = <16>; 799 bias-disable; 800 }; 801 802 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 803 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 804 function = "gpio"; 805 drive-strength = <2>; 806 bias-disable; 807 }; 808 809 i2c1_default: i2c1-default-state { 810 pins = "gpio2", "gpio3"; 811 function = "blsp_i2c1"; 812 drive-strength = <2>; 813 bias-disable; 814 }; 815 816 i2c1_sleep: i2c1-sleep-state { 817 pins = "gpio2", "gpio3"; 818 function = "gpio"; 819 drive-strength = <2>; 820 bias-disable; 821 }; 822 823 i2c2_default: i2c2-default-state { 824 pins = "gpio6", "gpio7"; 825 function = "blsp_i2c2"; 826 drive-strength = <2>; 827 bias-disable; 828 }; 829 830 i2c2_sleep: i2c2-sleep-state { 831 pins = "gpio6", "gpio7"; 832 function = "gpio"; 833 drive-strength = <2>; 834 bias-disable; 835 }; 836 837 i2c4_default: i2c4-default-state { 838 pins = "gpio19", "gpio20"; 839 function = "blsp_i2c4"; 840 drive-strength = <2>; 841 bias-disable; 842 }; 843 844 i2c4_sleep: i2c4-sleep-state { 845 pins = "gpio19", "gpio20"; 846 function = "gpio"; 847 drive-strength = <2>; 848 bias-pull-down; 849 }; 850 851 i2c5_default: i2c5-default-state { 852 pins = "gpio23", "gpio24"; 853 function = "blsp_i2c5"; 854 drive-strength = <2>; 855 bias-disable; 856 }; 857 858 i2c5_sleep: i2c5-sleep-state { 859 pins = "gpio23", "gpio24"; 860 function = "gpio"; 861 drive-strength = <2>; 862 bias-disable; 863 }; 864 865 i2c6_default: i2c6-default-state { 866 pins = "gpio28", "gpio27"; 867 function = "blsp_i2c6"; 868 drive-strength = <2>; 869 bias-disable; 870 }; 871 872 i2c6_sleep: i2c6-sleep-state { 873 pins = "gpio28", "gpio27"; 874 function = "gpio"; 875 drive-strength = <2>; 876 bias-disable; 877 }; 878 879 i2c7_default: i2c7-default-state { 880 pins = "gpio44", "gpio43"; 881 function = "blsp_i2c7"; 882 drive-strength = <2>; 883 bias-disable; 884 }; 885 886 i2c7_sleep: i2c7-sleep-state { 887 pins = "gpio44", "gpio43"; 888 function = "gpio"; 889 drive-strength = <2>; 890 bias-disable; 891 }; 892 893 blsp2_spi10_default: blsp2-spi10-default-state { 894 default-pins { 895 pins = "gpio53", "gpio54", "gpio55"; 896 function = "blsp_spi10"; 897 drive-strength = <10>; 898 bias-pull-down; 899 }; 900 901 cs-pins { 902 pins = "gpio67"; 903 function = "gpio"; 904 drive-strength = <2>; 905 bias-disable; 906 }; 907 }; 908 909 blsp2_spi10_sleep: blsp2-spi10-sleep-state { 910 pins = "gpio53", "gpio54", "gpio55"; 911 function = "gpio"; 912 drive-strength = <2>; 913 bias-disable; 914 }; 915 916 i2c11_default: i2c11-default-state { 917 pins = "gpio83", "gpio84"; 918 function = "blsp_i2c11"; 919 drive-strength = <2>; 920 bias-disable; 921 }; 922 923 i2c11_sleep: i2c11-sleep-state { 924 pins = "gpio83", "gpio84"; 925 function = "gpio"; 926 drive-strength = <2>; 927 bias-disable; 928 }; 929 930 blsp1_spi1_default: blsp1-spi1-default-state { 931 default-pins { 932 pins = "gpio0", "gpio1", "gpio3"; 933 function = "blsp_spi1"; 934 drive-strength = <10>; 935 bias-pull-down; 936 }; 937 938 cs-pins { 939 pins = "gpio8"; 940 function = "gpio"; 941 drive-strength = <2>; 942 bias-disable; 943 }; 944 }; 945 946 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 947 pins = "gpio0", "gpio1", "gpio3"; 948 function = "gpio"; 949 drive-strength = <2>; 950 bias-disable; 951 }; 952 953 sdc1_clk_on: clk-on-state { 954 pins = "sdc1_clk"; 955 bias-disable; 956 drive-strength = <16>; 957 }; 958 959 sdc1_clk_off: clk-off-state { 960 pins = "sdc1_clk"; 961 bias-disable; 962 drive-strength = <2>; 963 }; 964 965 sdc1_cmd_on: cmd-on-state { 966 pins = "sdc1_cmd"; 967 bias-pull-up; 968 drive-strength = <8>; 969 }; 970 971 sdc1_cmd_off: cmd-off-state { 972 pins = "sdc1_cmd"; 973 bias-pull-up; 974 drive-strength = <2>; 975 }; 976 977 sdc1_data_on: data-on-state { 978 pins = "sdc1_data"; 979 bias-pull-up; 980 drive-strength = <8>; 981 }; 982 983 sdc1_data_off: data-off-state { 984 pins = "sdc1_data"; 985 bias-pull-up; 986 drive-strength = <2>; 987 }; 988 989 sdc1_rclk_on: rclk-on-state { 990 pins = "sdc1_rclk"; 991 bias-pull-down; 992 }; 993 994 sdc1_rclk_off: rclk-off-state { 995 pins = "sdc1_rclk"; 996 bias-pull-down; 997 }; 998 999 sdc2_clk_on: sdc2-clk-on-state { 1000 pins = "sdc2_clk"; 1001 bias-disable; 1002 drive-strength = <10>; 1003 }; 1004 1005 sdc2_clk_off: sdc2-clk-off-state { 1006 pins = "sdc2_clk"; 1007 bias-disable; 1008 drive-strength = <2>; 1009 }; 1010 1011 sdc2_cmd_on: sdc2-cmd-on-state { 1012 pins = "sdc2_cmd"; 1013 bias-pull-up; 1014 drive-strength = <10>; 1015 }; 1016 1017 sdc2_cmd_off: sdc2-cmd-off-state { 1018 pins = "sdc2_cmd"; 1019 bias-pull-up; 1020 drive-strength = <2>; 1021 }; 1022 1023 sdc2_data_on: sdc2-data-on-state { 1024 pins = "sdc2_data"; 1025 bias-pull-up; 1026 drive-strength = <10>; 1027 }; 1028 1029 sdc2_data_off: sdc2-data-off-state { 1030 pins = "sdc2_data"; 1031 bias-pull-up; 1032 drive-strength = <2>; 1033 }; 1034 }; 1035 1036 mmcc: clock-controller@fd8c0000 { 1037 compatible = "qcom,mmcc-msm8994"; 1038 reg = <0xfd8c0000 0x5200>; 1039 #clock-cells = <1>; 1040 #reset-cells = <1>; 1041 #power-domain-cells = <1>; 1042 1043 clock-names = "xo", 1044 "gpll0", 1045 "mmssnoc_ahb", 1046 "oxili_gfx3d_clk_src", 1047 "dsi0pll", 1048 "dsi0pllbyte", 1049 "dsi1pll", 1050 "dsi1pllbyte", 1051 "hdmipll"; 1052 clocks = <&xo_board>, 1053 <&gcc GPLL0_OUT_MMSSCC>, 1054 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, 1055 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1056 <0>, 1057 <0>, 1058 <0>, 1059 <0>, 1060 <0>; 1061 1062 assigned-clocks = <&mmcc MMPLL0_PLL>, 1063 <&mmcc MMPLL1_PLL>, 1064 <&mmcc MMPLL3_PLL>, 1065 <&mmcc MMPLL4_PLL>, 1066 <&mmcc MMPLL5_PLL>; 1067 assigned-clock-rates = <800000000>, 1068 <1167000000>, 1069 <1020000000>, 1070 <960000000>, 1071 <600000000>; 1072 }; 1073 1074 ocmem: sram@fdd00000 { 1075 compatible = "qcom,msm8974-ocmem"; 1076 reg = <0xfdd00000 0x2000>, 1077 <0xfec00000 0x200000>; 1078 reg-names = "ctrl", "mem"; 1079 ranges = <0 0xfec00000 0x200000>; 1080 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1081 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1082 clock-names = "core", "iface"; 1083 1084 #address-cells = <1>; 1085 #size-cells = <1>; 1086 1087 gmu_sram: gmu-sram@0 { 1088 reg = <0x0 0x180000>; 1089 }; 1090 }; 1091 }; 1092 1093 timer: timer { 1094 compatible = "arm,armv8-timer"; 1095 interrupts = <GIC_PPI 2 0xff08>, 1096 <GIC_PPI 3 0xff08>, 1097 <GIC_PPI 4 0xff08>, 1098 <GIC_PPI 1 0xff08>; 1099 }; 1100 1101 vph_pwr: vph-pwr-regulator { 1102 compatible = "regulator-fixed"; 1103 regulator-name = "vph_pwr"; 1104 1105 regulator-min-microvolt = <3600000>; 1106 regulator-max-microvolt = <3600000>; 1107 1108 regulator-always-on; 1109 }; 1110}; 1111 1112