1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8994.h> 7 8/ { 9 interrupt-parent = <&intc>; 10 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 chosen { }; 15 16 clocks { 17 xo_board: xo_board { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <19200000>; 21 }; 22 23 sleep_clk: sleep_clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <32768>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 CPU0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&L2_0>; 40 L2_0: l2-cache { 41 compatible = "cache"; 42 cache-level = <2>; 43 }; 44 }; 45 46 CPU1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x1>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 }; 53 54 CPU2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x0 0x2>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 }; 61 62 CPU3: cpu@3 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x3>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 }; 69 70 CPU4: cpu@100 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a57"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 next-level-cache = <&L2_1>; 76 L2_1: l2-cache { 77 compatible = "cache"; 78 cache-level = <2>; 79 }; 80 }; 81 82 CPU5: cpu@101 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a57"; 85 reg = <0x0 0x101>; 86 enable-method = "psci"; 87 next-level-cache = <&L2_1>; 88 }; 89 90 CPU6: cpu@102 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a57"; 93 reg = <0x0 0x101>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_1>; 96 }; 97 98 CPU7: cpu@103 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a57"; 101 reg = <0x0 0x101>; 102 enable-method = "psci"; 103 next-level-cache = <&L2_1>; 104 }; 105 106 cpu-map { 107 cluster0 { 108 core0 { 109 cpu = <&CPU0>; 110 }; 111 112 core1 { 113 cpu = <&CPU1>; 114 }; 115 116 core2 { 117 cpu = <&CPU2>; 118 }; 119 120 core3 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 125 cluster1 { 126 core0 { 127 cpu = <&CPU4>; 128 }; 129 130 core1 { 131 cpu = <&CPU5>; 132 }; 133 134 core2 { 135 cpu = <&CPU6>; 136 }; 137 138 core3 { 139 cpu = <&CPU7>; 140 }; 141 }; 142 }; 143 }; 144 145 firmware { 146 scm { 147 compatible = "qcom,scm-msm8994", "qcom,scm"; 148 }; 149 }; 150 151 memory { 152 device_type = "memory"; 153 /* We expect the bootloader to fill in the reg */ 154 reg = <0 0 0 0>; 155 }; 156 157 pmu { 158 compatible = "arm,cortex-a53-pmu"; 159 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 160 }; 161 162 psci { 163 compatible = "arm,psci-0.2"; 164 method = "hvc"; 165 }; 166 167 reserved-memory { 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 smem_mem: smem_region@6a00000 { 173 reg = <0x0 0x6a00000 0x0 0x200000>; 174 no-map; 175 }; 176 }; 177 178 smd { 179 compatible = "qcom,smd"; 180 rpm { 181 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 182 qcom,ipc = <&apcs 8 0>; 183 qcom,smd-edge = <15>; 184 qcom,local-pid = <0>; 185 qcom,remote-pid = <6>; 186 187 rpm_requests: rpm-requests { 188 compatible = "qcom,rpm-msm8994"; 189 qcom,smd-channels = "rpm_requests"; 190 191 rpmcc: rpmcc { 192 compatible = "qcom,rpmcc-msm8994"; 193 #clock-cells = <1>; 194 }; 195 }; 196 }; 197 }; 198 199 smem { 200 compatible = "qcom,smem"; 201 memory-region = <&smem_mem>; 202 qcom,rpm-msg-ram = <&rpm_msg_ram>; 203 hwlocks = <&tcsr_mutex 3>; 204 }; 205 206 soc: soc { 207 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges = <0 0 0 0xffffffff>; 211 compatible = "simple-bus"; 212 213 intc: interrupt-controller@f9000000 { 214 compatible = "qcom,msm-qgic2"; 215 interrupt-controller; 216 #interrupt-cells = <3>; 217 reg = <0xf9000000 0x1000>, 218 <0xf9002000 0x1000>; 219 }; 220 221 apcs: mailbox@f900d000 { 222 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 223 reg = <0xf900d000 0x2000>; 224 #mbox-cells = <1>; 225 }; 226 227 timer@f9020000 { 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges; 231 compatible = "arm,armv7-timer-mem"; 232 reg = <0xf9020000 0x1000>; 233 234 frame@f9021000 { 235 frame-number = <0>; 236 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 238 reg = <0xf9021000 0x1000>, 239 <0xf9022000 0x1000>; 240 }; 241 242 frame@f9023000 { 243 frame-number = <1>; 244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 245 reg = <0xf9023000 0x1000>; 246 status = "disabled"; 247 }; 248 249 frame@f9024000 { 250 frame-number = <2>; 251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 252 reg = <0xf9024000 0x1000>; 253 status = "disabled"; 254 }; 255 256 frame@f9025000 { 257 frame-number = <3>; 258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 259 reg = <0xf9025000 0x1000>; 260 status = "disabled"; 261 }; 262 263 frame@f9026000 { 264 frame-number = <4>; 265 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 266 reg = <0xf9026000 0x1000>; 267 status = "disabled"; 268 }; 269 270 frame@f9027000 { 271 frame-number = <5>; 272 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 273 reg = <0xf9027000 0x1000>; 274 status = "disabled"; 275 }; 276 277 frame@f9028000 { 278 frame-number = <6>; 279 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 280 reg = <0xf9028000 0x1000>; 281 status = "disabled"; 282 }; 283 }; 284 285 usb3: usb@f92f8800 { 286 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 287 reg = <0xf92f8800 0x400>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 292 clocks = <&gcc GCC_USB30_MASTER_CLK>, 293 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 294 <&gcc GCC_USB30_SLEEP_CLK>, 295 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 296 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; 297 298 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 299 <&gcc GCC_USB30_MASTER_CLK>; 300 assigned-clock-rates = <19200000>, <120000000>; 301 302 power-domains = <&gcc USB30_GDSC>; 303 qcom,select-utmi-as-pipe-clk; 304 305 dwc3@f9200000 { 306 compatible = "snps,dwc3"; 307 reg = <0xf9200000 0xcc00>; 308 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 309 snps,dis_u2_susphy_quirk; 310 snps,dis_enblslpm_quirk; 311 maximum-speed = "high-speed"; 312 dr_mode = "peripheral"; 313 }; 314 }; 315 316 sdhc1: sdhci@f9824900 { 317 compatible = "qcom,sdhci-msm-v4"; 318 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 319 reg-names = "hc_mem", "core_mem"; 320 321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 323 interrupt-names = "hc_irq", "pwr_irq"; 324 325 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 326 <&gcc GCC_SDCC1_AHB_CLK>, 327 <&xo_board>; 328 clock-names = "core", "iface", "xo"; 329 330 pinctrl-names = "default", "sleep"; 331 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 332 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 333 334 bus-width = <8>; 335 non-removable; 336 status = "disabled"; 337 }; 338 339 sdhc2: sdhci@f98a4900 { 340 compatible = "qcom,sdhci-msm-v4"; 341 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 342 reg-names = "hc_mem", "core_mem"; 343 344 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "hc_irq", "pwr_irq"; 347 348 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 349 <&gcc GCC_SDCC2_AHB_CLK>, 350 <&xo_board>; 351 clock-names = "core", "iface", "xo"; 352 353 pinctrl-names = "default", "sleep"; 354 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 355 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 356 357 cd-gpios = <&tlmm 100 0>; 358 bus-width = <4>; 359 status = "disabled"; 360 }; 361 362 blsp1_dma: dma-controller@f9904000 { 363 compatible = "qcom,bam-v1.7.0"; 364 reg = <0xf9904000 0x19000>; 365 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 367 clock-names = "bam_clk"; 368 #dma-cells = <1>; 369 qcom,ee = <0>; 370 qcom,controlled-remotely; 371 num-channels = <18>; 372 qcom,num-ees = <4>; 373 }; 374 375 blsp1_uart2: serial@f991e000 { 376 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 377 reg = <0xf991e000 0x1000>; 378 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 379 clock-names = "core", "iface"; 380 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 381 <&gcc GCC_BLSP1_AHB_CLK>; 382 pinctrl-names = "default", "sleep"; 383 pinctrl-0 = <&blsp1_uart2_default>; 384 pinctrl-1 = <&blsp1_uart2_sleep>; 385 status = "disabled"; 386 }; 387 388 blsp_i2c1: i2c@f9923000 { 389 compatible = "qcom,i2c-qup-v2.2.1"; 390 reg = <0xf9923000 0x500>; 391 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 393 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 394 clock-names = "iface", "core"; 395 clock-frequency = <400000>; 396 pinctrl-names = "default", "sleep"; 397 pinctrl-0 = <&i2c1_default>; 398 pinctrl-1 = <&i2c1_sleep>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 blsp_spi0: spi@f9923000 { 405 compatible = "qcom,spi-qup-v2.2.1"; 406 reg = <0xf9923000 0x500>; 407 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 409 <&gcc GCC_BLSP1_AHB_CLK>; 410 clock-names = "core", "iface"; 411 spi-max-frequency = <19200000>; 412 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 413 dma-names = "tx", "rx"; 414 pinctrl-names = "default", "sleep"; 415 pinctrl-0 = <&blsp1_spi0_default>; 416 pinctrl-1 = <&blsp1_spi0_sleep>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 blsp_i2c2: i2c@f9924000 { 423 compatible = "qcom,i2c-qup-v2.2.1"; 424 reg = <0xf9924000 0x500>; 425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 427 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 428 clock-names = "iface", "core"; 429 clock-frequency = <355000>; 430 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 431 dma-names = "tx", "rx"; 432 pinctrl-names = "default", "sleep"; 433 pinctrl-0 = <&i2c2_default>; 434 pinctrl-1 = <&i2c2_sleep>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 /* I2C3 doesn't exist */ 441 442 blsp_i2c4: i2c@f9926000 { 443 compatible = "qcom,i2c-qup-v2.2.1"; 444 reg = <0xf9926000 0x500>; 445 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 447 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 448 clock-names = "iface", "core"; 449 clock-frequency = <355000>; 450 pinctrl-names = "default", "sleep"; 451 pinctrl-0 = <&i2c4_default>; 452 pinctrl-1 = <&i2c4_sleep>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 blsp2_dma: dma-controller@f9944000 { 459 compatible = "qcom,bam-v1.7.0"; 460 reg = <0xf9944000 0x19000>; 461 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 463 clock-names = "bam_clk"; 464 #dma-cells = <1>; 465 qcom,ee = <0>; 466 qcom,controlled-remotely; 467 num-channels = <18>; 468 qcom,num-ees = <4>; 469 }; 470 471 /* According to downstream kernels, i2c6 472 * comes before i2c5 address-wise... 473 */ 474 475 blsp_i2c6: i2c@f9928000 { 476 compatible = "qcom,i2c-qup-v2.2.1"; 477 reg = <0xf9928000 0x500>; 478 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 480 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 481 clock-names = "iface", "core"; 482 clock-frequency = <355000>; 483 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 484 dma-names = "tx", "rx"; 485 pinctrl-names = "default", "sleep"; 486 pinctrl-0 = <&i2c6_default>; 487 pinctrl-1 = <&i2c6_sleep>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 blsp2_uart2: serial@f995e000 { 494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 495 reg = <0xf995e000 0x1000>; 496 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>; 497 clock-names = "core", "iface"; 498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 499 <&gcc GCC_BLSP2_AHB_CLK>; 500 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 501 dma-names = "tx", "rx"; 502 pinctrl-names = "default", "sleep"; 503 pinctrl-0 = <&blsp2_uart2_default>; 504 pinctrl-1 = <&blsp2_uart2_sleep>; 505 status = "disabled"; 506 }; 507 508 blsp_i2c5: i2c@f9967000 { 509 compatible = "qcom,i2c-qup-v2.2.1"; 510 reg = <0xf9967000 0x500>; 511 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 513 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; 514 clock-names = "iface", "core"; 515 clock-frequency = <355000>; 516 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 517 dma-names = "tx", "rx"; 518 pinctrl-names = "default", "sleep"; 519 pinctrl-0 = <&i2c5_default>; 520 pinctrl-1 = <&i2c5_sleep>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 gcc: clock-controller@fc400000 { 527 compatible = "qcom,gcc-msm8994"; 528 #clock-cells = <1>; 529 #reset-cells = <1>; 530 #power-domain-cells = <1>; 531 reg = <0xfc400000 0x2000>; 532 }; 533 534 rpm_msg_ram: memory@fc428000 { 535 compatible = "qcom,rpm-msg-ram"; 536 reg = <0xfc428000 0x4000>; 537 }; 538 539 restart@fc4ab000 { 540 compatible = "qcom,pshold"; 541 reg = <0xfc4ab000 0x4>; 542 }; 543 544 spmi_bus: spmi@fc4c0000 { 545 compatible = "qcom,spmi-pmic-arb"; 546 reg = <0xfc4cf000 0x1000>, 547 <0xfc4cb000 0x1000>, 548 <0xfc4ca000 0x1000>; 549 reg-names = "core", "intr", "cnfg"; 550 interrupt-names = "periph_irq"; 551 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 552 qcom,ee = <0>; 553 qcom,channel = <0>; 554 #address-cells = <2>; 555 #size-cells = <0>; 556 interrupt-controller; 557 #interrupt-cells = <4>; 558 }; 559 560 tcsr_mutex_regs: syscon@fd484000 { 561 compatible = "syscon"; 562 reg = <0xfd484000 0x2000>; 563 }; 564 565 tlmm: pinctrl@fd510000 { 566 compatible = "qcom,msm8994-pinctrl"; 567 reg = <0xfd510000 0x4000>; 568 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 569 gpio-controller; 570 gpio-ranges = <&tlmm 0 0 146>; 571 #gpio-cells = <2>; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 575 blsp1_uart2_default: blsp1-uart2-default { 576 function = "blsp_uart2"; 577 pins = "gpio4", "gpio5"; 578 drive-strength = <16>; 579 bias-disable; 580 }; 581 582 blsp1_uart2_sleep: blsp1-uart2-sleep { 583 function = "gpio"; 584 pins = "gpio4", "gpio5"; 585 drive-strength = <2>; 586 bias-pull-down; 587 }; 588 589 blsp2_uart2_default: blsp2-uart2-default { 590 function = "blsp_uart8"; 591 pins = "gpio45", "gpio46"; 592 drive-strength = <2>; 593 bias-disable; 594 }; 595 596 blsp2_uart2_sleep: blsp2-uart2-sleep { 597 function = "gpio"; 598 pins = "gpio45", "gpio46"; 599 drive-strength = <2>; 600 bias-pull-down; 601 }; 602 603 i2c1_default: i2c1-default { 604 function = "blsp_i2c1"; 605 pins = "gpio2", "gpio3"; 606 drive-strength = <2>; 607 bias-disable; 608 }; 609 610 i2c1_sleep: i2c1-sleep { 611 function = "gpio"; 612 pins = "gpio2", "gpio3"; 613 drive-strength = <2>; 614 bias-disable; 615 }; 616 617 i2c2_default: i2c2-default { 618 function = "blsp_i2c2"; 619 pins = "gpio6", "gpio7"; 620 drive-strength = <2>; 621 bias-disable; 622 }; 623 624 i2c2_sleep: i2c2-sleep { 625 function = "gpio"; 626 pins = "gpio6", "gpio7"; 627 drive-strength = <2>; 628 bias-disable; 629 }; 630 631 i2c4_default: i2c4-default { 632 function = "blsp_i2c4"; 633 pins = "gpio19", "gpio20"; 634 drive-strength = <2>; 635 bias-disable; 636 }; 637 638 i2c4_sleep: i2c4-sleep { 639 function = "gpio"; 640 pins = "gpio19", "gpio20"; 641 drive-strength = <2>; 642 bias-pull-down; 643 input-enable; 644 }; 645 646 i2c5_default: i2c5-default { 647 function = "blsp_i2c5"; 648 pins = "gpio23", "gpio24"; 649 drive-strength = <2>; 650 bias-disable; 651 }; 652 653 i2c5_sleep: i2c5-sleep { 654 function = "gpio"; 655 pins = "gpio23", "gpio24"; 656 drive-strength = <2>; 657 bias-disable; 658 }; 659 660 i2c6_default: i2c6-default { 661 function = "blsp_i2c6"; 662 pins = "gpio28", "gpio27"; 663 drive-strength = <2>; 664 bias-disable; 665 }; 666 667 i2c6_sleep: i2c6-sleep { 668 function = "gpio"; 669 pins = "gpio28", "gpio27"; 670 drive-strength = <2>; 671 bias-disable; 672 }; 673 674 blsp1_spi0_default: blsp1-spi0-default { 675 default { 676 function = "blsp_spi1"; 677 pins = "gpio0", "gpio1", "gpio3"; 678 drive-strength = <10>; 679 bias-pull-down; 680 }; 681 cs { 682 function = "gpio"; 683 pins = "gpio8"; 684 drive-strength = <2>; 685 bias-disable; 686 }; 687 }; 688 689 blsp1_spi0_sleep: blsp1-spi0-sleep { 690 pins = "gpio0", "gpio1", "gpio3"; 691 drive-strength = <2>; 692 bias-disable; 693 }; 694 695 sdc1_clk_on: clk-on { 696 pins = "sdc1_clk"; 697 bias-disable; 698 drive-strength = <16>; 699 }; 700 701 sdc1_clk_off: clk-off { 702 pins = "sdc1_clk"; 703 bias-disable; 704 drive-strength = <2>; 705 }; 706 707 sdc1_cmd_on: cmd-on { 708 pins = "sdc1_cmd"; 709 bias-pull-up; 710 drive-strength = <8>; 711 }; 712 713 sdc1_cmd_off: cmd-off { 714 pins = "sdc1_cmd"; 715 bias-pull-up; 716 drive-strength = <2>; 717 }; 718 719 sdc1_data_on: data-on { 720 pins = "sdc1_data"; 721 bias-pull-up; 722 drive-strength = <8>; 723 }; 724 725 sdc1_data_off: data-off { 726 pins = "sdc1_data"; 727 bias-pull-up; 728 drive-strength = <2>; 729 }; 730 731 sdc1_rclk_on: rclk-on { 732 pins = "sdc1_rclk"; 733 bias-pull-down; 734 }; 735 736 sdc1_rclk_off: rclk-off { 737 pins = "sdc1_rclk"; 738 bias-pull-down; 739 }; 740 741 sdc2_clk_on: sdc2-clk-on { 742 pins = "sdc2_clk"; 743 bias-disable; 744 drive-strength = <10>; 745 }; 746 747 sdc2_clk_off: sdc2-clk-off { 748 pins = "sdc2_clk"; 749 bias-disable; 750 drive-strength = <2>; 751 }; 752 753 sdc2_cmd_on: sdc2-cmd-on { 754 pins = "sdc2_cmd"; 755 bias-pull-up; 756 drive-strength = <10>; 757 }; 758 759 sdc2_cmd_off: sdc2-cmd-off { 760 pins = "sdc2_cmd"; 761 bias-pull-up; 762 drive-strength = <2>; 763 }; 764 765 sdc2_data_on: sdc2-data-on { 766 pins = "sdc2_data"; 767 bias-pull-up; 768 drive-strength = <10>; 769 }; 770 771 sdc2_data_off: sdc2-data-off { 772 pins = "sdc2_data"; 773 bias-pull-up; 774 drive-strength = <2>; 775 }; 776 }; 777 }; 778 779 tcsr_mutex: hwlock { 780 compatible = "qcom,tcsr-mutex"; 781 syscon = <&tcsr_mutex_regs 0 0x80>; 782 #hwlock-cells = <1>; 783 }; 784 785 timer { 786 compatible = "arm,armv8-timer"; 787 interrupts = <GIC_PPI 2 0xff08>, 788 <GIC_PPI 3 0xff08>, 789 <GIC_PPI 4 0xff08>, 790 <GIC_PPI 1 0xff08>; 791 }; 792 793 vreg_vph_pwr: vreg-vph-pwr { 794 compatible = "regulator-fixed"; 795 regulator-name = "vph-pwr"; 796 797 regulator-min-microvolt = <3600000>; 798 regulator-max-microvolt = <3600000>; 799 800 regulator-always-on; 801 }; 802}; 803 804