1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8994.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8994.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc1 = &sdhc1; 21 mmc2 = &sdhc2; 22 }; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x1>; 62 enable-method = "psci"; 63 next-level-cache = <&L2_0>; 64 }; 65 66 CPU2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 next-level-cache = <&L2_0>; 80 }; 81 82 CPU4: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a57"; 85 reg = <0x0 0x100>; 86 enable-method = "psci"; 87 next-level-cache = <&L2_1>; 88 L2_1: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 }; 92 }; 93 94 CPU5: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x0 0x101>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_1>; 100 }; 101 102 CPU6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a57"; 105 reg = <0x0 0x102>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_1>; 108 }; 109 110 CPU7: cpu@103 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a57"; 113 reg = <0x0 0x103>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_1>; 116 }; 117 118 cpu-map { 119 cluster0 { 120 core0 { 121 cpu = <&CPU0>; 122 }; 123 124 core1 { 125 cpu = <&CPU1>; 126 }; 127 128 core2 { 129 cpu = <&CPU2>; 130 }; 131 132 core3 { 133 cpu = <&CPU3>; 134 }; 135 }; 136 137 cluster1 { 138 core0 { 139 cpu = <&CPU4>; 140 }; 141 142 core1 { 143 cpu = <&CPU5>; 144 }; 145 146 cpu6_map: core2 { 147 cpu = <&CPU6>; 148 }; 149 150 cpu7_map: core3 { 151 cpu = <&CPU7>; 152 }; 153 }; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-msm8994", "qcom,scm"; 160 }; 161 }; 162 163 memory@80000000 { 164 device_type = "memory"; 165 /* We expect the bootloader to fill in the reg */ 166 reg = <0 0x80000000 0 0>; 167 }; 168 169 pmu { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 psci { 175 compatible = "arm,psci-0.2"; 176 method = "hvc"; 177 }; 178 179 reserved-memory { 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 dfps_data_mem: dfps_data_mem@3400000 { 185 reg = <0 0x03400000 0 0x1000>; 186 no-map; 187 }; 188 189 cont_splash_mem: memory@3401000 { 190 reg = <0 0x03401000 0 0x2200000>; 191 no-map; 192 }; 193 194 smem_mem: smem_region@6a00000 { 195 reg = <0 0x06a00000 0 0x200000>; 196 no-map; 197 }; 198 199 mpss_mem: memory@7000000 { 200 reg = <0 0x07000000 0 0x5a00000>; 201 no-map; 202 }; 203 204 peripheral_region: memory@ca00000 { 205 reg = <0 0x0ca00000 0 0x1f00000>; 206 no-map; 207 }; 208 209 rmtfs_mem: memory@c6400000 { 210 compatible = "qcom,rmtfs-mem"; 211 reg = <0 0xc6400000 0 0x180000>; 212 no-map; 213 214 qcom,client-id = <1>; 215 }; 216 217 mba_mem: memory@c6700000 { 218 reg = <0 0xc6700000 0 0x100000>; 219 no-map; 220 }; 221 222 audio_mem: memory@c7000000 { 223 reg = <0 0xc7000000 0 0x800000>; 224 no-map; 225 }; 226 227 adsp_mem: memory@c9400000 { 228 reg = <0 0xc9400000 0 0x3f00000>; 229 no-map; 230 }; 231 232 reserved@6c00000 { 233 reg = <0 0x06c00000 0 0x400000>; 234 no-map; 235 }; 236 }; 237 238 smd { 239 compatible = "qcom,smd"; 240 rpm { 241 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 242 qcom,ipc = <&apcs 8 0>; 243 qcom,smd-edge = <15>; 244 qcom,remote-pid = <6>; 245 246 rpm_requests: rpm-requests { 247 compatible = "qcom,rpm-msm8994"; 248 qcom,smd-channels = "rpm_requests"; 249 250 rpmcc: clock-controller { 251 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; 252 #clock-cells = <1>; 253 }; 254 255 rpmpd: power-controller { 256 compatible = "qcom,msm8994-rpmpd"; 257 #power-domain-cells = <1>; 258 operating-points-v2 = <&rpmpd_opp_table>; 259 260 rpmpd_opp_table: opp-table { 261 compatible = "operating-points-v2"; 262 263 rpmpd_opp_ret: opp1 { 264 opp-level = <1>; 265 }; 266 rpmpd_opp_svs_krait: opp2 { 267 opp-level = <2>; 268 }; 269 rpmpd_opp_svs_soc: opp3 { 270 opp-level = <3>; 271 }; 272 rpmpd_opp_nom: opp4 { 273 opp-level = <4>; 274 }; 275 rpmpd_opp_turbo: opp5 { 276 opp-level = <5>; 277 }; 278 rpmpd_opp_super_turbo: opp6 { 279 opp-level = <6>; 280 }; 281 }; 282 }; 283 }; 284 }; 285 }; 286 287 smem { 288 compatible = "qcom,smem"; 289 memory-region = <&smem_mem>; 290 qcom,rpm-msg-ram = <&rpm_msg_ram>; 291 hwlocks = <&tcsr_mutex 3>; 292 }; 293 294 smp2p-lpass { 295 compatible = "qcom,smp2p"; 296 qcom,smem = <443>, <429>; 297 298 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 299 300 qcom,ipc = <&apcs 8 10>; 301 302 qcom,local-pid = <0>; 303 qcom,remote-pid = <2>; 304 305 adsp_smp2p_out: master-kernel { 306 qcom,entry-name = "master-kernel"; 307 #qcom,smem-state-cells = <1>; 308 }; 309 310 adsp_smp2p_in: slave-kernel { 311 qcom,entry-name = "slave-kernel"; 312 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 }; 317 318 smp2p-modem { 319 compatible = "qcom,smp2p"; 320 qcom,smem = <435>, <428>; 321 322 interrupt-parent = <&intc>; 323 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 324 325 qcom,ipc = <&apcs 8 14>; 326 327 qcom,local-pid = <0>; 328 qcom,remote-pid = <1>; 329 330 modem_smp2p_out: master-kernel { 331 qcom,entry-name = "master-kernel"; 332 #qcom,smem-state-cells = <1>; 333 }; 334 335 modem_smp2p_in: slave-kernel { 336 qcom,entry-name = "slave-kernel"; 337 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 }; 342 343 soc: soc@0 { 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0 0 0 0xffffffff>; 347 compatible = "simple-bus"; 348 349 intc: interrupt-controller@f9000000 { 350 compatible = "qcom,msm-qgic2"; 351 interrupt-controller; 352 #interrupt-cells = <3>; 353 reg = <0xf9000000 0x1000>, 354 <0xf9002000 0x1000>; 355 }; 356 357 apcs: mailbox@f900d000 { 358 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 359 reg = <0xf900d000 0x2000>; 360 #mbox-cells = <1>; 361 }; 362 363 watchdog@f9017000 { 364 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; 365 reg = <0xf9017000 0x1000>; 366 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 368 clocks = <&sleep_clk>; 369 timeout-sec = <10>; 370 }; 371 372 timer@f9020000 { 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges; 376 compatible = "arm,armv7-timer-mem"; 377 reg = <0xf9020000 0x1000>; 378 379 frame@f9021000 { 380 frame-number = <0>; 381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 383 reg = <0xf9021000 0x1000>, 384 <0xf9022000 0x1000>; 385 }; 386 387 frame@f9023000 { 388 frame-number = <1>; 389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 390 reg = <0xf9023000 0x1000>; 391 status = "disabled"; 392 }; 393 394 frame@f9024000 { 395 frame-number = <2>; 396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 397 reg = <0xf9024000 0x1000>; 398 status = "disabled"; 399 }; 400 401 frame@f9025000 { 402 frame-number = <3>; 403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 404 reg = <0xf9025000 0x1000>; 405 status = "disabled"; 406 }; 407 408 frame@f9026000 { 409 frame-number = <4>; 410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 411 reg = <0xf9026000 0x1000>; 412 status = "disabled"; 413 }; 414 415 frame@f9027000 { 416 frame-number = <5>; 417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 418 reg = <0xf9027000 0x1000>; 419 status = "disabled"; 420 }; 421 422 frame@f9028000 { 423 frame-number = <6>; 424 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 425 reg = <0xf9028000 0x1000>; 426 status = "disabled"; 427 }; 428 }; 429 430 usb3: usb@f92f8800 { 431 compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; 432 reg = <0xf92f8800 0x400>; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges; 436 437 clocks = <&gcc GCC_USB30_MASTER_CLK>, 438 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 439 <&gcc GCC_USB30_SLEEP_CLK>, 440 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 441 clock-names = "core", 442 "iface", 443 "sleep", 444 "mock_utmi"; 445 446 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 447 <&gcc GCC_USB30_MASTER_CLK>; 448 assigned-clock-rates = <19200000>, <120000000>; 449 450 power-domains = <&gcc USB30_GDSC>; 451 qcom,select-utmi-as-pipe-clk; 452 453 usb@f9200000 { 454 compatible = "snps,dwc3"; 455 reg = <0xf9200000 0xcc00>; 456 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 457 snps,dis_u2_susphy_quirk; 458 snps,dis_enblslpm_quirk; 459 maximum-speed = "high-speed"; 460 dr_mode = "peripheral"; 461 }; 462 }; 463 464 sdhc1: mmc@f9824900 { 465 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 466 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 467 reg-names = "hc", "core"; 468 469 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "hc_irq", "pwr_irq"; 472 473 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 474 <&gcc GCC_SDCC1_APPS_CLK>, 475 <&xo_board>; 476 clock-names = "iface", "core", "xo"; 477 478 pinctrl-names = "default", "sleep"; 479 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 480 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 481 482 bus-width = <8>; 483 non-removable; 484 status = "disabled"; 485 }; 486 487 sdhc2: mmc@f98a4900 { 488 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 489 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 490 reg-names = "hc", "core"; 491 492 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "hc_irq", "pwr_irq"; 495 496 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 497 <&gcc GCC_SDCC2_APPS_CLK>, 498 <&xo_board>; 499 clock-names = "iface", "core", "xo"; 500 501 pinctrl-names = "default", "sleep"; 502 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 503 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 504 505 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; 506 bus-width = <4>; 507 status = "disabled"; 508 }; 509 510 blsp1_dma: dma-controller@f9904000 { 511 compatible = "qcom,bam-v1.7.0"; 512 reg = <0xf9904000 0x19000>; 513 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "bam_clk"; 516 #dma-cells = <1>; 517 qcom,ee = <0>; 518 qcom,controlled-remotely; 519 num-channels = <24>; 520 qcom,num-ees = <4>; 521 }; 522 523 blsp1_uart2: serial@f991e000 { 524 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 525 reg = <0xf991e000 0x1000>; 526 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 527 clock-names = "core", "iface"; 528 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 529 <&gcc GCC_BLSP1_AHB_CLK>; 530 pinctrl-names = "default", "sleep"; 531 pinctrl-0 = <&blsp1_uart2_default>; 532 pinctrl-1 = <&blsp1_uart2_sleep>; 533 status = "disabled"; 534 }; 535 536 blsp1_i2c1: i2c@f9923000 { 537 compatible = "qcom,i2c-qup-v2.2.1"; 538 reg = <0xf9923000 0x500>; 539 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 541 <&gcc GCC_BLSP1_AHB_CLK>; 542 clock-names = "core", "iface"; 543 clock-frequency = <400000>; 544 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 545 dma-names = "tx", "rx"; 546 pinctrl-names = "default", "sleep"; 547 pinctrl-0 = <&i2c1_default>; 548 pinctrl-1 = <&i2c1_sleep>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 blsp1_spi1: spi@f9923000 { 555 compatible = "qcom,spi-qup-v2.2.1"; 556 reg = <0xf9923000 0x500>; 557 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 559 <&gcc GCC_BLSP1_AHB_CLK>; 560 clock-names = "core", "iface"; 561 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 562 dma-names = "tx", "rx"; 563 pinctrl-names = "default", "sleep"; 564 pinctrl-0 = <&blsp1_spi1_default>; 565 pinctrl-1 = <&blsp1_spi1_sleep>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 blsp1_i2c2: i2c@f9924000 { 572 compatible = "qcom,i2c-qup-v2.2.1"; 573 reg = <0xf9924000 0x500>; 574 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 576 <&gcc GCC_BLSP1_AHB_CLK>; 577 clock-names = "core", "iface"; 578 clock-frequency = <400000>; 579 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 580 dma-names = "tx", "rx"; 581 pinctrl-names = "default", "sleep"; 582 pinctrl-0 = <&i2c2_default>; 583 pinctrl-1 = <&i2c2_sleep>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 /* I2C3 doesn't exist */ 590 591 blsp1_i2c4: i2c@f9926000 { 592 compatible = "qcom,i2c-qup-v2.2.1"; 593 reg = <0xf9926000 0x500>; 594 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 596 <&gcc GCC_BLSP1_AHB_CLK>; 597 clock-names = "core", "iface"; 598 clock-frequency = <400000>; 599 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; 600 dma-names = "tx", "rx"; 601 pinctrl-names = "default", "sleep"; 602 pinctrl-0 = <&i2c4_default>; 603 pinctrl-1 = <&i2c4_sleep>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 status = "disabled"; 607 }; 608 609 blsp1_i2c5: i2c@f9927000 { 610 compatible = "qcom,i2c-qup-v2.2.1"; 611 reg = <0xf9927000 0x500>; 612 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 614 <&gcc GCC_BLSP1_AHB_CLK>; 615 clock-names = "core", "iface"; 616 clock-frequency = <400000>; 617 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 618 dma-names = "tx", "rx"; 619 pinctrl-names = "default", "sleep"; 620 pinctrl-0 = <&i2c5_default>; 621 pinctrl-1 = <&i2c5_sleep>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 blsp1_i2c6: i2c@f9928000 { 628 compatible = "qcom,i2c-qup-v2.2.1"; 629 reg = <0xf9928000 0x500>; 630 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 632 <&gcc GCC_BLSP1_AHB_CLK>; 633 clock-names = "core", "iface"; 634 clock-frequency = <400000>; 635 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 636 dma-names = "tx", "rx"; 637 pinctrl-names = "default", "sleep"; 638 pinctrl-0 = <&i2c6_default>; 639 pinctrl-1 = <&i2c6_sleep>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 status = "disabled"; 643 }; 644 645 blsp2_dma: dma-controller@f9944000 { 646 compatible = "qcom,bam-v1.7.0"; 647 reg = <0xf9944000 0x19000>; 648 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 650 clock-names = "bam_clk"; 651 #dma-cells = <1>; 652 qcom,ee = <0>; 653 qcom,controlled-remotely; 654 num-channels = <24>; 655 qcom,num-ees = <4>; 656 }; 657 658 blsp2_uart2: serial@f995e000 { 659 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 660 reg = <0xf995e000 0x1000>; 661 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 662 clock-names = "core", "iface"; 663 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 664 <&gcc GCC_BLSP2_AHB_CLK>; 665 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 666 dma-names = "tx", "rx"; 667 pinctrl-names = "default", "sleep"; 668 pinctrl-0 = <&blsp2_uart2_default>; 669 pinctrl-1 = <&blsp2_uart2_sleep>; 670 status = "disabled"; 671 }; 672 673 blsp2_i2c1: i2c@f9963000 { 674 compatible = "qcom,i2c-qup-v2.2.1"; 675 reg = <0xf9963000 0x500>; 676 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 678 <&gcc GCC_BLSP2_AHB_CLK>; 679 clock-names = "core", "iface"; 680 clock-frequency = <400000>; 681 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 682 dma-names = "tx", "rx"; 683 pinctrl-names = "default", "sleep"; 684 pinctrl-0 = <&i2c7_default>; 685 pinctrl-1 = <&i2c7_sleep>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 blsp2_spi4: spi@f9966000 { 692 compatible = "qcom,spi-qup-v2.2.1"; 693 reg = <0xf9966000 0x500>; 694 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 696 <&gcc GCC_BLSP2_AHB_CLK>; 697 clock-names = "core", "iface"; 698 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; 699 dma-names = "tx", "rx"; 700 pinctrl-names = "default", "sleep"; 701 pinctrl-0 = <&blsp2_spi10_default>; 702 pinctrl-1 = <&blsp2_spi10_sleep>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 status = "disabled"; 706 }; 707 708 blsp2_i2c5: i2c@f9967000 { 709 compatible = "qcom,i2c-qup-v2.2.1"; 710 reg = <0xf9967000 0x500>; 711 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 713 <&gcc GCC_BLSP2_AHB_CLK>; 714 clock-names = "core", "iface"; 715 clock-frequency = <355000>; 716 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 717 dma-names = "tx", "rx"; 718 pinctrl-names = "default", "sleep"; 719 pinctrl-0 = <&i2c11_default>; 720 pinctrl-1 = <&i2c11_sleep>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 gcc: clock-controller@fc400000 { 727 compatible = "qcom,gcc-msm8994"; 728 #clock-cells = <1>; 729 #reset-cells = <1>; 730 #power-domain-cells = <1>; 731 reg = <0xfc400000 0x2000>; 732 733 clock-names = "xo", "sleep"; 734 clocks = <&xo_board>, <&sleep_clk>; 735 }; 736 737 rpm_msg_ram: sram@fc428000 { 738 compatible = "qcom,rpm-msg-ram"; 739 reg = <0xfc428000 0x4000>; 740 }; 741 742 restart@fc4ab000 { 743 compatible = "qcom,pshold"; 744 reg = <0xfc4ab000 0x4>; 745 }; 746 747 spmi_bus: spmi@fc4cf000 { 748 compatible = "qcom,spmi-pmic-arb"; 749 reg = <0xfc4cf000 0x1000>, 750 <0xfc4cb000 0x1000>, 751 <0xfc4ca000 0x1000>; 752 reg-names = "core", "intr", "cnfg"; 753 interrupt-names = "periph_irq"; 754 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 755 qcom,ee = <0>; 756 qcom,channel = <0>; 757 #address-cells = <2>; 758 #size-cells = <0>; 759 interrupt-controller; 760 #interrupt-cells = <4>; 761 }; 762 763 tcsr_mutex: hwlock@fd484000 { 764 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; 765 reg = <0xfd484000 0x1000>; 766 #hwlock-cells = <1>; 767 }; 768 769 tlmm: pinctrl@fd510000 { 770 compatible = "qcom,msm8994-pinctrl"; 771 reg = <0xfd510000 0x4000>; 772 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 773 gpio-controller; 774 gpio-ranges = <&tlmm 0 0 146>; 775 #gpio-cells = <2>; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 779 blsp1_uart2_default: blsp1-uart2-default-state { 780 pins = "gpio4", "gpio5"; 781 function = "blsp_uart2"; 782 drive-strength = <16>; 783 bias-disable; 784 }; 785 786 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 787 pins = "gpio4", "gpio5"; 788 function = "gpio"; 789 drive-strength = <2>; 790 bias-pull-down; 791 }; 792 793 blsp2_uart2_default: blsp2-uart2-default-state { 794 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 795 function = "blsp_uart8"; 796 drive-strength = <16>; 797 bias-disable; 798 }; 799 800 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 801 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 802 function = "gpio"; 803 drive-strength = <2>; 804 bias-disable; 805 }; 806 807 i2c1_default: i2c1-default-state { 808 pins = "gpio2", "gpio3"; 809 function = "blsp_i2c1"; 810 drive-strength = <2>; 811 bias-disable; 812 }; 813 814 i2c1_sleep: i2c1-sleep-state { 815 pins = "gpio2", "gpio3"; 816 function = "gpio"; 817 drive-strength = <2>; 818 bias-disable; 819 }; 820 821 i2c2_default: i2c2-default-state { 822 pins = "gpio6", "gpio7"; 823 function = "blsp_i2c2"; 824 drive-strength = <2>; 825 bias-disable; 826 }; 827 828 i2c2_sleep: i2c2-sleep-state { 829 pins = "gpio6", "gpio7"; 830 function = "gpio"; 831 drive-strength = <2>; 832 bias-disable; 833 }; 834 835 i2c4_default: i2c4-default-state { 836 pins = "gpio19", "gpio20"; 837 function = "blsp_i2c4"; 838 drive-strength = <2>; 839 bias-disable; 840 }; 841 842 i2c4_sleep: i2c4-sleep-state { 843 pins = "gpio19", "gpio20"; 844 function = "gpio"; 845 drive-strength = <2>; 846 bias-pull-down; 847 }; 848 849 i2c5_default: i2c5-default-state { 850 pins = "gpio23", "gpio24"; 851 function = "blsp_i2c5"; 852 drive-strength = <2>; 853 bias-disable; 854 }; 855 856 i2c5_sleep: i2c5-sleep-state { 857 pins = "gpio23", "gpio24"; 858 function = "gpio"; 859 drive-strength = <2>; 860 bias-disable; 861 }; 862 863 i2c6_default: i2c6-default-state { 864 pins = "gpio28", "gpio27"; 865 function = "blsp_i2c6"; 866 drive-strength = <2>; 867 bias-disable; 868 }; 869 870 i2c6_sleep: i2c6-sleep-state { 871 pins = "gpio28", "gpio27"; 872 function = "gpio"; 873 drive-strength = <2>; 874 bias-disable; 875 }; 876 877 i2c7_default: i2c7-default-state { 878 pins = "gpio44", "gpio43"; 879 function = "blsp_i2c7"; 880 drive-strength = <2>; 881 bias-disable; 882 }; 883 884 i2c7_sleep: i2c7-sleep-state { 885 pins = "gpio44", "gpio43"; 886 function = "gpio"; 887 drive-strength = <2>; 888 bias-disable; 889 }; 890 891 blsp2_spi10_default: blsp2-spi10-default-state { 892 default-pins { 893 pins = "gpio53", "gpio54", "gpio55"; 894 function = "blsp_spi10"; 895 drive-strength = <10>; 896 bias-pull-down; 897 }; 898 899 cs-pins { 900 pins = "gpio67"; 901 function = "gpio"; 902 drive-strength = <2>; 903 bias-disable; 904 }; 905 }; 906 907 blsp2_spi10_sleep: blsp2-spi10-sleep-state { 908 pins = "gpio53", "gpio54", "gpio55"; 909 function = "gpio"; 910 drive-strength = <2>; 911 bias-disable; 912 }; 913 914 i2c11_default: i2c11-default-state { 915 pins = "gpio83", "gpio84"; 916 function = "blsp_i2c11"; 917 drive-strength = <2>; 918 bias-disable; 919 }; 920 921 i2c11_sleep: i2c11-sleep-state { 922 pins = "gpio83", "gpio84"; 923 function = "gpio"; 924 drive-strength = <2>; 925 bias-disable; 926 }; 927 928 blsp1_spi1_default: blsp1-spi1-default-state { 929 default-pins { 930 pins = "gpio0", "gpio1", "gpio3"; 931 function = "blsp_spi1"; 932 drive-strength = <10>; 933 bias-pull-down; 934 }; 935 936 cs-pins { 937 pins = "gpio8"; 938 function = "gpio"; 939 drive-strength = <2>; 940 bias-disable; 941 }; 942 }; 943 944 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 945 pins = "gpio0", "gpio1", "gpio3"; 946 function = "gpio"; 947 drive-strength = <2>; 948 bias-disable; 949 }; 950 951 sdc1_clk_on: clk-on-state { 952 pins = "sdc1_clk"; 953 bias-disable; 954 drive-strength = <16>; 955 }; 956 957 sdc1_clk_off: clk-off-state { 958 pins = "sdc1_clk"; 959 bias-disable; 960 drive-strength = <2>; 961 }; 962 963 sdc1_cmd_on: cmd-on-state { 964 pins = "sdc1_cmd"; 965 bias-pull-up; 966 drive-strength = <8>; 967 }; 968 969 sdc1_cmd_off: cmd-off-state { 970 pins = "sdc1_cmd"; 971 bias-pull-up; 972 drive-strength = <2>; 973 }; 974 975 sdc1_data_on: data-on-state { 976 pins = "sdc1_data"; 977 bias-pull-up; 978 drive-strength = <8>; 979 }; 980 981 sdc1_data_off: data-off-state { 982 pins = "sdc1_data"; 983 bias-pull-up; 984 drive-strength = <2>; 985 }; 986 987 sdc1_rclk_on: rclk-on-state { 988 pins = "sdc1_rclk"; 989 bias-pull-down; 990 }; 991 992 sdc1_rclk_off: rclk-off-state { 993 pins = "sdc1_rclk"; 994 bias-pull-down; 995 }; 996 997 sdc2_clk_on: sdc2-clk-on-state { 998 pins = "sdc2_clk"; 999 bias-disable; 1000 drive-strength = <10>; 1001 }; 1002 1003 sdc2_clk_off: sdc2-clk-off-state { 1004 pins = "sdc2_clk"; 1005 bias-disable; 1006 drive-strength = <2>; 1007 }; 1008 1009 sdc2_cmd_on: sdc2-cmd-on-state { 1010 pins = "sdc2_cmd"; 1011 bias-pull-up; 1012 drive-strength = <10>; 1013 }; 1014 1015 sdc2_cmd_off: sdc2-cmd-off-state { 1016 pins = "sdc2_cmd"; 1017 bias-pull-up; 1018 drive-strength = <2>; 1019 }; 1020 1021 sdc2_data_on: sdc2-data-on-state { 1022 pins = "sdc2_data"; 1023 bias-pull-up; 1024 drive-strength = <10>; 1025 }; 1026 1027 sdc2_data_off: sdc2-data-off-state { 1028 pins = "sdc2_data"; 1029 bias-pull-up; 1030 drive-strength = <2>; 1031 }; 1032 }; 1033 1034 mmcc: clock-controller@fd8c0000 { 1035 compatible = "qcom,mmcc-msm8994"; 1036 reg = <0xfd8c0000 0x5200>; 1037 #clock-cells = <1>; 1038 #reset-cells = <1>; 1039 #power-domain-cells = <1>; 1040 1041 clock-names = "xo", 1042 "gpll0", 1043 "mmssnoc_ahb", 1044 "oxili_gfx3d_clk_src", 1045 "dsi0pll", 1046 "dsi0pllbyte", 1047 "dsi1pll", 1048 "dsi1pllbyte", 1049 "hdmipll"; 1050 clocks = <&xo_board>, 1051 <&gcc GPLL0_OUT_MMSSCC>, 1052 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, 1053 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1054 <0>, 1055 <0>, 1056 <0>, 1057 <0>, 1058 <0>; 1059 1060 assigned-clocks = <&mmcc MMPLL0_PLL>, 1061 <&mmcc MMPLL1_PLL>, 1062 <&mmcc MMPLL3_PLL>, 1063 <&mmcc MMPLL4_PLL>, 1064 <&mmcc MMPLL5_PLL>; 1065 assigned-clock-rates = <800000000>, 1066 <1167000000>, 1067 <1020000000>, 1068 <960000000>, 1069 <600000000>; 1070 }; 1071 1072 ocmem: sram@fdd00000 { 1073 compatible = "qcom,msm8974-ocmem"; 1074 reg = <0xfdd00000 0x2000>, 1075 <0xfec00000 0x200000>; 1076 reg-names = "ctrl", "mem"; 1077 ranges = <0 0xfec00000 0x200000>; 1078 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1079 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1080 clock-names = "core", "iface"; 1081 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 1085 gmu_sram: gmu-sram@0 { 1086 reg = <0x0 0x180000>; 1087 }; 1088 }; 1089 }; 1090 1091 timer: timer { 1092 compatible = "arm,armv8-timer"; 1093 interrupts = <GIC_PPI 2 0xff08>, 1094 <GIC_PPI 3 0xff08>, 1095 <GIC_PPI 4 0xff08>, 1096 <GIC_PPI 1 0xff08>; 1097 }; 1098 1099 vph_pwr: vph-pwr-regulator { 1100 compatible = "regulator-fixed"; 1101 regulator-name = "vph_pwr"; 1102 1103 regulator-min-microvolt = <3600000>; 1104 regulator-max-microvolt = <3600000>; 1105 1106 regulator-always-on; 1107 }; 1108}; 1109 1110