1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8994.h> 7 8/ { 9 interrupt-parent = <&intc>; 10 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 chosen { }; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 CPU0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a53"; 23 reg = <0x0 0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 L2_0: l2-cache { 27 compatible = "cache"; 28 cache-level = <2>; 29 }; 30 }; 31 32 CPU1: cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 reg = <0x0 0x1>; 36 next-level-cache = <&L2_0>; 37 enable-method = "psci"; 38 }; 39 40 CPU2: cpu@2 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x2>; 44 next-level-cache = <&L2_0>; 45 enable-method = "psci"; 46 }; 47 48 CPU3: cpu@3 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x0 0x3>; 52 next-level-cache = <&L2_0>; 53 enable-method = "psci"; 54 }; 55 56 CPU4: cpu@100 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57"; 59 reg = <0x0 0x100>; 60 next-level-cache = <&L2_1>; 61 enable-method = "psci"; 62 L2_1: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 }; 66 }; 67 68 CPU5: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a57"; 71 reg = <0x0 0x101>; 72 next-level-cache = <&L2_1>; 73 enable-method = "psci"; 74 }; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&CPU0>; 80 }; 81 82 core1 { 83 cpu = <&CPU1>; 84 }; 85 86 core2 { 87 cpu = <&CPU2>; 88 }; 89 90 core3 { 91 cpu = <&CPU3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&CPU4>; 98 }; 99 100 core1 { 101 cpu = <&CPU5>; 102 }; 103 }; 104 }; 105 }; 106 107 clocks { 108 xo_board: xo_board { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <19200000>; 112 }; 113 114 sleep_clk: sleep_clk { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32768>; 118 }; 119 }; 120 121 firmware { 122 scm { 123 compatible = "qcom,scm-msm8994", "qcom,scm"; 124 }; 125 }; 126 127 memory { 128 device_type = "memory"; 129 /* We expect the bootloader to fill in the reg */ 130 reg = <0 0 0 0>; 131 }; 132 133 pmu { 134 compatible = "arm,cortex-a53-pmu"; 135 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 psci { 139 compatible = "arm,psci-0.2"; 140 method = "hvc"; 141 }; 142 143 reserved-memory { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 smem_region: smem@6a00000 { 149 reg = <0x0 0x6a00000 0x0 0x200000>; 150 no-map; 151 }; 152 }; 153 154 sfpb_mutex: hwmutex { 155 compatible = "qcom,sfpb-mutex"; 156 syscon = <&sfpb_mutex_regs 0x0 0x100>; 157 #hwlock-cells = <1>; 158 }; 159 160 smem { 161 compatible = "qcom,smem"; 162 memory-region = <&smem_region>; 163 qcom,rpm-msg-ram = <&rpm_msg_ram>; 164 hwlocks = <&sfpb_mutex 3>; 165 }; 166 167 soc { 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0 0 0 0xffffffff>; 171 compatible = "simple-bus"; 172 173 intc: interrupt-controller@f9000000 { 174 compatible = "qcom,msm-qgic2"; 175 interrupt-controller; 176 #interrupt-cells = <3>; 177 reg = <0xf9000000 0x1000>, 178 <0xf9002000 0x1000>; 179 }; 180 181 apcs: mailbox@f900d000 { 182 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 183 reg = <0xf900d000 0x2000>; 184 #mbox-cells = <1>; 185 }; 186 187 timer@f9020000 { 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges; 191 compatible = "arm,armv7-timer-mem"; 192 reg = <0xf9020000 0x1000>; 193 194 frame@f9021000 { 195 frame-number = <0>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 198 reg = <0xf9021000 0x1000>, 199 <0xf9022000 0x1000>; 200 }; 201 202 frame@f9023000 { 203 frame-number = <1>; 204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 205 reg = <0xf9023000 0x1000>; 206 status = "disabled"; 207 }; 208 209 frame@f9024000 { 210 frame-number = <2>; 211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 212 reg = <0xf9024000 0x1000>; 213 status = "disabled"; 214 }; 215 216 frame@f9025000 { 217 frame-number = <3>; 218 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 219 reg = <0xf9025000 0x1000>; 220 status = "disabled"; 221 }; 222 223 frame@f9026000 { 224 frame-number = <4>; 225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 226 reg = <0xf9026000 0x1000>; 227 status = "disabled"; 228 }; 229 230 frame@f9027000 { 231 frame-number = <5>; 232 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 233 reg = <0xf9027000 0x1000>; 234 status = "disabled"; 235 }; 236 237 frame@f9028000 { 238 frame-number = <6>; 239 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 240 reg = <0xf9028000 0x1000>; 241 status = "disabled"; 242 }; 243 }; 244 245 usb3: usb@f92f8800 { 246 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 247 reg = <0xf92f8800 0x400>; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges; 251 252 clocks = <&gcc GCC_USB30_MASTER_CLK>, 253 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 254 <&gcc GCC_USB30_SLEEP_CLK>, 255 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 256 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; 257 258 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 259 <&gcc GCC_USB30_MASTER_CLK>; 260 assigned-clock-rates = <19200000>, <120000000>; 261 262 power-domains = <&gcc USB30_GDSC>; 263 qcom,select-utmi-as-pipe-clk; 264 265 dwc3@f9200000 { 266 compatible = "snps,dwc3"; 267 reg = <0xf9200000 0xcc00>; 268 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 269 snps,dis_u2_susphy_quirk; 270 snps,dis_enblslpm_quirk; 271 maximum-speed = "high-speed"; 272 dr_mode = "peripheral"; 273 }; 274 }; 275 276 sdhc_1: sdhci@f9824900 { 277 compatible = "qcom,sdhci-msm-v4"; 278 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 279 reg-names = "hc_mem", "core_mem"; 280 281 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "hc_irq", "pwr_irq"; 284 285 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 286 <&gcc GCC_SDCC1_AHB_CLK>, 287 <&xo_board>; 288 clock-names = "core", "iface", "xo"; 289 290 pinctrl-names = "default", "sleep"; 291 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on 292 &sdc1_rclk_on>; 293 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off 294 &sdc1_rclk_off>; 295 296 regulator-always-on; 297 bus-width = <8>; 298 non-removable; 299 300 status = "disabled"; 301 }; 302 303 sdhc_2: sdhci@f98a4900 { 304 compatible = "qcom,sdhci-msm-v4"; 305 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 306 reg-names = "hc_mem", "core_mem"; 307 308 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "hc_irq", "pwr_irq"; 311 312 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 313 <&gcc GCC_SDCC2_AHB_CLK>, 314 <&xo_board>; 315 clock-names = "core", "iface", "xo"; 316 317 pinctrl-names = "default", "sleep"; 318 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 319 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 320 321 cd-gpios = <&tlmm 100 0>; 322 bus-width = <4>; 323 status = "disabled"; 324 }; 325 326 blsp1_uart2: serial@f991e000 { 327 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 328 reg = <0xf991e000 0x1000>; 329 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>; 330 clock-names = "core", "iface"; 331 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 332 <&gcc GCC_BLSP1_AHB_CLK>; 333 pinctrl-names = "default", "sleep"; 334 pinctrl-0 = <&blsp1_uart2_default>; 335 pinctrl-1 = <&blsp1_uart2_sleep>; 336 status = "disabled"; 337 }; 338 339 blsp_i2c1: i2c@f9923000 { 340 compatible = "qcom,i2c-qup-v2.2.1"; 341 reg = <0xf9923000 0x500>; 342 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 344 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 345 clock-names = "iface", "core"; 346 clock-frequency = <400000>; 347 pinctrl-names = "default", "sleep"; 348 pinctrl-0 = <&i2c1_default>; 349 pinctrl-1 = <&i2c1_sleep>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 355 blsp_i2c2: i2c@f9924000 { 356 compatible = "qcom,i2c-qup-v2.2.1"; 357 reg = <0xf9924000 0x500>; 358 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 360 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 361 clock-names = "iface", "core"; 362 clock-frequency = <400000>; 363 pinctrl-names = "default", "sleep"; 364 pinctrl-0 = <&i2c2_default>; 365 pinctrl-1 = <&i2c2_sleep>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 status = "disabled"; 369 }; 370 371 /* Somebody was very creative with their numbering scheme downstream... */ 372 373 blsp_i2c13: i2c@f9927000 { 374 compatible = "qcom,i2c-qup-v2.2.1"; 375 reg = <0xf9927000 0x500>; 376 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 378 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 379 clock-names = "iface", "core"; 380 clock-frequency = <400000>; 381 pinctrl-names = "default", "sleep"; 382 pinctrl-0 = <&i2c13_default>; 383 pinctrl-1 = <&i2c13_sleep>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 blsp_i2c6: i2c@f9928000 { 390 compatible = "qcom,i2c-qup-v2.2.1"; 391 reg = <0xf9928000 0x500>; 392 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 394 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 395 clock-names = "iface", "core"; 396 clock-frequency = <400000>; 397 pinctrl-names = "default", "sleep"; 398 pinctrl-0 = <&i2c6_default>; 399 pinctrl-1 = <&i2c6_sleep>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 blsp2_uart2: serial@f995e000 { 406 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 407 reg = <0xf995e000 0x1000>; 408 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 409 clock-names = "core", "iface"; 410 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 411 <&gcc GCC_BLSP2_AHB_CLK>; 412 pinctrl-names = "default", "sleep"; 413 pinctrl-0 = <&blsp2_uart2_default>; 414 pinctrl-1 = <&blsp2_uart2_sleep>; 415 status = "disabled"; 416 }; 417 418 blsp_i2c7: i2c@f9963000 { 419 compatible = "qcom,i2c-qup-v2.2.1"; 420 reg = <0xf9963000 0x500>; 421 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 423 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 424 clock-names = "iface", "core"; 425 clock-frequency = <400000>; 426 pinctrl-names = "default", "sleep"; 427 pinctrl-0 = <&i2c7_default>; 428 pinctrl-1 = <&i2c7_sleep>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 blsp_i2c5: i2c@f9967000 { 435 compatible = "qcom,i2c-qup-v2.2.1"; 436 reg = <0xf9967000 0x500>; 437 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 439 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; 440 clock-names = "iface", "core"; 441 clock-frequency = <100000>; 442 pinctrl-names = "default", "sleep"; 443 pinctrl-0 = <&i2c5_default>; 444 pinctrl-1 = <&i2c5_sleep>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 gcc: clock-controller@fc400000 { 451 compatible = "qcom,gcc-msm8994"; 452 #clock-cells = <1>; 453 #reset-cells = <1>; 454 #power-domain-cells = <1>; 455 reg = <0xfc400000 0x2000>; 456 }; 457 458 rpm_msg_ram: memory@fc428000 { 459 compatible = "qcom,rpm-msg-ram"; 460 reg = <0xfc428000 0x4000>; 461 }; 462 463 restart@fc4ab000 { 464 compatible = "qcom,pshold"; 465 reg = <0xfc4ab000 0x4>; 466 }; 467 468 spmi_bus: spmi@fc4c0000 { 469 compatible = "qcom,spmi-pmic-arb"; 470 reg = <0xfc4cf000 0x1000>, 471 <0xfc4cb000 0x1000>, 472 <0xfc4ca000 0x1000>; 473 reg-names = "core", "intr", "cnfg"; 474 interrupt-names = "periph_irq"; 475 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 476 qcom,ee = <0>; 477 qcom,channel = <0>; 478 #address-cells = <2>; 479 #size-cells = <0>; 480 interrupt-controller; 481 #interrupt-cells = <4>; 482 }; 483 484 sfpb_mutex_regs: syscon@fd484000 { 485 #address-cells = <1>; 486 #size-cells = <1>; 487 compatible = "syscon"; 488 reg = <0xfd484000 0x400>; 489 }; 490 491 tlmm: pinctrl@fd510000 { 492 compatible = "qcom,msm8994-pinctrl"; 493 reg = <0xfd510000 0x4000>; 494 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 gpio-ranges = <&tlmm 0 0 146>; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 501 blsp1_uart2_default: blsp1-uart2-default { 502 function = "blsp_uart2"; 503 pins = "gpio4", "gpio5"; 504 drive-strength = <16>; 505 bias-disable; 506 }; 507 508 blsp1_uart2_sleep: blsp1-uart2-sleep { 509 function = "gpio"; 510 pins = "gpio4", "gpio5"; 511 drive-strength = <2>; 512 bias-pull-down; 513 }; 514 515 blsp2_uart2_default: blsp2-uart2-default { 516 function = "blsp_uart8"; 517 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 518 drive-strength = <16>; 519 bias-disable; 520 }; 521 522 blsp2_uart2_sleep: blsp2-uart2-sleep { 523 function = "gpio"; 524 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 525 drive-strength = <2>; 526 bias-pull-down; 527 }; 528 529 sdc1_clk_on: clk-on { 530 pins = "sdc1_clk"; 531 bias-disable; 532 drive-strength = <6>; 533 }; 534 535 sdc1_clk_off: clk-off { 536 pins = "sdc1_clk"; 537 bias-disable; 538 drive-strength = <2>; 539 }; 540 541 sdc1_cmd_on: cmd-on { 542 pins = "sdc1_cmd"; 543 bias-pull-up; 544 drive-strength = <6>; 545 }; 546 547 sdc1_cmd_off: cmd-off { 548 pins = "sdc1_cmd"; 549 bias-pull-up; 550 drive-strength = <2>; 551 }; 552 553 sdc1_data_on: data-on { 554 pins = "sdc1_data"; 555 bias-pull-up; 556 drive-strength = <6>; 557 }; 558 559 sdc1_data_off: data-off { 560 pins = "sdc1_data"; 561 bias-pull-up; 562 drive-strength = <2>; 563 }; 564 565 sdc1_rclk_on: rclk-on { 566 pins = "sdc1_rclk"; 567 bias-pull-down; 568 }; 569 570 sdc1_rclk_off: rclk-off { 571 pins = "sdc1_rclk"; 572 bias-pull-down; 573 }; 574 575 i2c1_default: i2c1-default { 576 function = "blsp_i2c1"; 577 pins = "gpio2", "gpio3"; 578 drive-strength = <2>; 579 bias-disable; 580 }; 581 582 i2c1_sleep: i2c1-sleep { 583 function = "gpio"; 584 pins = "gpio2", "gpio3"; 585 drive-strength = <2>; 586 bias-disable; 587 }; 588 589 i2c2_default: i2c2-default { 590 function = "blsp_i2c2"; 591 pins = "gpio6", "gpio7"; 592 drive-strength = <2>; 593 bias-disable; 594 }; 595 596 i2c2_sleep: i2c2-sleep { 597 function = "gpio"; 598 pins = "gpio6", "gpio7"; 599 drive-strength = <2>; 600 bias-disable; 601 }; 602 603 i2c5_default: i2c5-default { 604 /* Don't be fooled! Nobody knows the reason why though... */ 605 function = "blsp_i2c11"; 606 pins = "gpio83", "gpio84"; 607 drive-strength = <2>; 608 bias-disable; 609 }; 610 611 i2c5_sleep: i2c5-sleep { 612 function = "gpio"; 613 pins = "gpio83", "gpio84"; 614 drive-strength = <2>; 615 bias-disable; 616 }; 617 618 i2c6_default: i2c6-default { 619 function = "blsp_i2c6"; 620 pins = "gpio28", "gpio27"; 621 drive-strength = <2>; 622 bias-disable; 623 }; 624 625 i2c6_sleep: i2c6-sleep { 626 function = "gpio"; 627 pins = "gpio28", "gpio27"; 628 drive-strength = <2>; 629 bias-disable; 630 }; 631 632 i2c7_default: i2c7-default { 633 function = "blsp_i2c7"; 634 pins = "gpio43", "gpio44"; 635 drive-strength = <2>; 636 bias-disable; 637 }; 638 639 i2c7_sleep: i2c7-sleep { 640 function = "gpio"; 641 pins = "gpio43", "gpio44"; 642 drive-strength = <2>; 643 bias-disable; 644 }; 645 646 i2c13_default: i2c13-default { 647 /* Not a typo either. */ 648 function = "blsp_i2c5"; 649 pins = "gpio23", "gpio24"; 650 drive-strength = <2>; 651 bias-disable; 652 }; 653 654 i2c13_sleep: i2c13-sleep { 655 function = "gpio"; 656 pins = "gpio23", "gpio24"; 657 drive-strength = <2>; 658 bias-disable; 659 }; 660 661 sdc2_clk_on: sdc2-clk-on { 662 pins = "sdc2_clk"; 663 bias-disable; 664 drive-strength = <16>; 665 }; 666 667 sdc2_clk_off: sdc2-clk-off { 668 pins = "sdc2_clk"; 669 bias-disable; 670 drive-strength = <2>; 671 }; 672 673 sdc2_cmd_on: sdc2-cmd-on { 674 pins = "sdc2_cmd"; 675 bias-pull-up; 676 drive-strength = <10>; 677 }; 678 679 sdc2_cmd_off: sdc2-cmd-off { 680 pins = "sdc2_cmd"; 681 bias-pull-up; 682 drive-strength = <2>; 683 }; 684 685 sdc2_data_on: sdc2-data-on { 686 pins = "sdc2_data"; 687 bias-pull-up; 688 drive-strength = <10>; 689 }; 690 691 sdc2_data_off: sdc2-data-off { 692 pins = "sdc2_data"; 693 bias-pull-up; 694 drive-strength = <2>; 695 }; 696 }; 697 }; 698 699 smd_rpm: smd { 700 compatible = "qcom,smd"; 701 rpm { 702 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 703 qcom,ipc = <&apcs 8 0>; 704 qcom,smd-edge = <15>; 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <6>; 707 708 rpm_requests: rpm-requests { 709 compatible = "qcom,rpm-msm8994"; 710 qcom,smd-channels = "rpm_requests"; 711 712 rpmcc: rpmcc { 713 compatible = "qcom,rpmcc-msm8992"; 714 #clock-cells = <1>; 715 }; 716 }; 717 }; 718 }; 719 720 timer { 721 compatible = "arm,armv8-timer"; 722 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 723 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 724 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 725 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 726 }; 727 728 vreg_vph_pwr: vreg-vph-pwr { 729 compatible = "regulator-fixed"; 730 status = "okay"; 731 regulator-name = "vph-pwr"; 732 733 regulator-min-microvolt = <3600000>; 734 regulator-max-microvolt = <3600000>; 735 736 regulator-always-on; 737 }; 738}; 739 740