1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8994.h> 7 8/ { 9 interrupt-parent = <&intc>; 10 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 chosen { }; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 CPU0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a53"; 23 reg = <0x0 0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 L2_0: l2-cache { 27 compatible = "cache"; 28 cache-level = <2>; 29 }; 30 }; 31 32 CPU1: cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 reg = <0x0 0x1>; 36 next-level-cache = <&L2_0>; 37 enable-method = "psci"; 38 }; 39 40 CPU2: cpu@2 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x2>; 44 next-level-cache = <&L2_0>; 45 enable-method = "psci"; 46 }; 47 48 CPU3: cpu@3 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x0 0x3>; 52 next-level-cache = <&L2_0>; 53 enable-method = "psci"; 54 }; 55 56 CPU4: cpu@100 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57"; 59 reg = <0x0 0x100>; 60 next-level-cache = <&L2_1>; 61 enable-method = "psci"; 62 L2_1: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 }; 66 }; 67 68 CPU5: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a57"; 71 reg = <0x0 0x101>; 72 next-level-cache = <&L2_1>; 73 enable-method = "psci"; 74 }; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&CPU0>; 80 }; 81 82 core1 { 83 cpu = <&CPU1>; 84 }; 85 86 core2 { 87 cpu = <&CPU2>; 88 }; 89 90 core3 { 91 cpu = <&CPU3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&CPU4>; 98 }; 99 100 core1 { 101 cpu = <&CPU5>; 102 }; 103 }; 104 }; 105 }; 106 107 clocks { 108 xo_board: xo_board { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <19200000>; 112 }; 113 114 sleep_clk: sleep_clk { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32768>; 118 }; 119 }; 120 121 firmware { 122 scm { 123 compatible = "qcom,scm-msm8994", "qcom,scm"; 124 }; 125 }; 126 127 memory { 128 device_type = "memory"; 129 /* We expect the bootloader to fill in the reg */ 130 reg = <0 0 0 0>; 131 }; 132 133 pmu { 134 compatible = "arm,cortex-a53-pmu"; 135 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 psci { 139 compatible = "arm,psci-0.2"; 140 method = "hvc"; 141 }; 142 143 reserved-memory { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 smem_region: smem@6a00000 { 149 reg = <0x0 0x6a00000 0x0 0x200000>; 150 no-map; 151 }; 152 }; 153 154 sfpb_mutex: hwmutex { 155 compatible = "qcom,sfpb-mutex"; 156 syscon = <&sfpb_mutex_regs 0x0 0x100>; 157 #hwlock-cells = <1>; 158 }; 159 160 smem { 161 compatible = "qcom,smem"; 162 memory-region = <&smem_region>; 163 qcom,rpm-msg-ram = <&rpm_msg_ram>; 164 hwlocks = <&sfpb_mutex 3>; 165 }; 166 167 soc { 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0 0 0 0xffffffff>; 171 compatible = "simple-bus"; 172 173 intc: interrupt-controller@f9000000 { 174 compatible = "qcom,msm-qgic2"; 175 interrupt-controller; 176 #interrupt-cells = <3>; 177 reg = <0xf9000000 0x1000>, 178 <0xf9002000 0x1000>; 179 }; 180 181 apcs: mailbox@f900d000 { 182 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 183 reg = <0xf900d000 0x2000>; 184 #mbox-cells = <1>; 185 }; 186 187 timer@f9020000 { 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges; 191 compatible = "arm,armv7-timer-mem"; 192 reg = <0xf9020000 0x1000>; 193 194 frame@f9021000 { 195 frame-number = <0>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 198 reg = <0xf9021000 0x1000>, 199 <0xf9022000 0x1000>; 200 }; 201 202 frame@f9023000 { 203 frame-number = <1>; 204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 205 reg = <0xf9023000 0x1000>; 206 status = "disabled"; 207 }; 208 209 frame@f9024000 { 210 frame-number = <2>; 211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 212 reg = <0xf9024000 0x1000>; 213 status = "disabled"; 214 }; 215 216 frame@f9025000 { 217 frame-number = <3>; 218 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 219 reg = <0xf9025000 0x1000>; 220 status = "disabled"; 221 }; 222 223 frame@f9026000 { 224 frame-number = <4>; 225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 226 reg = <0xf9026000 0x1000>; 227 status = "disabled"; 228 }; 229 230 frame@f9027000 { 231 frame-number = <5>; 232 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 233 reg = <0xf9027000 0x1000>; 234 status = "disabled"; 235 }; 236 237 frame@f9028000 { 238 frame-number = <6>; 239 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 240 reg = <0xf9028000 0x1000>; 241 status = "disabled"; 242 }; 243 }; 244 245 sdhc_1: sdhci@f9824900 { 246 compatible = "qcom,sdhci-msm-v4"; 247 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 248 reg-names = "hc_mem", "core_mem"; 249 250 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "hc_irq", "pwr_irq"; 253 254 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 255 <&gcc GCC_SDCC1_AHB_CLK>, 256 <&xo_board>; 257 clock-names = "core", "iface", "xo"; 258 259 pinctrl-names = "default", "sleep"; 260 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on 261 &sdc1_rclk_on>; 262 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off 263 &sdc1_rclk_off>; 264 265 regulator-always-on; 266 bus-width = <8>; 267 non-removable; 268 269 status = "disabled"; 270 }; 271 272 blsp1_uart2: serial@f991e000 { 273 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 274 reg = <0xf991e000 0x1000>; 275 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>; 276 clock-names = "core", "iface"; 277 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 278 <&gcc GCC_BLSP1_AHB_CLK>; 279 pinctrl-names = "default", "sleep"; 280 pinctrl-0 = <&blsp1_uart2_default>; 281 pinctrl-1 = <&blsp1_uart2_sleep>; 282 status = "disabled"; 283 }; 284 285 blsp_i2c2: i2c@f9924000 { 286 compatible = "qcom,i2c-qup-v2.2.1"; 287 reg = <0xf9924000 0x500>; 288 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 290 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 291 clock-names = "iface", "core"; 292 clock-frequency = <400000>; 293 pinctrl-names = "default", "sleep"; 294 pinctrl-0 = <&i2c2_default>; 295 pinctrl-1 = <&i2c2_sleep>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 /* Somebody was very creative with their numbering scheme downstream... */ 302 303 blsp_i2c13: i2c@f9927000 { 304 compatible = "qcom,i2c-qup-v2.2.1"; 305 reg = <0xf9927000 0x500>; 306 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 308 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 309 clock-names = "iface", "core"; 310 clock-frequency = <400000>; 311 pinctrl-names = "default", "sleep"; 312 pinctrl-0 = <&i2c13_default>; 313 pinctrl-1 = <&i2c13_sleep>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 blsp_i2c6: i2c@f9928000 { 320 compatible = "qcom,i2c-qup-v2.2.1"; 321 reg = <0xf9928000 0x500>; 322 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 324 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 325 clock-names = "iface", "core"; 326 clock-frequency = <400000>; 327 pinctrl-names = "default", "sleep"; 328 pinctrl-0 = <&i2c6_default>; 329 pinctrl-1 = <&i2c6_sleep>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 status = "disabled"; 333 }; 334 335 blsp2_uart2: serial@f995e000 { 336 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 337 reg = <0xf995e000 0x1000>; 338 interrupt = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 339 clock-names = "core", "iface"; 340 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 341 <&gcc GCC_BLSP2_AHB_CLK>; 342 pinctrl-names = "default", "sleep"; 343 pinctrl-0 = <&blsp2_uart2_default>; 344 pinctrl-1 = <&blsp2_uart2_sleep>; 345 status = "disabled"; 346 }; 347 348 blsp_i2c7: i2c@f9963000 { 349 compatible = "qcom,i2c-qup-v2.2.1"; 350 reg = <0xf9963000 0x500>; 351 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 353 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 354 clock-names = "iface", "core"; 355 clock-frequency = <400000>; 356 pinctrl-names = "default", "sleep"; 357 pinctrl-0 = <&i2c7_default>; 358 pinctrl-1 = <&i2c7_sleep>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 status = "disabled"; 362 }; 363 364 blsp_i2c5: i2c@f9967000 { 365 compatible = "qcom,i2c-qup-v2.2.1"; 366 reg = <0xf9967000 0x500>; 367 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 369 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; 370 clock-names = "iface", "core"; 371 clock-frequency = <100000>; 372 pinctrl-names = "default", "sleep"; 373 pinctrl-0 = <&i2c5_default>; 374 pinctrl-1 = <&i2c5_sleep>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 gcc: clock-controller@fc400000 { 381 compatible = "qcom,gcc-msm8994"; 382 #clock-cells = <1>; 383 #reset-cells = <1>; 384 #power-domain-cells = <1>; 385 reg = <0xfc400000 0x2000>; 386 }; 387 388 rpm_msg_ram: memory@fc428000 { 389 compatible = "qcom,rpm-msg-ram"; 390 reg = <0xfc428000 0x4000>; 391 }; 392 393 restart@fc4ab000 { 394 compatible = "qcom,pshold"; 395 reg = <0xfc4ab000 0x4>; 396 }; 397 398 spmi_bus: spmi@fc4c0000 { 399 compatible = "qcom,spmi-pmic-arb"; 400 reg = <0xfc4cf000 0x1000>, 401 <0xfc4cb000 0x1000>, 402 <0xfc4ca000 0x1000>; 403 reg-names = "core", "intr", "cnfg"; 404 interrupt-names = "periph_irq"; 405 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 406 qcom,ee = <0>; 407 qcom,channel = <0>; 408 #address-cells = <2>; 409 #size-cells = <0>; 410 interrupt-controller; 411 #interrupt-cells = <4>; 412 }; 413 414 sfpb_mutex_regs: syscon@fd484000 { 415 #address-cells = <1>; 416 #size-cells = <1>; 417 compatible = "syscon"; 418 reg = <0xfd484000 0x400>; 419 }; 420 421 tlmm: pinctrl@fd510000 { 422 compatible = "qcom,msm8994-pinctrl"; 423 reg = <0xfd510000 0x4000>; 424 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 425 gpio-controller; 426 gpio-ranges = <&tlmm 0 0 146>; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 431 blsp1_uart2_default: blsp1-uart2-default { 432 function = "blsp_uart2"; 433 pins = "gpio4", "gpio5"; 434 drive-strength = <16>; 435 bias-disable; 436 }; 437 438 blsp1_uart2_sleep: blsp1-uart2-sleep { 439 function = "gpio"; 440 pins = "gpio4", "gpio5"; 441 drive-strength = <2>; 442 bias-pull-down; 443 }; 444 445 blsp2_uart2_default: blsp2-uart2-default { 446 function = "blsp_uart8"; 447 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 448 drive-strength = <16>; 449 bias-disable; 450 }; 451 452 blsp2_uart2_sleep: blsp2-uart2-sleep { 453 function = "gpio"; 454 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 455 drive-strength = <2>; 456 bias-pull-down; 457 }; 458 459 sdc1_clk_on: clk-on { 460 pins = "sdc1_clk"; 461 bias-disable; 462 drive-strength = <6>; 463 }; 464 465 sdc1_clk_off: clk-off { 466 pins = "sdc1_clk"; 467 bias-disable; 468 drive-strength = <2>; 469 }; 470 471 sdc1_cmd_on: cmd-on { 472 pins = "sdc1_cmd"; 473 bias-pull-up; 474 drive-strength = <6>; 475 }; 476 477 sdc1_cmd_off: cmd-off { 478 pins = "sdc1_cmd"; 479 bias-pull-up; 480 drive-strength = <2>; 481 }; 482 483 sdc1_data_on: data-on { 484 pins = "sdc1_data"; 485 bias-pull-up; 486 drive-strength = <6>; 487 }; 488 489 sdc1_data_off: data-off { 490 pins = "sdc1_data"; 491 bias-pull-up; 492 drive-strength = <2>; 493 }; 494 495 sdc1_rclk_on: rclk-on { 496 pins = "sdc1_rclk"; 497 bias-pull-down; 498 }; 499 500 sdc1_rclk_off: rclk-off { 501 pins = "sdc1_rclk"; 502 bias-pull-down; 503 }; 504 505 i2c2_default: i2c2-default { 506 function = "blsp_i2c2"; 507 pins = "gpio6", "gpio7"; 508 drive-strength = <2>; 509 bias-disable; 510 }; 511 512 i2c2_sleep: i2c2-sleep { 513 function = "gpio"; 514 pins = "gpio6", "gpio7"; 515 drive-strength = <2>; 516 bias-disable; 517 }; 518 519 i2c5_default: i2c5-default { 520 /* Don't be fooled! Nobody knows the reason why though... */ 521 function = "blsp_i2c11"; 522 pins = "gpio83", "gpio84"; 523 drive-strength = <2>; 524 bias-disable; 525 }; 526 527 i2c5_sleep: i2c5-sleep { 528 function = "gpio"; 529 pins = "gpio83", "gpio84"; 530 drive-strength = <2>; 531 bias-disable; 532 }; 533 534 i2c6_default: i2c6-default { 535 function = "blsp_i2c6"; 536 pins = "gpio28", "gpio27"; 537 drive-strength = <2>; 538 bias-disable; 539 }; 540 541 i2c6_sleep: i2c6-sleep { 542 function = "gpio"; 543 pins = "gpio28", "gpio27"; 544 drive-strength = <2>; 545 bias-disable; 546 }; 547 548 i2c7_default: i2c7-default { 549 function = "blsp_i2c7"; 550 pins = "gpio43", "gpio44"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 i2c7_sleep: i2c7-sleep { 556 function = "gpio"; 557 pins = "gpio43", "gpio44"; 558 drive-strength = <2>; 559 bias-disable; 560 }; 561 562 i2c13_default: i2c13-default { 563 /* Not a typo either. */ 564 function = "blsp_i2c5"; 565 pins = "gpio23", "gpio24"; 566 drive-strength = <2>; 567 bias-disable; 568 }; 569 570 i2c13_sleep: i2c13-sleep { 571 function = "gpio"; 572 pins = "gpio23", "gpio24"; 573 drive-strength = <2>; 574 bias-disable; 575 }; 576 }; 577 }; 578 579 smd_rpm: smd { 580 compatible = "qcom,smd"; 581 rpm { 582 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 583 qcom,ipc = <&apcs 8 0>; 584 qcom,smd-edge = <15>; 585 qcom,local-pid = <0>; 586 qcom,remote-pid = <6>; 587 588 rpm_requests: rpm-requests { 589 compatible = "qcom,rpm-msm8994"; 590 qcom,smd-channels = "rpm_requests"; 591 592 rpmcc: rpmcc { 593 compatible = "qcom,rpmcc-msm8992"; 594 #clock-cells = <1>; 595 }; 596 }; 597 }; 598 }; 599 600 timer { 601 compatible = "arm,armv8-timer"; 602 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 603 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 604 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 605 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 606 }; 607 608 vreg_vph_pwr: vreg-vph-pwr { 609 compatible = "regulator-fixed"; 610 status = "okay"; 611 regulator-name = "vph-pwr"; 612 613 regulator-min-microvolt = <3600000>; 614 regulator-max-microvolt = <3600000>; 615 616 regulator-always-on; 617 }; 618}; 619 620