1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-msm8976.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 CPU0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 cpu-idle-states = <&little_cpu_sleep_0>; 40 capacity-dmips-mhz = <573>; 41 next-level-cache = <&l2_0>; 42 #cooling-cells = <2>; 43 }; 44 45 CPU1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x1>; 49 enable-method = "psci"; 50 cpu-idle-states = <&little_cpu_sleep_0>; 51 capacity-dmips-mhz = <573>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 CPU2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x2>; 60 enable-method = "psci"; 61 cpu-idle-states = <&little_cpu_sleep_0>; 62 capacity-dmips-mhz = <573>; 63 next-level-cache = <&l2_0>; 64 #cooling-cells = <2>; 65 }; 66 67 CPU3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x3>; 71 enable-method = "psci"; 72 cpu-idle-states = <&little_cpu_sleep_0>; 73 capacity-dmips-mhz = <573>; 74 next-level-cache = <&l2_0>; 75 #cooling-cells = <2>; 76 }; 77 78 CPU4: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 reg = <0x100>; 82 enable-method = "psci"; 83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 84 capacity-dmips-mhz = <1024>; 85 next-level-cache = <&l2_1>; 86 #cooling-cells = <2>; 87 }; 88 89 CPU5: cpu@101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x101>; 93 enable-method = "psci"; 94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 95 capacity-dmips-mhz = <1024>; 96 next-level-cache = <&l2_1>; 97 #cooling-cells = <2>; 98 }; 99 100 CPU6: cpu@102 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a72"; 103 reg = <0x102>; 104 enable-method = "psci"; 105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&l2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a72"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 117 capacity-dmips-mhz = <1024>; 118 next-level-cache = <&l2_1>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu-map { 123 cluster0 { 124 core0 { 125 cpu = <&CPU0>; 126 }; 127 128 core1 { 129 cpu = <&CPU1>; 130 }; 131 132 core2 { 133 cpu = <&CPU2>; 134 }; 135 136 core3 { 137 cpu = <&CPU3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&CPU4>; 144 }; 145 146 core1 { 147 cpu = <&CPU5>; 148 }; 149 150 core2 { 151 cpu = <&CPU6>; 152 }; 153 154 core3 { 155 cpu = <&CPU7>; 156 }; 157 }; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 little_cpu_sleep_0: cpu-sleep-0-0 { 164 compatible = "arm,idle-state"; 165 idle-state-name = "little-power-collapse"; 166 arm,psci-suspend-param = <0x40000003>; 167 entry-latency-us = <181>; 168 exit-latency-us = <149>; 169 min-residency-us = <703>; 170 local-timer-stop; 171 }; 172 173 big_cpu_sleep_0: cpu-sleep-1-0 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "big-retention"; 176 arm,psci-suspend-param = <0x00000002>; 177 entry-latency-us = <142>; 178 exit-latency-us = <99>; 179 min-residency-us = <242>; 180 }; 181 182 big_cpu_sleep_1: cpu-sleep-1-1 { 183 compatible = "arm,idle-state"; 184 idle-state-name = "big-power-collapse"; 185 arm,psci-suspend-param = <0x40000003>; 186 entry-latency-us = <158>; 187 exit-latency-us = <144>; 188 min-residency-us = <863>; 189 local-timer-stop; 190 }; 191 }; 192 193 l2_0: l2-cache0 { 194 compatible = "cache"; 195 cache-level = <2>; 196 }; 197 198 l2_1: l2-cache1 { 199 compatible = "cache"; 200 cache-level = <2>; 201 }; 202 }; 203 204 firmware { 205 scm: scm { 206 compatible = "qcom,scm-msm8976", "qcom,scm"; 207 clocks = <&gcc GCC_CRYPTO_CLK>, 208 <&gcc GCC_CRYPTO_AXI_CLK>, 209 <&gcc GCC_CRYPTO_AHB_CLK>; 210 clock-names = "core", "bus", "iface"; 211 #reset-cells = <1>; 212 213 qcom,dload-mode = <&tcsr 0x6100>; 214 }; 215 }; 216 217 memory@80000000 { 218 device_type = "memory"; 219 /* We expect the bootloader to fill in the size */ 220 reg = <0x0 0x80000000 0x0 0x0>; 221 }; 222 223 pmu: pmu { 224 compatible = "arm,armv8-pmuv3"; 225 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 226 }; 227 228 psci { 229 compatible = "arm,psci-1.0"; 230 method = "smc"; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 ext-region@85b00000 { 239 reg = <0x0 0x85b00000 0x0 0x500000>; 240 no-map; 241 }; 242 243 smem@86300000 { 244 compatible = "qcom,smem"; 245 reg = <0x0 0x86300000 0x0 0x100000>; 246 no-map; 247 248 hwlocks = <&tcsr_mutex 3>; 249 qcom,rpm-msg-ram = <&rpm_msg_ram>; 250 }; 251 252 reserved@86400000 { 253 reg = <0x0 0x86400000 0x0 0x800000>; 254 no-map; 255 }; 256 257 mpss_mem: mpss@86c00000 { 258 reg = <0x0 0x86c00000 0x0 0x5600000>; 259 no-map; 260 }; 261 262 lpass_mem: lpass@8c200000 { 263 reg = <0x0 0x8c200000 0x0 0x1800000>; 264 no-map; 265 }; 266 267 venus_mem: memory@8da00000 { 268 reg = <0x0 0x8da00000 0x0 0x2600000>; 269 no-map; 270 }; 271 272 tz-apps@8dd00000 { 273 reg = <0x0 0x8dd00000 0x0 0x1400000>; 274 no-map; 275 }; 276 }; 277 278 smp2p-hexagon { 279 compatible = "qcom,smp2p"; 280 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 281 qcom,ipc = <&apcs 8 10>; 282 283 qcom,local-pid = <0>; 284 qcom,remote-pid = <2>; 285 qcom,smem = <443>, <429>; 286 287 adsp_smp2p_out: master-kernel { 288 qcom,entry-name = "master-kernel"; 289 290 #qcom,smem-state-cells = <1>; 291 }; 292 293 adsp_smp2p_in: slave-kernel { 294 qcom,entry-name = "slave-kernel"; 295 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 }; 299 }; 300 301 smp2p-modem { 302 compatible = "qcom,smp2p"; 303 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 304 qcom,ipc = <&apcs 8 13>; 305 306 qcom,local-pid = <0>; 307 qcom,remote-pid = <1>; 308 qcom,smem = <435>, <428>; 309 310 modem_smp2p_out: master-kernel { 311 qcom,entry-name = "master-kernel"; 312 313 #qcom,smem-state-cells = <1>; 314 }; 315 316 modem_smp2p_in: slave-kernel { 317 qcom,entry-name = "slave-kernel"; 318 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 }; 323 324 smp2p-wcnss { 325 compatible = "qcom,smp2p"; 326 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 327 qcom,ipc = <&apcs 8 17>; 328 329 qcom,local-pid = <0>; 330 qcom,remote-pid = <4>; 331 qcom,smem = <451>, <431>; 332 333 wcnss_smp2p_out: master-kernel { 334 qcom,entry-name = "master-kernel"; 335 336 #qcom,smem-state-cells = <1>; 337 }; 338 339 wcnss_smp2p_in: slave-kernel { 340 qcom,entry-name = "slave-kernel"; 341 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 }; 345 }; 346 347 smd { 348 compatible = "qcom,smd"; 349 350 rpm { 351 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 352 qcom,ipc = <&apcs 8 0>; 353 qcom,smd-edge = <15>; 354 355 rpm_requests: rpm-requests { 356 compatible = "qcom,rpm-msm8976"; 357 qcom,smd-channels = "rpm_requests"; 358 359 rpmcc: clock-controller { 360 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 361 clocks = <&xo_board>; 362 clock-names = "xo"; 363 #clock-cells = <1>; 364 }; 365 366 rpmpd: power-controller { 367 compatible = "qcom,msm8976-rpmpd"; 368 #power-domain-cells = <1>; 369 operating-points-v2 = <&rpmpd_opp_table>; 370 371 rpmpd_opp_table: opp-table { 372 compatible = "operating-points-v2"; 373 374 rpmpd_opp_ret: opp1 { 375 opp-level = <RPM_SMD_LEVEL_RETENTION>; 376 }; 377 378 rpmpd_opp_ret_plus: opp2 { 379 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 380 }; 381 382 rpmpd_opp_min_svs: opp3 { 383 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 384 }; 385 386 rpmpd_opp_low_svs: opp4 { 387 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 388 }; 389 390 rpmpd_opp_svs: opp5 { 391 opp-level = <RPM_SMD_LEVEL_SVS>; 392 }; 393 394 rpmpd_opp_svs_plus: opp6 { 395 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 396 }; 397 398 rpmpd_opp_nom: opp7 { 399 opp-level = <RPM_SMD_LEVEL_NOM>; 400 }; 401 402 rpmpd_opp_nom_plus: opp8 { 403 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 404 }; 405 406 rpmpd_opp_turbo: opp9 { 407 opp-level = <RPM_SMD_LEVEL_TURBO>; 408 }; 409 410 rpmpd_opp_turbo_no_cpr: opp10 { 411 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 412 }; 413 414 rpmpd_opp_turbo_high: opp111 { 415 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 416 }; 417 }; 418 }; 419 }; 420 }; 421 }; 422 423 smsm { 424 compatible = "qcom,smsm"; 425 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 qcom,ipc-1 = <&apcs 8 12>; 430 qcom,ipc-2 = <&apcs 8 9>; 431 qcom,ipc-3 = <&apcs 8 18>; 432 433 apps_smsm: apps@0 { 434 reg = <0>; 435 #qcom,smem-state-cells = <1>; 436 }; 437 438 hexagon_smsm: hexagon@1 { 439 reg = <1>; 440 interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; 441 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 446 wcnss_smsm: wcnss@6 { 447 reg = <6>; 448 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 449 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 }; 453 }; 454 455 soc: soc@0 { 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0 0 0 0xffffffff>; 459 compatible = "simple-bus"; 460 461 rng@22000 { 462 compatible = "qcom,prng"; 463 reg = <0x00022000 0x140>; 464 clocks = <&gcc GCC_PRNG_AHB_CLK>; 465 clock-names = "core"; 466 }; 467 468 rpm_msg_ram: sram@60000 { 469 compatible = "qcom,rpm-msg-ram"; 470 reg = <0x00060000 0x8000>; 471 }; 472 473 usb_hs_phy: phy@6c000 { 474 compatible = "qcom,usb-hs-28nm-femtophy"; 475 reg = <0x0006c000 0x200>; 476 #phy-cells = <0>; 477 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 478 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 479 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 480 clock-names = "ref", "ahb", "sleep"; 481 resets = <&gcc RST_QUSB2_PHY_BCR>, 482 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 483 reset-names = "phy", "por"; 484 status = "disabled"; 485 }; 486 487 qfprom: qfprom@a4000 { 488 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 489 reg = <0x000a4000 0x1000>; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 493 tsens_base1: base1@218 { 494 reg = <0x218 1>; 495 bits = <0 8>; 496 }; 497 498 tsens_s0_p1: s0-p1@219 { 499 reg = <0x219 0x1>; 500 bits = <0 6>; 501 }; 502 503 tsens_s0_p2: s0-p2@219 { 504 reg = <0x219 0x2>; 505 bits = <6 6>; 506 }; 507 508 tsens_s1_p1: s1-p1@21a { 509 reg = <0x21a 0x2>; 510 bits = <4 6>; 511 }; 512 513 tsens_s1_p2: s1-p2@21b { 514 reg = <0x21b 0x1>; 515 bits = <2 6>; 516 }; 517 518 tsens_s2_p1: s2-p1@21c { 519 reg = <0x21c 0x1>; 520 bits = <0 6>; 521 }; 522 523 tsens_s2_p2: s2-p2@21c { 524 reg = <0x21c 0x2>; 525 bits = <6 6>; 526 }; 527 528 tsens_s3_p1: s3-p1@21d { 529 reg = <0x21d 0x2>; 530 bits = <4 6>; 531 }; 532 533 tsens_s3_p2: s3-p2@21e { 534 reg = <0x21e 0x1>; 535 bits = <2 6>; 536 }; 537 538 tsens_base2: base2@220 { 539 reg = <0x220 1>; 540 bits = <0 8>; 541 }; 542 543 tsens_s4_p1: s4-p1@221 { 544 reg = <0x221 0x1>; 545 bits = <0 6>; 546 }; 547 548 tsens_s4_p2: s4-p2@221 { 549 reg = <0x221 0x2>; 550 bits = <6 6>; 551 }; 552 553 tsens_s5_p1: s5-p1@222 { 554 reg = <0x222 0x2>; 555 bits = <4 6>; 556 }; 557 558 tsens_s5_p2: s5-p2@223 { 559 reg = <0x224 0x1>; 560 bits = <2 6>; 561 }; 562 563 tsens_s6_p1: s6-p1@224 { 564 reg = <0x224 0x1>; 565 bits = <0 6>; 566 }; 567 568 tsens_s6_p2: s6-p2@224 { 569 reg = <0x224 0x2>; 570 bits = <6 6>; 571 }; 572 573 tsens_s7_p1: s7-p1@225 { 574 reg = <0x225 0x2>; 575 bits = <4 6>; 576 }; 577 578 tsens_s7_p2: s7-p2@226 { 579 reg = <0x226 0x2>; 580 bits = <2 6>; 581 }; 582 583 tsens_mode: mode@228 { 584 reg = <0x228 1>; 585 bits = <0 3>; 586 }; 587 588 tsens_s8_p1: s8-p1@228 { 589 reg = <0x228 0x2>; 590 bits = <3 6>; 591 }; 592 593 tsens_s8_p2: s8-p2@229 { 594 reg = <0x229 0x1>; 595 bits = <1 6>; 596 }; 597 598 tsens_s9_p1: s9-p1@229 { 599 reg = <0x229 0x2>; 600 bits = <7 6>; 601 }; 602 603 tsens_s9_p2: s9-p2@22a { 604 reg = <0x22a 0x2>; 605 bits = <5 6>; 606 }; 607 608 tsens_s10_p1: s10-p1@22b { 609 reg = <0x22b 0x2>; 610 bits = <3 6>; 611 }; 612 613 tsens_s10_p2: s10-p2@22c { 614 reg = <0x22c 0x1>; 615 bits = <1 6>; 616 }; 617 }; 618 619 tsens: thermal-sensor@4a9000 { 620 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 621 reg = <0x004a9000 0x1000>, /* TM */ 622 <0x004a8000 0x1000>; /* SROT */ 623 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 624 interrupt-names = "uplow"; 625 nvmem-cells = <&tsens_mode>, 626 <&tsens_base1>, <&tsens_base2>, 627 <&tsens_s0_p1>, <&tsens_s0_p2>, 628 <&tsens_s1_p1>, <&tsens_s1_p2>, 629 <&tsens_s2_p1>, <&tsens_s2_p2>, 630 <&tsens_s3_p1>, <&tsens_s3_p2>, 631 <&tsens_s4_p1>, <&tsens_s4_p2>, 632 <&tsens_s5_p1>, <&tsens_s5_p2>, 633 <&tsens_s6_p1>, <&tsens_s6_p2>, 634 <&tsens_s7_p1>, <&tsens_s7_p2>, 635 <&tsens_s8_p1>, <&tsens_s8_p2>, 636 <&tsens_s9_p1>, <&tsens_s9_p2>, 637 <&tsens_s10_p1>, <&tsens_s10_p2>; 638 nvmem-cell-names = "mode", 639 "base1", "base2", 640 "s0_p1", "s0_p2", 641 "s1_p1", "s1_p2", 642 "s2_p1", "s2_p2", 643 "s3_p1", "s3_p2", 644 "s4_p1", "s4_p2", 645 "s5_p1", "s5_p2", 646 "s6_p1", "s6_p2", 647 "s7_p1", "s7_p2", 648 "s8_p1", "s8_p2", 649 "s9_p1", "s9_p2", 650 "s10_p1", "s10_p2"; 651 #qcom,sensors = <11>; 652 #thermal-sensor-cells = <1>; 653 }; 654 655 tlmm: pinctrl@1000000 { 656 compatible = "qcom,msm8976-pinctrl"; 657 reg = <0x01000000 0x300000>; 658 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 659 #gpio-cells = <2>; 660 gpio-controller; 661 gpio-ranges = <&tlmm 0 0 145>; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 665 spi1_default: spi0-default-state { 666 spi-pins { 667 pins = "gpio0", "gpio1", "gpio3"; 668 function = "blsp_spi1"; 669 drive-strength = <12>; 670 bias-disable; 671 }; 672 673 cs-pins { 674 pins = "gpio2"; 675 function = "blsp_spi1"; 676 drive-strength = <2>; 677 bias-disable; 678 }; 679 }; 680 681 spi1_sleep: spi0-sleep-state { 682 spi-pins { 683 pins = "gpio0", "gpio1", "gpio3"; 684 function = "gpio"; 685 drive-strength = <2>; 686 bias-pull-down; 687 }; 688 689 cs-pins { 690 pins = "gpio2"; 691 function = "gpio"; 692 drive-strength = <2>; 693 bias-disable; 694 }; 695 }; 696 697 blsp1_i2c2_default: blsp1-i2c2-default-state { 698 pins = "gpio6", "gpio7"; 699 function = "blsp_i2c2"; 700 drive-strength = <2>; 701 bias-disable; 702 }; 703 704 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 705 pins = "gpio6", "gpio7"; 706 function = "gpio"; 707 drive-strength = <2>; 708 bias-disable; 709 }; 710 711 blsp1_i2c4_default: blsp1-i2c4-default-state { 712 pins = "gpio14", "gpio15"; 713 function = "blsp_i2c4"; 714 drive-strength = <2>; 715 bias-disable; 716 }; 717 718 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 719 pins = "gpio14", "gpio15"; 720 function = "gpio"; 721 drive-strength = <2>; 722 bias-disable; 723 }; 724 725 blsp2_uart2_active: blsp2-uart2-active-state { 726 pins = "gpio20", "gpio21"; 727 function = "blsp_uart6"; 728 drive-strength = <4>; 729 bias-disable; 730 }; 731 732 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 733 pins = "gpio20", "gpio21"; 734 function = "gpio"; 735 drive-strength = <2>; 736 bias-disable; 737 }; 738 739 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 740 blsp2_i2c2_default: blsp2-i2c2-default-state { 741 pins = "gpio22", "gpio23"; 742 function = "blsp_i2c6"; 743 drive-strength = <2>; 744 bias-disable; 745 }; 746 747 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 748 pins = "gpio22", "gpio23"; 749 function = "gpio"; 750 drive-strength = <2>; 751 bias-disable; 752 }; 753 754 blsp2_i2c4_default: blsp2-i2c4-default-state { 755 pins = "gpio18", "gpio19"; 756 function = "blsp_i2c8"; 757 drive-strength = <2>; 758 bias-disable; 759 }; 760 761 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 762 pins = "gpio18", "gpio19"; 763 function = "gpio"; 764 drive-strength = <2>; 765 bias-disable; 766 }; 767 }; 768 769 gcc: clock-controller@1800000 { 770 compatible = "qcom,gcc-msm8976"; 771 reg = <0x01800000 0x80000>; 772 #clock-cells = <1>; 773 #reset-cells = <1>; 774 #power-domain-cells = <1>; 775 776 assigned-clocks = <&gcc GPLL3>; 777 assigned-clock-rates = <1100000000>; 778 779 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 780 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 781 <0>, 782 <0>, 783 <0>, 784 <0>; 785 clock-names = "xo", 786 "xo_a", 787 "dsi0pll", 788 "dsi0pllbyte", 789 "dsi1pll", 790 "dsi1pllbyte"; 791 }; 792 793 tcsr_mutex: hwlock@1905000 { 794 compatible = "qcom,tcsr-mutex"; 795 reg = <0x01905000 0x20000>; 796 #hwlock-cells = <1>; 797 }; 798 799 tcsr: syscon@1937000 { 800 compatible = "qcom,msm8976-tcsr", "syscon"; 801 reg = <0x01937000 0x30000>; 802 }; 803 804 spmi_bus: spmi@200f000 { 805 compatible = "qcom,spmi-pmic-arb"; 806 reg = <0x0200f000 0x1000>, 807 <0x02400000 0x800000>, 808 <0x02c00000 0x800000>, 809 <0x03800000 0x200000>, 810 <0x0200a000 0x2100>; 811 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 812 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 813 interrupt-names = "periph_irq"; 814 qcom,channel = <0>; 815 qcom,ee = <0>; 816 817 #address-cells = <2>; 818 #size-cells = <0>; 819 interrupt-controller; 820 #interrupt-cells = <4>; 821 }; 822 823 sdhc_1: mmc@7824000 { 824 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 825 reg = <0x07824900 0x500>, <0x07824000 0x800>; 826 reg-names = "hc", "core"; 827 828 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "hc_irq", "pwr_irq"; 831 832 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 833 <&gcc GCC_SDCC1_APPS_CLK>, 834 <&rpmcc RPM_SMD_XO_CLK_SRC>; 835 clock-names = "iface", "core", "xo"; 836 status = "disabled"; 837 }; 838 839 sdhc_2: mmc@7864000 { 840 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 841 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 842 reg-names = "hc", "core"; 843 844 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "hc_irq", "pwr_irq"; 847 848 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 849 <&gcc GCC_SDCC2_APPS_CLK>, 850 <&rpmcc RPM_SMD_XO_CLK_SRC>; 851 clock-names = "iface", "core", "xo"; 852 status = "disabled"; 853 }; 854 855 blsp1_dma: dma-controller@7884000 { 856 compatible = "qcom,bam-v1.7.0"; 857 reg = <0x07884000 0x1f000>; 858 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 860 clock-names = "bam_clk"; 861 #dma-cells = <1>; 862 qcom,ee = <0>; 863 }; 864 865 blsp1_uart1: serial@78af000 { 866 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 867 reg = <0x078af000 0x200>; 868 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 870 clock-names = "core", "iface"; 871 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 872 dma-names = "tx", "rx"; 873 status = "disabled"; 874 }; 875 876 blsp1_uart2: serial@78b0000 { 877 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 878 reg = <0x078b0000 0x200>; 879 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 881 clock-names = "core", "iface"; 882 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 883 dma-names = "tx", "rx"; 884 status = "disabled"; 885 }; 886 887 blsp1_spi1: spi@78b5000 { 888 compatible = "qcom,spi-qup-v2.2.1"; 889 reg = <0x078b5000 0x500>; 890 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 892 clock-names = "core", "iface"; 893 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 894 dma-names = "tx", "rx"; 895 pinctrl-names = "default", "sleep"; 896 pinctrl-0 = <&spi1_default>; 897 pinctrl-1 = <&spi1_sleep>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 status = "disabled"; 901 }; 902 903 blsp1_i2c2: i2c@78b6000 { 904 compatible = "qcom,i2c-qup-v2.2.1"; 905 reg = <0x078b6000 0x500>; 906 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 908 clock-names = "core", "iface"; 909 clock-frequency = <400000>; 910 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 911 dma-names = "tx", "rx"; 912 pinctrl-names = "default", "sleep"; 913 pinctrl-0 = <&blsp1_i2c2_default>; 914 pinctrl-1 = <&blsp1_i2c2_default>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 blsp1_i2c4: i2c@78b8000 { 921 compatible = "qcom,i2c-qup-v2.2.1"; 922 reg = <0x078b8000 0x500>; 923 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 925 clock-names = "core", "iface"; 926 clock-frequency = <400000>; 927 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 928 dma-names = "tx", "rx"; 929 pinctrl-names = "default", "sleep"; 930 pinctrl-0 = <&blsp1_i2c4_default>; 931 pinctrl-1 = <&blsp1_i2c4_sleep>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 otg: usb@78db000 { 938 compatible = "qcom,ci-hdrc"; 939 reg = <0x078db000 0x200>, 940 <0x078db200 0x200>; 941 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 944 clock-names = "iface", "core"; 945 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 946 assigned-clock-rates = <80000000>; 947 resets = <&gcc RST_USB_HS_BCR>; 948 reset-names = "core"; 949 ahb-burst-config = <0>; 950 dr_mode = "peripheral"; 951 phy_type = "ulpi"; 952 phy-names = "usb-phy"; 953 phys = <&usb_hs_phy>; 954 status = "disabled"; 955 #reset-cells = <1>; 956 }; 957 958 sdhc_3: mmc@7a24000 { 959 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 960 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 961 reg-names = "hc", "core"; 962 963 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-names = "hc_irq", "pwr_irq"; 966 967 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 968 <&gcc GCC_SDCC3_APPS_CLK>, 969 <&rpmcc RPM_SMD_XO_CLK_SRC>; 970 clock-names = "iface", "core", "xo"; 971 972 status = "disabled"; 973 }; 974 975 blsp2_dma: dma-controller@7ac4000 { 976 compatible = "qcom,bam-v1.7.0"; 977 reg = <0x07ac4000 0x1f000>; 978 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 980 clock-names = "bam_clk"; 981 #dma-cells = <1>; 982 qcom,ee = <0>; 983 }; 984 985 blsp2_uart2: serial@7af0000 { 986 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 987 reg = <0x07af0000 0x200>; 988 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 990 clock-names = "core", "iface"; 991 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 992 dma-names = "tx", "rx"; 993 status = "disabled"; 994 }; 995 996 blsp2_i2c2: i2c@7af6000 { 997 compatible = "qcom,i2c-qup-v2.2.1"; 998 reg = <0x07af6000 0x600>; 999 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1001 clock-names = "core", "iface"; 1002 clock-frequency = <400000>; 1003 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1004 dma-names = "tx", "rx"; 1005 pinctrl-names = "default", "sleep"; 1006 pinctrl-0 = <&blsp2_i2c2_default>; 1007 pinctrl-1 = <&blsp2_i2c2_sleep>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 blsp2_i2c4: i2c@7af8000 { 1014 compatible = "qcom,i2c-qup-v2.2.1"; 1015 reg = <0x07af8000 0x600>; 1016 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1018 clock-names = "core", "iface"; 1019 clock-frequency = <400000>; 1020 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1021 dma-names = "tx", "rx"; 1022 pinctrl-names = "default", "sleep"; 1023 pinctrl-0 = <&blsp2_i2c4_default>; 1024 pinctrl-1 = <&blsp2_i2c4_sleep>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 intc: interrupt-controller@b000000 { 1031 compatible = "qcom,msm-qgic2"; 1032 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1033 interrupt-controller; 1034 #interrupt-cells = <3>; 1035 }; 1036 1037 apcs: mailbox@b011000 { 1038 compatible = "qcom,msm8976-apcs-kpss-global", 1039 "qcom,msm8994-apcs-kpss-global", "syscon"; 1040 reg = <0x0b011000 0x1000>; 1041 #mbox-cells = <1>; 1042 }; 1043 1044 timer@b120000 { 1045 compatible = "arm,armv7-timer-mem"; 1046 reg = <0x0b120000 0x1000>; 1047 #address-cells = <1>; 1048 #size-cells = <1>; 1049 ranges; 1050 clock-frequency = <19200000>; 1051 1052 frame@b121000 { 1053 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1054 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1056 frame-number = <0>; 1057 }; 1058 1059 frame@b123000 { 1060 reg = <0x0b123000 0x1000>; 1061 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1062 frame-number = <1>; 1063 status = "disabled"; 1064 }; 1065 1066 frame@b124000 { 1067 reg = <0x0b124000 0x1000>; 1068 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1069 frame-number = <2>; 1070 status = "disabled"; 1071 }; 1072 1073 frame@b125000 { 1074 reg = <0x0b125000 0x1000>; 1075 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1076 frame-number = <3>; 1077 status = "disabled"; 1078 }; 1079 1080 frame@b126000 { 1081 reg = <0x0b126000 0x1000>; 1082 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1083 frame-number = <4>; 1084 status = "disabled"; 1085 }; 1086 1087 frame@b127000 { 1088 reg = <0x0b127000 0x1000>; 1089 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1090 frame-number = <5>; 1091 status = "disabled"; 1092 }; 1093 1094 frame@b128000 { 1095 reg = <0x0b128000 0x1000>; 1096 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1097 frame-number = <6>; 1098 status = "disabled"; 1099 }; 1100 }; 1101 1102 imem: sram@8600000 { 1103 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1104 reg = <0x08600000 0x1000>; 1105 #address-cells = <1>; 1106 #size-cells = <1>; 1107 1108 ranges = <0 0x08600000 0x1000>; 1109 1110 pil-reloc@94c { 1111 compatible = "qcom,pil-reloc-info"; 1112 reg = <0x94c 0xc8>; 1113 }; 1114 }; 1115 }; 1116 1117 thermal-zones { 1118 aoss0-thermal { 1119 polling-delay-passive = <250>; 1120 polling-delay = <1000>; 1121 1122 thermal-sensors = <&tsens 0>; 1123 1124 trips { 1125 aoss0_alert0: trip-point0 { 1126 temperature = <75000>; 1127 hysteresis = <2000>; 1128 type = "hot"; 1129 }; 1130 }; 1131 }; 1132 1133 modem-thermal { 1134 polling-delay-passive = <250>; 1135 polling-delay = <1000>; 1136 1137 thermal-sensors = <&tsens 1>; 1138 trips { 1139 modem_alert0: trip-point0 { 1140 temperature = <75000>; 1141 hysteresis = <2000>; 1142 type = "hot"; 1143 }; 1144 }; 1145 }; 1146 1147 qdsp-thermal { 1148 polling-delay-passive = <250>; 1149 polling-delay = <1000>; 1150 1151 thermal-sensors = <&tsens 2>; 1152 trips { 1153 qdsp_alert0: trip-point0 { 1154 temperature = <75000>; 1155 hysteresis = <2000>; 1156 type = "hot"; 1157 }; 1158 }; 1159 }; 1160 1161 cam-isp-thermal { 1162 polling-delay-passive = <250>; 1163 polling-delay = <1000>; 1164 1165 thermal-sensors = <&tsens 3>; 1166 trips { 1167 cam_isp_alert0: trip-point0 { 1168 temperature = <75000>; 1169 hysteresis = <2000>; 1170 type = "hot"; 1171 }; 1172 }; 1173 }; 1174 1175 cpu4-thermal { 1176 polling-delay-passive = <250>; 1177 polling-delay = <1000>; 1178 thermal-sensors = <&tsens 4>; 1179 1180 trips { 1181 cpu4_alert0: trip-point0 { 1182 temperature = <50000>; 1183 hysteresis = <2000>; 1184 type = "hot"; 1185 }; 1186 cpu4_alert1: trip-point1 { 1187 temperature = <55000>; 1188 hysteresis = <2000>; 1189 type = "passive"; 1190 }; 1191 cpu4_crit: cpu-crit { 1192 temperature = <75000>; 1193 hysteresis = <2000>; 1194 type = "critical"; 1195 }; 1196 }; 1197 }; 1198 1199 cpu5-thermal { 1200 polling-delay-passive = <250>; 1201 polling-delay = <1000>; 1202 thermal-sensors = <&tsens 5>; 1203 1204 trips { 1205 cpu5_alert0: trip-point0 { 1206 temperature = <50000>; 1207 hysteresis = <2000>; 1208 type = "hot"; 1209 }; 1210 cpu5_alert1: trip-point1 { 1211 temperature = <55000>; 1212 hysteresis = <2000>; 1213 type = "passive"; 1214 }; 1215 cpu5_crit: cpu-crit { 1216 temperature = <75000>; 1217 hysteresis = <2000>; 1218 type = "critical"; 1219 }; 1220 }; 1221 }; 1222 1223 cpu6-thermal { 1224 polling-delay-passive = <250>; 1225 polling-delay = <1000>; 1226 thermal-sensors = <&tsens 6>; 1227 1228 trips { 1229 cpu6_alert0: trip-point0 { 1230 temperature = <50000>; 1231 hysteresis = <2000>; 1232 type = "hot"; 1233 }; 1234 cpu6_alert1: trip-point1 { 1235 temperature = <55000>; 1236 hysteresis = <2000>; 1237 type = "passive"; 1238 }; 1239 cpu6_crit: cpu-crit { 1240 temperature = <75000>; 1241 hysteresis = <2000>; 1242 type = "critical"; 1243 }; 1244 }; 1245 }; 1246 1247 cpu7-thermal { 1248 polling-delay-passive = <250>; 1249 polling-delay = <1000>; 1250 thermal-sensors = <&tsens 7>; 1251 1252 trips { 1253 cpu7_alert0: trip-point0 { 1254 temperature = <50000>; 1255 hysteresis = <2000>; 1256 type = "hot"; 1257 }; 1258 cpu7_alert1: trip-point1 { 1259 temperature = <55000>; 1260 hysteresis = <2000>; 1261 type = "passive"; 1262 }; 1263 cpu7_crit: cpu-crit { 1264 temperature = <75000>; 1265 hysteresis = <2000>; 1266 type = "critical"; 1267 }; 1268 }; 1269 }; 1270 1271 big-l2-thermal { 1272 polling-delay-passive = <250>; 1273 polling-delay = <1000>; 1274 thermal-sensors = <&tsens 8>; 1275 1276 trips { 1277 l2_alert0: trip-point0 { 1278 temperature = <50000>; 1279 hysteresis = <2000>; 1280 type = "hot"; 1281 }; 1282 l2_alert1: trip-point1 { 1283 temperature = <55000>; 1284 hysteresis = <2000>; 1285 type = "passive"; 1286 }; 1287 l2_crit: l2-crit { 1288 temperature = <75000>; 1289 hysteresis = <2000>; 1290 type = "critical"; 1291 }; 1292 }; 1293 }; 1294 1295 cpu0-thermal { 1296 polling-delay-passive = <250>; 1297 polling-delay = <1000>; 1298 thermal-sensors = <&tsens 9>; 1299 1300 trips { 1301 cpu0_alert0: trip-point0 { 1302 temperature = <50000>; 1303 hysteresis = <2000>; 1304 type = "hot"; 1305 }; 1306 cpu0_alert1: trip-point1 { 1307 temperature = <55000>; 1308 hysteresis = <2000>; 1309 type = "passive"; 1310 }; 1311 cpu0_crit: cpu-crit { 1312 temperature = <75000>; 1313 hysteresis = <2000>; 1314 type = "critical"; 1315 }; 1316 }; 1317 }; 1318 1319 gpu-thermal { 1320 polling-delay-passive = <250>; 1321 polling-delay = <1000>; 1322 thermal-sensors = <&tsens 10>; 1323 1324 trips { 1325 gpu_alert0: trip-point0 { 1326 temperature = <50000>; 1327 hysteresis = <2000>; 1328 type = "hot"; 1329 }; 1330 gpu_alert1: trip-point1 { 1331 temperature = <55000>; 1332 hysteresis = <2000>; 1333 type = "passive"; 1334 }; 1335 gpu_crit: gpu-crit { 1336 temperature = <75000>; 1337 hysteresis = <2000>; 1338 type = "critical"; 1339 }; 1340 }; 1341 }; 1342 }; 1343 1344 timer { 1345 compatible = "arm,armv8-timer"; 1346 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1347 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1348 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1349 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1350 clock-frequency = <19200000>; 1351 }; 1352}; 1353