1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-msm8976.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 CPU0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a53"; 30 reg = <0x0>; 31 enable-method = "psci"; 32 cpu-idle-states = <&little_cpu_sleep_0>; 33 capacity-dmips-mhz = <573>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 }; 37 38 CPU1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x1>; 42 enable-method = "psci"; 43 cpu-idle-states = <&little_cpu_sleep_0>; 44 capacity-dmips-mhz = <573>; 45 next-level-cache = <&l2_0>; 46 #cooling-cells = <2>; 47 }; 48 49 CPU2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x2>; 53 enable-method = "psci"; 54 cpu-idle-states = <&little_cpu_sleep_0>; 55 capacity-dmips-mhz = <573>; 56 next-level-cache = <&l2_0>; 57 #cooling-cells = <2>; 58 }; 59 60 CPU3: cpu@3 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x3>; 64 enable-method = "psci"; 65 cpu-idle-states = <&little_cpu_sleep_0>; 66 capacity-dmips-mhz = <573>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 CPU4: cpu@100 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a72"; 74 reg = <0x100>; 75 enable-method = "psci"; 76 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 77 capacity-dmips-mhz = <1024>; 78 next-level-cache = <&l2_1>; 79 #cooling-cells = <2>; 80 }; 81 82 CPU5: cpu@101 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a72"; 85 reg = <0x101>; 86 enable-method = "psci"; 87 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 88 capacity-dmips-mhz = <1024>; 89 next-level-cache = <&l2_1>; 90 #cooling-cells = <2>; 91 }; 92 93 CPU6: cpu@102 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a72"; 96 reg = <0x102>; 97 enable-method = "psci"; 98 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 99 capacity-dmips-mhz = <1024>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 CPU7: cpu@103 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a72"; 107 reg = <0x103>; 108 enable-method = "psci"; 109 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 110 capacity-dmips-mhz = <1024>; 111 next-level-cache = <&l2_1>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu-map { 116 cluster0 { 117 core0 { 118 cpu = <&CPU0>; 119 }; 120 121 core1 { 122 cpu = <&CPU1>; 123 }; 124 125 core2 { 126 cpu = <&CPU2>; 127 }; 128 129 core3 { 130 cpu = <&CPU3>; 131 }; 132 }; 133 134 cluster1 { 135 core0 { 136 cpu = <&CPU4>; 137 }; 138 139 core1 { 140 cpu = <&CPU5>; 141 }; 142 143 core2 { 144 cpu = <&CPU6>; 145 }; 146 147 core3 { 148 cpu = <&CPU7>; 149 }; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 little_cpu_sleep_0: cpu-sleep-0-0 { 157 compatible = "arm,idle-state"; 158 idle-state-name = "little-power-collapse"; 159 arm,psci-suspend-param = <0x40000003>; 160 entry-latency-us = <181>; 161 exit-latency-us = <149>; 162 min-residency-us = <703>; 163 local-timer-stop; 164 }; 165 166 big_cpu_sleep_0: cpu-sleep-1-0 { 167 compatible = "arm,idle-state"; 168 idle-state-name = "big-retention"; 169 arm,psci-suspend-param = <0x00000002>; 170 entry-latency-us = <142>; 171 exit-latency-us = <99>; 172 min-residency-us = <242>; 173 }; 174 175 big_cpu_sleep_1: cpu-sleep-1-1 { 176 compatible = "arm,idle-state"; 177 idle-state-name = "big-power-collapse"; 178 arm,psci-suspend-param = <0x40000003>; 179 entry-latency-us = <158>; 180 exit-latency-us = <144>; 181 min-residency-us = <863>; 182 local-timer-stop; 183 }; 184 }; 185 186 l2_0: l2-cache0 { 187 compatible = "cache"; 188 cache-level = <2>; 189 }; 190 191 l2_1: l2-cache1 { 192 compatible = "cache"; 193 cache-level = <2>; 194 }; 195 }; 196 197 firmware { 198 scm: scm { 199 compatible = "qcom,scm-msm8976", "qcom,scm"; 200 clocks = <&gcc GCC_CRYPTO_CLK>, 201 <&gcc GCC_CRYPTO_AXI_CLK>, 202 <&gcc GCC_CRYPTO_AHB_CLK>; 203 clock-names = "core", "bus", "iface"; 204 #reset-cells = <1>; 205 206 qcom,dload-mode = <&tcsr 0x6100>; 207 }; 208 }; 209 210 memory@80000000 { 211 device_type = "memory"; 212 /* We expect the bootloader to fill in the size */ 213 reg = <0x0 0x80000000 0x0 0x0>; 214 }; 215 216 pmu: pmu { 217 compatible = "arm,armv8-pmuv3"; 218 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 reserved-memory { 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges; 230 231 ext-region@85b00000 { 232 reg = <0x0 0x85b00000 0x0 0x500000>; 233 no-map; 234 }; 235 236 smem@86300000 { 237 compatible = "qcom,smem"; 238 reg = <0x0 0x86300000 0x0 0x100000>; 239 no-map; 240 241 hwlocks = <&tcsr_mutex 3>; 242 qcom,rpm-msg-ram = <&rpm_msg_ram>; 243 }; 244 245 reserved@86400000 { 246 reg = <0x0 0x86400000 0x0 0x800000>; 247 no-map; 248 }; 249 250 mpss_mem: mpss@86c00000 { 251 reg = <0x0 0x86c00000 0x0 0x5600000>; 252 no-map; 253 }; 254 255 lpass_mem: lpass@8c200000 { 256 reg = <0x0 0x8c200000 0x0 0x1800000>; 257 no-map; 258 }; 259 260 venus_mem: memory@8da00000 { 261 reg = <0x0 0x8da00000 0x0 0x2600000>; 262 no-map; 263 }; 264 265 tz-apps@8dd00000 { 266 reg = <0x0 0x8dd00000 0x0 0x1400000>; 267 no-map; 268 }; 269 }; 270 271 smp2p-hexagon { 272 compatible = "qcom,smp2p"; 273 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 274 qcom,ipc = <&apcs 8 10>; 275 276 qcom,local-pid = <0>; 277 qcom,remote-pid = <2>; 278 qcom,smem = <443>, <429>; 279 280 adsp_smp2p_out: master-kernel { 281 qcom,entry-name = "master-kernel"; 282 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 adsp_smp2p_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smp2p-modem { 295 compatible = "qcom,smp2p"; 296 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 297 qcom,ipc = <&apcs 8 13>; 298 299 qcom,local-pid = <0>; 300 qcom,remote-pid = <1>; 301 qcom,smem = <435>, <428>; 302 303 modem_smp2p_out: master-kernel { 304 qcom,entry-name = "master-kernel"; 305 306 #qcom,smem-state-cells = <1>; 307 }; 308 309 modem_smp2p_in: slave-kernel { 310 qcom,entry-name = "slave-kernel"; 311 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 }; 316 317 smp2p-wcnss { 318 compatible = "qcom,smp2p"; 319 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 320 qcom,ipc = <&apcs 8 17>; 321 322 qcom,local-pid = <0>; 323 qcom,remote-pid = <4>; 324 qcom,smem = <451>, <431>; 325 326 wcnss_smp2p_out: master-kernel { 327 qcom,entry-name = "master-kernel"; 328 329 #qcom,smem-state-cells = <1>; 330 }; 331 332 wcnss_smp2p_in: slave-kernel { 333 qcom,entry-name = "slave-kernel"; 334 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 }; 339 340 smd { 341 compatible = "qcom,smd"; 342 343 rpm { 344 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 345 qcom,ipc = <&apcs 8 0>; 346 qcom,smd-edge = <15>; 347 348 rpm_requests: rpm-requests { 349 compatible = "qcom,rpm-msm8976"; 350 qcom,smd-channels = "rpm_requests"; 351 352 rpmcc: clock-controller { 353 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 354 #clock-cells = <1>; 355 }; 356 357 rpmpd: power-controller { 358 compatible = "qcom,msm8976-rpmpd"; 359 #power-domain-cells = <1>; 360 operating-points-v2 = <&rpmpd_opp_table>; 361 362 rpmpd_opp_table: opp-table { 363 compatible = "operating-points-v2"; 364 365 rpmpd_opp_ret: opp1 { 366 opp-level = <RPM_SMD_LEVEL_RETENTION>; 367 }; 368 369 rpmpd_opp_ret_plus: opp2 { 370 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 371 }; 372 373 rpmpd_opp_min_svs: opp3 { 374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 375 }; 376 377 rpmpd_opp_low_svs: opp4 { 378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 379 }; 380 381 rpmpd_opp_svs: opp5 { 382 opp-level = <RPM_SMD_LEVEL_SVS>; 383 }; 384 385 rpmpd_opp_svs_plus: opp6 { 386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 387 }; 388 389 rpmpd_opp_nom: opp7 { 390 opp-level = <RPM_SMD_LEVEL_NOM>; 391 }; 392 393 rpmpd_opp_nom_plus: opp8 { 394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 395 }; 396 397 rpmpd_opp_turbo: opp9 { 398 opp-level = <RPM_SMD_LEVEL_TURBO>; 399 }; 400 401 rpmpd_opp_turbo_no_cpr: opp10 { 402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 403 }; 404 405 rpmpd_opp_turbo_high: opp111 { 406 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 407 }; 408 }; 409 }; 410 }; 411 }; 412 }; 413 414 smsm { 415 compatible = "qcom,smsm"; 416 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 qcom,ipc-1 = <&apcs 8 12>; 421 qcom,ipc-2 = <&apcs 8 9>; 422 qcom,ipc-3 = <&apcs 8 18>; 423 424 apps_smsm: apps@0 { 425 reg = <0>; 426 #qcom,smem-state-cells = <1>; 427 }; 428 429 hexagon_smsm: hexagon@1 { 430 reg = <1>; 431 interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 437 wcnss_smsm: wcnss@6 { 438 reg = <6>; 439 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 440 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 }; 445 446 soc: soc@0 { 447 #address-cells = <1>; 448 #size-cells = <1>; 449 ranges = <0 0 0 0xffffffff>; 450 compatible = "simple-bus"; 451 452 rng@22000 { 453 compatible = "qcom,prng"; 454 reg = <0x00022000 0x140>; 455 clocks = <&gcc GCC_PRNG_AHB_CLK>; 456 clock-names = "core"; 457 }; 458 459 rpm_msg_ram: sram@60000 { 460 compatible = "qcom,rpm-msg-ram"; 461 reg = <0x00060000 0x8000>; 462 }; 463 464 usb_hs_phy: phy@6c000 { 465 compatible = "qcom,usb-hs-28nm-femtophy"; 466 reg = <0x0006c000 0x200>; 467 #phy-cells = <0>; 468 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 469 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 470 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 471 clock-names = "ref", "ahb", "sleep"; 472 resets = <&gcc RST_QUSB2_PHY_BCR>, 473 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 474 reset-names = "phy", "por"; 475 status = "disabled"; 476 }; 477 478 qfprom: qfprom@a4000 { 479 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 480 reg = <0x000a4000 0x1000>; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 484 tsens_base1: base1@218 { 485 reg = <0x218 1>; 486 bits = <0 8>; 487 }; 488 489 tsens_s0_p1: s0-p1@219 { 490 reg = <0x219 0x1>; 491 bits = <0 6>; 492 }; 493 494 tsens_s0_p2: s0-p2@219 { 495 reg = <0x219 0x2>; 496 bits = <6 6>; 497 }; 498 499 tsens_s1_p1: s1-p1@21a { 500 reg = <0x21a 0x2>; 501 bits = <4 6>; 502 }; 503 504 tsens_s1_p2: s1-p2@21b { 505 reg = <0x21b 0x1>; 506 bits = <2 6>; 507 }; 508 509 tsens_s2_p1: s2-p1@21c { 510 reg = <0x21c 0x1>; 511 bits = <0 6>; 512 }; 513 514 tsens_s2_p2: s2-p2@21c { 515 reg = <0x21c 0x2>; 516 bits = <6 6>; 517 }; 518 519 tsens_s3_p1: s3-p1@21d { 520 reg = <0x21d 0x2>; 521 bits = <4 6>; 522 }; 523 524 tsens_s3_p2: s3-p2@21e { 525 reg = <0x21e 0x1>; 526 bits = <2 6>; 527 }; 528 529 tsens_base2: base2@220 { 530 reg = <0x220 1>; 531 bits = <0 8>; 532 }; 533 534 tsens_s4_p1: s4-p1@221 { 535 reg = <0x221 0x1>; 536 bits = <0 6>; 537 }; 538 539 tsens_s4_p2: s4-p2@221 { 540 reg = <0x221 0x2>; 541 bits = <6 6>; 542 }; 543 544 tsens_s5_p1: s5-p1@222 { 545 reg = <0x222 0x2>; 546 bits = <4 6>; 547 }; 548 549 tsens_s5_p2: s5-p2@223 { 550 reg = <0x224 0x1>; 551 bits = <2 6>; 552 }; 553 554 tsens_s6_p1: s6-p1@224 { 555 reg = <0x224 0x1>; 556 bits = <0 6>; 557 }; 558 559 tsens_s6_p2: s6-p2@224 { 560 reg = <0x224 0x2>; 561 bits = <6 6>; 562 }; 563 564 tsens_s7_p1: s7-p1@225 { 565 reg = <0x225 0x2>; 566 bits = <4 6>; 567 }; 568 569 tsens_s7_p2: s7-p2@226 { 570 reg = <0x226 0x2>; 571 bits = <2 6>; 572 }; 573 574 tsens_mode: mode@228 { 575 reg = <0x228 1>; 576 bits = <0 3>; 577 }; 578 579 tsens_s8_p1: s8-p1@228 { 580 reg = <0x228 0x2>; 581 bits = <3 6>; 582 }; 583 584 tsens_s8_p2: s8-p2@229 { 585 reg = <0x229 0x1>; 586 bits = <1 6>; 587 }; 588 589 tsens_s9_p1: s9-p1@229 { 590 reg = <0x229 0x2>; 591 bits = <7 6>; 592 }; 593 594 tsens_s9_p2: s9-p2@22a { 595 reg = <0x22a 0x2>; 596 bits = <5 6>; 597 }; 598 599 tsens_s10_p1: s10-p1@22b { 600 reg = <0x22b 0x2>; 601 bits = <3 6>; 602 }; 603 604 tsens_s10_p2: s10-p2@22c { 605 reg = <0x22c 0x1>; 606 bits = <1 6>; 607 }; 608 }; 609 610 tsens: thermal-sensor@4a9000 { 611 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 612 reg = <0x004a9000 0x1000>, /* TM */ 613 <0x004a8000 0x1000>; /* SROT */ 614 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "uplow"; 616 nvmem-cells = <&tsens_mode>, 617 <&tsens_base1>, <&tsens_base2>, 618 <&tsens_s0_p1>, <&tsens_s0_p2>, 619 <&tsens_s1_p1>, <&tsens_s1_p2>, 620 <&tsens_s2_p1>, <&tsens_s2_p2>, 621 <&tsens_s3_p1>, <&tsens_s3_p2>, 622 <&tsens_s4_p1>, <&tsens_s4_p2>, 623 <&tsens_s5_p1>, <&tsens_s5_p2>, 624 <&tsens_s6_p1>, <&tsens_s6_p2>, 625 <&tsens_s7_p1>, <&tsens_s7_p2>, 626 <&tsens_s8_p1>, <&tsens_s8_p2>, 627 <&tsens_s9_p1>, <&tsens_s9_p2>, 628 <&tsens_s10_p1>, <&tsens_s10_p2>; 629 nvmem-cell-names = "mode", 630 "base1", "base2", 631 "s0_p1", "s0_p2", 632 "s1_p1", "s1_p2", 633 "s2_p1", "s2_p2", 634 "s3_p1", "s3_p2", 635 "s4_p1", "s4_p2", 636 "s5_p1", "s5_p2", 637 "s6_p1", "s6_p2", 638 "s7_p1", "s7_p2", 639 "s8_p1", "s8_p2", 640 "s9_p1", "s9_p2", 641 "s10_p1", "s10_p2"; 642 #qcom,sensors = <11>; 643 #thermal-sensor-cells = <1>; 644 }; 645 646 tlmm: pinctrl@1000000 { 647 compatible = "qcom,msm8976-pinctrl"; 648 reg = <0x01000000 0x300000>; 649 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 650 #gpio-cells = <2>; 651 gpio-controller; 652 gpio-ranges = <&tlmm 0 0 145>; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 656 spi1_default: spi0-default-state { 657 spi-pins { 658 pins = "gpio0", "gpio1", "gpio3"; 659 function = "blsp_spi1"; 660 drive-strength = <12>; 661 bias-disable; 662 }; 663 664 cs-pins { 665 pins = "gpio2"; 666 function = "blsp_spi1"; 667 drive-strength = <2>; 668 bias-disable; 669 }; 670 }; 671 672 spi1_sleep: spi0-sleep-state { 673 spi-pins { 674 pins = "gpio0", "gpio1", "gpio3"; 675 function = "gpio"; 676 drive-strength = <2>; 677 bias-pull-down; 678 }; 679 680 cs-pins { 681 pins = "gpio2"; 682 function = "gpio"; 683 drive-strength = <2>; 684 bias-disable; 685 }; 686 }; 687 688 blsp1_i2c2_default: blsp1-i2c2-default-state { 689 pins = "gpio6", "gpio7"; 690 function = "blsp_i2c2"; 691 drive-strength = <2>; 692 bias-disable; 693 }; 694 695 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 696 pins = "gpio6", "gpio7"; 697 function = "gpio"; 698 drive-strength = <2>; 699 bias-disable; 700 }; 701 702 blsp1_i2c4_default: blsp1-i2c4-default-state { 703 pins = "gpio14", "gpio15"; 704 function = "blsp_i2c4"; 705 drive-strength = <2>; 706 bias-disable; 707 }; 708 709 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 710 pins = "gpio14", "gpio15"; 711 function = "gpio"; 712 drive-strength = <2>; 713 bias-disable; 714 }; 715 716 blsp2_uart2_active: blsp2-uart2-active-state { 717 pins = "gpio20", "gpio21"; 718 function = "blsp_uart6"; 719 drive-strength = <4>; 720 bias-disable; 721 }; 722 723 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 724 pins = "gpio20", "gpio21"; 725 function = "gpio"; 726 drive-strength = <2>; 727 bias-disable; 728 }; 729 730 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 731 blsp2_i2c2_default: blsp2-i2c2-default-state { 732 pins = "gpio22", "gpio23"; 733 function = "blsp_i2c6"; 734 drive-strength = <2>; 735 bias-disable; 736 }; 737 738 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 739 pins = "gpio22", "gpio23"; 740 function = "gpio"; 741 drive-strength = <2>; 742 bias-disable; 743 }; 744 745 blsp2_i2c4_default: blsp2-i2c4-default-state { 746 pins = "gpio18", "gpio19"; 747 function = "blsp_i2c8"; 748 drive-strength = <2>; 749 bias-disable; 750 }; 751 752 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 753 pins = "gpio18", "gpio19"; 754 function = "gpio"; 755 drive-strength = <2>; 756 bias-disable; 757 }; 758 }; 759 760 gcc: clock-controller@1800000 { 761 compatible = "qcom,gcc-msm8976"; 762 reg = <0x01800000 0x80000>; 763 #clock-cells = <1>; 764 #reset-cells = <1>; 765 #power-domain-cells = <1>; 766 767 assigned-clocks = <&gcc GPLL3>; 768 assigned-clock-rates = <1100000000>; 769 770 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 771 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 772 <0>, 773 <0>, 774 <0>, 775 <0>; 776 clock-names = "xo", 777 "xo_a", 778 "dsi0pll", 779 "dsi0pllbyte", 780 "dsi1pll", 781 "dsi1pllbyte"; 782 }; 783 784 tcsr_mutex: hwlock@1905000 { 785 compatible = "qcom,tcsr-mutex"; 786 reg = <0x01905000 0x20000>; 787 #hwlock-cells = <1>; 788 }; 789 790 tcsr: syscon@1937000 { 791 compatible = "qcom,msm8976-tcsr", "syscon"; 792 reg = <0x01937000 0x30000>; 793 }; 794 795 spmi_bus: spmi@200f000 { 796 compatible = "qcom,spmi-pmic-arb"; 797 reg = <0x0200f000 0x1000>, 798 <0x02400000 0x800000>, 799 <0x02c00000 0x800000>, 800 <0x03800000 0x200000>, 801 <0x0200a000 0x2100>; 802 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 803 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 804 interrupt-names = "periph_irq"; 805 qcom,channel = <0>; 806 qcom,ee = <0>; 807 808 #address-cells = <2>; 809 #size-cells = <0>; 810 interrupt-controller; 811 #interrupt-cells = <4>; 812 cell-index = <0>; 813 }; 814 815 sdhc_1: mmc@7824000 { 816 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 817 reg = <0x07824900 0x500>, <0x07824000 0x800>; 818 reg-names = "hc", "core"; 819 820 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 822 interrupt-names = "hc_irq", "pwr_irq"; 823 824 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 825 <&gcc GCC_SDCC1_APPS_CLK>, 826 <&rpmcc RPM_SMD_XO_CLK_SRC>; 827 clock-names = "iface", "core", "xo"; 828 status = "disabled"; 829 }; 830 831 sdhc_2: mmc@7864000 { 832 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 833 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 834 reg-names = "hc", "core"; 835 836 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "hc_irq", "pwr_irq"; 839 840 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 841 <&gcc GCC_SDCC2_APPS_CLK>, 842 <&rpmcc RPM_SMD_XO_CLK_SRC>; 843 clock-names = "iface", "core", "xo"; 844 status = "disabled"; 845 }; 846 847 blsp1_dma: dma-controller@7884000 { 848 compatible = "qcom,bam-v1.7.0"; 849 reg = <0x07884000 0x1f000>; 850 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 852 clock-names = "bam_clk"; 853 #dma-cells = <1>; 854 qcom,ee = <0>; 855 }; 856 857 blsp1_uart1: serial@78af000 { 858 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 859 reg = <0x078af000 0x200>; 860 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 862 clock-names = "core", "iface"; 863 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 864 dma-names = "tx", "rx"; 865 status = "disabled"; 866 }; 867 868 blsp1_uart2: serial@78b0000 { 869 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 870 reg = <0x078b0000 0x200>; 871 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 873 clock-names = "core", "iface"; 874 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 875 dma-names = "tx", "rx"; 876 status = "disabled"; 877 }; 878 879 blsp1_spi1: spi@78b5000 { 880 compatible = "qcom,spi-qup-v2.2.1"; 881 reg = <0x078b5000 0x500>; 882 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 884 clock-names = "core", "iface"; 885 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 886 dma-names = "tx", "rx"; 887 pinctrl-names = "default", "sleep"; 888 pinctrl-0 = <&spi1_default>; 889 pinctrl-1 = <&spi1_sleep>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 blsp1_i2c2: i2c@78b6000 { 896 compatible = "qcom,i2c-qup-v2.2.1"; 897 reg = <0x078b6000 0x500>; 898 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 900 clock-names = "core", "iface"; 901 clock-frequency = <400000>; 902 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 903 dma-names = "tx", "rx"; 904 pinctrl-names = "default", "sleep"; 905 pinctrl-0 = <&blsp1_i2c2_default>; 906 pinctrl-1 = <&blsp1_i2c2_default>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 }; 911 912 blsp1_i2c4: i2c@78b8000 { 913 compatible = "qcom,i2c-qup-v2.2.1"; 914 reg = <0x078b8000 0x500>; 915 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 917 clock-names = "core", "iface"; 918 clock-frequency = <400000>; 919 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 920 dma-names = "tx", "rx"; 921 pinctrl-names = "default", "sleep"; 922 pinctrl-0 = <&blsp1_i2c4_default>; 923 pinctrl-1 = <&blsp1_i2c4_sleep>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 otg: usb@78db000 { 930 compatible = "qcom,ci-hdrc"; 931 reg = <0x078db000 0x200>, 932 <0x078db200 0x200>; 933 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 936 clock-names = "iface", "core"; 937 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 938 assigned-clock-rates = <80000000>; 939 resets = <&gcc RST_USB_HS_BCR>; 940 reset-names = "core"; 941 ahb-burst-config = <0>; 942 dr_mode = "peripheral"; 943 phy_type = "ulpi"; 944 phy-names = "usb-phy"; 945 phys = <&usb_hs_phy>; 946 status = "disabled"; 947 #reset-cells = <1>; 948 }; 949 950 sdhc_3: mmc@7a24000 { 951 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 952 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 953 reg-names = "hc", "core"; 954 955 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "hc_irq", "pwr_irq"; 958 959 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 960 <&gcc GCC_SDCC3_APPS_CLK>, 961 <&rpmcc RPM_SMD_XO_CLK_SRC>; 962 clock-names = "iface", "core", "xo"; 963 964 status = "disabled"; 965 }; 966 967 blsp2_dma: dma-controller@7ac4000 { 968 compatible = "qcom,bam-v1.7.0"; 969 reg = <0x07ac4000 0x1f000>; 970 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 972 clock-names = "bam_clk"; 973 #dma-cells = <1>; 974 qcom,ee = <0>; 975 }; 976 977 blsp2_uart2: serial@7af0000 { 978 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 979 reg = <0x07af0000 0x200>; 980 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 982 clock-names = "core", "iface"; 983 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 984 dma-names = "tx", "rx"; 985 status = "disabled"; 986 }; 987 988 blsp2_i2c2: i2c@7af6000 { 989 compatible = "qcom,i2c-qup-v2.2.1"; 990 reg = <0x07af6000 0x600>; 991 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 993 clock-names = "core", "iface"; 994 clock-frequency = <400000>; 995 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 996 dma-names = "tx", "rx"; 997 pinctrl-names = "default", "sleep"; 998 pinctrl-0 = <&blsp2_i2c2_default>; 999 pinctrl-1 = <&blsp2_i2c2_sleep>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 blsp2_i2c4: i2c@7af8000 { 1006 compatible = "qcom,i2c-qup-v2.2.1"; 1007 reg = <0x07af8000 0x600>; 1008 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1010 clock-names = "core", "iface"; 1011 clock-frequency = <400000>; 1012 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1013 dma-names = "tx", "rx"; 1014 pinctrl-names = "default", "sleep"; 1015 pinctrl-0 = <&blsp2_i2c4_default>; 1016 pinctrl-1 = <&blsp2_i2c4_sleep>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 intc: interrupt-controller@b000000 { 1023 compatible = "qcom,msm-qgic2"; 1024 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1025 interrupt-controller; 1026 #interrupt-cells = <3>; 1027 }; 1028 1029 apcs: mailbox@b011000 { 1030 compatible = "qcom,msm8976-apcs-kpss-global", "syscon"; 1031 reg = <0x0b011000 0x1000>; 1032 #mbox-cells = <1>; 1033 }; 1034 1035 timer@b120000 { 1036 compatible = "arm,armv7-timer-mem"; 1037 reg = <0x0b120000 0x1000>; 1038 #address-cells = <1>; 1039 #size-cells = <1>; 1040 ranges; 1041 clock-frequency = <19200000>; 1042 1043 frame@b121000 { 1044 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1045 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1047 frame-number = <0>; 1048 }; 1049 1050 frame@b123000 { 1051 reg = <0x0b123000 0x1000>; 1052 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1053 frame-number = <1>; 1054 status = "disabled"; 1055 }; 1056 1057 frame@b124000 { 1058 reg = <0x0b124000 0x1000>; 1059 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1060 frame-number = <2>; 1061 status = "disabled"; 1062 }; 1063 1064 frame@b125000 { 1065 reg = <0x0b125000 0x1000>; 1066 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1067 frame-number = <3>; 1068 status = "disabled"; 1069 }; 1070 1071 frame@b126000 { 1072 reg = <0x0b126000 0x1000>; 1073 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1074 frame-number = <4>; 1075 status = "disabled"; 1076 }; 1077 1078 frame@b127000 { 1079 reg = <0x0b127000 0x1000>; 1080 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1081 frame-number = <5>; 1082 status = "disabled"; 1083 }; 1084 1085 frame@b128000 { 1086 reg = <0x0b128000 0x1000>; 1087 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1088 frame-number = <6>; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 imem: sram@8600000 { 1094 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1095 reg = <0x08600000 0x1000>; 1096 #address-cells = <1>; 1097 #size-cells = <1>; 1098 1099 ranges = <0 0x08600000 0x1000>; 1100 1101 pil-reloc@94c { 1102 compatible = "qcom,pil-reloc-info"; 1103 reg = <0x94c 0xc8>; 1104 }; 1105 }; 1106 }; 1107 1108 thermal-zones { 1109 aoss0-thermal { 1110 polling-delay-passive = <250>; 1111 polling-delay = <1000>; 1112 1113 thermal-sensors = <&tsens 0>; 1114 1115 trips { 1116 aoss0_alert0: trip-point0 { 1117 temperature = <75000>; 1118 hysteresis = <2000>; 1119 type = "hot"; 1120 }; 1121 }; 1122 }; 1123 1124 modem-thermal { 1125 polling-delay-passive = <250>; 1126 polling-delay = <1000>; 1127 1128 thermal-sensors = <&tsens 1>; 1129 trips { 1130 modem_alert0: trip-point0 { 1131 temperature = <75000>; 1132 hysteresis = <2000>; 1133 type = "hot"; 1134 }; 1135 }; 1136 }; 1137 1138 qdsp-thermal { 1139 polling-delay-passive = <250>; 1140 polling-delay = <1000>; 1141 1142 thermal-sensors = <&tsens 2>; 1143 trips { 1144 qdsp_alert0: trip-point0 { 1145 temperature = <75000>; 1146 hysteresis = <2000>; 1147 type = "hot"; 1148 }; 1149 }; 1150 }; 1151 1152 cam-isp-thermal { 1153 polling-delay-passive = <250>; 1154 polling-delay = <1000>; 1155 1156 thermal-sensors = <&tsens 3>; 1157 trips { 1158 cam_isp_alert0: trip-point0 { 1159 temperature = <75000>; 1160 hysteresis = <2000>; 1161 type = "hot"; 1162 }; 1163 }; 1164 }; 1165 1166 cpu4-thermal { 1167 polling-delay-passive = <250>; 1168 polling-delay = <1000>; 1169 thermal-sensors = <&tsens 4>; 1170 1171 trips { 1172 cpu4_alert0: trip-point0 { 1173 temperature = <50000>; 1174 hysteresis = <2000>; 1175 type = "hot"; 1176 }; 1177 cpu4_alert1: trip-point1 { 1178 temperature = <55000>; 1179 hysteresis = <2000>; 1180 type = "passive"; 1181 }; 1182 cpu4_crit: cpu-crit { 1183 temperature = <75000>; 1184 hysteresis = <2000>; 1185 type = "critical"; 1186 }; 1187 }; 1188 }; 1189 1190 cpu5-thermal { 1191 polling-delay-passive = <250>; 1192 polling-delay = <1000>; 1193 thermal-sensors = <&tsens 5>; 1194 1195 trips { 1196 cpu5_alert0: trip-point0 { 1197 temperature = <50000>; 1198 hysteresis = <2000>; 1199 type = "hot"; 1200 }; 1201 cpu5_alert1: trip-point1 { 1202 temperature = <55000>; 1203 hysteresis = <2000>; 1204 type = "passive"; 1205 }; 1206 cpu5_crit: cpu-crit { 1207 temperature = <75000>; 1208 hysteresis = <2000>; 1209 type = "critical"; 1210 }; 1211 }; 1212 }; 1213 1214 cpu6-thermal { 1215 polling-delay-passive = <250>; 1216 polling-delay = <1000>; 1217 thermal-sensors = <&tsens 6>; 1218 1219 trips { 1220 cpu6_alert0: trip-point0 { 1221 temperature = <50000>; 1222 hysteresis = <2000>; 1223 type = "hot"; 1224 }; 1225 cpu6_alert1: trip-point1 { 1226 temperature = <55000>; 1227 hysteresis = <2000>; 1228 type = "passive"; 1229 }; 1230 cpu6_crit: cpu-crit { 1231 temperature = <75000>; 1232 hysteresis = <2000>; 1233 type = "critical"; 1234 }; 1235 }; 1236 }; 1237 1238 cpu7-thermal { 1239 polling-delay-passive = <250>; 1240 polling-delay = <1000>; 1241 thermal-sensors = <&tsens 7>; 1242 1243 trips { 1244 cpu7_alert0: trip-point0 { 1245 temperature = <50000>; 1246 hysteresis = <2000>; 1247 type = "hot"; 1248 }; 1249 cpu7_alert1: trip-point1 { 1250 temperature = <55000>; 1251 hysteresis = <2000>; 1252 type = "passive"; 1253 }; 1254 cpu7_crit: cpu-crit { 1255 temperature = <75000>; 1256 hysteresis = <2000>; 1257 type = "critical"; 1258 }; 1259 }; 1260 }; 1261 1262 big-l2-thermal { 1263 polling-delay-passive = <250>; 1264 polling-delay = <1000>; 1265 thermal-sensors = <&tsens 8>; 1266 1267 trips { 1268 l2_alert0: trip-point0 { 1269 temperature = <50000>; 1270 hysteresis = <2000>; 1271 type = "hot"; 1272 }; 1273 l2_alert1: trip-point1 { 1274 temperature = <55000>; 1275 hysteresis = <2000>; 1276 type = "passive"; 1277 }; 1278 l2_crit: l2-crit { 1279 temperature = <75000>; 1280 hysteresis = <2000>; 1281 type = "critical"; 1282 }; 1283 }; 1284 }; 1285 1286 cpu0-thermal { 1287 polling-delay-passive = <250>; 1288 polling-delay = <1000>; 1289 thermal-sensors = <&tsens 9>; 1290 1291 trips { 1292 cpu0_alert0: trip-point0 { 1293 temperature = <50000>; 1294 hysteresis = <2000>; 1295 type = "hot"; 1296 }; 1297 cpu0_alert1: trip-point1 { 1298 temperature = <55000>; 1299 hysteresis = <2000>; 1300 type = "passive"; 1301 }; 1302 cpu0_crit: cpu-crit { 1303 temperature = <75000>; 1304 hysteresis = <2000>; 1305 type = "critical"; 1306 }; 1307 }; 1308 }; 1309 1310 gpu-thermal { 1311 polling-delay-passive = <250>; 1312 polling-delay = <1000>; 1313 thermal-sensors = <&tsens 10>; 1314 1315 trips { 1316 gpu_alert0: trip-point0 { 1317 temperature = <50000>; 1318 hysteresis = <2000>; 1319 type = "hot"; 1320 }; 1321 gpu_alert1: trip-point1 { 1322 temperature = <55000>; 1323 hysteresis = <2000>; 1324 type = "passive"; 1325 }; 1326 gpu_crit: gpu-crit { 1327 temperature = <75000>; 1328 hysteresis = <2000>; 1329 type = "critical"; 1330 }; 1331 }; 1332 }; 1333 }; 1334 1335 timer { 1336 compatible = "arm,armv8-timer"; 1337 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1338 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1339 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1340 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1341 clock-frequency = <19200000>; 1342 }; 1343}; 1344