1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-msm8976.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 CPU0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 cpu-idle-states = <&little_cpu_sleep_0>; 40 capacity-dmips-mhz = <573>; 41 next-level-cache = <&l2_0>; 42 #cooling-cells = <2>; 43 }; 44 45 CPU1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x1>; 49 enable-method = "psci"; 50 cpu-idle-states = <&little_cpu_sleep_0>; 51 capacity-dmips-mhz = <573>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 CPU2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x2>; 60 enable-method = "psci"; 61 cpu-idle-states = <&little_cpu_sleep_0>; 62 capacity-dmips-mhz = <573>; 63 next-level-cache = <&l2_0>; 64 #cooling-cells = <2>; 65 }; 66 67 CPU3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x3>; 71 enable-method = "psci"; 72 cpu-idle-states = <&little_cpu_sleep_0>; 73 capacity-dmips-mhz = <573>; 74 next-level-cache = <&l2_0>; 75 #cooling-cells = <2>; 76 }; 77 78 CPU4: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 reg = <0x100>; 82 enable-method = "psci"; 83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 84 capacity-dmips-mhz = <1024>; 85 next-level-cache = <&l2_1>; 86 #cooling-cells = <2>; 87 }; 88 89 CPU5: cpu@101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x101>; 93 enable-method = "psci"; 94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 95 capacity-dmips-mhz = <1024>; 96 next-level-cache = <&l2_1>; 97 #cooling-cells = <2>; 98 }; 99 100 CPU6: cpu@102 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a72"; 103 reg = <0x102>; 104 enable-method = "psci"; 105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&l2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a72"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 117 capacity-dmips-mhz = <1024>; 118 next-level-cache = <&l2_1>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu-map { 123 cluster0 { 124 core0 { 125 cpu = <&CPU0>; 126 }; 127 128 core1 { 129 cpu = <&CPU1>; 130 }; 131 132 core2 { 133 cpu = <&CPU2>; 134 }; 135 136 core3 { 137 cpu = <&CPU3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&CPU4>; 144 }; 145 146 core1 { 147 cpu = <&CPU5>; 148 }; 149 150 core2 { 151 cpu = <&CPU6>; 152 }; 153 154 core3 { 155 cpu = <&CPU7>; 156 }; 157 }; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 little_cpu_sleep_0: cpu-sleep-0-0 { 164 compatible = "arm,idle-state"; 165 idle-state-name = "little-power-collapse"; 166 arm,psci-suspend-param = <0x40000003>; 167 entry-latency-us = <181>; 168 exit-latency-us = <149>; 169 min-residency-us = <703>; 170 local-timer-stop; 171 }; 172 173 big_cpu_sleep_0: cpu-sleep-1-0 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "big-retention"; 176 arm,psci-suspend-param = <0x00000002>; 177 entry-latency-us = <142>; 178 exit-latency-us = <99>; 179 min-residency-us = <242>; 180 }; 181 182 big_cpu_sleep_1: cpu-sleep-1-1 { 183 compatible = "arm,idle-state"; 184 idle-state-name = "big-power-collapse"; 185 arm,psci-suspend-param = <0x40000003>; 186 entry-latency-us = <158>; 187 exit-latency-us = <144>; 188 min-residency-us = <863>; 189 local-timer-stop; 190 }; 191 }; 192 193 l2_0: l2-cache0 { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 }; 198 199 l2_1: l2-cache1 { 200 compatible = "cache"; 201 cache-level = <2>; 202 cache-unified; 203 }; 204 }; 205 206 firmware { 207 scm: scm { 208 compatible = "qcom,scm-msm8976", "qcom,scm"; 209 clocks = <&gcc GCC_CRYPTO_CLK>, 210 <&gcc GCC_CRYPTO_AXI_CLK>, 211 <&gcc GCC_CRYPTO_AHB_CLK>; 212 clock-names = "core", "bus", "iface"; 213 #reset-cells = <1>; 214 215 qcom,dload-mode = <&tcsr 0x6100>; 216 }; 217 }; 218 219 memory@80000000 { 220 device_type = "memory"; 221 /* We expect the bootloader to fill in the size */ 222 reg = <0x0 0x80000000 0x0 0x0>; 223 }; 224 225 pmu: pmu { 226 compatible = "arm,armv8-pmuv3"; 227 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 228 }; 229 230 psci { 231 compatible = "arm,psci-1.0"; 232 method = "smc"; 233 }; 234 235 reserved-memory { 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges; 239 240 ext-region@85b00000 { 241 reg = <0x0 0x85b00000 0x0 0x500000>; 242 no-map; 243 }; 244 245 smem@86300000 { 246 compatible = "qcom,smem"; 247 reg = <0x0 0x86300000 0x0 0x100000>; 248 no-map; 249 250 hwlocks = <&tcsr_mutex 3>; 251 qcom,rpm-msg-ram = <&rpm_msg_ram>; 252 }; 253 254 reserved@86400000 { 255 reg = <0x0 0x86400000 0x0 0x800000>; 256 no-map; 257 }; 258 259 mpss_mem: mpss@86c00000 { 260 reg = <0x0 0x86c00000 0x0 0x5600000>; 261 no-map; 262 }; 263 264 lpass_mem: lpass@8c200000 { 265 reg = <0x0 0x8c200000 0x0 0x1800000>; 266 no-map; 267 }; 268 269 venus_mem: memory@8da00000 { 270 reg = <0x0 0x8da00000 0x0 0x2600000>; 271 no-map; 272 }; 273 274 tz-apps@8dd00000 { 275 reg = <0x0 0x8dd00000 0x0 0x1400000>; 276 no-map; 277 }; 278 }; 279 280 smp2p-hexagon { 281 compatible = "qcom,smp2p"; 282 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 283 qcom,ipc = <&apcs 8 10>; 284 285 qcom,local-pid = <0>; 286 qcom,remote-pid = <2>; 287 qcom,smem = <443>, <429>; 288 289 adsp_smp2p_out: master-kernel { 290 qcom,entry-name = "master-kernel"; 291 292 #qcom,smem-state-cells = <1>; 293 }; 294 295 adsp_smp2p_in: slave-kernel { 296 qcom,entry-name = "slave-kernel"; 297 298 interrupt-controller; 299 #interrupt-cells = <2>; 300 }; 301 }; 302 303 smp2p-modem { 304 compatible = "qcom,smp2p"; 305 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 306 qcom,ipc = <&apcs 8 13>; 307 308 qcom,local-pid = <0>; 309 qcom,remote-pid = <1>; 310 qcom,smem = <435>, <428>; 311 312 modem_smp2p_out: master-kernel { 313 qcom,entry-name = "master-kernel"; 314 315 #qcom,smem-state-cells = <1>; 316 }; 317 318 modem_smp2p_in: slave-kernel { 319 qcom,entry-name = "slave-kernel"; 320 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 }; 324 }; 325 326 smp2p-wcnss { 327 compatible = "qcom,smp2p"; 328 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 329 qcom,ipc = <&apcs 8 17>; 330 331 qcom,local-pid = <0>; 332 qcom,remote-pid = <4>; 333 qcom,smem = <451>, <431>; 334 335 wcnss_smp2p_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 338 #qcom,smem-state-cells = <1>; 339 }; 340 341 wcnss_smp2p_in: slave-kernel { 342 qcom,entry-name = "slave-kernel"; 343 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 }; 348 349 smd { 350 compatible = "qcom,smd"; 351 352 rpm { 353 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 354 qcom,ipc = <&apcs 8 0>; 355 qcom,smd-edge = <15>; 356 357 rpm_requests: rpm-requests { 358 compatible = "qcom,rpm-msm8976"; 359 qcom,smd-channels = "rpm_requests"; 360 361 rpmcc: clock-controller { 362 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 363 clocks = <&xo_board>; 364 clock-names = "xo"; 365 #clock-cells = <1>; 366 }; 367 368 rpmpd: power-controller { 369 compatible = "qcom,msm8976-rpmpd"; 370 #power-domain-cells = <1>; 371 operating-points-v2 = <&rpmpd_opp_table>; 372 373 rpmpd_opp_table: opp-table { 374 compatible = "operating-points-v2"; 375 376 rpmpd_opp_ret: opp1 { 377 opp-level = <RPM_SMD_LEVEL_RETENTION>; 378 }; 379 380 rpmpd_opp_ret_plus: opp2 { 381 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 382 }; 383 384 rpmpd_opp_min_svs: opp3 { 385 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 386 }; 387 388 rpmpd_opp_low_svs: opp4 { 389 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 390 }; 391 392 rpmpd_opp_svs: opp5 { 393 opp-level = <RPM_SMD_LEVEL_SVS>; 394 }; 395 396 rpmpd_opp_svs_plus: opp6 { 397 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 398 }; 399 400 rpmpd_opp_nom: opp7 { 401 opp-level = <RPM_SMD_LEVEL_NOM>; 402 }; 403 404 rpmpd_opp_nom_plus: opp8 { 405 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 406 }; 407 408 rpmpd_opp_turbo: opp9 { 409 opp-level = <RPM_SMD_LEVEL_TURBO>; 410 }; 411 412 rpmpd_opp_turbo_no_cpr: opp10 { 413 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 414 }; 415 416 rpmpd_opp_turbo_high: opp111 { 417 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 418 }; 419 }; 420 }; 421 }; 422 }; 423 }; 424 425 smsm { 426 compatible = "qcom,smsm"; 427 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 qcom,ipc-1 = <&apcs 8 12>; 432 qcom,ipc-2 = <&apcs 8 9>; 433 qcom,ipc-3 = <&apcs 8 18>; 434 435 apps_smsm: apps@0 { 436 reg = <0>; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 hexagon_smsm: hexagon@1 { 441 reg = <1>; 442 interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; 443 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 }; 447 448 wcnss_smsm: wcnss@6 { 449 reg = <6>; 450 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 451 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 }; 455 }; 456 457 soc: soc@0 { 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges = <0 0 0 0xffffffff>; 461 compatible = "simple-bus"; 462 463 rng@22000 { 464 compatible = "qcom,prng"; 465 reg = <0x00022000 0x140>; 466 clocks = <&gcc GCC_PRNG_AHB_CLK>; 467 clock-names = "core"; 468 }; 469 470 rpm_msg_ram: sram@60000 { 471 compatible = "qcom,rpm-msg-ram"; 472 reg = <0x00060000 0x8000>; 473 }; 474 475 usb_hs_phy: phy@6c000 { 476 compatible = "qcom,usb-hs-28nm-femtophy"; 477 reg = <0x0006c000 0x200>; 478 #phy-cells = <0>; 479 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 480 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 481 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 482 clock-names = "ref", "ahb", "sleep"; 483 resets = <&gcc RST_QUSB2_PHY_BCR>, 484 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 485 reset-names = "phy", "por"; 486 status = "disabled"; 487 }; 488 489 qfprom: qfprom@a4000 { 490 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 491 reg = <0x000a4000 0x1000>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 495 tsens_base1: base1@218 { 496 reg = <0x218 1>; 497 bits = <0 8>; 498 }; 499 500 tsens_s0_p1: s0-p1@219 { 501 reg = <0x219 0x1>; 502 bits = <0 6>; 503 }; 504 505 tsens_s0_p2: s0-p2@219 { 506 reg = <0x219 0x2>; 507 bits = <6 6>; 508 }; 509 510 tsens_s1_p1: s1-p1@21a { 511 reg = <0x21a 0x2>; 512 bits = <4 6>; 513 }; 514 515 tsens_s1_p2: s1-p2@21b { 516 reg = <0x21b 0x1>; 517 bits = <2 6>; 518 }; 519 520 tsens_s2_p1: s2-p1@21c { 521 reg = <0x21c 0x1>; 522 bits = <0 6>; 523 }; 524 525 tsens_s2_p2: s2-p2@21c { 526 reg = <0x21c 0x2>; 527 bits = <6 6>; 528 }; 529 530 tsens_s3_p1: s3-p1@21d { 531 reg = <0x21d 0x2>; 532 bits = <4 6>; 533 }; 534 535 tsens_s3_p2: s3-p2@21e { 536 reg = <0x21e 0x1>; 537 bits = <2 6>; 538 }; 539 540 tsens_base2: base2@220 { 541 reg = <0x220 1>; 542 bits = <0 8>; 543 }; 544 545 tsens_s4_p1: s4-p1@221 { 546 reg = <0x221 0x1>; 547 bits = <0 6>; 548 }; 549 550 tsens_s4_p2: s4-p2@221 { 551 reg = <0x221 0x2>; 552 bits = <6 6>; 553 }; 554 555 tsens_s5_p1: s5-p1@222 { 556 reg = <0x222 0x2>; 557 bits = <4 6>; 558 }; 559 560 tsens_s5_p2: s5-p2@223 { 561 reg = <0x224 0x1>; 562 bits = <2 6>; 563 }; 564 565 tsens_s6_p1: s6-p1@224 { 566 reg = <0x224 0x1>; 567 bits = <0 6>; 568 }; 569 570 tsens_s6_p2: s6-p2@224 { 571 reg = <0x224 0x2>; 572 bits = <6 6>; 573 }; 574 575 tsens_s7_p1: s7-p1@225 { 576 reg = <0x225 0x2>; 577 bits = <4 6>; 578 }; 579 580 tsens_s7_p2: s7-p2@226 { 581 reg = <0x226 0x2>; 582 bits = <2 6>; 583 }; 584 585 tsens_mode: mode@228 { 586 reg = <0x228 1>; 587 bits = <0 3>; 588 }; 589 590 tsens_s8_p1: s8-p1@228 { 591 reg = <0x228 0x2>; 592 bits = <3 6>; 593 }; 594 595 tsens_s8_p2: s8-p2@229 { 596 reg = <0x229 0x1>; 597 bits = <1 6>; 598 }; 599 600 tsens_s9_p1: s9-p1@229 { 601 reg = <0x229 0x2>; 602 bits = <7 6>; 603 }; 604 605 tsens_s9_p2: s9-p2@22a { 606 reg = <0x22a 0x2>; 607 bits = <5 6>; 608 }; 609 610 tsens_s10_p1: s10-p1@22b { 611 reg = <0x22b 0x2>; 612 bits = <3 6>; 613 }; 614 615 tsens_s10_p2: s10-p2@22c { 616 reg = <0x22c 0x1>; 617 bits = <1 6>; 618 }; 619 }; 620 621 tsens: thermal-sensor@4a9000 { 622 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 623 reg = <0x004a9000 0x1000>, /* TM */ 624 <0x004a8000 0x1000>; /* SROT */ 625 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "uplow"; 627 nvmem-cells = <&tsens_mode>, 628 <&tsens_base1>, <&tsens_base2>, 629 <&tsens_s0_p1>, <&tsens_s0_p2>, 630 <&tsens_s1_p1>, <&tsens_s1_p2>, 631 <&tsens_s2_p1>, <&tsens_s2_p2>, 632 <&tsens_s3_p1>, <&tsens_s3_p2>, 633 <&tsens_s4_p1>, <&tsens_s4_p2>, 634 <&tsens_s5_p1>, <&tsens_s5_p2>, 635 <&tsens_s6_p1>, <&tsens_s6_p2>, 636 <&tsens_s7_p1>, <&tsens_s7_p2>, 637 <&tsens_s8_p1>, <&tsens_s8_p2>, 638 <&tsens_s9_p1>, <&tsens_s9_p2>, 639 <&tsens_s10_p1>, <&tsens_s10_p2>; 640 nvmem-cell-names = "mode", 641 "base1", "base2", 642 "s0_p1", "s0_p2", 643 "s1_p1", "s1_p2", 644 "s2_p1", "s2_p2", 645 "s3_p1", "s3_p2", 646 "s4_p1", "s4_p2", 647 "s5_p1", "s5_p2", 648 "s6_p1", "s6_p2", 649 "s7_p1", "s7_p2", 650 "s8_p1", "s8_p2", 651 "s9_p1", "s9_p2", 652 "s10_p1", "s10_p2"; 653 #qcom,sensors = <11>; 654 #thermal-sensor-cells = <1>; 655 }; 656 657 tlmm: pinctrl@1000000 { 658 compatible = "qcom,msm8976-pinctrl"; 659 reg = <0x01000000 0x300000>; 660 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 661 #gpio-cells = <2>; 662 gpio-controller; 663 gpio-ranges = <&tlmm 0 0 145>; 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 667 spi1_default: spi0-default-state { 668 spi-pins { 669 pins = "gpio0", "gpio1", "gpio3"; 670 function = "blsp_spi1"; 671 drive-strength = <12>; 672 bias-disable; 673 }; 674 675 cs-pins { 676 pins = "gpio2"; 677 function = "blsp_spi1"; 678 drive-strength = <2>; 679 bias-disable; 680 }; 681 }; 682 683 spi1_sleep: spi0-sleep-state { 684 spi-pins { 685 pins = "gpio0", "gpio1", "gpio3"; 686 function = "gpio"; 687 drive-strength = <2>; 688 bias-pull-down; 689 }; 690 691 cs-pins { 692 pins = "gpio2"; 693 function = "gpio"; 694 drive-strength = <2>; 695 bias-disable; 696 }; 697 }; 698 699 blsp1_i2c2_default: blsp1-i2c2-default-state { 700 pins = "gpio6", "gpio7"; 701 function = "blsp_i2c2"; 702 drive-strength = <2>; 703 bias-disable; 704 }; 705 706 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 707 pins = "gpio6", "gpio7"; 708 function = "gpio"; 709 drive-strength = <2>; 710 bias-disable; 711 }; 712 713 blsp1_i2c4_default: blsp1-i2c4-default-state { 714 pins = "gpio14", "gpio15"; 715 function = "blsp_i2c4"; 716 drive-strength = <2>; 717 bias-disable; 718 }; 719 720 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 721 pins = "gpio14", "gpio15"; 722 function = "gpio"; 723 drive-strength = <2>; 724 bias-disable; 725 }; 726 727 blsp2_uart2_active: blsp2-uart2-active-state { 728 pins = "gpio20", "gpio21"; 729 function = "blsp_uart6"; 730 drive-strength = <4>; 731 bias-disable; 732 }; 733 734 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 735 pins = "gpio20", "gpio21"; 736 function = "gpio"; 737 drive-strength = <2>; 738 bias-disable; 739 }; 740 741 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 742 blsp2_i2c2_default: blsp2-i2c2-default-state { 743 pins = "gpio22", "gpio23"; 744 function = "blsp_i2c6"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 750 pins = "gpio22", "gpio23"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 blsp2_i2c4_default: blsp2-i2c4-default-state { 757 pins = "gpio18", "gpio19"; 758 function = "blsp_i2c8"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 764 pins = "gpio18", "gpio19"; 765 function = "gpio"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 }; 770 771 gcc: clock-controller@1800000 { 772 compatible = "qcom,gcc-msm8976"; 773 reg = <0x01800000 0x80000>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 #power-domain-cells = <1>; 777 778 assigned-clocks = <&gcc GPLL3>; 779 assigned-clock-rates = <1100000000>; 780 781 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 782 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 783 <0>, 784 <0>, 785 <0>, 786 <0>; 787 clock-names = "xo", 788 "xo_a", 789 "dsi0pll", 790 "dsi0pllbyte", 791 "dsi1pll", 792 "dsi1pllbyte"; 793 }; 794 795 tcsr_mutex: hwlock@1905000 { 796 compatible = "qcom,tcsr-mutex"; 797 reg = <0x01905000 0x20000>; 798 #hwlock-cells = <1>; 799 }; 800 801 tcsr: syscon@1937000 { 802 compatible = "qcom,msm8976-tcsr", "syscon"; 803 reg = <0x01937000 0x30000>; 804 }; 805 806 spmi_bus: spmi@200f000 { 807 compatible = "qcom,spmi-pmic-arb"; 808 reg = <0x0200f000 0x1000>, 809 <0x02400000 0x800000>, 810 <0x02c00000 0x800000>, 811 <0x03800000 0x200000>, 812 <0x0200a000 0x2100>; 813 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 814 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-names = "periph_irq"; 816 qcom,channel = <0>; 817 qcom,ee = <0>; 818 819 #address-cells = <2>; 820 #size-cells = <0>; 821 interrupt-controller; 822 #interrupt-cells = <4>; 823 }; 824 825 sdhc_1: mmc@7824900 { 826 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 827 reg = <0x07824900 0x500>, <0x07824000 0x800>; 828 reg-names = "hc", "core"; 829 830 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "hc_irq", "pwr_irq"; 833 834 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 835 <&gcc GCC_SDCC1_APPS_CLK>, 836 <&rpmcc RPM_SMD_XO_CLK_SRC>; 837 clock-names = "iface", "core", "xo"; 838 status = "disabled"; 839 }; 840 841 sdhc_2: mmc@7864900 { 842 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 843 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 844 reg-names = "hc", "core"; 845 846 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "hc_irq", "pwr_irq"; 849 850 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 851 <&gcc GCC_SDCC2_APPS_CLK>, 852 <&rpmcc RPM_SMD_XO_CLK_SRC>; 853 clock-names = "iface", "core", "xo"; 854 status = "disabled"; 855 }; 856 857 blsp1_dma: dma-controller@7884000 { 858 compatible = "qcom,bam-v1.7.0"; 859 reg = <0x07884000 0x1f000>; 860 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 862 clock-names = "bam_clk"; 863 #dma-cells = <1>; 864 qcom,ee = <0>; 865 }; 866 867 blsp1_uart1: serial@78af000 { 868 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 869 reg = <0x078af000 0x200>; 870 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 872 clock-names = "core", "iface"; 873 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 874 dma-names = "tx", "rx"; 875 status = "disabled"; 876 }; 877 878 blsp1_uart2: serial@78b0000 { 879 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 880 reg = <0x078b0000 0x200>; 881 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 883 clock-names = "core", "iface"; 884 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 885 dma-names = "tx", "rx"; 886 status = "disabled"; 887 }; 888 889 blsp1_spi1: spi@78b5000 { 890 compatible = "qcom,spi-qup-v2.2.1"; 891 reg = <0x078b5000 0x500>; 892 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 894 clock-names = "core", "iface"; 895 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 896 dma-names = "tx", "rx"; 897 pinctrl-names = "default", "sleep"; 898 pinctrl-0 = <&spi1_default>; 899 pinctrl-1 = <&spi1_sleep>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 blsp1_i2c2: i2c@78b6000 { 906 compatible = "qcom,i2c-qup-v2.2.1"; 907 reg = <0x078b6000 0x500>; 908 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 910 clock-names = "core", "iface"; 911 clock-frequency = <400000>; 912 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 913 dma-names = "tx", "rx"; 914 pinctrl-names = "default", "sleep"; 915 pinctrl-0 = <&blsp1_i2c2_default>; 916 pinctrl-1 = <&blsp1_i2c2_default>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 blsp1_i2c4: i2c@78b8000 { 923 compatible = "qcom,i2c-qup-v2.2.1"; 924 reg = <0x078b8000 0x500>; 925 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 927 clock-names = "core", "iface"; 928 clock-frequency = <400000>; 929 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 930 dma-names = "tx", "rx"; 931 pinctrl-names = "default", "sleep"; 932 pinctrl-0 = <&blsp1_i2c4_default>; 933 pinctrl-1 = <&blsp1_i2c4_sleep>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 }; 938 939 otg: usb@78db000 { 940 compatible = "qcom,ci-hdrc"; 941 reg = <0x078db000 0x200>, 942 <0x078db200 0x200>; 943 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 946 clock-names = "iface", "core"; 947 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 948 assigned-clock-rates = <80000000>; 949 resets = <&gcc RST_USB_HS_BCR>; 950 reset-names = "core"; 951 ahb-burst-config = <0>; 952 dr_mode = "peripheral"; 953 phy_type = "ulpi"; 954 phy-names = "usb-phy"; 955 phys = <&usb_hs_phy>; 956 status = "disabled"; 957 #reset-cells = <1>; 958 }; 959 960 sdhc_3: mmc@7a24900 { 961 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 962 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 963 reg-names = "hc", "core"; 964 965 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-names = "hc_irq", "pwr_irq"; 968 969 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 970 <&gcc GCC_SDCC3_APPS_CLK>, 971 <&rpmcc RPM_SMD_XO_CLK_SRC>; 972 clock-names = "iface", "core", "xo"; 973 974 status = "disabled"; 975 }; 976 977 blsp2_dma: dma-controller@7ac4000 { 978 compatible = "qcom,bam-v1.7.0"; 979 reg = <0x07ac4000 0x1f000>; 980 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 982 clock-names = "bam_clk"; 983 #dma-cells = <1>; 984 qcom,ee = <0>; 985 }; 986 987 blsp2_uart2: serial@7af0000 { 988 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 989 reg = <0x07af0000 0x200>; 990 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 992 clock-names = "core", "iface"; 993 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 994 dma-names = "tx", "rx"; 995 status = "disabled"; 996 }; 997 998 blsp2_i2c2: i2c@7af6000 { 999 compatible = "qcom,i2c-qup-v2.2.1"; 1000 reg = <0x07af6000 0x600>; 1001 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1003 clock-names = "core", "iface"; 1004 clock-frequency = <400000>; 1005 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1006 dma-names = "tx", "rx"; 1007 pinctrl-names = "default", "sleep"; 1008 pinctrl-0 = <&blsp2_i2c2_default>; 1009 pinctrl-1 = <&blsp2_i2c2_sleep>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 blsp2_i2c4: i2c@7af8000 { 1016 compatible = "qcom,i2c-qup-v2.2.1"; 1017 reg = <0x07af8000 0x600>; 1018 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1020 clock-names = "core", "iface"; 1021 clock-frequency = <400000>; 1022 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1023 dma-names = "tx", "rx"; 1024 pinctrl-names = "default", "sleep"; 1025 pinctrl-0 = <&blsp2_i2c4_default>; 1026 pinctrl-1 = <&blsp2_i2c4_sleep>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 intc: interrupt-controller@b000000 { 1033 compatible = "qcom,msm-qgic2"; 1034 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1035 interrupt-controller; 1036 #interrupt-cells = <3>; 1037 }; 1038 1039 apcs: mailbox@b011000 { 1040 compatible = "qcom,msm8976-apcs-kpss-global", 1041 "qcom,msm8994-apcs-kpss-global", "syscon"; 1042 reg = <0x0b011000 0x1000>; 1043 #mbox-cells = <1>; 1044 }; 1045 1046 timer@b120000 { 1047 compatible = "arm,armv7-timer-mem"; 1048 reg = <0x0b120000 0x1000>; 1049 #address-cells = <1>; 1050 #size-cells = <1>; 1051 ranges; 1052 clock-frequency = <19200000>; 1053 1054 frame@b121000 { 1055 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1056 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1058 frame-number = <0>; 1059 }; 1060 1061 frame@b123000 { 1062 reg = <0x0b123000 0x1000>; 1063 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1064 frame-number = <1>; 1065 status = "disabled"; 1066 }; 1067 1068 frame@b124000 { 1069 reg = <0x0b124000 0x1000>; 1070 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1071 frame-number = <2>; 1072 status = "disabled"; 1073 }; 1074 1075 frame@b125000 { 1076 reg = <0x0b125000 0x1000>; 1077 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1078 frame-number = <3>; 1079 status = "disabled"; 1080 }; 1081 1082 frame@b126000 { 1083 reg = <0x0b126000 0x1000>; 1084 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1085 frame-number = <4>; 1086 status = "disabled"; 1087 }; 1088 1089 frame@b127000 { 1090 reg = <0x0b127000 0x1000>; 1091 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1092 frame-number = <5>; 1093 status = "disabled"; 1094 }; 1095 1096 frame@b128000 { 1097 reg = <0x0b128000 0x1000>; 1098 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1099 frame-number = <6>; 1100 status = "disabled"; 1101 }; 1102 }; 1103 1104 imem: sram@8600000 { 1105 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1106 reg = <0x08600000 0x1000>; 1107 #address-cells = <1>; 1108 #size-cells = <1>; 1109 1110 ranges = <0 0x08600000 0x1000>; 1111 1112 pil-reloc@94c { 1113 compatible = "qcom,pil-reloc-info"; 1114 reg = <0x94c 0xc8>; 1115 }; 1116 }; 1117 }; 1118 1119 thermal-zones { 1120 aoss0-thermal { 1121 polling-delay-passive = <250>; 1122 polling-delay = <1000>; 1123 1124 thermal-sensors = <&tsens 0>; 1125 1126 trips { 1127 aoss0_alert0: trip-point0 { 1128 temperature = <75000>; 1129 hysteresis = <2000>; 1130 type = "hot"; 1131 }; 1132 }; 1133 }; 1134 1135 modem-thermal { 1136 polling-delay-passive = <250>; 1137 polling-delay = <1000>; 1138 1139 thermal-sensors = <&tsens 1>; 1140 trips { 1141 modem_alert0: trip-point0 { 1142 temperature = <75000>; 1143 hysteresis = <2000>; 1144 type = "hot"; 1145 }; 1146 }; 1147 }; 1148 1149 qdsp-thermal { 1150 polling-delay-passive = <250>; 1151 polling-delay = <1000>; 1152 1153 thermal-sensors = <&tsens 2>; 1154 trips { 1155 qdsp_alert0: trip-point0 { 1156 temperature = <75000>; 1157 hysteresis = <2000>; 1158 type = "hot"; 1159 }; 1160 }; 1161 }; 1162 1163 cam-isp-thermal { 1164 polling-delay-passive = <250>; 1165 polling-delay = <1000>; 1166 1167 thermal-sensors = <&tsens 3>; 1168 trips { 1169 cam_isp_alert0: trip-point0 { 1170 temperature = <75000>; 1171 hysteresis = <2000>; 1172 type = "hot"; 1173 }; 1174 }; 1175 }; 1176 1177 cpu4-thermal { 1178 polling-delay-passive = <250>; 1179 polling-delay = <1000>; 1180 thermal-sensors = <&tsens 4>; 1181 1182 trips { 1183 cpu4_alert0: trip-point0 { 1184 temperature = <50000>; 1185 hysteresis = <2000>; 1186 type = "hot"; 1187 }; 1188 cpu4_alert1: trip-point1 { 1189 temperature = <55000>; 1190 hysteresis = <2000>; 1191 type = "passive"; 1192 }; 1193 cpu4_crit: cpu-crit { 1194 temperature = <75000>; 1195 hysteresis = <2000>; 1196 type = "critical"; 1197 }; 1198 }; 1199 }; 1200 1201 cpu5-thermal { 1202 polling-delay-passive = <250>; 1203 polling-delay = <1000>; 1204 thermal-sensors = <&tsens 5>; 1205 1206 trips { 1207 cpu5_alert0: trip-point0 { 1208 temperature = <50000>; 1209 hysteresis = <2000>; 1210 type = "hot"; 1211 }; 1212 cpu5_alert1: trip-point1 { 1213 temperature = <55000>; 1214 hysteresis = <2000>; 1215 type = "passive"; 1216 }; 1217 cpu5_crit: cpu-crit { 1218 temperature = <75000>; 1219 hysteresis = <2000>; 1220 type = "critical"; 1221 }; 1222 }; 1223 }; 1224 1225 cpu6-thermal { 1226 polling-delay-passive = <250>; 1227 polling-delay = <1000>; 1228 thermal-sensors = <&tsens 6>; 1229 1230 trips { 1231 cpu6_alert0: trip-point0 { 1232 temperature = <50000>; 1233 hysteresis = <2000>; 1234 type = "hot"; 1235 }; 1236 cpu6_alert1: trip-point1 { 1237 temperature = <55000>; 1238 hysteresis = <2000>; 1239 type = "passive"; 1240 }; 1241 cpu6_crit: cpu-crit { 1242 temperature = <75000>; 1243 hysteresis = <2000>; 1244 type = "critical"; 1245 }; 1246 }; 1247 }; 1248 1249 cpu7-thermal { 1250 polling-delay-passive = <250>; 1251 polling-delay = <1000>; 1252 thermal-sensors = <&tsens 7>; 1253 1254 trips { 1255 cpu7_alert0: trip-point0 { 1256 temperature = <50000>; 1257 hysteresis = <2000>; 1258 type = "hot"; 1259 }; 1260 cpu7_alert1: trip-point1 { 1261 temperature = <55000>; 1262 hysteresis = <2000>; 1263 type = "passive"; 1264 }; 1265 cpu7_crit: cpu-crit { 1266 temperature = <75000>; 1267 hysteresis = <2000>; 1268 type = "critical"; 1269 }; 1270 }; 1271 }; 1272 1273 big-l2-thermal { 1274 polling-delay-passive = <250>; 1275 polling-delay = <1000>; 1276 thermal-sensors = <&tsens 8>; 1277 1278 trips { 1279 l2_alert0: trip-point0 { 1280 temperature = <50000>; 1281 hysteresis = <2000>; 1282 type = "hot"; 1283 }; 1284 l2_alert1: trip-point1 { 1285 temperature = <55000>; 1286 hysteresis = <2000>; 1287 type = "passive"; 1288 }; 1289 l2_crit: l2-crit { 1290 temperature = <75000>; 1291 hysteresis = <2000>; 1292 type = "critical"; 1293 }; 1294 }; 1295 }; 1296 1297 cpu0-thermal { 1298 polling-delay-passive = <250>; 1299 polling-delay = <1000>; 1300 thermal-sensors = <&tsens 9>; 1301 1302 trips { 1303 cpu0_alert0: trip-point0 { 1304 temperature = <50000>; 1305 hysteresis = <2000>; 1306 type = "hot"; 1307 }; 1308 cpu0_alert1: trip-point1 { 1309 temperature = <55000>; 1310 hysteresis = <2000>; 1311 type = "passive"; 1312 }; 1313 cpu0_crit: cpu-crit { 1314 temperature = <75000>; 1315 hysteresis = <2000>; 1316 type = "critical"; 1317 }; 1318 }; 1319 }; 1320 1321 gpu-thermal { 1322 polling-delay-passive = <250>; 1323 polling-delay = <1000>; 1324 thermal-sensors = <&tsens 10>; 1325 1326 trips { 1327 gpu_alert0: trip-point0 { 1328 temperature = <50000>; 1329 hysteresis = <2000>; 1330 type = "hot"; 1331 }; 1332 gpu_alert1: trip-point1 { 1333 temperature = <55000>; 1334 hysteresis = <2000>; 1335 type = "passive"; 1336 }; 1337 gpu_crit: gpu-crit { 1338 temperature = <75000>; 1339 hysteresis = <2000>; 1340 type = "critical"; 1341 }; 1342 }; 1343 }; 1344 }; 1345 1346 timer { 1347 compatible = "arm,armv8-timer"; 1348 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1349 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1350 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1351 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1352 clock-frequency = <19200000>; 1353 }; 1354}; 1355