1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-msm8976.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 CPU0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a53"; 30 reg = <0x0>; 31 enable-method = "psci"; 32 cpu-idle-states = <&little_cpu_sleep_0>; 33 capacity-dmips-mhz = <573>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 }; 37 38 CPU1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x1>; 42 enable-method = "psci"; 43 cpu-idle-states = <&little_cpu_sleep_0>; 44 capacity-dmips-mhz = <573>; 45 next-level-cache = <&l2_0>; 46 #cooling-cells = <2>; 47 }; 48 49 CPU2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x2>; 53 enable-method = "psci"; 54 cpu-idle-states = <&little_cpu_sleep_0>; 55 capacity-dmips-mhz = <573>; 56 next-level-cache = <&l2_0>; 57 #cooling-cells = <2>; 58 }; 59 60 CPU3: cpu@3 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x3>; 64 enable-method = "psci"; 65 cpu-idle-states = <&little_cpu_sleep_0>; 66 capacity-dmips-mhz = <573>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 CPU4: cpu@100 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a72"; 74 reg = <0x100>; 75 enable-method = "psci"; 76 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 77 capacity-dmips-mhz = <1024>; 78 next-level-cache = <&l2_1>; 79 #cooling-cells = <2>; 80 }; 81 82 CPU5: cpu@101 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a72"; 85 reg = <0x101>; 86 enable-method = "psci"; 87 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 88 capacity-dmips-mhz = <1024>; 89 next-level-cache = <&l2_1>; 90 #cooling-cells = <2>; 91 }; 92 93 CPU6: cpu@102 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a72"; 96 reg = <0x102>; 97 enable-method = "psci"; 98 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 99 capacity-dmips-mhz = <1024>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 CPU7: cpu@103 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a72"; 107 reg = <0x103>; 108 enable-method = "psci"; 109 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 110 capacity-dmips-mhz = <1024>; 111 next-level-cache = <&l2_1>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu-map { 116 cluster0 { 117 core0 { 118 cpu = <&CPU0>; 119 }; 120 121 core1 { 122 cpu = <&CPU1>; 123 }; 124 125 core2 { 126 cpu = <&CPU2>; 127 }; 128 129 core3 { 130 cpu = <&CPU3>; 131 }; 132 }; 133 134 cluster1 { 135 core0 { 136 cpu = <&CPU4>; 137 }; 138 139 core1 { 140 cpu = <&CPU5>; 141 }; 142 143 core2 { 144 cpu = <&CPU6>; 145 }; 146 147 core3 { 148 cpu = <&CPU7>; 149 }; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 little_cpu_sleep_0: cpu-sleep-0-0 { 157 compatible = "arm,idle-state"; 158 idle-state-name = "little-power-collapse"; 159 arm,psci-suspend-param = <0x40000003>; 160 entry-latency-us = <181>; 161 exit-latency-us = <149>; 162 min-residency-us = <703>; 163 local-timer-stop; 164 }; 165 166 big_cpu_sleep_0: cpu-sleep-1-0 { 167 compatible = "arm,idle-state"; 168 idle-state-name = "big-retention"; 169 arm,psci-suspend-param = <0x00000002>; 170 entry-latency-us = <142>; 171 exit-latency-us = <99>; 172 min-residency-us = <242>; 173 }; 174 175 big_cpu_sleep_1: cpu-sleep-1-1 { 176 compatible = "arm,idle-state"; 177 idle-state-name = "big-power-collapse"; 178 arm,psci-suspend-param = <0x40000003>; 179 entry-latency-us = <158>; 180 exit-latency-us = <144>; 181 min-residency-us = <863>; 182 local-timer-stop; 183 }; 184 }; 185 186 l2_0: l2-cache0 { 187 compatible = "cache"; 188 cache-level = <2>; 189 }; 190 191 l2_1: l2-cache1 { 192 compatible = "cache"; 193 cache-level = <2>; 194 }; 195 }; 196 197 firmware { 198 scm: scm { 199 compatible = "qcom,scm-msm8976", "qcom,scm"; 200 clocks = <&gcc GCC_CRYPTO_CLK>, 201 <&gcc GCC_CRYPTO_AXI_CLK>, 202 <&gcc GCC_CRYPTO_AHB_CLK>; 203 clock-names = "core", "bus", "iface"; 204 #reset-cells = <1>; 205 206 qcom,dload-mode = <&tcsr 0x6100>; 207 }; 208 }; 209 210 memory@80000000 { 211 device_type = "memory"; 212 /* We expect the bootloader to fill in the size */ 213 reg = <0x0 0x80000000 0x0 0x0>; 214 }; 215 216 pmu: pmu { 217 compatible = "arm,armv8-pmuv3"; 218 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 reserved-memory { 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges; 230 231 ext-region@85b00000 { 232 reg = <0x0 0x85b00000 0x0 0x500000>; 233 no-map; 234 }; 235 236 smem@86300000 { 237 compatible = "qcom,smem"; 238 reg = <0x0 0x86300000 0x0 0x100000>; 239 no-map; 240 241 hwlocks = <&tcsr_mutex 3>; 242 qcom,rpm-msg-ram = <&rpm_msg_ram>; 243 }; 244 245 reserved@86400000 { 246 reg = <0x0 0x86400000 0x0 0x800000>; 247 no-map; 248 }; 249 250 mpss_mem: mpss@86c00000 { 251 reg = <0x0 0x86c00000 0x0 0x5600000>; 252 no-map; 253 }; 254 255 lpass_mem: lpass@8c200000 { 256 reg = <0x0 0x8c200000 0x0 0x1800000>; 257 no-map; 258 }; 259 260 venus_mem: memory@8da00000 { 261 reg = <0x0 0x8da00000 0x0 0x2600000>; 262 no-map; 263 }; 264 265 tz-apps@8dd00000 { 266 reg = <0x0 0x8dd00000 0x0 0x1400000>; 267 no-map; 268 }; 269 }; 270 271 smp2p-hexagon { 272 compatible = "qcom,smp2p"; 273 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 274 qcom,ipc = <&apcs 8 10>; 275 276 qcom,local-pid = <0>; 277 qcom,remote-pid = <2>; 278 qcom,smem = <443>, <429>; 279 280 adsp_smp2p_out: master-kernel { 281 qcom,entry-name = "master-kernel"; 282 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 adsp_smp2p_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smp2p-modem { 295 compatible = "qcom,smp2p"; 296 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 297 qcom,ipc = <&apcs 8 13>; 298 299 qcom,local-pid = <0>; 300 qcom,remote-pid = <1>; 301 qcom,smem = <435>, <428>; 302 303 modem_smp2p_out: master-kernel { 304 qcom,entry-name = "master-kernel"; 305 306 #qcom,smem-state-cells = <1>; 307 }; 308 309 modem_smp2p_in: slave-kernel { 310 qcom,entry-name = "slave-kernel"; 311 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 }; 316 317 smp2p-wcnss { 318 compatible = "qcom,smp2p"; 319 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 320 qcom,ipc = <&apcs 8 17>; 321 322 qcom,local-pid = <0>; 323 qcom,remote-pid = <4>; 324 qcom,smem = <451>, <431>; 325 326 wcnss_smp2p_out: master-kernel { 327 qcom,entry-name = "master-kernel"; 328 329 #qcom,smem-state-cells = <1>; 330 }; 331 332 wcnss_smp2p_in: slave-kernel { 333 qcom,entry-name = "slave-kernel"; 334 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 }; 339 340 smd { 341 compatible = "qcom,smd"; 342 343 rpm { 344 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 345 qcom,ipc = <&apcs 8 0>; 346 qcom,smd-edge = <15>; 347 348 rpm_requests: rpm-requests { 349 compatible = "qcom,rpm-msm8976"; 350 qcom,smd-channels = "rpm_requests"; 351 352 rpmcc: clock-controller { 353 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 354 #clock-cells = <1>; 355 }; 356 357 rpmpd: power-controller { 358 compatible = "qcom,msm8976-rpmpd"; 359 #power-domain-cells = <1>; 360 operating-points-v2 = <&rpmpd_opp_table>; 361 362 rpmpd_opp_table: opp-table { 363 compatible = "operating-points-v2"; 364 365 rpmpd_opp_ret: opp1 { 366 opp-level = <RPM_SMD_LEVEL_RETENTION>; 367 }; 368 369 rpmpd_opp_ret_plus: opp2 { 370 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 371 }; 372 373 rpmpd_opp_min_svs: opp3 { 374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 375 }; 376 377 rpmpd_opp_low_svs: opp4 { 378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 379 }; 380 381 rpmpd_opp_svs: opp5 { 382 opp-level = <RPM_SMD_LEVEL_SVS>; 383 }; 384 385 rpmpd_opp_svs_plus: opp6 { 386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 387 }; 388 389 rpmpd_opp_nom: opp7 { 390 opp-level = <RPM_SMD_LEVEL_NOM>; 391 }; 392 393 rpmpd_opp_nom_plus: opp8 { 394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 395 }; 396 397 rpmpd_opp_turbo: opp9 { 398 opp-level = <RPM_SMD_LEVEL_TURBO>; 399 }; 400 401 rpmpd_opp_turbo_no_cpr: opp10 { 402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 403 }; 404 405 rpmpd_opp_turbo_high: opp111 { 406 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 407 }; 408 }; 409 }; 410 }; 411 }; 412 }; 413 414 smsm { 415 compatible = "qcom,smsm"; 416 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 qcom,ipc-1 = <&apcs 8 12>; 421 qcom,ipc-2 = <&apcs 8 9>; 422 qcom,ipc-3 = <&apcs 8 18>; 423 424 apps_smsm: apps@0 { 425 reg = <0>; 426 #qcom,smem-state-cells = <1>; 427 }; 428 429 hexagon_smsm: hexagon@1 { 430 reg = <1>; 431 interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 437 wcnss_smsm: wcnss@6 { 438 reg = <6>; 439 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 440 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 }; 445 446 soc: soc@0 { 447 #address-cells = <1>; 448 #size-cells = <1>; 449 ranges = <0 0 0 0xffffffff>; 450 compatible = "simple-bus"; 451 452 rng@22000 { 453 compatible = "qcom,prng"; 454 reg = <0x00022000 0x140>; 455 clocks = <&gcc GCC_PRNG_AHB_CLK>; 456 clock-names = "core"; 457 }; 458 459 rpm_msg_ram: sram@60000 { 460 compatible = "qcom,rpm-msg-ram"; 461 reg = <0x00060000 0x8000>; 462 }; 463 464 usb_hs_phy: phy@6c000 { 465 compatible = "qcom,usb-hs-28nm-femtophy"; 466 reg = <0x0006c000 0x200>; 467 #phy-cells = <0>; 468 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 469 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 470 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 471 clock-names = "ref", "ahb", "sleep"; 472 resets = <&gcc RST_QUSB2_PHY_BCR>, 473 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 474 reset-names = "phy", "por"; 475 status = "disabled"; 476 }; 477 478 qfprom: qfprom@a4000 { 479 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 480 reg = <0x000a4000 0x1000>; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 484 tsens_caldata: caldata@218 { 485 reg = <0x218 0x18>; 486 }; 487 }; 488 489 tsens: thermal-sensor@4a9000 { 490 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 491 reg = <0x004a9000 0x1000>, /* TM */ 492 <0x004a8000 0x1000>; /* SROT */ 493 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "uplow"; 495 nvmem-cells = <&tsens_caldata>; 496 nvmem-cell-names = "calib"; 497 #qcom,sensors = <11>; 498 #thermal-sensor-cells = <1>; 499 }; 500 501 tlmm: pinctrl@1000000 { 502 compatible = "qcom,msm8976-pinctrl"; 503 reg = <0x01000000 0x300000>; 504 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 505 #gpio-cells = <2>; 506 gpio-controller; 507 gpio-ranges = <&tlmm 0 0 145>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 511 spi1_default: spi0-default-state { 512 spi-pins { 513 pins = "gpio0", "gpio1", "gpio3"; 514 function = "blsp_spi1"; 515 drive-strength = <12>; 516 bias-disable; 517 }; 518 519 cs-pins { 520 pins = "gpio2"; 521 function = "blsp_spi1"; 522 drive-strength = <2>; 523 bias-disable; 524 }; 525 }; 526 527 spi1_sleep: spi0-sleep-state { 528 spi-pins { 529 pins = "gpio0", "gpio1", "gpio3"; 530 function = "gpio"; 531 drive-strength = <2>; 532 bias-pull-down; 533 }; 534 535 cs-pins { 536 pins = "gpio2"; 537 function = "gpio"; 538 drive-strength = <2>; 539 bias-disable; 540 }; 541 }; 542 543 blsp1_i2c2_default: blsp1-i2c2-default-state { 544 pins = "gpio6", "gpio7"; 545 function = "blsp_i2c2"; 546 drive-strength = <2>; 547 bias-disable; 548 }; 549 550 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 551 pins = "gpio6", "gpio7"; 552 function = "gpio"; 553 drive-strength = <2>; 554 bias-disable; 555 }; 556 557 blsp1_i2c4_default: blsp1-i2c4-default-state { 558 pins = "gpio14", "gpio15"; 559 function = "blsp_i2c4"; 560 drive-strength = <2>; 561 bias-disable; 562 }; 563 564 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 565 pins = "gpio14", "gpio15"; 566 function = "gpio"; 567 drive-strength = <2>; 568 bias-disable; 569 }; 570 571 blsp2_uart2_active: blsp2-uart2-active-state { 572 pins = "gpio20", "gpio21"; 573 function = "blsp_uart6"; 574 drive-strength = <4>; 575 bias-disable; 576 }; 577 578 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 579 pins = "gpio20", "gpio21"; 580 function = "gpio"; 581 drive-strength = <2>; 582 bias-disable; 583 }; 584 585 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 586 blsp2_i2c2_default: blsp2-i2c2-default-state { 587 pins = "gpio22", "gpio23"; 588 function = "blsp_i2c6"; 589 drive-strength = <2>; 590 bias-disable; 591 }; 592 593 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 594 pins = "gpio22", "gpio23"; 595 function = "gpio"; 596 drive-strength = <2>; 597 bias-disable; 598 }; 599 600 blsp2_i2c4_default: blsp2-i2c4-default-state { 601 pins = "gpio18", "gpio19"; 602 function = "blsp_i2c8"; 603 drive-strength = <2>; 604 bias-disable; 605 }; 606 607 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 608 pins = "gpio18", "gpio19"; 609 function = "gpio"; 610 drive-strength = <2>; 611 bias-disable; 612 }; 613 }; 614 615 gcc: clock-controller@1800000 { 616 compatible = "qcom,gcc-msm8976"; 617 reg = <0x01800000 0x80000>; 618 #clock-cells = <1>; 619 #reset-cells = <1>; 620 #power-domain-cells = <1>; 621 622 assigned-clocks = <&gcc GPLL3>; 623 assigned-clock-rates = <1100000000>; 624 625 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 626 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 627 <0>, 628 <0>, 629 <0>, 630 <0>; 631 clock-names = "xo", 632 "xo_a", 633 "dsi0pll", 634 "dsi0pllbyte", 635 "dsi1pll", 636 "dsi1pllbyte"; 637 }; 638 639 tcsr_mutex: hwlock@1905000 { 640 compatible = "qcom,tcsr-mutex"; 641 reg = <0x01905000 0x20000>; 642 #hwlock-cells = <1>; 643 }; 644 645 tcsr: syscon@1937000 { 646 compatible = "qcom,msm8976-tcsr", "syscon"; 647 reg = <0x01937000 0x30000>; 648 }; 649 650 spmi_bus: spmi@200f000 { 651 compatible = "qcom,spmi-pmic-arb"; 652 reg = <0x0200f000 0x1000>, 653 <0x02400000 0x800000>, 654 <0x02c00000 0x800000>, 655 <0x03800000 0x200000>, 656 <0x0200a000 0x2100>; 657 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 658 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "periph_irq"; 660 qcom,channel = <0>; 661 qcom,ee = <0>; 662 663 #address-cells = <2>; 664 #size-cells = <0>; 665 interrupt-controller; 666 #interrupt-cells = <4>; 667 cell-index = <0>; 668 }; 669 670 sdhc_1: mmc@7824000 { 671 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 672 reg = <0x07824900 0x500>, <0x07824000 0x800>; 673 reg-names = "hc", "core"; 674 675 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 677 interrupt-names = "hc_irq", "pwr_irq"; 678 679 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 680 <&gcc GCC_SDCC1_APPS_CLK>, 681 <&rpmcc RPM_SMD_XO_CLK_SRC>; 682 clock-names = "iface", "core", "xo"; 683 status = "disabled"; 684 }; 685 686 sdhc_2: mmc@7864000 { 687 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 688 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 689 reg-names = "hc", "core"; 690 691 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 693 interrupt-names = "hc_irq", "pwr_irq"; 694 695 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 696 <&gcc GCC_SDCC2_APPS_CLK>, 697 <&rpmcc RPM_SMD_XO_CLK_SRC>; 698 clock-names = "iface", "core", "xo"; 699 status = "disabled"; 700 }; 701 702 blsp1_dma: dma-controller@7884000 { 703 compatible = "qcom,bam-v1.7.0"; 704 reg = <0x07884000 0x1f000>; 705 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 707 clock-names = "bam_clk"; 708 #dma-cells = <1>; 709 qcom,ee = <0>; 710 }; 711 712 blsp1_uart1: serial@78af000 { 713 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 714 reg = <0x078af000 0x200>; 715 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 717 clock-names = "core", "iface"; 718 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 719 dma-names = "tx", "rx"; 720 status = "disabled"; 721 }; 722 723 blsp1_uart2: serial@78b0000 { 724 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 725 reg = <0x078b0000 0x200>; 726 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 728 clock-names = "core", "iface"; 729 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 730 dma-names = "tx", "rx"; 731 status = "disabled"; 732 }; 733 734 blsp1_spi1: spi@78b5000 { 735 compatible = "qcom,spi-qup-v2.2.1"; 736 reg = <0x078b5000 0x500>; 737 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 739 clock-names = "core", "iface"; 740 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 741 dma-names = "tx", "rx"; 742 pinctrl-names = "default", "sleep"; 743 pinctrl-0 = <&spi1_default>; 744 pinctrl-1 = <&spi1_sleep>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 blsp1_i2c2: i2c@78b6000 { 751 compatible = "qcom,i2c-qup-v2.2.1"; 752 reg = <0x078b6000 0x500>; 753 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 755 clock-names = "core", "iface"; 756 clock-frequency = <400000>; 757 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 758 dma-names = "tx", "rx"; 759 pinctrl-names = "default", "sleep"; 760 pinctrl-0 = <&blsp1_i2c2_default>; 761 pinctrl-1 = <&blsp1_i2c2_default>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 blsp1_i2c4: i2c@78b8000 { 768 compatible = "qcom,i2c-qup-v2.2.1"; 769 reg = <0x078b8000 0x500>; 770 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 772 clock-names = "core", "iface"; 773 clock-frequency = <400000>; 774 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 775 dma-names = "tx", "rx"; 776 pinctrl-names = "default", "sleep"; 777 pinctrl-0 = <&blsp1_i2c4_default>; 778 pinctrl-1 = <&blsp1_i2c4_sleep>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 otg: usb@78db000 { 785 compatible = "qcom,ci-hdrc"; 786 reg = <0x078db000 0x200>, 787 <0x078db200 0x200>; 788 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 791 clock-names = "iface", "core"; 792 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 793 assigned-clock-rates = <80000000>; 794 resets = <&gcc RST_USB_HS_BCR>; 795 reset-names = "core"; 796 ahb-burst-config = <0>; 797 dr_mode = "peripheral"; 798 phy_type = "ulpi"; 799 phy-names = "usb-phy"; 800 phys = <&usb_hs_phy>; 801 status = "disabled"; 802 #reset-cells = <1>; 803 }; 804 805 sdhc_3: mmc@7a24000 { 806 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 807 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 808 reg-names = "hc", "core"; 809 810 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "hc_irq", "pwr_irq"; 813 814 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 815 <&gcc GCC_SDCC3_APPS_CLK>, 816 <&rpmcc RPM_SMD_XO_CLK_SRC>; 817 clock-names = "iface", "core", "xo"; 818 819 status = "disabled"; 820 }; 821 822 blsp2_dma: dma-controller@7ac4000 { 823 compatible = "qcom,bam-v1.7.0"; 824 reg = <0x07ac4000 0x1f000>; 825 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 827 clock-names = "bam_clk"; 828 #dma-cells = <1>; 829 qcom,ee = <0>; 830 }; 831 832 blsp2_uart2: serial@7af0000 { 833 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 834 reg = <0x07af0000 0x200>; 835 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 837 clock-names = "core", "iface"; 838 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 839 dma-names = "tx", "rx"; 840 status = "disabled"; 841 }; 842 843 blsp2_i2c2: i2c@7af6000 { 844 compatible = "qcom,i2c-qup-v2.2.1"; 845 reg = <0x07af6000 0x600>; 846 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 848 clock-names = "core", "iface"; 849 clock-frequency = <400000>; 850 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 851 dma-names = "tx", "rx"; 852 pinctrl-names = "default", "sleep"; 853 pinctrl-0 = <&blsp2_i2c2_default>; 854 pinctrl-1 = <&blsp2_i2c2_sleep>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 status = "disabled"; 858 }; 859 860 blsp2_i2c4: i2c@7af8000 { 861 compatible = "qcom,i2c-qup-v2.2.1"; 862 reg = <0x07af8000 0x600>; 863 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 865 clock-names = "core", "iface"; 866 clock-frequency = <400000>; 867 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 868 dma-names = "tx", "rx"; 869 pinctrl-names = "default", "sleep"; 870 pinctrl-0 = <&blsp2_i2c4_default>; 871 pinctrl-1 = <&blsp2_i2c4_sleep>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 intc: interrupt-controller@b000000 { 878 compatible = "qcom,msm-qgic2"; 879 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 880 interrupt-controller; 881 #interrupt-cells = <3>; 882 }; 883 884 apcs: mailbox@b011000 { 885 compatible = "qcom,msm8976-apcs-kpss-global", "syscon"; 886 reg = <0x0b011000 0x1000>; 887 #mbox-cells = <1>; 888 }; 889 890 timer@b120000 { 891 compatible = "arm,armv7-timer-mem"; 892 reg = <0x0b120000 0x1000>; 893 #address-cells = <1>; 894 #size-cells = <1>; 895 ranges; 896 clock-frequency = <19200000>; 897 898 frame@b121000 { 899 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 900 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 902 frame-number = <0>; 903 }; 904 905 frame@b123000 { 906 reg = <0x0b123000 0x1000>; 907 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 908 frame-number = <1>; 909 status = "disabled"; 910 }; 911 912 frame@b124000 { 913 reg = <0x0b124000 0x1000>; 914 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 915 frame-number = <2>; 916 status = "disabled"; 917 }; 918 919 frame@b125000 { 920 reg = <0x0b125000 0x1000>; 921 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 922 frame-number = <3>; 923 status = "disabled"; 924 }; 925 926 frame@b126000 { 927 reg = <0x0b126000 0x1000>; 928 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 929 frame-number = <4>; 930 status = "disabled"; 931 }; 932 933 frame@b127000 { 934 reg = <0x0b127000 0x1000>; 935 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 936 frame-number = <5>; 937 status = "disabled"; 938 }; 939 940 frame@b128000 { 941 reg = <0x0b128000 0x1000>; 942 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 943 frame-number = <6>; 944 status = "disabled"; 945 }; 946 }; 947 948 imem: sram@8600000 { 949 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 950 reg = <0x08600000 0x1000>; 951 #address-cells = <1>; 952 #size-cells = <1>; 953 954 ranges = <0 0x08600000 0x1000>; 955 956 pil-reloc@94c { 957 compatible = "qcom,pil-reloc-info"; 958 reg = <0x94c 0xc8>; 959 }; 960 }; 961 }; 962 963 thermal-zones { 964 aoss0-thermal { 965 polling-delay-passive = <250>; 966 polling-delay = <1000>; 967 968 thermal-sensors = <&tsens 0>; 969 970 trips { 971 aoss0_alert0: trip-point0 { 972 temperature = <75000>; 973 hysteresis = <2000>; 974 type = "hot"; 975 }; 976 }; 977 }; 978 979 modem-thermal { 980 polling-delay-passive = <250>; 981 polling-delay = <1000>; 982 983 thermal-sensors = <&tsens 1>; 984 trips { 985 modem_alert0: trip-point0 { 986 temperature = <75000>; 987 hysteresis = <2000>; 988 type = "hot"; 989 }; 990 }; 991 }; 992 993 qdsp-thermal { 994 polling-delay-passive = <250>; 995 polling-delay = <1000>; 996 997 thermal-sensors = <&tsens 2>; 998 trips { 999 qdsp_alert0: trip-point0 { 1000 temperature = <75000>; 1001 hysteresis = <2000>; 1002 type = "hot"; 1003 }; 1004 }; 1005 }; 1006 1007 cam-isp-thermal { 1008 polling-delay-passive = <250>; 1009 polling-delay = <1000>; 1010 1011 thermal-sensors = <&tsens 3>; 1012 trips { 1013 cam_isp_alert0: trip-point0 { 1014 temperature = <75000>; 1015 hysteresis = <2000>; 1016 type = "hot"; 1017 }; 1018 }; 1019 }; 1020 1021 cpu4-thermal { 1022 polling-delay-passive = <250>; 1023 polling-delay = <1000>; 1024 thermal-sensors = <&tsens 4>; 1025 1026 trips { 1027 cpu4_alert0: trip-point0 { 1028 temperature = <50000>; 1029 hysteresis = <2000>; 1030 type = "hot"; 1031 }; 1032 cpu4_alert1: trip-point1 { 1033 temperature = <55000>; 1034 hysteresis = <2000>; 1035 type = "passive"; 1036 }; 1037 cpu4_crit: cpu-crit { 1038 temperature = <75000>; 1039 hysteresis = <2000>; 1040 type = "critical"; 1041 }; 1042 }; 1043 }; 1044 1045 cpu5-thermal { 1046 polling-delay-passive = <250>; 1047 polling-delay = <1000>; 1048 thermal-sensors = <&tsens 5>; 1049 1050 trips { 1051 cpu5_alert0: trip-point0 { 1052 temperature = <50000>; 1053 hysteresis = <2000>; 1054 type = "hot"; 1055 }; 1056 cpu5_alert1: trip-point1 { 1057 temperature = <55000>; 1058 hysteresis = <2000>; 1059 type = "passive"; 1060 }; 1061 cpu5_crit: cpu-crit { 1062 temperature = <75000>; 1063 hysteresis = <2000>; 1064 type = "critical"; 1065 }; 1066 }; 1067 }; 1068 1069 cpu6-thermal { 1070 polling-delay-passive = <250>; 1071 polling-delay = <1000>; 1072 thermal-sensors = <&tsens 6>; 1073 1074 trips { 1075 cpu6_alert0: trip-point0 { 1076 temperature = <50000>; 1077 hysteresis = <2000>; 1078 type = "hot"; 1079 }; 1080 cpu6_alert1: trip-point1 { 1081 temperature = <55000>; 1082 hysteresis = <2000>; 1083 type = "passive"; 1084 }; 1085 cpu6_crit: cpu-crit { 1086 temperature = <75000>; 1087 hysteresis = <2000>; 1088 type = "critical"; 1089 }; 1090 }; 1091 }; 1092 1093 cpu7-thermal { 1094 polling-delay-passive = <250>; 1095 polling-delay = <1000>; 1096 thermal-sensors = <&tsens 7>; 1097 1098 trips { 1099 cpu7_alert0: trip-point0 { 1100 temperature = <50000>; 1101 hysteresis = <2000>; 1102 type = "hot"; 1103 }; 1104 cpu7_alert1: trip-point1 { 1105 temperature = <55000>; 1106 hysteresis = <2000>; 1107 type = "passive"; 1108 }; 1109 cpu7_crit: cpu-crit { 1110 temperature = <75000>; 1111 hysteresis = <2000>; 1112 type = "critical"; 1113 }; 1114 }; 1115 }; 1116 1117 big-l2-thermal { 1118 polling-delay-passive = <250>; 1119 polling-delay = <1000>; 1120 thermal-sensors = <&tsens 8>; 1121 1122 trips { 1123 l2_alert0: trip-point0 { 1124 temperature = <50000>; 1125 hysteresis = <2000>; 1126 type = "hot"; 1127 }; 1128 l2_alert1: trip-point1 { 1129 temperature = <55000>; 1130 hysteresis = <2000>; 1131 type = "passive"; 1132 }; 1133 l2_crit: l2-crit { 1134 temperature = <75000>; 1135 hysteresis = <2000>; 1136 type = "critical"; 1137 }; 1138 }; 1139 }; 1140 1141 cpu0-thermal { 1142 polling-delay-passive = <250>; 1143 polling-delay = <1000>; 1144 thermal-sensors = <&tsens 9>; 1145 1146 trips { 1147 cpu0_alert0: trip-point0 { 1148 temperature = <50000>; 1149 hysteresis = <2000>; 1150 type = "hot"; 1151 }; 1152 cpu0_alert1: trip-point1 { 1153 temperature = <55000>; 1154 hysteresis = <2000>; 1155 type = "passive"; 1156 }; 1157 cpu0_crit: cpu-crit { 1158 temperature = <75000>; 1159 hysteresis = <2000>; 1160 type = "critical"; 1161 }; 1162 }; 1163 }; 1164 1165 gpu-thermal { 1166 polling-delay-passive = <250>; 1167 polling-delay = <1000>; 1168 thermal-sensors = <&tsens 10>; 1169 1170 trips { 1171 gpu_alert0: trip-point0 { 1172 temperature = <50000>; 1173 hysteresis = <2000>; 1174 type = "hot"; 1175 }; 1176 gpu_alert1: trip-point1 { 1177 temperature = <55000>; 1178 hysteresis = <2000>; 1179 type = "passive"; 1180 }; 1181 gpu_crit: gpu-crit { 1182 temperature = <75000>; 1183 hysteresis = <2000>; 1184 type = "critical"; 1185 }; 1186 }; 1187 }; 1188 }; 1189 1190 timer { 1191 compatible = "arm,armv8-timer"; 1192 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1193 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1194 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1195 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1196 clock-frequency = <19200000>; 1197 }; 1198}; 1199