1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,gcc-msm8953.h> 5#include <dt-bindings/clock/qcom,rpmcc.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/soc/qcom,apr.h> 10#include <dt-bindings/sound/qcom,q6afe.h> 11#include <dt-bindings/sound/qcom,q6asm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 sleep_clk: sleep-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <32768>; 27 }; 28 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 clock-output-names = "xo"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 next-level-cache = <&L2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 CPU1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x1>; 55 enable-method = "psci"; 56 capacity-dmips-mhz = <1024>; 57 next-level-cache = <&L2_0>; 58 #cooling-cells = <2>; 59 }; 60 61 CPU2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x2>; 65 enable-method = "psci"; 66 capacity-dmips-mhz = <1024>; 67 next-level-cache = <&L2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 #cooling-cells = <2>; 79 }; 80 81 CPU4: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x100>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <1024>; 87 next-level-cache = <&L2_1>; 88 #cooling-cells = <2>; 89 }; 90 91 CPU5: cpu@101 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x101>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <1024>; 97 next-level-cache = <&L2_1>; 98 #cooling-cells = <2>; 99 }; 100 101 CPU6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x102>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&L2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1024>; 117 next-level-cache = <&L2_1>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu-map { 122 cluster0 { 123 core0 { 124 cpu = <&CPU0>; 125 }; 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 core2 { 130 cpu = <&CPU2>; 131 }; 132 core3 { 133 cpu = <&CPU3>; 134 }; 135 }; 136 137 cluster1 { 138 core0 { 139 cpu = <&CPU4>; 140 }; 141 core1 { 142 cpu = <&CPU5>; 143 }; 144 core2 { 145 cpu = <&CPU6>; 146 }; 147 core3 { 148 cpu = <&CPU7>; 149 }; 150 }; 151 }; 152 153 L2_0: l2-cache-0 { 154 compatible = "cache"; 155 cache-level = <2>; 156 }; 157 158 L2_1: l2-cache-1 { 159 compatible = "cache"; 160 cache-level = <2>; 161 }; 162 }; 163 164 firmware { 165 scm: scm { 166 compatible = "qcom,scm-msm8953", "qcom,scm"; 167 clocks = <&gcc GCC_CRYPTO_CLK>, 168 <&gcc GCC_CRYPTO_AXI_CLK>, 169 <&gcc GCC_CRYPTO_AHB_CLK>; 170 clock-names = "core", "bus", "iface"; 171 #reset-cells = <1>; 172 }; 173 }; 174 175 memory { 176 device_type = "memory"; 177 /* We expect the bootloader to fill in the reg */ 178 reg = <0 0 0 0>; 179 }; 180 181 pmu { 182 compatible = "arm,cortex-a53-pmu"; 183 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 184 }; 185 186 psci { 187 compatible = "arm,psci-1.0"; 188 method = "smc"; 189 }; 190 191 reserved-memory { 192 #address-cells = <2>; 193 #size-cells = <2>; 194 ranges; 195 196 zap_shader_region: zap@81800000 { 197 compatible = "shared-dma-pool"; 198 reg = <0x0 0x81800000 0x0 0x2000>; 199 no-map; 200 }; 201 202 qseecom_mem: qseecom@85b00000 { 203 reg = <0x0 0x85b00000 0x0 0x800000>; 204 no-map; 205 }; 206 207 smem_mem: smem@86300000 { 208 compatible = "qcom,smem"; 209 reg = <0x0 0x86300000 0x0 0x100000>; 210 qcom,rpm-msg-ram = <&rpm_msg_ram>; 211 hwlocks = <&tcsr_mutex 3>; 212 no-map; 213 }; 214 215 reserved@86400000 { 216 reg = <0x0 0x86400000 0x0 0x400000>; 217 no-map; 218 }; 219 220 mpss_mem: mpss@86c00000 { 221 reg = <0x0 0x86c00000 0x0 0x6a00000>; 222 no-map; 223 }; 224 225 adsp_fw_mem: adsp@8d600000 { 226 reg = <0x0 0x8d600000 0x0 0x1100000>; 227 no-map; 228 }; 229 230 wcnss_fw_mem: wcnss@8e700000 { 231 reg = <0x0 0x8e700000 0x0 0x700000>; 232 no-map; 233 }; 234 235 dfps_data_mem: dfps-data@90000000 { 236 reg = <0 0x90000000 0 0x1000>; 237 no-map; 238 }; 239 240 cont_splash_mem: cont-splash@90001000 { 241 reg = <0x0 0x90001000 0x0 0x13ff000>; 242 no-map; 243 }; 244 245 venus_mem: venus@91400000 { 246 reg = <0x0 0x91400000 0x0 0x700000>; 247 no-map; 248 }; 249 250 mba_mem: mba@92000000 { 251 reg = <0x0 0x92000000 0x0 0x100000>; 252 no-map; 253 }; 254 255 rmtfs@f2d00000 { 256 compatible = "qcom,rmtfs-mem"; 257 reg = <0x0 0xf2d00000 0x0 0x180000>; 258 no-map; 259 260 qcom,client-id = <1>; 261 }; 262 }; 263 264 smd { 265 compatible = "qcom,smd"; 266 267 rpm { 268 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 269 qcom,ipc = <&apcs 8 0>; 270 qcom,smd-edge = <15>; 271 272 rpm_requests: rpm-requests { 273 compatible = "qcom,rpm-msm8953"; 274 qcom,smd-channels = "rpm_requests"; 275 276 rpmcc: clock-controller { 277 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 278 clocks = <&xo_board>; 279 clock-names = "xo"; 280 #clock-cells = <1>; 281 }; 282 283 rpmpd: power-controller { 284 compatible = "qcom,msm8953-rpmpd"; 285 #power-domain-cells = <1>; 286 operating-points-v2 = <&rpmpd_opp_table>; 287 288 rpmpd_opp_table: opp-table { 289 compatible = "operating-points-v2"; 290 291 rpmpd_opp_ret: opp1 { 292 opp-level = <RPM_SMD_LEVEL_RETENTION>; 293 }; 294 295 rpmpd_opp_ret_plus: opp2 { 296 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 297 }; 298 299 rpmpd_opp_min_svs: opp3 { 300 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 301 }; 302 303 rpmpd_opp_low_svs: opp4 { 304 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 305 }; 306 307 rpmpd_opp_svs: opp5 { 308 opp-level = <RPM_SMD_LEVEL_SVS>; 309 }; 310 311 rpmpd_opp_svs_plus: opp6 { 312 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 313 }; 314 315 rpmpd_opp_nom: opp7 { 316 opp-level = <RPM_SMD_LEVEL_NOM>; 317 }; 318 319 rpmpd_opp_nom_plus: opp8 { 320 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 321 }; 322 323 rpmpd_opp_turbo: opp9 { 324 opp-level = <RPM_SMD_LEVEL_TURBO>; 325 }; 326 }; 327 }; 328 }; 329 }; 330 }; 331 332 smp2p-adsp { 333 compatible = "qcom,smp2p"; 334 qcom,smem = <443>, <429>; 335 336 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 337 338 mboxes = <&apcs 10>; 339 340 qcom,local-pid = <0>; 341 qcom,remote-pid = <2>; 342 343 smp2p_adsp_out: master-kernel { 344 qcom,entry-name = "master-kernel"; 345 #qcom,smem-state-cells = <1>; 346 }; 347 348 smp2p_adsp_in: slave-kernel { 349 qcom,entry-name = "slave-kernel"; 350 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 }; 354 }; 355 356 smp2p-modem { 357 compatible = "qcom,smp2p"; 358 qcom,smem = <435>, <428>; 359 360 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 361 362 qcom,ipc = <&apcs 8 14>; 363 364 qcom,local-pid = <0>; 365 qcom,remote-pid = <1>; 366 367 smp2p_modem_out: master-kernel { 368 qcom,entry-name = "master-kernel"; 369 370 #qcom,smem-state-cells = <1>; 371 }; 372 373 smp2p_modem_in: slave-kernel { 374 qcom,entry-name = "slave-kernel"; 375 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 }; 380 381 smp2p-wcnss { 382 compatible = "qcom,smp2p"; 383 qcom,smem = <451>, <431>; 384 385 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 386 387 qcom,ipc = <&apcs 8 18>; 388 389 qcom,local-pid = <0>; 390 qcom,remote-pid = <4>; 391 392 smp2p_wcnss_out: master-kernel { 393 qcom,entry-name = "master-kernel"; 394 395 #qcom,smem-state-cells = <1>; 396 }; 397 398 smp2p_wcnss_in: slave-kernel { 399 qcom,entry-name = "slave-kernel"; 400 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 }; 404 }; 405 406 smsm { 407 compatible = "qcom,smsm"; 408 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412 qcom,ipc-1 = <&apcs 8 13>; 413 qcom,ipc-3 = <&apcs 8 19>; 414 415 apps_smsm: apps@0 { 416 reg = <0>; 417 418 #qcom,smem-state-cells = <1>; 419 }; 420 421 modem_smsm: modem@1 { 422 reg = <1>; 423 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 424 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 }; 428 429 wcnss_smsm: wcnss@6 { 430 reg = <6>; 431 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0 0 0 0xffffffff>; 442 compatible = "simple-bus"; 443 444 rpm_msg_ram: sram@60000 { 445 compatible = "qcom,rpm-msg-ram"; 446 reg = <0x00060000 0x8000>; 447 }; 448 449 hsusb_phy: phy@79000 { 450 compatible = "qcom,msm8953-qusb2-phy"; 451 reg = <0x00079000 0x180>; 452 #phy-cells = <0>; 453 454 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 455 <&gcc GCC_QUSB_REF_CLK>; 456 clock-names = "cfg_ahb", "ref"; 457 458 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 459 460 resets = <&gcc GCC_QUSB2_PHY_BCR>; 461 462 status = "disabled"; 463 }; 464 465 rng@e3000 { 466 compatible = "qcom,prng"; 467 reg = <0x000e3000 0x1000>; 468 clocks = <&gcc GCC_PRNG_AHB_CLK>; 469 clock-names = "core"; 470 }; 471 472 tsens0: thermal-sensor@4a9000 { 473 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 474 reg = <0x004a9000 0x1000>, /* TM */ 475 <0x004a8000 0x1000>; /* SROT */ 476 #qcom,sensors = <16>; 477 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "uplow", "critical"; 480 #thermal-sensor-cells = <1>; 481 }; 482 483 restart@4ab000 { 484 compatible = "qcom,pshold"; 485 reg = <0x004ab000 0x4>; 486 }; 487 488 tlmm: pinctrl@1000000 { 489 compatible = "qcom,msm8953-pinctrl"; 490 reg = <0x01000000 0x300000>; 491 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 492 gpio-controller; 493 gpio-ranges = <&tlmm 0 0 142>; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 498 uart_console_active: uart-console-active-state { 499 pins = "gpio4", "gpio5"; 500 function = "blsp_uart2"; 501 drive-strength = <2>; 502 bias-disable; 503 }; 504 505 uart_console_sleep: uart-console-sleep-state { 506 pins = "gpio4", "gpio5"; 507 function = "blsp_uart2"; 508 drive-strength = <2>; 509 bias-pull-down; 510 }; 511 512 sdc1_clk_on: sdc1-clk-on-state { 513 pins = "sdc1_clk"; 514 bias-disable; 515 drive-strength = <16>; 516 }; 517 518 sdc1_clk_off: sdc1-clk-off-state { 519 pins = "sdc1_clk"; 520 bias-disable; 521 drive-strength = <2>; 522 }; 523 524 sdc1_cmd_on: sdc1-cmd-on-state { 525 pins = "sdc1_cmd"; 526 bias-disable; 527 drive-strength = <10>; 528 }; 529 530 sdc1_cmd_off: sdc1-cmd-off-state { 531 pins = "sdc1_cmd"; 532 bias-disable; 533 drive-strength = <2>; 534 }; 535 536 sdc1_data_on: sdc1-data-on-state { 537 pins = "sdc1_data"; 538 bias-pull-up; 539 drive-strength = <10>; 540 }; 541 542 sdc1_data_off: sdc1-data-off-state { 543 pins = "sdc1_data"; 544 bias-pull-up; 545 drive-strength = <2>; 546 }; 547 548 sdc1_rclk_on: sdc1-rclk-on-state { 549 pins = "sdc1_rclk"; 550 bias-pull-down; 551 }; 552 553 sdc1_rclk_off: sdc1-rclk-off-state { 554 pins = "sdc1_rclk"; 555 bias-pull-down; 556 }; 557 558 sdc2_clk_on: sdc2-clk-on-state { 559 pins = "sdc2_clk"; 560 drive-strength = <16>; 561 bias-disable; 562 }; 563 564 sdc2_clk_off: sdc2-clk-off-state { 565 pins = "sdc2_clk"; 566 bias-disable; 567 drive-strength = <2>; 568 }; 569 570 sdc2_cmd_on: sdc2-cmd-on-state { 571 pins = "sdc2_cmd"; 572 bias-pull-up; 573 drive-strength = <10>; 574 }; 575 576 sdc2_cmd_off: sdc2-cmd-off-state { 577 pins = "sdc2_cmd"; 578 bias-pull-up; 579 drive-strength = <2>; 580 }; 581 582 sdc2_data_on: sdc2-data-on-state { 583 pins = "sdc2_data"; 584 bias-pull-up; 585 drive-strength = <10>; 586 }; 587 588 sdc2_data_off: sdc2-data-off-state { 589 pins = "sdc2_data"; 590 bias-pull-up; 591 drive-strength = <2>; 592 }; 593 594 sdc2_cd_on: cd-on-state { 595 pins = "gpio133"; 596 function = "gpio"; 597 drive-strength = <2>; 598 bias-pull-up; 599 }; 600 601 sdc2_cd_off: cd-off-state { 602 pins = "gpio133"; 603 function = "gpio"; 604 drive-strength = <2>; 605 bias-disable; 606 }; 607 608 gpio_key_default: gpio-key-default-state { 609 pins = "gpio85"; 610 function = "gpio"; 611 drive-strength = <2>; 612 bias-pull-up; 613 }; 614 615 i2c_1_default: i2c-1-default-state { 616 pins = "gpio2", "gpio3"; 617 function = "blsp_i2c1"; 618 drive-strength = <2>; 619 bias-disable; 620 }; 621 622 i2c_1_sleep: i2c-1-sleep-state { 623 pins = "gpio2", "gpio3"; 624 function = "gpio"; 625 drive-strength = <2>; 626 bias-disable; 627 }; 628 629 i2c_2_default: i2c-2-default-state { 630 pins = "gpio6", "gpio7"; 631 function = "blsp_i2c2"; 632 drive-strength = <2>; 633 bias-disable; 634 }; 635 636 i2c_2_sleep: i2c-2-sleep-state { 637 pins = "gpio6", "gpio7"; 638 function = "gpio"; 639 drive-strength = <2>; 640 bias-disable; 641 }; 642 643 i2c_3_default: i2c-3-default-state { 644 pins = "gpio10", "gpio11"; 645 function = "blsp_i2c3"; 646 drive-strength = <2>; 647 bias-disable; 648 }; 649 650 i2c_3_sleep: i2c-3-sleep-state { 651 pins = "gpio10", "gpio11"; 652 function = "gpio"; 653 drive-strength = <2>; 654 bias-disable; 655 }; 656 657 i2c_4_default: i2c-4-default-state { 658 pins = "gpio14", "gpio15"; 659 function = "blsp_i2c4"; 660 drive-strength = <2>; 661 bias-disable; 662 }; 663 664 i2c_4_sleep: i2c-4-sleep-state { 665 pins = "gpio14", "gpio15"; 666 function = "gpio"; 667 drive-strength = <2>; 668 bias-disable; 669 }; 670 671 i2c_5_default: i2c-5-default-state { 672 pins = "gpio18", "gpio19"; 673 function = "blsp_i2c5"; 674 drive-strength = <2>; 675 bias-disable; 676 }; 677 678 i2c_5_sleep: i2c-5-sleep-state { 679 pins = "gpio18", "gpio19"; 680 function = "gpio"; 681 drive-strength = <2>; 682 bias-disable; 683 }; 684 685 i2c_6_default: i2c-6-default-state { 686 pins = "gpio22", "gpio23"; 687 function = "blsp_i2c6"; 688 drive-strength = <2>; 689 bias-disable; 690 }; 691 692 i2c_6_sleep: i2c-6-sleep-state { 693 pins = "gpio22", "gpio23"; 694 function = "gpio"; 695 drive-strength = <2>; 696 bias-disable; 697 }; 698 699 i2c_7_default: i2c-7-default-state { 700 pins = "gpio135", "gpio136"; 701 function = "blsp_i2c7"; 702 drive-strength = <2>; 703 bias-disable; 704 }; 705 706 i2c_7_sleep: i2c-7-sleep-state { 707 pins = "gpio135", "gpio136"; 708 function = "gpio"; 709 drive-strength = <2>; 710 bias-disable; 711 }; 712 713 i2c_8_default: i2c-8-default-state { 714 pins = "gpio98", "gpio99"; 715 function = "blsp_i2c8"; 716 drive-strength = <2>; 717 bias-disable; 718 }; 719 720 i2c_8_sleep: i2c-8-sleep-state { 721 pins = "gpio98", "gpio99"; 722 function = "gpio"; 723 drive-strength = <2>; 724 bias-disable; 725 }; 726 727 wcnss_pin_a: wcnss-active-state { 728 729 wcss-wlan2-pins { 730 pins = "gpio76"; 731 function = "wcss_wlan2"; 732 drive-strength = <6>; 733 bias-pull-up; 734 }; 735 736 wcss-wlan1-pins { 737 pins = "gpio77"; 738 function = "wcss_wlan1"; 739 drive-strength = <6>; 740 bias-pull-up; 741 }; 742 743 wcss-wlan0-pins { 744 pins = "gpio78"; 745 function = "wcss_wlan0"; 746 drive-strength = <6>; 747 bias-pull-up; 748 }; 749 750 wcss-wlan-pins { 751 pins = "gpio79", "gpio80"; 752 function = "wcss_wlan"; 753 drive-strength = <6>; 754 bias-pull-up; 755 }; 756 }; 757 }; 758 759 gcc: clock-controller@1800000 { 760 compatible = "qcom,gcc-msm8953"; 761 reg = <0x01800000 0x80000>; 762 #clock-cells = <1>; 763 #reset-cells = <1>; 764 #power-domain-cells = <1>; 765 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 766 <&sleep_clk>, 767 <&dsi0_phy 1>, 768 <&dsi0_phy 0>, 769 <&dsi1_phy 1>, 770 <&dsi1_phy 0>; 771 clock-names = "xo", 772 "sleep", 773 "dsi0pll", 774 "dsi0pllbyte", 775 "dsi1pll", 776 "dsi1pllbyte"; 777 }; 778 779 tcsr_mutex: hwlock@1905000 { 780 compatible = "qcom,tcsr-mutex"; 781 reg = <0x01905000 0x20000>; 782 #hwlock-cells = <1>; 783 }; 784 785 tcsr: syscon@1937000 { 786 compatible = "qcom,tcsr-msm8953", "syscon"; 787 reg = <0x01937000 0x30000>; 788 }; 789 790 tcsr_phy_clk_scheme_sel: syscon@193f044 { 791 compatible = "qcom,tcsr-msm8953", "syscon"; 792 reg = <0x0193f044 0x4>; 793 }; 794 795 mdss: display-subsystem@1a00000 { 796 compatible = "qcom,mdss"; 797 798 reg = <0x01a00000 0x1000>, 799 <0x01ab0000 0x1040>; 800 reg-names = "mdss_phys", 801 "vbif_phys"; 802 803 power-domains = <&gcc MDSS_GDSC>; 804 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 805 806 interrupt-controller; 807 #interrupt-cells = <1>; 808 809 clocks = <&gcc GCC_MDSS_AHB_CLK>, 810 <&gcc GCC_MDSS_AXI_CLK>, 811 <&gcc GCC_MDSS_VSYNC_CLK>, 812 <&gcc GCC_MDSS_MDP_CLK>; 813 clock-names = "iface", 814 "bus", 815 "vsync", 816 "core"; 817 818 #address-cells = <1>; 819 #size-cells = <1>; 820 ranges; 821 822 status = "disabled"; 823 824 mdp: display-controller@1a01000 { 825 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 826 reg = <0x01a01000 0x89000>; 827 reg-names = "mdp_phys"; 828 829 interrupt-parent = <&mdss>; 830 interrupts = <0>; 831 832 power-domains = <&gcc MDSS_GDSC>; 833 834 clocks = <&gcc GCC_MDSS_AHB_CLK>, 835 <&gcc GCC_MDSS_AXI_CLK>, 836 <&gcc GCC_MDSS_MDP_CLK>, 837 <&gcc GCC_MDSS_VSYNC_CLK>; 838 clock-names = "iface", 839 "bus", 840 "core", 841 "vsync"; 842 843 iommus = <&apps_iommu 0x15>; 844 845 ports { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 port@0 { 850 reg = <0>; 851 mdp5_intf1_out: endpoint { 852 remote-endpoint = <&dsi0_in>; 853 }; 854 }; 855 856 port@1 { 857 reg = <1>; 858 mdp5_intf2_out: endpoint { 859 remote-endpoint = <&dsi1_in>; 860 }; 861 }; 862 }; 863 }; 864 865 dsi0: dsi@1a94000 { 866 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 867 reg = <0x01a94000 0x400>; 868 reg-names = "dsi_ctrl"; 869 870 interrupt-parent = <&mdss>; 871 interrupts = <4>; 872 873 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 874 <&gcc PCLK0_CLK_SRC>; 875 assigned-clock-parents = <&dsi0_phy 0>, 876 <&dsi0_phy 1>; 877 878 clocks = <&gcc GCC_MDSS_MDP_CLK>, 879 <&gcc GCC_MDSS_AHB_CLK>, 880 <&gcc GCC_MDSS_AXI_CLK>, 881 <&gcc GCC_MDSS_BYTE0_CLK>, 882 <&gcc GCC_MDSS_PCLK0_CLK>, 883 <&gcc GCC_MDSS_ESC0_CLK>; 884 clock-names = "mdp_core", 885 "iface", 886 "bus", 887 "byte", 888 "pixel", 889 "core"; 890 891 phys = <&dsi0_phy>; 892 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 status = "disabled"; 897 898 ports { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 902 port@0 { 903 reg = <0>; 904 dsi0_in: endpoint { 905 remote-endpoint = <&mdp5_intf1_out>; 906 }; 907 }; 908 909 port@1 { 910 reg = <1>; 911 dsi0_out: endpoint { 912 }; 913 }; 914 }; 915 }; 916 917 dsi0_phy: phy@1a94400 { 918 compatible = "qcom,dsi-phy-14nm-8953"; 919 reg = <0x01a94400 0x100>, 920 <0x01a94500 0x300>, 921 <0x01a94800 0x188>; 922 reg-names = "dsi_phy", 923 "dsi_phy_lane", 924 "dsi_pll"; 925 926 #clock-cells = <1>; 927 #phy-cells = <0>; 928 929 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 930 clock-names = "iface", "ref"; 931 932 status = "disabled"; 933 }; 934 935 dsi1: dsi@1a96000 { 936 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 937 reg = <0x01a96000 0x400>; 938 reg-names = "dsi_ctrl"; 939 940 interrupt-parent = <&mdss>; 941 interrupts = <5>; 942 943 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 944 <&gcc PCLK1_CLK_SRC>; 945 assigned-clock-parents = <&dsi1_phy 0>, 946 <&dsi1_phy 1>; 947 948 clocks = <&gcc GCC_MDSS_MDP_CLK>, 949 <&gcc GCC_MDSS_AHB_CLK>, 950 <&gcc GCC_MDSS_AXI_CLK>, 951 <&gcc GCC_MDSS_BYTE1_CLK>, 952 <&gcc GCC_MDSS_PCLK1_CLK>, 953 <&gcc GCC_MDSS_ESC1_CLK>; 954 clock-names = "mdp_core", 955 "iface", 956 "bus", 957 "byte", 958 "pixel", 959 "core"; 960 961 phys = <&dsi1_phy>; 962 963 status = "disabled"; 964 965 ports { 966 #address-cells = <1>; 967 #size-cells = <0>; 968 969 port@0 { 970 reg = <0>; 971 dsi1_in: endpoint { 972 remote-endpoint = <&mdp5_intf2_out>; 973 }; 974 }; 975 976 port@1 { 977 reg = <1>; 978 dsi1_out: endpoint { 979 }; 980 }; 981 }; 982 }; 983 984 dsi1_phy: phy@1a96400 { 985 compatible = "qcom,dsi-phy-14nm-8953"; 986 reg = <0x01a96400 0x100>, 987 <0x01a96500 0x300>, 988 <0x01a96800 0x188>; 989 reg-names = "dsi_phy", 990 "dsi_phy_lane", 991 "dsi_pll"; 992 993 #clock-cells = <1>; 994 #phy-cells = <0>; 995 996 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 997 clock-names = "iface", "ref"; 998 999 status = "disabled"; 1000 }; 1001 }; 1002 1003 apps_iommu: iommu@1e00000 { 1004 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1005 ranges = <0 0x01e20000 0x20000>; 1006 1007 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1008 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1009 clock-names = "iface", "bus"; 1010 1011 qcom,iommu-secure-id = <17>; 1012 1013 #address-cells = <1>; 1014 #iommu-cells = <1>; 1015 #size-cells = <1>; 1016 1017 /* VFE */ 1018 iommu-ctx@14000 { 1019 compatible = "qcom,msm-iommu-v1-ns"; 1020 reg = <0x14000 0x1000>; 1021 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1022 }; 1023 1024 /* MDP_0 */ 1025 iommu-ctx@15000 { 1026 compatible = "qcom,msm-iommu-v1-ns"; 1027 reg = <0x15000 0x1000>; 1028 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1029 }; 1030 1031 /* VENUS_NS */ 1032 iommu-ctx@16000 { 1033 compatible = "qcom,msm-iommu-v1-ns"; 1034 reg = <0x16000 0x1000>; 1035 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1036 }; 1037 }; 1038 1039 spmi_bus: spmi@200f000 { 1040 compatible = "qcom,spmi-pmic-arb"; 1041 reg = <0x0200f000 0x1000>, 1042 <0x02400000 0x800000>, 1043 <0x02c00000 0x800000>, 1044 <0x03800000 0x200000>, 1045 <0x0200a000 0x2100>; 1046 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1047 interrupt-names = "periph_irq"; 1048 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1049 qcom,ee = <0>; 1050 qcom,channel = <0>; 1051 interrupt-controller; 1052 1053 #interrupt-cells = <4>; 1054 #address-cells = <2>; 1055 #size-cells = <0>; 1056 }; 1057 1058 mpss: remoteproc@4080000 { 1059 compatible = "qcom,msm8953-mss-pil"; 1060 reg = <0x04080000 0x100>, 1061 <0x04020000 0x040>; 1062 reg-names = "qdsp6", "rmb"; 1063 1064 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1065 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1066 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1067 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1068 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1069 interrupt-names = "wdog", "fatal", "ready", 1070 "handover", "stop-ack"; 1071 1072 power-domains = <&rpmpd MSM8953_VDDCX>, 1073 <&rpmpd MSM8953_VDDMX>, 1074 <&rpmpd MSM8953_VDDMD>; 1075 power-domain-names = "cx", "mx","mss"; 1076 1077 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1078 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1079 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1080 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1081 clock-names = "iface", "bus", "mem", "xo"; 1082 1083 qcom,smem-states = <&smp2p_modem_out 0>; 1084 qcom,smem-state-names = "stop"; 1085 1086 resets = <&gcc GCC_MSS_BCR>; 1087 reset-names = "mss_restart"; 1088 1089 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1090 1091 status = "disabled"; 1092 1093 mba { 1094 memory-region = <&mba_mem>; 1095 }; 1096 1097 mpss { 1098 memory-region = <&mpss_mem>; 1099 }; 1100 1101 smd-edge { 1102 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1103 1104 qcom,smd-edge = <0>; 1105 qcom,ipc = <&apcs 8 12>; 1106 qcom,remote-pid = <1>; 1107 1108 label = "modem"; 1109 }; 1110 }; 1111 1112 usb3: usb@70f8800 { 1113 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1114 reg = <0x070f8800 0x400>; 1115 #address-cells = <1>; 1116 #size-cells = <1>; 1117 ranges; 1118 1119 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1121 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1122 1123 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1124 <&gcc GCC_USB30_MASTER_CLK>, 1125 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1126 <&gcc GCC_USB30_SLEEP_CLK>, 1127 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1128 clock-names = "cfg_noc", 1129 "core", 1130 "iface", 1131 "sleep", 1132 "mock_utmi"; 1133 1134 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1135 <&gcc GCC_USB30_MASTER_CLK>; 1136 assigned-clock-rates = <19200000>, <133330000>; 1137 1138 power-domains = <&gcc USB30_GDSC>; 1139 1140 qcom,select-utmi-as-pipe-clk; 1141 1142 status = "disabled"; 1143 1144 usb3_dwc3: usb@7000000 { 1145 compatible = "snps,dwc3"; 1146 reg = <0x07000000 0xcc00>; 1147 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1148 phys = <&hsusb_phy>; 1149 phy-names = "usb2-phy"; 1150 1151 snps,usb2-gadget-lpm-disable; 1152 snps,dis-u1-entry-quirk; 1153 snps,dis-u2-entry-quirk; 1154 snps,is-utmi-l1-suspend; 1155 snps,hird-threshold = /bits/ 8 <0x00>; 1156 1157 maximum-speed = "high-speed"; 1158 }; 1159 }; 1160 1161 sdhc_1: mmc@7824900 { 1162 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1163 1164 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1165 reg-names = "hc", "core"; 1166 1167 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1169 interrupt-names = "hc_irq", "pwr_irq"; 1170 1171 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1172 <&gcc GCC_SDCC1_APPS_CLK>, 1173 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1174 clock-names = "iface", "core", "xo"; 1175 1176 power-domains = <&rpmpd MSM8953_VDDCX>; 1177 operating-points-v2 = <&sdhc1_opp_table>; 1178 1179 pinctrl-names = "default", "sleep"; 1180 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1181 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1182 1183 mmc-hs400-1_8v; 1184 mmc-hs200-1_8v; 1185 mmc-ddr-1_8v; 1186 bus-width = <8>; 1187 non-removable; 1188 1189 status = "disabled"; 1190 1191 sdhc1_opp_table: opp-table-sdhc1 { 1192 compatible = "operating-points-v2"; 1193 1194 opp-25000000 { 1195 opp-hz = /bits/ 64 <25000000>; 1196 required-opps = <&rpmpd_opp_low_svs>; 1197 }; 1198 1199 opp-50000000 { 1200 opp-hz = /bits/ 64 <50000000>; 1201 required-opps = <&rpmpd_opp_svs>; 1202 }; 1203 1204 opp-100000000 { 1205 opp-hz = /bits/ 64 <100000000>; 1206 required-opps = <&rpmpd_opp_svs>; 1207 }; 1208 1209 opp-192000000 { 1210 opp-hz = /bits/ 64 <192000000>; 1211 required-opps = <&rpmpd_opp_nom>; 1212 }; 1213 1214 opp-384000000 { 1215 opp-hz = /bits/ 64 <384000000>; 1216 required-opps = <&rpmpd_opp_nom>; 1217 }; 1218 }; 1219 }; 1220 1221 sdhc_2: mmc@7864900 { 1222 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1223 1224 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1225 reg-names = "hc", "core"; 1226 1227 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1229 interrupt-names = "hc_irq", "pwr_irq"; 1230 1231 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1232 <&gcc GCC_SDCC2_APPS_CLK>, 1233 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1234 clock-names = "iface", "core", "xo"; 1235 1236 power-domains = <&rpmpd MSM8953_VDDCX>; 1237 operating-points-v2 = <&sdhc2_opp_table>; 1238 1239 pinctrl-names = "default", "sleep"; 1240 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1241 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1242 1243 bus-width = <4>; 1244 1245 status = "disabled"; 1246 1247 sdhc2_opp_table: opp-table-sdhc2 { 1248 compatible = "operating-points-v2"; 1249 1250 opp-25000000 { 1251 opp-hz = /bits/ 64 <25000000>; 1252 required-opps = <&rpmpd_opp_low_svs>; 1253 }; 1254 1255 opp-50000000 { 1256 opp-hz = /bits/ 64 <50000000>; 1257 required-opps = <&rpmpd_opp_svs>; 1258 }; 1259 1260 opp-100000000 { 1261 opp-hz = /bits/ 64 <100000000>; 1262 required-opps = <&rpmpd_opp_svs>; 1263 }; 1264 1265 opp-177770000 { 1266 opp-hz = /bits/ 64 <177770000>; 1267 required-opps = <&rpmpd_opp_nom>; 1268 }; 1269 1270 opp-200000000 { 1271 opp-hz = /bits/ 64 <200000000>; 1272 required-opps = <&rpmpd_opp_nom>; 1273 }; 1274 }; 1275 }; 1276 1277 uart_0: serial@78af000 { 1278 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1279 reg = <0x078af000 0x200>; 1280 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1282 <&gcc GCC_BLSP1_AHB_CLK>; 1283 clock-names = "core", "iface"; 1284 1285 status = "disabled"; 1286 }; 1287 1288 i2c_1: i2c@78b5000 { 1289 compatible = "qcom,i2c-qup-v2.2.1"; 1290 reg = <0x078b5000 0x600>; 1291 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1292 clock-names = "core", "iface"; 1293 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1294 <&gcc GCC_BLSP1_AHB_CLK>; 1295 1296 pinctrl-names = "default", "sleep"; 1297 pinctrl-0 = <&i2c_1_default>; 1298 pinctrl-1 = <&i2c_1_sleep>; 1299 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 1303 status = "disabled"; 1304 }; 1305 1306 i2c_2: i2c@78b6000 { 1307 compatible = "qcom,i2c-qup-v2.2.1"; 1308 reg = <0x078b6000 0x600>; 1309 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1310 clock-names = "core", "iface"; 1311 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1312 <&gcc GCC_BLSP1_AHB_CLK>; 1313 1314 pinctrl-names = "default", "sleep"; 1315 pinctrl-0 = <&i2c_2_default>; 1316 pinctrl-1 = <&i2c_2_sleep>; 1317 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 1321 status = "disabled"; 1322 }; 1323 1324 i2c_3: i2c@78b7000 { 1325 compatible = "qcom,i2c-qup-v2.2.1"; 1326 reg = <0x078b7000 0x600>; 1327 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1328 clock-names = "core", "iface"; 1329 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1330 <&gcc GCC_BLSP1_AHB_CLK>; 1331 pinctrl-names = "default", "sleep"; 1332 pinctrl-0 = <&i2c_3_default>; 1333 pinctrl-1 = <&i2c_3_sleep>; 1334 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 1338 status = "disabled"; 1339 }; 1340 1341 i2c_4: i2c@78b8000 { 1342 compatible = "qcom,i2c-qup-v2.2.1"; 1343 reg = <0x078b8000 0x600>; 1344 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1345 clock-names = "core", "iface"; 1346 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1347 <&gcc GCC_BLSP1_AHB_CLK>; 1348 pinctrl-names = "default", "sleep"; 1349 pinctrl-0 = <&i2c_4_default>; 1350 pinctrl-1 = <&i2c_4_sleep>; 1351 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 1355 status = "disabled"; 1356 }; 1357 1358 i2c_5: i2c@7af5000 { 1359 compatible = "qcom,i2c-qup-v2.2.1"; 1360 reg = <0x07af5000 0x600>; 1361 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1362 clock-names = "core", "iface"; 1363 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1364 <&gcc GCC_BLSP2_AHB_CLK>; 1365 pinctrl-names = "default", "sleep"; 1366 pinctrl-0 = <&i2c_5_default>; 1367 pinctrl-1 = <&i2c_5_sleep>; 1368 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 1372 status = "disabled"; 1373 }; 1374 1375 i2c_6: i2c@7af6000 { 1376 compatible = "qcom,i2c-qup-v2.2.1"; 1377 reg = <0x07af6000 0x600>; 1378 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1379 clock-names = "core", "iface"; 1380 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1381 <&gcc GCC_BLSP2_AHB_CLK>; 1382 pinctrl-names = "default", "sleep"; 1383 pinctrl-0 = <&i2c_6_default>; 1384 pinctrl-1 = <&i2c_6_sleep>; 1385 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 1389 status = "disabled"; 1390 }; 1391 1392 i2c_7: i2c@7af7000 { 1393 compatible = "qcom,i2c-qup-v2.2.1"; 1394 reg = <0x07af7000 0x600>; 1395 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1396 clock-names = "core", "iface"; 1397 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1398 <&gcc GCC_BLSP2_AHB_CLK>; 1399 pinctrl-names = "default", "sleep"; 1400 pinctrl-0 = <&i2c_7_default>; 1401 pinctrl-1 = <&i2c_7_sleep>; 1402 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 status = "disabled"; 1407 }; 1408 1409 i2c_8: i2c@7af8000 { 1410 compatible = "qcom,i2c-qup-v2.2.1"; 1411 reg = <0x07af8000 0x600>; 1412 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1413 clock-names = "core", "iface"; 1414 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1415 <&gcc GCC_BLSP2_AHB_CLK>; 1416 pinctrl-names = "default", "sleep"; 1417 pinctrl-0 = <&i2c_8_default>; 1418 pinctrl-1 = <&i2c_8_sleep>; 1419 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 1423 status = "disabled"; 1424 }; 1425 1426 wcnss: remoteproc@a21b000 { 1427 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1428 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1429 reg-names = "ccu", "dxe", "pmu"; 1430 1431 memory-region = <&wcnss_fw_mem>; 1432 1433 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1434 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 1435 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 1436 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 1437 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 1438 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1439 1440 power-domains = <&rpmpd MSM8953_VDDCX>, 1441 <&rpmpd MSM8953_VDDMX>; 1442 power-domain-names = "cx", "mx"; 1443 1444 qcom,smem-states = <&smp2p_wcnss_out 0>; 1445 qcom,smem-state-names = "stop"; 1446 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&wcnss_pin_a>; 1449 1450 status = "disabled"; 1451 1452 wcnss_iris: iris { 1453 /* Separate chip, compatible is board-specific */ 1454 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1455 clock-names = "xo"; 1456 }; 1457 1458 smd-edge { 1459 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1460 1461 qcom,ipc = <&apcs 8 17>; 1462 qcom,smd-edge = <6>; 1463 qcom,remote-pid = <4>; 1464 1465 label = "pronto"; 1466 1467 wcnss_ctrl: wcnss { 1468 compatible = "qcom,wcnss"; 1469 qcom,smd-channels = "WCNSS_CTRL"; 1470 1471 qcom,mmio = <&wcnss>; 1472 1473 wcnss_bt: bluetooth { 1474 compatible = "qcom,wcnss-bt"; 1475 }; 1476 1477 wcnss_wifi: wifi { 1478 compatible = "qcom,wcnss-wlan"; 1479 1480 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1482 interrupt-names = "tx", "rx"; 1483 1484 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1485 qcom,smem-state-names = "tx-enable", 1486 "tx-rings-empty"; 1487 }; 1488 }; 1489 }; 1490 }; 1491 1492 intc: interrupt-controller@b000000 { 1493 compatible = "qcom,msm-qgic2"; 1494 interrupt-controller; 1495 #interrupt-cells = <3>; 1496 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1497 }; 1498 1499 apcs: mailbox@b011000 { 1500 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1501 reg = <0x0b011000 0x1000>; 1502 #mbox-cells = <1>; 1503 }; 1504 1505 timer@b120000 { 1506 compatible = "arm,armv7-timer-mem"; 1507 reg = <0x0b120000 0x1000>; 1508 #address-cells = <0x01>; 1509 #size-cells = <0x01>; 1510 ranges; 1511 1512 frame@b121000 { 1513 frame-number = <0>; 1514 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1516 reg = <0x0b121000 0x1000>, 1517 <0x0b122000 0x1000>; 1518 }; 1519 1520 frame@b123000 { 1521 frame-number = <1>; 1522 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1523 reg = <0x0b123000 0x1000>; 1524 status = "disabled"; 1525 }; 1526 1527 frame@b124000 { 1528 frame-number = <2>; 1529 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1530 reg = <0x0b124000 0x1000>; 1531 status = "disabled"; 1532 }; 1533 1534 frame@b125000 { 1535 frame-number = <3>; 1536 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1537 reg = <0x0b125000 0x1000>; 1538 status = "disabled"; 1539 }; 1540 1541 frame@b126000 { 1542 frame-number = <4>; 1543 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1544 reg = <0x0b126000 0x1000>; 1545 status = "disabled"; 1546 }; 1547 1548 frame@b127000 { 1549 frame-number = <5>; 1550 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1551 reg = <0x0b127000 0x1000>; 1552 status = "disabled"; 1553 }; 1554 1555 frame@b128000 { 1556 frame-number = <6>; 1557 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1558 reg = <0x0b128000 0x1000>; 1559 status = "disabled"; 1560 }; 1561 }; 1562 1563 lpass: remoteproc@c200000 { 1564 compatible = "qcom,msm8953-adsp-pil"; 1565 reg = <0x0c200000 0x100>; 1566 1567 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 1568 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1569 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1570 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1571 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1572 interrupt-names = "wdog", "fatal", "ready", 1573 "handover", "stop-ack"; 1574 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1575 clock-names = "xo"; 1576 1577 power-domains = <&rpmpd MSM8953_VDDCX>; 1578 power-domain-names = "cx"; 1579 1580 memory-region = <&adsp_fw_mem>; 1581 1582 qcom,smem-states = <&smp2p_adsp_out 0>; 1583 qcom,smem-state-names = "stop"; 1584 1585 status = "disabled"; 1586 1587 smd-edge { 1588 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1589 1590 label = "lpass"; 1591 mboxes = <&apcs 8>; 1592 qcom,smd-edge = <1>; 1593 qcom,remote-pid = <2>; 1594 1595 apr { 1596 compatible = "qcom,apr-v2"; 1597 qcom,smd-channels = "apr_audio_svc"; 1598 qcom,apr-domain = <APR_DOMAIN_ADSP>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 1602 q6core: service@3 { 1603 reg = <APR_SVC_ADSP_CORE>; 1604 compatible = "qcom,q6core"; 1605 }; 1606 1607 q6afe: service@4 { 1608 compatible = "qcom,q6afe"; 1609 reg = <APR_SVC_AFE>; 1610 q6afedai: dais { 1611 compatible = "qcom,q6afe-dais"; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 #sound-dai-cells = <1>; 1615 1616 dai@16 { 1617 reg = <PRIMARY_MI2S_RX>; 1618 qcom,sd-lines = <0 1>; 1619 }; 1620 dai@20 { 1621 reg = <TERTIARY_MI2S_TX>; 1622 qcom,sd-lines = <0 1>; 1623 }; 1624 dai@127 { 1625 reg = <QUINARY_MI2S_RX>; 1626 qcom,sd-lines = <0>; 1627 }; 1628 }; 1629 1630 q6afecc: clock-controller { 1631 compatible = "qcom,q6afe-clocks"; 1632 #clock-cells = <2>; 1633 }; 1634 }; 1635 1636 q6asm: service@7 { 1637 compatible = "qcom,q6asm"; 1638 reg = <APR_SVC_ASM>; 1639 q6asmdai: dais { 1640 compatible = "qcom,q6asm-dais"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 #sound-dai-cells = <1>; 1644 1645 dai@0 { 1646 reg = <0>; 1647 direction = <Q6ASM_DAI_RX>; 1648 }; 1649 dai@1 { 1650 reg = <1>; 1651 direction = <Q6ASM_DAI_TX>; 1652 }; 1653 dai@2 { 1654 reg = <2>; 1655 direction = <Q6ASM_DAI_RX>; 1656 }; 1657 dai@3 { 1658 reg = <3>; 1659 direction = <Q6ASM_DAI_RX>; 1660 is-compress-dai; 1661 }; 1662 }; 1663 }; 1664 1665 q6adm: service@8 { 1666 compatible = "qcom,q6adm"; 1667 reg = <APR_SVC_ADM>; 1668 q6routing: routing { 1669 compatible = "qcom,q6adm-routing"; 1670 #sound-dai-cells = <0>; 1671 }; 1672 }; 1673 }; 1674 }; 1675 }; 1676 }; 1677 1678 thermal-zones { 1679 cpu0-thermal { 1680 polling-delay-passive = <250>; 1681 polling-delay = <1000>; 1682 thermal-sensors = <&tsens0 9>; 1683 trips { 1684 cpu0_alert: trip-point0 { 1685 temperature = <80000>; 1686 hysteresis = <2000>; 1687 type = "passive"; 1688 }; 1689 cpu0_crit: crit { 1690 temperature = <100000>; 1691 hysteresis = <2000>; 1692 type = "critical"; 1693 }; 1694 }; 1695 cooling-maps { 1696 map0 { 1697 trip = <&cpu0_alert>; 1698 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1699 }; 1700 }; 1701 }; 1702 cpu1-thermal { 1703 polling-delay-passive = <250>; 1704 polling-delay = <1000>; 1705 thermal-sensors = <&tsens0 10>; 1706 trips { 1707 cpu1_alert: trip-point0 { 1708 temperature = <80000>; 1709 hysteresis = <2000>; 1710 type = "passive"; 1711 }; 1712 cpu1_crit: crit { 1713 temperature = <100000>; 1714 hysteresis = <2000>; 1715 type = "critical"; 1716 }; 1717 }; 1718 cooling-maps { 1719 map0 { 1720 trip = <&cpu1_alert>; 1721 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1722 }; 1723 }; 1724 }; 1725 cpu2-thermal { 1726 polling-delay-passive = <250>; 1727 polling-delay = <1000>; 1728 thermal-sensors = <&tsens0 11>; 1729 trips { 1730 cpu2_alert: trip-point0 { 1731 temperature = <80000>; 1732 hysteresis = <2000>; 1733 type = "passive"; 1734 }; 1735 cpu2_crit: crit { 1736 temperature = <100000>; 1737 hysteresis = <2000>; 1738 type = "critical"; 1739 }; 1740 }; 1741 cooling-maps { 1742 map0 { 1743 trip = <&cpu2_alert>; 1744 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1745 }; 1746 }; 1747 }; 1748 cpu3-thermal { 1749 polling-delay-passive = <250>; 1750 polling-delay = <1000>; 1751 thermal-sensors = <&tsens0 12>; 1752 trips { 1753 cpu3_alert: trip-point0 { 1754 temperature = <80000>; 1755 hysteresis = <2000>; 1756 type = "passive"; 1757 }; 1758 cpu3_crit: crit { 1759 temperature = <100000>; 1760 hysteresis = <2000>; 1761 type = "critical"; 1762 }; 1763 }; 1764 cooling-maps { 1765 map0 { 1766 trip = <&cpu3_alert>; 1767 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1768 }; 1769 }; 1770 }; 1771 cpu4-thermal { 1772 polling-delay-passive = <250>; 1773 polling-delay = <1000>; 1774 thermal-sensors = <&tsens0 4>; 1775 trips { 1776 cpu4_alert: trip-point0 { 1777 temperature = <80000>; 1778 hysteresis = <2000>; 1779 type = "passive"; 1780 }; 1781 cpu4_crit: crit { 1782 temperature = <100000>; 1783 hysteresis = <2000>; 1784 type = "critical"; 1785 }; 1786 }; 1787 cooling-maps { 1788 map0 { 1789 trip = <&cpu4_alert>; 1790 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1791 }; 1792 }; 1793 }; 1794 cpu5-thermal { 1795 polling-delay-passive = <250>; 1796 polling-delay = <1000>; 1797 thermal-sensors = <&tsens0 5>; 1798 trips { 1799 cpu5_alert: trip-point0 { 1800 temperature = <80000>; 1801 hysteresis = <2000>; 1802 type = "passive"; 1803 }; 1804 cpu5_crit: crit { 1805 temperature = <100000>; 1806 hysteresis = <2000>; 1807 type = "critical"; 1808 }; 1809 }; 1810 cooling-maps { 1811 map0 { 1812 trip = <&cpu5_alert>; 1813 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1814 }; 1815 }; 1816 }; 1817 cpu6-thermal { 1818 polling-delay-passive = <250>; 1819 polling-delay = <1000>; 1820 thermal-sensors = <&tsens0 6>; 1821 trips { 1822 cpu6_alert: trip-point0 { 1823 temperature = <80000>; 1824 hysteresis = <2000>; 1825 type = "passive"; 1826 }; 1827 cpu6_crit: crit { 1828 temperature = <100000>; 1829 hysteresis = <2000>; 1830 type = "critical"; 1831 }; 1832 }; 1833 cooling-maps { 1834 map0 { 1835 trip = <&cpu6_alert>; 1836 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1837 }; 1838 }; 1839 }; 1840 cpu7-thermal { 1841 polling-delay-passive = <250>; 1842 polling-delay = <1000>; 1843 thermal-sensors = <&tsens0 7>; 1844 trips { 1845 cpu7_alert: trip-point0 { 1846 temperature = <80000>; 1847 hysteresis = <2000>; 1848 type = "passive"; 1849 }; 1850 cpu7_crit: crit { 1851 temperature = <100000>; 1852 hysteresis = <2000>; 1853 type = "critical"; 1854 }; 1855 }; 1856 cooling-maps { 1857 map0 { 1858 trip = <&cpu7_alert>; 1859 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1860 }; 1861 }; 1862 }; 1863 }; 1864 1865 timer { 1866 compatible = "arm,armv8-timer"; 1867 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1868 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1869 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1870 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1871 }; 1872}; 1873