1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,gcc-msm8953.h> 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <32768>; 23 }; 24 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo"; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 capacity-dmips-mhz = <1024>; 43 next-level-cache = <&L2_0>; 44 #cooling-cells = <2>; 45 46 l1-icache { 47 compatible = "cache"; 48 }; 49 l1-dcache { 50 compatible = "cache"; 51 }; 52 }; 53 54 CPU1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x1>; 58 enable-method = "psci"; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 #cooling-cells = <2>; 62 63 l1-icache { 64 compatible = "cache"; 65 }; 66 l1-dcache { 67 compatible = "cache"; 68 }; 69 }; 70 71 CPU2: cpu@2 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x2>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 #cooling-cells = <2>; 79 80 l1-icache { 81 compatible = "cache"; 82 }; 83 l1-dcache { 84 compatible = "cache"; 85 }; 86 }; 87 88 CPU3: cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x3>; 92 enable-method = "psci"; 93 capacity-dmips-mhz = <1024>; 94 next-level-cache = <&L2_0>; 95 #cooling-cells = <2>; 96 97 l1-icache { 98 compatible = "cache"; 99 }; 100 l1-dcache { 101 compatible = "cache"; 102 }; 103 }; 104 105 CPU4: cpu@100 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x100>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 next-level-cache = <&L2_1>; 112 #cooling-cells = <2>; 113 114 l1-icache { 115 compatible = "cache"; 116 }; 117 l1-dcache { 118 compatible = "cache"; 119 }; 120 }; 121 122 CPU5: cpu@101 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x101>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <1024>; 128 next-level-cache = <&L2_1>; 129 #cooling-cells = <2>; 130 131 l1-icache { 132 compatible = "cache"; 133 }; 134 l1-dcache { 135 compatible = "cache"; 136 }; 137 }; 138 139 CPU6: cpu@102 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a53"; 142 reg = <0x102>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 next-level-cache = <&L2_1>; 146 #cooling-cells = <2>; 147 148 l1-icache { 149 compatible = "cache"; 150 }; 151 l1-dcache { 152 compatible = "cache"; 153 }; 154 }; 155 156 CPU7: cpu@103 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a53"; 159 reg = <0x103>; 160 enable-method = "psci"; 161 capacity-dmips-mhz = <1024>; 162 next-level-cache = <&L2_1>; 163 #cooling-cells = <2>; 164 165 l1-icache { 166 compatible = "cache"; 167 }; 168 l1-dcache { 169 compatible = "cache"; 170 }; 171 }; 172 173 cpu-map { 174 cluster0 { 175 core0 { 176 cpu = <&CPU0>; 177 }; 178 core1 { 179 cpu = <&CPU1>; 180 }; 181 core2 { 182 cpu = <&CPU2>; 183 }; 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 }; 188 189 cluster1 { 190 core0 { 191 cpu = <&CPU4>; 192 }; 193 core1 { 194 cpu = <&CPU5>; 195 }; 196 core2 { 197 cpu = <&CPU6>; 198 }; 199 core3 { 200 cpu = <&CPU7>; 201 }; 202 }; 203 }; 204 205 L2_0: l2-cache_0 { 206 compatible = "cache"; 207 cache-level = <2>; 208 }; 209 210 L2_1: l2-cache_1 { 211 compatible = "cache"; 212 cache-level = <2>; 213 }; 214 }; 215 216 firmware { 217 scm: scm { 218 compatible = "qcom,scm-msm8953", "qcom,scm"; 219 clocks = <&gcc GCC_CRYPTO_CLK>, 220 <&gcc GCC_CRYPTO_AXI_CLK>, 221 <&gcc GCC_CRYPTO_AHB_CLK>; 222 clock-names = "core", "bus", "iface"; 223 #reset-cells = <1>; 224 }; 225 }; 226 227 memory { 228 device_type = "memory"; 229 /* We expect the bootloader to fill in the reg */ 230 reg = <0 0 0 0>; 231 }; 232 233 pmu { 234 compatible = "arm,cortex-a53-pmu"; 235 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 236 }; 237 238 psci { 239 compatible = "arm,psci-1.0"; 240 method = "smc"; 241 }; 242 243 reserved-memory { 244 #address-cells = <2>; 245 #size-cells = <2>; 246 ranges; 247 248 zap_shader_region: memory@81800000 { 249 compatible = "shared-dma-pool"; 250 reg = <0x0 0x81800000 0x0 0x2000>; 251 no-map; 252 }; 253 254 memory@85b00000 { 255 reg = <0x0 0x85b00000 0x0 0x800000>; 256 no-map; 257 }; 258 259 smem_mem: memory@86300000 { 260 compatible = "qcom,smem"; 261 reg = <0x0 0x86300000 0x0 0x100000>; 262 qcom,rpm-msg-ram = <&rpm_msg_ram>; 263 hwlocks = <&tcsr_mutex 3>; 264 no-map; 265 }; 266 267 memory@86400000 { 268 reg = <0x0 0x86400000 0x0 0x400000>; 269 no-map; 270 }; 271 272 mpss_mem: memory@86c00000 { 273 reg = <0x0 0x86c00000 0x0 0x6a00000>; 274 no-map; 275 }; 276 277 adsp_fw_mem: memory@8d600000 { 278 reg = <0x0 0x8d600000 0x0 0x1100000>; 279 no-map; 280 }; 281 282 wcnss_fw_mem: memory@8e700000 { 283 reg = <0x0 0x8e700000 0x0 0x700000>; 284 no-map; 285 }; 286 287 memory@90000000 { 288 reg = <0 0x90000000 0 0x1000>; 289 no-map; 290 }; 291 292 memory@90001000 { 293 reg = <0x0 0x90001000 0x0 0x13ff000>; 294 no-map; 295 }; 296 297 venus_mem: memory@91400000 { 298 reg = <0x0 0x91400000 0x0 0x700000>; 299 no-map; 300 }; 301 302 mba_mem: memory@92000000 { 303 reg = <0x0 0x92000000 0x0 0x100000>; 304 no-map; 305 }; 306 307 memory@f2d00000 { 308 compatible = "qcom,rmtfs-mem"; 309 reg = <0x0 0xf2d00000 0x0 0x180000>; 310 no-map; 311 312 qcom,client-id = <1>; 313 }; 314 }; 315 316 smd { 317 compatible = "qcom,smd"; 318 319 rpm { 320 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 321 qcom,ipc = <&apcs 8 0>; 322 qcom,smd-edge = <15>; 323 324 rpm_requests: rpm-requests { 325 compatible = "qcom,rpm-msm8953"; 326 qcom,smd-channels = "rpm_requests"; 327 328 rpmcc: rpmcc { 329 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 330 clocks = <&xo_board>; 331 clock-names = "xo"; 332 #clock-cells = <1>; 333 }; 334 335 rpmpd: power-controller { 336 compatible = "qcom,msm8953-rpmpd"; 337 #power-domain-cells = <1>; 338 operating-points-v2 = <&rpmpd_opp_table>; 339 340 clocks = <&xo_board>; 341 clock-names = "ref"; 342 343 rpmpd_opp_table: opp-table { 344 compatible = "operating-points-v2"; 345 346 rpmpd_opp_ret: opp1 { 347 opp-level = <RPM_SMD_LEVEL_RETENTION>; 348 }; 349 350 rpmpd_opp_ret_plus: opp2 { 351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 352 }; 353 354 rpmpd_opp_min_svs: opp3 { 355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 356 }; 357 358 rpmpd_opp_low_svs: opp4 { 359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 360 }; 361 362 rpmpd_opp_svs: opp5 { 363 opp-level = <RPM_SMD_LEVEL_SVS>; 364 }; 365 366 rpmpd_opp_svs_plus: opp6 { 367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 368 }; 369 370 rpmpd_opp_nom: opp7 { 371 opp-level = <RPM_SMD_LEVEL_NOM>; 372 }; 373 374 rpmpd_opp_nom_plus: opp8 { 375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 376 }; 377 378 rpmpd_opp_turbo: opp9 { 379 opp-level = <RPM_SMD_LEVEL_TURBO>; 380 }; 381 }; 382 }; 383 }; 384 }; 385 }; 386 387 smsm { 388 compatible = "qcom,smsm"; 389 390 #address-cells = <1>; 391 #size-cells = <0>; 392 393 qcom,ipc-1 = <&apcs 8 13>; 394 qcom,ipc-3 = <&apcs 8 19>; 395 396 apps_smsm: apps@0 { 397 reg = <0>; 398 399 #qcom,smem-state-cells = <1>; 400 }; 401 }; 402 403 soc: soc@0 { 404 #address-cells = <1>; 405 #size-cells = <1>; 406 ranges = <0 0 0 0xffffffff>; 407 compatible = "simple-bus"; 408 409 rpm_msg_ram: sram@60000 { 410 compatible = "qcom,rpm-msg-ram"; 411 reg = <0x60000 0x8000>; 412 }; 413 414 hsusb_phy: phy@79000 { 415 compatible = "qcom,msm8953-qusb2-phy"; 416 reg = <0x79000 0x180>; 417 #phy-cells = <0>; 418 419 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 420 <&gcc GCC_QUSB_REF_CLK>; 421 clock-names = "cfg_ahb", "ref"; 422 423 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 424 425 resets = <&gcc GCC_QUSB2_PHY_BCR>; 426 427 status = "disabled"; 428 }; 429 430 rng@e3000 { 431 compatible = "qcom,prng"; 432 reg = <0x000e3000 0x1000>; 433 clocks = <&gcc GCC_PRNG_AHB_CLK>; 434 clock-names = "core"; 435 }; 436 437 tsens0: thermal-sensor@4a9000 { 438 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 439 reg = <0x4a9000 0x1000>, /* TM */ 440 <0x4a8000 0x1000>; /* SROT */ 441 #qcom,sensors = <16>; 442 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 444 interrupt-names = "uplow", "critical"; 445 #thermal-sensor-cells = <1>; 446 }; 447 448 restart@4ab000 { 449 compatible = "qcom,pshold"; 450 reg = <0x4ab000 0x4>; 451 }; 452 453 tlmm: pinctrl@1000000 { 454 compatible = "qcom,msm8953-pinctrl"; 455 reg = <0x1000000 0x300000>; 456 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 457 gpio-controller; 458 gpio-ranges = <&tlmm 0 0 155>; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 463 uart_console_active: uart-console-active-state { 464 pins = "gpio4", "gpio5"; 465 function = "blsp_uart2"; 466 drive-strength = <2>; 467 bias-disable; 468 }; 469 470 uart_console_sleep: uart-console-sleep-state { 471 pins = "gpio4", "gpio5"; 472 function = "blsp_uart2"; 473 drive-strength = <2>; 474 bias-pull-down; 475 }; 476 477 sdc1_clk_on: sdc1-clk-on-state { 478 pins = "sdc1_clk"; 479 bias-disable; 480 drive-strength = <16>; 481 }; 482 483 sdc1_clk_off: sdc1-clk-off-state { 484 pins = "sdc1_clk"; 485 bias-disable; 486 drive-strength = <2>; 487 }; 488 489 sdc1_cmd_on: sdc1-cmd-on-state { 490 pins = "sdc1_cmd"; 491 bias-disable; 492 drive-strength = <10>; 493 }; 494 495 sdc1_cmd_off: sdc1-cmd-off-state { 496 pins = "sdc1_cmd"; 497 bias-disable; 498 drive-strength = <2>; 499 }; 500 501 sdc1_data_on: sdc1-data-on-state { 502 pins = "sdc1_data"; 503 bias-pull-up; 504 drive-strength = <10>; 505 }; 506 507 sdc1_data_off: sdc1-data-off-state { 508 pins = "sdc1_data"; 509 bias-pull-up; 510 drive-strength = <2>; 511 }; 512 513 sdc1_rclk_on: sdc1-rclk-on-state { 514 pins = "sdc1_rclk"; 515 bias-pull-down; 516 }; 517 518 sdc1_rclk_off: sdc1-rclk-off-state { 519 pins = "sdc1_rclk"; 520 bias-pull-down; 521 }; 522 523 sdc2_clk_on: sdc2-clk-on-state { 524 pins = "sdc2_clk"; 525 drive-strength = <16>; 526 bias-disable; 527 }; 528 529 sdc2_clk_off: sdc2-clk-off-state { 530 pins = "sdc2_clk"; 531 bias-disable; 532 drive-strength = <2>; 533 }; 534 535 sdc2_cmd_on: sdc2-cmd-on-state { 536 pins = "sdc2_cmd"; 537 bias-pull-up; 538 drive-strength = <10>; 539 }; 540 541 sdc2_cmd_off: sdc2-cmd-off-state { 542 pins = "sdc2_cmd"; 543 bias-pull-up; 544 drive-strength = <2>; 545 }; 546 547 sdc2_data_on: sdc2-data-on-state { 548 pins = "sdc2_data"; 549 bias-pull-up; 550 drive-strength = <10>; 551 }; 552 553 sdc2_data_off: sdc2-data-off-state { 554 pins = "sdc2_data"; 555 bias-pull-up; 556 drive-strength = <2>; 557 }; 558 559 sdc2_cd_on: cd-on-state { 560 pins = "gpio133"; 561 function = "gpio"; 562 drive-strength = <2>; 563 bias-pull-up; 564 }; 565 566 sdc2_cd_off: cd-off-state { 567 pins = "gpio133"; 568 function = "gpio"; 569 drive-strength = <2>; 570 bias-disable; 571 }; 572 573 gpio_key_default: gpio-key-default-state { 574 pins = "gpio85"; 575 function = "gpio"; 576 drive-strength = <2>; 577 bias-pull-up; 578 }; 579 580 i2c_1_default: i2c-1-default-state { 581 pins = "gpio2", "gpio3"; 582 function = "blsp_i2c1"; 583 drive-strength = <2>; 584 bias-disable; 585 }; 586 587 i2c_1_sleep: i2c-1-sleep-state { 588 pins = "gpio2", "gpio3"; 589 function = "gpio"; 590 drive-strength = <2>; 591 bias-disable; 592 }; 593 594 i2c_2_default: i2c-2-default-state { 595 pins = "gpio6", "gpio7"; 596 function = "blsp_i2c2"; 597 drive-strength = <2>; 598 bias-disable; 599 }; 600 601 i2c_2_sleep: i2c-2-sleep-state { 602 pins = "gpio6", "gpio7"; 603 function = "gpio"; 604 drive-strength = <2>; 605 bias-disable; 606 }; 607 608 i2c_3_default: i2c-3-default-state { 609 pins = "gpio10", "gpio11"; 610 function = "blsp_i2c3"; 611 drive-strength = <2>; 612 bias-disable; 613 }; 614 615 i2c_3_sleep: i2c-3-sleep-state { 616 pins = "gpio10", "gpio11"; 617 function = "gpio"; 618 drive-strength = <2>; 619 bias-disable; 620 }; 621 622 i2c_4_default: i2c-4-default-state { 623 pins = "gpio14", "gpio15"; 624 function = "blsp_i2c4"; 625 drive-strength = <2>; 626 bias-disable; 627 }; 628 629 i2c_4_sleep: i2c-4-sleep-state { 630 pins = "gpio14", "gpio15"; 631 function = "gpio"; 632 drive-strength = <2>; 633 bias-disable; 634 }; 635 636 i2c_5_default: i2c-5-default-state { 637 pins = "gpio18", "gpio19"; 638 function = "blsp_i2c5"; 639 drive-strength = <2>; 640 bias-disable; 641 }; 642 643 i2c_5_sleep: i2c-5-sleep-state { 644 pins = "gpio18", "gpio19"; 645 function = "gpio"; 646 drive-strength = <2>; 647 bias-disable; 648 }; 649 650 i2c_6_default: i2c-6-default-state { 651 pins = "gpio22", "gpio23"; 652 function = "blsp_i2c6"; 653 drive-strength = <2>; 654 bias-disable; 655 }; 656 657 i2c_6_sleep: i2c-6-sleep-state { 658 pins = "gpio22", "gpio23"; 659 function = "gpio"; 660 drive-strength = <2>; 661 bias-disable; 662 }; 663 664 i2c_7_default: i2c-7-default-state { 665 pins = "gpio135", "gpio136"; 666 function = "blsp_i2c7"; 667 drive-strength = <2>; 668 bias-disable; 669 }; 670 671 i2c_7_sleep: i2c-7-sleep-state { 672 pins = "gpio135", "gpio136"; 673 function = "gpio"; 674 drive-strength = <2>; 675 bias-disable; 676 }; 677 678 i2c_8_default: i2c-8-default-state { 679 pins = "gpio98", "gpio99"; 680 function = "blsp_i2c8"; 681 drive-strength = <2>; 682 bias-disable; 683 }; 684 685 i2c_8_sleep: i2c-8-sleep-state { 686 pins = "gpio98", "gpio99"; 687 function = "gpio"; 688 drive-strength = <2>; 689 bias-disable; 690 }; 691 }; 692 693 gcc: clock-controller@1800000 { 694 compatible = "qcom,gcc-msm8953"; 695 reg = <0x1800000 0x80000>; 696 #clock-cells = <1>; 697 #reset-cells = <1>; 698 #power-domain-cells = <1>; 699 clocks = <&xo_board>, 700 <&sleep_clk>, 701 <0>, 702 <0>, 703 <0>, 704 <0>; 705 clock-names = "xo", 706 "sleep", 707 "dsi0pll", 708 "dsi0pllbyte", 709 "dsi1pll", 710 "dsi1pllbyte"; 711 }; 712 713 tcsr_mutex: hwlock@1905000 { 714 compatible = "qcom,tcsr-mutex"; 715 reg = <0x1905000 0x20000>; 716 #hwlock-cells = <1>; 717 }; 718 719 tcsr: syscon@1937000 { 720 compatible = "qcom,tcsr-msm8953", "syscon"; 721 reg = <0x1937000 0x30000>; 722 }; 723 724 tcsr_phy_clk_scheme_sel: syscon@193f044 { 725 compatible = "qcom,tcsr-msm8953", "syscon"; 726 reg = <0x193f044 0x4>; 727 }; 728 729 mdss: mdss@1a00000 { 730 compatible = "qcom,mdss"; 731 732 reg = <0x1a00000 0x1000>, 733 <0x1ab0000 0x1040>; 734 reg-names = "mdss_phys", 735 "vbif_phys"; 736 737 power-domains = <&gcc MDSS_GDSC>; 738 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 739 740 interrupt-controller; 741 #interrupt-cells = <1>; 742 743 clocks = <&gcc GCC_MDSS_AHB_CLK>, 744 <&gcc GCC_MDSS_AXI_CLK>, 745 <&gcc GCC_MDSS_VSYNC_CLK>, 746 <&gcc GCC_MDSS_MDP_CLK>; 747 clock-names = "iface", 748 "bus", 749 "vsync", 750 "core"; 751 752 #address-cells = <1>; 753 #size-cells = <1>; 754 ranges; 755 756 status = "disabled"; 757 758 mdp: mdp@1a01000 { 759 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 760 reg = <0x1a01000 0x89000>; 761 reg-names = "mdp_phys"; 762 763 interrupt-parent = <&mdss>; 764 interrupts = <0>; 765 766 power-domains = <&gcc MDSS_GDSC>; 767 768 clocks = <&gcc GCC_MDSS_AHB_CLK>, 769 <&gcc GCC_MDSS_AXI_CLK>, 770 <&gcc GCC_MDSS_MDP_CLK>, 771 <&gcc GCC_MDSS_VSYNC_CLK>; 772 clock-names = "iface", 773 "bus", 774 "core", 775 "vsync"; 776 777 iommus = <&apps_iommu 0x15>; 778 779 ports { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 783 port@0 { 784 reg = <0>; 785 mdp5_intf1_out: endpoint { 786 remote-endpoint = <&dsi0_in>; 787 }; 788 }; 789 790 port@1 { 791 reg = <1>; 792 mdp5_intf2_out: endpoint { 793 remote-endpoint = <&dsi1_in>; 794 }; 795 }; 796 }; 797 }; 798 799 dsi0: dsi@1a94000 { 800 compatible = "qcom,mdss-dsi-ctrl"; 801 reg = <0x1a94000 0x400>; 802 reg-names = "dsi_ctrl"; 803 804 interrupt-parent = <&mdss>; 805 interrupts = <4>; 806 807 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 808 <&gcc PCLK0_CLK_SRC>; 809 assigned-clock-parents = <&dsi0_phy 0>, 810 <&dsi0_phy 1>; 811 812 clocks = <&gcc GCC_MDSS_MDP_CLK>, 813 <&gcc GCC_MDSS_AHB_CLK>, 814 <&gcc GCC_MDSS_AXI_CLK>, 815 <&gcc GCC_MDSS_BYTE0_CLK>, 816 <&gcc GCC_MDSS_PCLK0_CLK>, 817 <&gcc GCC_MDSS_ESC0_CLK>; 818 clock-names = "mdp_core", 819 "iface", 820 "bus", 821 "byte", 822 "pixel", 823 "core"; 824 825 phys = <&dsi0_phy>; 826 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 status = "disabled"; 831 832 ports { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 port@0 { 837 reg = <0>; 838 dsi0_in: endpoint { 839 remote-endpoint = <&mdp5_intf1_out>; 840 }; 841 }; 842 843 port@1 { 844 reg = <1>; 845 dsi0_out: endpoint { 846 }; 847 }; 848 }; 849 }; 850 851 dsi0_phy: phy@1a94400 { 852 compatible = "qcom,dsi-phy-14nm-8953"; 853 reg = <0x1a94400 0x100>, 854 <0x1a94500 0x300>, 855 <0x1a94800 0x188>; 856 reg-names = "dsi_phy", 857 "dsi_phy_lane", 858 "dsi_pll"; 859 860 #clock-cells = <1>; 861 #phy-cells = <0>; 862 863 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; 864 clock-names = "iface", "ref"; 865 866 status = "disabled"; 867 }; 868 869 dsi1: dsi@1a96000 { 870 compatible = "qcom,mdss-dsi-ctrl"; 871 reg = <0x1a96000 0x400>; 872 reg-names = "dsi_ctrl"; 873 874 interrupt-parent = <&mdss>; 875 interrupts = <5>; 876 877 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 878 <&gcc PCLK1_CLK_SRC>; 879 assigned-clock-parents = <&dsi1_phy 0>, 880 <&dsi1_phy 1>; 881 882 clocks = <&gcc GCC_MDSS_MDP_CLK>, 883 <&gcc GCC_MDSS_AHB_CLK>, 884 <&gcc GCC_MDSS_AXI_CLK>, 885 <&gcc GCC_MDSS_BYTE1_CLK>, 886 <&gcc GCC_MDSS_PCLK1_CLK>, 887 <&gcc GCC_MDSS_ESC1_CLK>; 888 clock-names = "mdp_core", 889 "iface", 890 "bus", 891 "byte", 892 "pixel", 893 "core"; 894 895 phys = <&dsi1_phy>; 896 897 status = "disabled"; 898 899 ports { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 port@0 { 904 reg = <0>; 905 dsi1_in: endpoint { 906 remote-endpoint = <&mdp5_intf2_out>; 907 }; 908 }; 909 910 port@1 { 911 reg = <1>; 912 dsi1_out: endpoint { 913 }; 914 }; 915 }; 916 }; 917 918 dsi1_phy: phy@1a96400 { 919 compatible = "qcom,dsi-phy-14nm-8953"; 920 reg = <0x1a96400 0x100>, 921 <0x1a96500 0x300>, 922 <0x1a96800 0x188>; 923 reg-names = "dsi_phy", 924 "dsi_phy_lane", 925 "dsi_pll"; 926 927 #clock-cells = <1>; 928 #phy-cells = <0>; 929 930 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; 931 clock-names = "iface", "ref"; 932 933 status = "disabled"; 934 }; 935 }; 936 937 apps_iommu: iommu@1e00000 { 938 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 939 ranges = <0 0x1e20000 0x20000>; 940 941 clocks = <&gcc GCC_SMMU_CFG_CLK>, 942 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 943 clock-names = "iface", "bus"; 944 945 qcom,iommu-secure-id = <17>; 946 947 #address-cells = <1>; 948 #iommu-cells = <1>; 949 #size-cells = <1>; 950 951 /* VFE */ 952 iommu-ctx@14000 { 953 compatible = "qcom,msm-iommu-v1-ns"; 954 reg = <0x14000 0x1000>; 955 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 956 }; 957 958 /* MDP_0 */ 959 iommu-ctx@15000 { 960 compatible = "qcom,msm-iommu-v1-ns"; 961 reg = <0x15000 0x1000>; 962 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 963 }; 964 965 /* VENUS_NS */ 966 iommu-ctx@16000 { 967 compatible = "qcom,msm-iommu-v1-ns"; 968 reg = <0x16000 0x1000>; 969 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 970 }; 971 }; 972 973 spmi_bus: spmi@200f000 { 974 compatible = "qcom,spmi-pmic-arb"; 975 reg = <0x200f000 0x1000>, 976 <0x2400000 0x800000>, 977 <0x2c00000 0x800000>, 978 <0x3800000 0x200000>, 979 <0x200a000 0x2100>; 980 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 981 interrupt-names = "periph_irq"; 982 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 983 qcom,ee = <0>; 984 qcom,channel = <0>; 985 interrupt-controller; 986 987 #interrupt-cells = <4>; 988 #address-cells = <2>; 989 #size-cells = <0>; 990 }; 991 992 usb3: usb@70f8800 { 993 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 994 reg = <0x70f8800 0x400>; 995 #address-cells = <1>; 996 #size-cells = <1>; 997 ranges; 998 999 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1002 1003 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1004 <&gcc GCC_USB30_MASTER_CLK>, 1005 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1006 <&gcc GCC_USB30_SLEEP_CLK>, 1007 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1008 clock-names = "cfg_noc", 1009 "core", 1010 "iface", 1011 "sleep", 1012 "mock_utmi"; 1013 1014 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1015 <&gcc GCC_USB30_MASTER_CLK>; 1016 assigned-clock-rates = <19200000>, <133330000>; 1017 1018 power-domains = <&gcc USB30_GDSC>; 1019 1020 qcom,select-utmi-as-pipe-clk; 1021 1022 status = "disabled"; 1023 1024 usb3_dwc3: usb@7000000 { 1025 compatible = "snps,dwc3"; 1026 reg = <0x07000000 0xcc00>; 1027 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1028 phys = <&hsusb_phy>; 1029 phy-names = "usb2-phy"; 1030 1031 snps,usb2-gadget-lpm-disable; 1032 snps,dis-u1-entry-quirk; 1033 snps,dis-u2-entry-quirk; 1034 snps,is-utmi-l1-suspend; 1035 snps,hird-threshold = /bits/ 8 <0x00>; 1036 1037 maximum-speed = "high-speed"; 1038 phy_mode = "utmi"; 1039 }; 1040 }; 1041 1042 sdhc_1: mmc@7824900 { 1043 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1044 1045 reg = <0x7824900 0x500>, <0x7824000 0x800>; 1046 reg-names = "hc", "core"; 1047 1048 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1050 interrupt-names = "hc_irq", "pwr_irq"; 1051 1052 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1053 <&gcc GCC_SDCC1_APPS_CLK>, 1054 <&xo_board>; 1055 clock-names = "iface", "core", "xo"; 1056 1057 power-domains = <&rpmpd MSM8953_VDDCX>; 1058 operating-points-v2 = <&sdhc1_opp_table>; 1059 1060 pinctrl-names = "default", "sleep"; 1061 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1062 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1063 1064 mmc-hs400-1_8v; 1065 mmc-hs200-1_8v; 1066 mmc-ddr-1_8v; 1067 bus-width = <8>; 1068 non-removable; 1069 1070 status = "disabled"; 1071 1072 sdhc1_opp_table: opp-table-sdhc1 { 1073 compatible = "operating-points-v2"; 1074 1075 opp-25000000 { 1076 opp-hz = /bits/ 64 <25000000>; 1077 required-opps = <&rpmpd_opp_low_svs>; 1078 }; 1079 1080 opp-50000000 { 1081 opp-hz = /bits/ 64 <50000000>; 1082 required-opps = <&rpmpd_opp_svs>; 1083 }; 1084 1085 opp-100000000 { 1086 opp-hz = /bits/ 64 <100000000>; 1087 required-opps = <&rpmpd_opp_svs>; 1088 }; 1089 1090 opp-192000000 { 1091 opp-hz = /bits/ 64 <192000000>; 1092 required-opps = <&rpmpd_opp_nom>; 1093 }; 1094 1095 opp-384000000 { 1096 opp-hz = /bits/ 64 <384000000>; 1097 required-opps = <&rpmpd_opp_nom>; 1098 }; 1099 }; 1100 }; 1101 1102 sdhc_2: mmc@7864900 { 1103 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1104 1105 reg = <0x7864900 0x500>, <0x7864000 0x800>; 1106 reg-names = "hc", "core"; 1107 1108 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupt-names = "hc_irq", "pwr_irq"; 1111 1112 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1113 <&gcc GCC_SDCC2_APPS_CLK>, 1114 <&xo_board>; 1115 clock-names = "iface", "core", "xo"; 1116 1117 power-domains = <&rpmpd MSM8953_VDDCX>; 1118 operating-points-v2 = <&sdhc2_opp_table>; 1119 1120 pinctrl-names = "default", "sleep"; 1121 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1122 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1123 1124 bus-width = <4>; 1125 1126 status = "disabled"; 1127 1128 sdhc2_opp_table: opp-table-sdhc2 { 1129 compatible = "operating-points-v2"; 1130 1131 opp-25000000 { 1132 opp-hz = /bits/ 64 <25000000>; 1133 required-opps = <&rpmpd_opp_low_svs>; 1134 }; 1135 1136 opp-50000000 { 1137 opp-hz = /bits/ 64 <50000000>; 1138 required-opps = <&rpmpd_opp_svs>; 1139 }; 1140 1141 opp-100000000 { 1142 opp-hz = /bits/ 64 <100000000>; 1143 required-opps = <&rpmpd_opp_svs>; 1144 }; 1145 1146 opp-177770000 { 1147 opp-hz = /bits/ 64 <177770000>; 1148 required-opps = <&rpmpd_opp_nom>; 1149 }; 1150 1151 opp-200000000 { 1152 opp-hz = /bits/ 64 <200000000>; 1153 required-opps = <&rpmpd_opp_nom>; 1154 }; 1155 }; 1156 }; 1157 1158 uart_0: serial@78af000 { 1159 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1160 reg = <0x78af000 0x200>; 1161 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1163 <&gcc GCC_BLSP1_AHB_CLK>; 1164 clock-names = "core", "iface"; 1165 1166 status = "disabled"; 1167 }; 1168 1169 i2c_1: i2c@78b5000 { 1170 compatible = "qcom,i2c-qup-v2.2.1"; 1171 reg = <0x78b5000 0x600>; 1172 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1173 clock-names = "core", "iface"; 1174 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1175 <&gcc GCC_BLSP1_AHB_CLK>; 1176 1177 pinctrl-names = "default", "sleep"; 1178 pinctrl-0 = <&i2c_1_default>; 1179 pinctrl-1 = <&i2c_1_sleep>; 1180 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 status = "disabled"; 1185 }; 1186 1187 i2c_2: i2c@78b6000 { 1188 compatible = "qcom,i2c-qup-v2.2.1"; 1189 reg = <0x78b6000 0x600>; 1190 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1191 clock-names = "core", "iface"; 1192 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1193 <&gcc GCC_BLSP1_AHB_CLK>; 1194 1195 pinctrl-names = "default", "sleep"; 1196 pinctrl-0 = <&i2c_2_default>; 1197 pinctrl-1 = <&i2c_2_sleep>; 1198 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 status = "disabled"; 1203 }; 1204 1205 i2c_3: i2c@78b7000 { 1206 compatible = "qcom,i2c-qup-v2.2.1"; 1207 reg = <0x78b7000 0x600>; 1208 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1209 clock-names = "core", "iface"; 1210 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1211 <&gcc GCC_BLSP1_AHB_CLK>; 1212 pinctrl-names = "default", "sleep"; 1213 pinctrl-0 = <&i2c_3_default>; 1214 pinctrl-1 = <&i2c_3_sleep>; 1215 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 1219 status = "disabled"; 1220 }; 1221 1222 i2c_4: i2c@78b8000 { 1223 compatible = "qcom,i2c-qup-v2.2.1"; 1224 reg = <0x78b8000 0x600>; 1225 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1226 clock-names = "core", "iface"; 1227 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1228 <&gcc GCC_BLSP1_AHB_CLK>; 1229 pinctrl-names = "default", "sleep"; 1230 pinctrl-0 = <&i2c_4_default>; 1231 pinctrl-1 = <&i2c_4_sleep>; 1232 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 1236 status = "disabled"; 1237 }; 1238 1239 i2c_5: i2c@7af5000 { 1240 compatible = "qcom,i2c-qup-v2.2.1"; 1241 reg = <0x7af5000 0x600>; 1242 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1243 clock-names = "core", "iface"; 1244 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1245 <&gcc GCC_BLSP2_AHB_CLK>; 1246 pinctrl-names = "default", "sleep"; 1247 pinctrl-0 = <&i2c_5_default>; 1248 pinctrl-1 = <&i2c_5_sleep>; 1249 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 1253 status = "disabled"; 1254 }; 1255 1256 i2c_6: i2c@7af6000 { 1257 compatible = "qcom,i2c-qup-v2.2.1"; 1258 reg = <0x7af6000 0x600>; 1259 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1260 clock-names = "core", "iface"; 1261 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1262 <&gcc GCC_BLSP2_AHB_CLK>; 1263 pinctrl-names = "default", "sleep"; 1264 pinctrl-0 = <&i2c_6_default>; 1265 pinctrl-1 = <&i2c_6_sleep>; 1266 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 status = "disabled"; 1271 }; 1272 1273 i2c_7: i2c@7af7000 { 1274 compatible = "qcom,i2c-qup-v2.2.1"; 1275 reg = <0x7af7000 0x600>; 1276 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1277 clock-names = "core", "iface"; 1278 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1279 <&gcc GCC_BLSP2_AHB_CLK>; 1280 pinctrl-names = "default", "sleep"; 1281 pinctrl-0 = <&i2c_7_default>; 1282 pinctrl-1 = <&i2c_7_sleep>; 1283 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 status = "disabled"; 1288 }; 1289 1290 i2c_8: i2c@7af8000 { 1291 compatible = "qcom,i2c-qup-v2.2.1"; 1292 reg = <0x7af8000 0x600>; 1293 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1294 clock-names = "core", "iface"; 1295 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1296 <&gcc GCC_BLSP2_AHB_CLK>; 1297 pinctrl-names = "default", "sleep"; 1298 pinctrl-0 = <&i2c_8_default>; 1299 pinctrl-1 = <&i2c_8_sleep>; 1300 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 status = "disabled"; 1305 }; 1306 1307 intc: interrupt-controller@b000000 { 1308 compatible = "qcom,msm-qgic2"; 1309 interrupt-controller; 1310 #interrupt-cells = <3>; 1311 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1312 }; 1313 1314 apcs: mailbox@b011000 { 1315 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1316 reg = <0xb011000 0x1000>; 1317 #mbox-cells = <1>; 1318 }; 1319 1320 timer@b120000 { 1321 compatible = "arm,armv7-timer-mem"; 1322 reg = <0xb120000 0x1000>; 1323 #address-cells = <0x01>; 1324 #size-cells = <0x01>; 1325 ranges; 1326 1327 frame@b121000 { 1328 frame-number = <0>; 1329 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1331 reg = <0xb121000 0x1000>, 1332 <0xb122000 0x1000>; 1333 }; 1334 1335 frame@b123000 { 1336 frame-number = <1>; 1337 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1338 reg = <0xb123000 0x1000>; 1339 status = "disabled"; 1340 }; 1341 1342 frame@b124000 { 1343 frame-number = <2>; 1344 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1345 reg = <0xb124000 0x1000>; 1346 status = "disabled"; 1347 }; 1348 1349 frame@b125000 { 1350 frame-number = <3>; 1351 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1352 reg = <0xb125000 0x1000>; 1353 status = "disabled"; 1354 }; 1355 1356 frame@b126000 { 1357 frame-number = <4>; 1358 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1359 reg = <0xb126000 0x1000>; 1360 status = "disabled"; 1361 }; 1362 1363 frame@b127000 { 1364 frame-number = <5>; 1365 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1366 reg = <0xb127000 0x1000>; 1367 status = "disabled"; 1368 }; 1369 1370 frame@b128000 { 1371 frame-number = <6>; 1372 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1373 reg = <0xb128000 0x1000>; 1374 status = "disabled"; 1375 }; 1376 }; 1377 }; 1378 1379 thermal-zones { 1380 cpu0-thermal { 1381 polling-delay-passive = <250>; 1382 polling-delay = <1000>; 1383 thermal-sensors = <&tsens0 9>; 1384 trips { 1385 cpu0_alert: trip-point0 { 1386 temperature = <80000>; 1387 hysteresis = <2000>; 1388 type = "passive"; 1389 }; 1390 cpu0_crit: crit { 1391 temperature = <100000>; 1392 hysteresis = <2000>; 1393 type = "critical"; 1394 }; 1395 }; 1396 cooling-maps { 1397 map0 { 1398 trip = <&cpu0_alert>; 1399 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1400 }; 1401 }; 1402 }; 1403 cpu1-thermal { 1404 polling-delay-passive = <250>; 1405 polling-delay = <1000>; 1406 thermal-sensors = <&tsens0 10>; 1407 trips { 1408 cpu1_alert: trip-point0 { 1409 temperature = <80000>; 1410 hysteresis = <2000>; 1411 type = "passive"; 1412 }; 1413 cpu1_crit: crit { 1414 temperature = <100000>; 1415 hysteresis = <2000>; 1416 type = "critical"; 1417 }; 1418 }; 1419 cooling-maps { 1420 map0 { 1421 trip = <&cpu1_alert>; 1422 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1423 }; 1424 }; 1425 }; 1426 cpu2-thermal { 1427 polling-delay-passive = <250>; 1428 polling-delay = <1000>; 1429 thermal-sensors = <&tsens0 11>; 1430 trips { 1431 cpu2_alert: trip-point0 { 1432 temperature = <80000>; 1433 hysteresis = <2000>; 1434 type = "passive"; 1435 }; 1436 cpu2_crit: crit { 1437 temperature = <100000>; 1438 hysteresis = <2000>; 1439 type = "critical"; 1440 }; 1441 }; 1442 cooling-maps { 1443 map0 { 1444 trip = <&cpu2_alert>; 1445 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1446 }; 1447 }; 1448 }; 1449 cpu3-thermal { 1450 polling-delay-passive = <250>; 1451 polling-delay = <1000>; 1452 thermal-sensors = <&tsens0 12>; 1453 trips { 1454 cpu3_alert: trip-point0 { 1455 temperature = <80000>; 1456 hysteresis = <2000>; 1457 type = "passive"; 1458 }; 1459 cpu3_crit: crit { 1460 temperature = <100000>; 1461 hysteresis = <2000>; 1462 type = "critical"; 1463 }; 1464 }; 1465 cooling-maps { 1466 map0 { 1467 trip = <&cpu3_alert>; 1468 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1469 }; 1470 }; 1471 }; 1472 cpu4-thermal { 1473 polling-delay-passive = <250>; 1474 polling-delay = <1000>; 1475 thermal-sensors = <&tsens0 4>; 1476 trips { 1477 cpu4_alert: trip-point0 { 1478 temperature = <80000>; 1479 hysteresis = <2000>; 1480 type = "passive"; 1481 }; 1482 cpu4_crit: crit { 1483 temperature = <100000>; 1484 hysteresis = <2000>; 1485 type = "critical"; 1486 }; 1487 }; 1488 cooling-maps { 1489 map0 { 1490 trip = <&cpu4_alert>; 1491 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1492 }; 1493 }; 1494 }; 1495 cpu5-thermal { 1496 polling-delay-passive = <250>; 1497 polling-delay = <1000>; 1498 thermal-sensors = <&tsens0 5>; 1499 trips { 1500 cpu5_alert: trip-point0 { 1501 temperature = <80000>; 1502 hysteresis = <2000>; 1503 type = "passive"; 1504 }; 1505 cpu5_crit: crit { 1506 temperature = <100000>; 1507 hysteresis = <2000>; 1508 type = "critical"; 1509 }; 1510 }; 1511 cooling-maps { 1512 map0 { 1513 trip = <&cpu5_alert>; 1514 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1515 }; 1516 }; 1517 }; 1518 cpu6-thermal { 1519 polling-delay-passive = <250>; 1520 polling-delay = <1000>; 1521 thermal-sensors = <&tsens0 6>; 1522 trips { 1523 cpu6_alert: trip-point0 { 1524 temperature = <80000>; 1525 hysteresis = <2000>; 1526 type = "passive"; 1527 }; 1528 cpu6_crit: crit { 1529 temperature = <100000>; 1530 hysteresis = <2000>; 1531 type = "critical"; 1532 }; 1533 }; 1534 cooling-maps { 1535 map0 { 1536 trip = <&cpu6_alert>; 1537 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1538 }; 1539 }; 1540 }; 1541 cpu7-thermal { 1542 polling-delay-passive = <250>; 1543 polling-delay = <1000>; 1544 thermal-sensors = <&tsens0 7>; 1545 trips { 1546 cpu7_alert: trip-point0 { 1547 temperature = <80000>; 1548 hysteresis = <2000>; 1549 type = "passive"; 1550 }; 1551 cpu7_crit: crit { 1552 temperature = <100000>; 1553 hysteresis = <2000>; 1554 type = "critical"; 1555 }; 1556 }; 1557 cooling-maps { 1558 map0 { 1559 trip = <&cpu7_alert>; 1560 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 timer { 1567 compatible = "arm,armv8-timer"; 1568 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1569 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1570 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1571 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1572 }; 1573}; 1574