1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,gcc-msm8953.h> 5#include <dt-bindings/clock/qcom,rpmcc.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/soc/qcom,apr.h> 10#include <dt-bindings/sound/qcom,q6afe.h> 11#include <dt-bindings/sound/qcom,q6asm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 sleep_clk: sleep-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <32768>; 27 }; 28 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 clock-output-names = "xo"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 next-level-cache = <&L2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 CPU1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x1>; 55 enable-method = "psci"; 56 capacity-dmips-mhz = <1024>; 57 next-level-cache = <&L2_0>; 58 #cooling-cells = <2>; 59 }; 60 61 CPU2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x2>; 65 enable-method = "psci"; 66 capacity-dmips-mhz = <1024>; 67 next-level-cache = <&L2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 #cooling-cells = <2>; 79 }; 80 81 CPU4: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x100>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <1024>; 87 next-level-cache = <&L2_1>; 88 #cooling-cells = <2>; 89 }; 90 91 CPU5: cpu@101 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x101>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <1024>; 97 next-level-cache = <&L2_1>; 98 #cooling-cells = <2>; 99 }; 100 101 CPU6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x102>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&L2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1024>; 117 next-level-cache = <&L2_1>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu-map { 122 cluster0 { 123 core0 { 124 cpu = <&CPU0>; 125 }; 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 core2 { 130 cpu = <&CPU2>; 131 }; 132 core3 { 133 cpu = <&CPU3>; 134 }; 135 }; 136 137 cluster1 { 138 core0 { 139 cpu = <&CPU4>; 140 }; 141 core1 { 142 cpu = <&CPU5>; 143 }; 144 core2 { 145 cpu = <&CPU6>; 146 }; 147 core3 { 148 cpu = <&CPU7>; 149 }; 150 }; 151 }; 152 153 L2_0: l2-cache-0 { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 }; 158 159 L2_1: l2-cache-1 { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 }; 164 }; 165 166 firmware { 167 scm: scm { 168 compatible = "qcom,scm-msm8953", "qcom,scm"; 169 clocks = <&gcc GCC_CRYPTO_CLK>, 170 <&gcc GCC_CRYPTO_AXI_CLK>, 171 <&gcc GCC_CRYPTO_AHB_CLK>; 172 clock-names = "core", "bus", "iface"; 173 #reset-cells = <1>; 174 }; 175 }; 176 177 memory { 178 device_type = "memory"; 179 /* We expect the bootloader to fill in the reg */ 180 reg = <0 0 0 0>; 181 }; 182 183 pmu { 184 compatible = "arm,cortex-a53-pmu"; 185 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 psci { 189 compatible = "arm,psci-1.0"; 190 method = "smc"; 191 }; 192 193 reserved-memory { 194 #address-cells = <2>; 195 #size-cells = <2>; 196 ranges; 197 198 zap_shader_region: zap@81800000 { 199 compatible = "shared-dma-pool"; 200 reg = <0x0 0x81800000 0x0 0x2000>; 201 no-map; 202 }; 203 204 qseecom_mem: qseecom@85b00000 { 205 reg = <0x0 0x85b00000 0x0 0x800000>; 206 no-map; 207 }; 208 209 smem_mem: smem@86300000 { 210 compatible = "qcom,smem"; 211 reg = <0x0 0x86300000 0x0 0x100000>; 212 qcom,rpm-msg-ram = <&rpm_msg_ram>; 213 hwlocks = <&tcsr_mutex 3>; 214 no-map; 215 }; 216 217 reserved@86400000 { 218 reg = <0x0 0x86400000 0x0 0x400000>; 219 no-map; 220 }; 221 222 mpss_mem: mpss@86c00000 { 223 reg = <0x0 0x86c00000 0x0 0x6a00000>; 224 no-map; 225 }; 226 227 adsp_fw_mem: adsp@8d600000 { 228 reg = <0x0 0x8d600000 0x0 0x1100000>; 229 no-map; 230 }; 231 232 wcnss_fw_mem: wcnss@8e700000 { 233 reg = <0x0 0x8e700000 0x0 0x700000>; 234 no-map; 235 }; 236 237 dfps_data_mem: dfps-data@90000000 { 238 reg = <0 0x90000000 0 0x1000>; 239 no-map; 240 }; 241 242 cont_splash_mem: cont-splash@90001000 { 243 reg = <0x0 0x90001000 0x0 0x13ff000>; 244 no-map; 245 }; 246 247 venus_mem: venus@91400000 { 248 reg = <0x0 0x91400000 0x0 0x700000>; 249 no-map; 250 }; 251 252 mba_mem: mba@92000000 { 253 reg = <0x0 0x92000000 0x0 0x100000>; 254 no-map; 255 }; 256 257 rmtfs@f2d00000 { 258 compatible = "qcom,rmtfs-mem"; 259 reg = <0x0 0xf2d00000 0x0 0x180000>; 260 no-map; 261 262 qcom,client-id = <1>; 263 }; 264 }; 265 266 smd { 267 compatible = "qcom,smd"; 268 269 rpm { 270 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 271 qcom,ipc = <&apcs 8 0>; 272 qcom,smd-edge = <15>; 273 274 rpm_requests: rpm-requests { 275 compatible = "qcom,rpm-msm8953"; 276 qcom,smd-channels = "rpm_requests"; 277 278 rpmcc: clock-controller { 279 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 280 clocks = <&xo_board>; 281 clock-names = "xo"; 282 #clock-cells = <1>; 283 }; 284 285 rpmpd: power-controller { 286 compatible = "qcom,msm8953-rpmpd"; 287 #power-domain-cells = <1>; 288 operating-points-v2 = <&rpmpd_opp_table>; 289 290 rpmpd_opp_table: opp-table { 291 compatible = "operating-points-v2"; 292 293 rpmpd_opp_ret: opp1 { 294 opp-level = <RPM_SMD_LEVEL_RETENTION>; 295 }; 296 297 rpmpd_opp_ret_plus: opp2 { 298 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 299 }; 300 301 rpmpd_opp_min_svs: opp3 { 302 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 303 }; 304 305 rpmpd_opp_low_svs: opp4 { 306 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 307 }; 308 309 rpmpd_opp_svs: opp5 { 310 opp-level = <RPM_SMD_LEVEL_SVS>; 311 }; 312 313 rpmpd_opp_svs_plus: opp6 { 314 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 315 }; 316 317 rpmpd_opp_nom: opp7 { 318 opp-level = <RPM_SMD_LEVEL_NOM>; 319 }; 320 321 rpmpd_opp_nom_plus: opp8 { 322 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 323 }; 324 325 rpmpd_opp_turbo: opp9 { 326 opp-level = <RPM_SMD_LEVEL_TURBO>; 327 }; 328 }; 329 }; 330 }; 331 }; 332 }; 333 334 smp2p-adsp { 335 compatible = "qcom,smp2p"; 336 qcom,smem = <443>, <429>; 337 338 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 339 340 mboxes = <&apcs 10>; 341 342 qcom,local-pid = <0>; 343 qcom,remote-pid = <2>; 344 345 smp2p_adsp_out: master-kernel { 346 qcom,entry-name = "master-kernel"; 347 #qcom,smem-state-cells = <1>; 348 }; 349 350 smp2p_adsp_in: slave-kernel { 351 qcom,entry-name = "slave-kernel"; 352 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 }; 357 358 smp2p-modem { 359 compatible = "qcom,smp2p"; 360 qcom,smem = <435>, <428>; 361 362 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 363 364 qcom,ipc = <&apcs 8 14>; 365 366 qcom,local-pid = <0>; 367 qcom,remote-pid = <1>; 368 369 smp2p_modem_out: master-kernel { 370 qcom,entry-name = "master-kernel"; 371 372 #qcom,smem-state-cells = <1>; 373 }; 374 375 smp2p_modem_in: slave-kernel { 376 qcom,entry-name = "slave-kernel"; 377 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 }; 382 383 smp2p-wcnss { 384 compatible = "qcom,smp2p"; 385 qcom,smem = <451>, <431>; 386 387 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 388 389 qcom,ipc = <&apcs 8 18>; 390 391 qcom,local-pid = <0>; 392 qcom,remote-pid = <4>; 393 394 smp2p_wcnss_out: master-kernel { 395 qcom,entry-name = "master-kernel"; 396 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 smp2p_wcnss_in: slave-kernel { 401 qcom,entry-name = "slave-kernel"; 402 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 smsm { 409 compatible = "qcom,smsm"; 410 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 qcom,ipc-1 = <&apcs 8 13>; 415 qcom,ipc-3 = <&apcs 8 19>; 416 417 apps_smsm: apps@0 { 418 reg = <0>; 419 420 #qcom,smem-state-cells = <1>; 421 }; 422 423 modem_smsm: modem@1 { 424 reg = <1>; 425 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 426 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 wcnss_smsm: wcnss@6 { 432 reg = <6>; 433 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 434 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 soc: soc@0 { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0 0 0 0xffffffff>; 444 compatible = "simple-bus"; 445 446 rpm_msg_ram: sram@60000 { 447 compatible = "qcom,rpm-msg-ram"; 448 reg = <0x00060000 0x8000>; 449 }; 450 451 hsusb_phy: phy@79000 { 452 compatible = "qcom,msm8953-qusb2-phy"; 453 reg = <0x00079000 0x180>; 454 #phy-cells = <0>; 455 456 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 457 <&gcc GCC_QUSB_REF_CLK>; 458 clock-names = "cfg_ahb", "ref"; 459 460 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 461 462 resets = <&gcc GCC_QUSB2_PHY_BCR>; 463 464 status = "disabled"; 465 }; 466 467 rng@e3000 { 468 compatible = "qcom,prng"; 469 reg = <0x000e3000 0x1000>; 470 clocks = <&gcc GCC_PRNG_AHB_CLK>; 471 clock-names = "core"; 472 }; 473 474 tsens0: thermal-sensor@4a9000 { 475 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 476 reg = <0x004a9000 0x1000>, /* TM */ 477 <0x004a8000 0x1000>; /* SROT */ 478 #qcom,sensors = <16>; 479 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "uplow", "critical"; 482 #thermal-sensor-cells = <1>; 483 }; 484 485 restart@4ab000 { 486 compatible = "qcom,pshold"; 487 reg = <0x004ab000 0x4>; 488 }; 489 490 tlmm: pinctrl@1000000 { 491 compatible = "qcom,msm8953-pinctrl"; 492 reg = <0x01000000 0x300000>; 493 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 494 gpio-controller; 495 gpio-ranges = <&tlmm 0 0 142>; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 500 uart_console_active: uart-console-active-state { 501 pins = "gpio4", "gpio5"; 502 function = "blsp_uart2"; 503 drive-strength = <2>; 504 bias-disable; 505 }; 506 507 uart_console_sleep: uart-console-sleep-state { 508 pins = "gpio4", "gpio5"; 509 function = "blsp_uart2"; 510 drive-strength = <2>; 511 bias-pull-down; 512 }; 513 514 sdc1_clk_on: sdc1-clk-on-state { 515 pins = "sdc1_clk"; 516 bias-disable; 517 drive-strength = <16>; 518 }; 519 520 sdc1_clk_off: sdc1-clk-off-state { 521 pins = "sdc1_clk"; 522 bias-disable; 523 drive-strength = <2>; 524 }; 525 526 sdc1_cmd_on: sdc1-cmd-on-state { 527 pins = "sdc1_cmd"; 528 bias-disable; 529 drive-strength = <10>; 530 }; 531 532 sdc1_cmd_off: sdc1-cmd-off-state { 533 pins = "sdc1_cmd"; 534 bias-disable; 535 drive-strength = <2>; 536 }; 537 538 sdc1_data_on: sdc1-data-on-state { 539 pins = "sdc1_data"; 540 bias-pull-up; 541 drive-strength = <10>; 542 }; 543 544 sdc1_data_off: sdc1-data-off-state { 545 pins = "sdc1_data"; 546 bias-pull-up; 547 drive-strength = <2>; 548 }; 549 550 sdc1_rclk_on: sdc1-rclk-on-state { 551 pins = "sdc1_rclk"; 552 bias-pull-down; 553 }; 554 555 sdc1_rclk_off: sdc1-rclk-off-state { 556 pins = "sdc1_rclk"; 557 bias-pull-down; 558 }; 559 560 sdc2_clk_on: sdc2-clk-on-state { 561 pins = "sdc2_clk"; 562 drive-strength = <16>; 563 bias-disable; 564 }; 565 566 sdc2_clk_off: sdc2-clk-off-state { 567 pins = "sdc2_clk"; 568 bias-disable; 569 drive-strength = <2>; 570 }; 571 572 sdc2_cmd_on: sdc2-cmd-on-state { 573 pins = "sdc2_cmd"; 574 bias-pull-up; 575 drive-strength = <10>; 576 }; 577 578 sdc2_cmd_off: sdc2-cmd-off-state { 579 pins = "sdc2_cmd"; 580 bias-pull-up; 581 drive-strength = <2>; 582 }; 583 584 sdc2_data_on: sdc2-data-on-state { 585 pins = "sdc2_data"; 586 bias-pull-up; 587 drive-strength = <10>; 588 }; 589 590 sdc2_data_off: sdc2-data-off-state { 591 pins = "sdc2_data"; 592 bias-pull-up; 593 drive-strength = <2>; 594 }; 595 596 sdc2_cd_on: cd-on-state { 597 pins = "gpio133"; 598 function = "gpio"; 599 drive-strength = <2>; 600 bias-pull-up; 601 }; 602 603 sdc2_cd_off: cd-off-state { 604 pins = "gpio133"; 605 function = "gpio"; 606 drive-strength = <2>; 607 bias-disable; 608 }; 609 610 gpio_key_default: gpio-key-default-state { 611 pins = "gpio85"; 612 function = "gpio"; 613 drive-strength = <2>; 614 bias-pull-up; 615 }; 616 617 i2c_1_default: i2c-1-default-state { 618 pins = "gpio2", "gpio3"; 619 function = "blsp_i2c1"; 620 drive-strength = <2>; 621 bias-disable; 622 }; 623 624 i2c_1_sleep: i2c-1-sleep-state { 625 pins = "gpio2", "gpio3"; 626 function = "gpio"; 627 drive-strength = <2>; 628 bias-disable; 629 }; 630 631 i2c_2_default: i2c-2-default-state { 632 pins = "gpio6", "gpio7"; 633 function = "blsp_i2c2"; 634 drive-strength = <2>; 635 bias-disable; 636 }; 637 638 i2c_2_sleep: i2c-2-sleep-state { 639 pins = "gpio6", "gpio7"; 640 function = "gpio"; 641 drive-strength = <2>; 642 bias-disable; 643 }; 644 645 i2c_3_default: i2c-3-default-state { 646 pins = "gpio10", "gpio11"; 647 function = "blsp_i2c3"; 648 drive-strength = <2>; 649 bias-disable; 650 }; 651 652 i2c_3_sleep: i2c-3-sleep-state { 653 pins = "gpio10", "gpio11"; 654 function = "gpio"; 655 drive-strength = <2>; 656 bias-disable; 657 }; 658 659 i2c_4_default: i2c-4-default-state { 660 pins = "gpio14", "gpio15"; 661 function = "blsp_i2c4"; 662 drive-strength = <2>; 663 bias-disable; 664 }; 665 666 i2c_4_sleep: i2c-4-sleep-state { 667 pins = "gpio14", "gpio15"; 668 function = "gpio"; 669 drive-strength = <2>; 670 bias-disable; 671 }; 672 673 i2c_5_default: i2c-5-default-state { 674 pins = "gpio18", "gpio19"; 675 function = "blsp_i2c5"; 676 drive-strength = <2>; 677 bias-disable; 678 }; 679 680 i2c_5_sleep: i2c-5-sleep-state { 681 pins = "gpio18", "gpio19"; 682 function = "gpio"; 683 drive-strength = <2>; 684 bias-disable; 685 }; 686 687 i2c_6_default: i2c-6-default-state { 688 pins = "gpio22", "gpio23"; 689 function = "blsp_i2c6"; 690 drive-strength = <2>; 691 bias-disable; 692 }; 693 694 i2c_6_sleep: i2c-6-sleep-state { 695 pins = "gpio22", "gpio23"; 696 function = "gpio"; 697 drive-strength = <2>; 698 bias-disable; 699 }; 700 701 i2c_7_default: i2c-7-default-state { 702 pins = "gpio135", "gpio136"; 703 function = "blsp_i2c7"; 704 drive-strength = <2>; 705 bias-disable; 706 }; 707 708 i2c_7_sleep: i2c-7-sleep-state { 709 pins = "gpio135", "gpio136"; 710 function = "gpio"; 711 drive-strength = <2>; 712 bias-disable; 713 }; 714 715 i2c_8_default: i2c-8-default-state { 716 pins = "gpio98", "gpio99"; 717 function = "blsp_i2c8"; 718 drive-strength = <2>; 719 bias-disable; 720 }; 721 722 i2c_8_sleep: i2c-8-sleep-state { 723 pins = "gpio98", "gpio99"; 724 function = "gpio"; 725 drive-strength = <2>; 726 bias-disable; 727 }; 728 729 wcnss_pin_a: wcnss-active-state { 730 731 wcss-wlan2-pins { 732 pins = "gpio76"; 733 function = "wcss_wlan2"; 734 drive-strength = <6>; 735 bias-pull-up; 736 }; 737 738 wcss-wlan1-pins { 739 pins = "gpio77"; 740 function = "wcss_wlan1"; 741 drive-strength = <6>; 742 bias-pull-up; 743 }; 744 745 wcss-wlan0-pins { 746 pins = "gpio78"; 747 function = "wcss_wlan0"; 748 drive-strength = <6>; 749 bias-pull-up; 750 }; 751 752 wcss-wlan-pins { 753 pins = "gpio79", "gpio80"; 754 function = "wcss_wlan"; 755 drive-strength = <6>; 756 bias-pull-up; 757 }; 758 }; 759 }; 760 761 gcc: clock-controller@1800000 { 762 compatible = "qcom,gcc-msm8953"; 763 reg = <0x01800000 0x80000>; 764 #clock-cells = <1>; 765 #reset-cells = <1>; 766 #power-domain-cells = <1>; 767 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 768 <&sleep_clk>, 769 <&dsi0_phy 1>, 770 <&dsi0_phy 0>, 771 <&dsi1_phy 1>, 772 <&dsi1_phy 0>; 773 clock-names = "xo", 774 "sleep", 775 "dsi0pll", 776 "dsi0pllbyte", 777 "dsi1pll", 778 "dsi1pllbyte"; 779 }; 780 781 tcsr_mutex: hwlock@1905000 { 782 compatible = "qcom,tcsr-mutex"; 783 reg = <0x01905000 0x20000>; 784 #hwlock-cells = <1>; 785 }; 786 787 tcsr: syscon@1937000 { 788 compatible = "qcom,tcsr-msm8953", "syscon"; 789 reg = <0x01937000 0x30000>; 790 }; 791 792 tcsr_phy_clk_scheme_sel: syscon@193f044 { 793 compatible = "qcom,tcsr-msm8953", "syscon"; 794 reg = <0x0193f044 0x4>; 795 }; 796 797 mdss: display-subsystem@1a00000 { 798 compatible = "qcom,mdss"; 799 800 reg = <0x01a00000 0x1000>, 801 <0x01ab0000 0x1040>; 802 reg-names = "mdss_phys", 803 "vbif_phys"; 804 805 power-domains = <&gcc MDSS_GDSC>; 806 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 807 808 interrupt-controller; 809 #interrupt-cells = <1>; 810 811 clocks = <&gcc GCC_MDSS_AHB_CLK>, 812 <&gcc GCC_MDSS_AXI_CLK>, 813 <&gcc GCC_MDSS_VSYNC_CLK>, 814 <&gcc GCC_MDSS_MDP_CLK>; 815 clock-names = "iface", 816 "bus", 817 "vsync", 818 "core"; 819 820 #address-cells = <1>; 821 #size-cells = <1>; 822 ranges; 823 824 status = "disabled"; 825 826 mdp: display-controller@1a01000 { 827 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 828 reg = <0x01a01000 0x89000>; 829 reg-names = "mdp_phys"; 830 831 interrupt-parent = <&mdss>; 832 interrupts = <0>; 833 834 power-domains = <&gcc MDSS_GDSC>; 835 836 clocks = <&gcc GCC_MDSS_AHB_CLK>, 837 <&gcc GCC_MDSS_AXI_CLK>, 838 <&gcc GCC_MDSS_MDP_CLK>, 839 <&gcc GCC_MDSS_VSYNC_CLK>; 840 clock-names = "iface", 841 "bus", 842 "core", 843 "vsync"; 844 845 iommus = <&apps_iommu 0x15>; 846 847 ports { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 851 port@0 { 852 reg = <0>; 853 mdp5_intf1_out: endpoint { 854 remote-endpoint = <&dsi0_in>; 855 }; 856 }; 857 858 port@1 { 859 reg = <1>; 860 mdp5_intf2_out: endpoint { 861 remote-endpoint = <&dsi1_in>; 862 }; 863 }; 864 }; 865 }; 866 867 dsi0: dsi@1a94000 { 868 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 869 reg = <0x01a94000 0x400>; 870 reg-names = "dsi_ctrl"; 871 872 interrupt-parent = <&mdss>; 873 interrupts = <4>; 874 875 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 876 <&gcc PCLK0_CLK_SRC>; 877 assigned-clock-parents = <&dsi0_phy 0>, 878 <&dsi0_phy 1>; 879 880 clocks = <&gcc GCC_MDSS_MDP_CLK>, 881 <&gcc GCC_MDSS_AHB_CLK>, 882 <&gcc GCC_MDSS_AXI_CLK>, 883 <&gcc GCC_MDSS_BYTE0_CLK>, 884 <&gcc GCC_MDSS_PCLK0_CLK>, 885 <&gcc GCC_MDSS_ESC0_CLK>; 886 clock-names = "mdp_core", 887 "iface", 888 "bus", 889 "byte", 890 "pixel", 891 "core"; 892 893 phys = <&dsi0_phy>; 894 895 #address-cells = <1>; 896 #size-cells = <0>; 897 898 status = "disabled"; 899 900 ports { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 port@0 { 905 reg = <0>; 906 dsi0_in: endpoint { 907 remote-endpoint = <&mdp5_intf1_out>; 908 }; 909 }; 910 911 port@1 { 912 reg = <1>; 913 dsi0_out: endpoint { 914 }; 915 }; 916 }; 917 }; 918 919 dsi0_phy: phy@1a94400 { 920 compatible = "qcom,dsi-phy-14nm-8953"; 921 reg = <0x01a94400 0x100>, 922 <0x01a94500 0x300>, 923 <0x01a94800 0x188>; 924 reg-names = "dsi_phy", 925 "dsi_phy_lane", 926 "dsi_pll"; 927 928 #clock-cells = <1>; 929 #phy-cells = <0>; 930 931 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 932 clock-names = "iface", "ref"; 933 934 status = "disabled"; 935 }; 936 937 dsi1: dsi@1a96000 { 938 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 939 reg = <0x01a96000 0x400>; 940 reg-names = "dsi_ctrl"; 941 942 interrupt-parent = <&mdss>; 943 interrupts = <5>; 944 945 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 946 <&gcc PCLK1_CLK_SRC>; 947 assigned-clock-parents = <&dsi1_phy 0>, 948 <&dsi1_phy 1>; 949 950 clocks = <&gcc GCC_MDSS_MDP_CLK>, 951 <&gcc GCC_MDSS_AHB_CLK>, 952 <&gcc GCC_MDSS_AXI_CLK>, 953 <&gcc GCC_MDSS_BYTE1_CLK>, 954 <&gcc GCC_MDSS_PCLK1_CLK>, 955 <&gcc GCC_MDSS_ESC1_CLK>; 956 clock-names = "mdp_core", 957 "iface", 958 "bus", 959 "byte", 960 "pixel", 961 "core"; 962 963 phys = <&dsi1_phy>; 964 965 status = "disabled"; 966 967 ports { 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 port@0 { 972 reg = <0>; 973 dsi1_in: endpoint { 974 remote-endpoint = <&mdp5_intf2_out>; 975 }; 976 }; 977 978 port@1 { 979 reg = <1>; 980 dsi1_out: endpoint { 981 }; 982 }; 983 }; 984 }; 985 986 dsi1_phy: phy@1a96400 { 987 compatible = "qcom,dsi-phy-14nm-8953"; 988 reg = <0x01a96400 0x100>, 989 <0x01a96500 0x300>, 990 <0x01a96800 0x188>; 991 reg-names = "dsi_phy", 992 "dsi_phy_lane", 993 "dsi_pll"; 994 995 #clock-cells = <1>; 996 #phy-cells = <0>; 997 998 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 999 clock-names = "iface", "ref"; 1000 1001 status = "disabled"; 1002 }; 1003 }; 1004 1005 apps_iommu: iommu@1e00000 { 1006 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1007 ranges = <0 0x01e20000 0x20000>; 1008 1009 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1010 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1011 clock-names = "iface", "bus"; 1012 1013 qcom,iommu-secure-id = <17>; 1014 1015 #address-cells = <1>; 1016 #iommu-cells = <1>; 1017 #size-cells = <1>; 1018 1019 /* VFE */ 1020 iommu-ctx@14000 { 1021 compatible = "qcom,msm-iommu-v1-ns"; 1022 reg = <0x14000 0x1000>; 1023 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1024 }; 1025 1026 /* MDP_0 */ 1027 iommu-ctx@15000 { 1028 compatible = "qcom,msm-iommu-v1-ns"; 1029 reg = <0x15000 0x1000>; 1030 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1031 }; 1032 1033 /* VENUS_NS */ 1034 iommu-ctx@16000 { 1035 compatible = "qcom,msm-iommu-v1-ns"; 1036 reg = <0x16000 0x1000>; 1037 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1038 }; 1039 }; 1040 1041 spmi_bus: spmi@200f000 { 1042 compatible = "qcom,spmi-pmic-arb"; 1043 reg = <0x0200f000 0x1000>, 1044 <0x02400000 0x800000>, 1045 <0x02c00000 0x800000>, 1046 <0x03800000 0x200000>, 1047 <0x0200a000 0x2100>; 1048 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1049 interrupt-names = "periph_irq"; 1050 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1051 qcom,ee = <0>; 1052 qcom,channel = <0>; 1053 interrupt-controller; 1054 1055 #interrupt-cells = <4>; 1056 #address-cells = <2>; 1057 #size-cells = <0>; 1058 }; 1059 1060 mpss: remoteproc@4080000 { 1061 compatible = "qcom,msm8953-mss-pil"; 1062 reg = <0x04080000 0x100>, 1063 <0x04020000 0x040>; 1064 reg-names = "qdsp6", "rmb"; 1065 1066 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1067 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1068 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1069 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1070 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1071 interrupt-names = "wdog", "fatal", "ready", 1072 "handover", "stop-ack"; 1073 1074 power-domains = <&rpmpd MSM8953_VDDCX>, 1075 <&rpmpd MSM8953_VDDMX>, 1076 <&rpmpd MSM8953_VDDMD>; 1077 power-domain-names = "cx", "mx","mss"; 1078 1079 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1080 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1081 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1082 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1083 clock-names = "iface", "bus", "mem", "xo"; 1084 1085 qcom,smem-states = <&smp2p_modem_out 0>; 1086 qcom,smem-state-names = "stop"; 1087 1088 resets = <&gcc GCC_MSS_BCR>; 1089 reset-names = "mss_restart"; 1090 1091 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1092 1093 status = "disabled"; 1094 1095 mba { 1096 memory-region = <&mba_mem>; 1097 }; 1098 1099 mpss { 1100 memory-region = <&mpss_mem>; 1101 }; 1102 1103 smd-edge { 1104 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1105 1106 qcom,smd-edge = <0>; 1107 qcom,ipc = <&apcs 8 12>; 1108 qcom,remote-pid = <1>; 1109 1110 label = "modem"; 1111 }; 1112 }; 1113 1114 usb3: usb@70f8800 { 1115 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1116 reg = <0x070f8800 0x400>; 1117 #address-cells = <1>; 1118 #size-cells = <1>; 1119 ranges; 1120 1121 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1123 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1124 1125 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1126 <&gcc GCC_USB30_MASTER_CLK>, 1127 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1128 <&gcc GCC_USB30_SLEEP_CLK>, 1129 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1130 clock-names = "cfg_noc", 1131 "core", 1132 "iface", 1133 "sleep", 1134 "mock_utmi"; 1135 1136 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1137 <&gcc GCC_USB30_MASTER_CLK>; 1138 assigned-clock-rates = <19200000>, <133330000>; 1139 1140 power-domains = <&gcc USB30_GDSC>; 1141 1142 qcom,select-utmi-as-pipe-clk; 1143 1144 status = "disabled"; 1145 1146 usb3_dwc3: usb@7000000 { 1147 compatible = "snps,dwc3"; 1148 reg = <0x07000000 0xcc00>; 1149 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1150 phys = <&hsusb_phy>; 1151 phy-names = "usb2-phy"; 1152 1153 snps,usb2-gadget-lpm-disable; 1154 snps,dis-u1-entry-quirk; 1155 snps,dis-u2-entry-quirk; 1156 snps,is-utmi-l1-suspend; 1157 snps,hird-threshold = /bits/ 8 <0x00>; 1158 1159 maximum-speed = "high-speed"; 1160 }; 1161 }; 1162 1163 sdhc_1: mmc@7824900 { 1164 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1165 1166 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1167 reg-names = "hc", "core"; 1168 1169 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "hc_irq", "pwr_irq"; 1172 1173 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1174 <&gcc GCC_SDCC1_APPS_CLK>, 1175 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1176 clock-names = "iface", "core", "xo"; 1177 1178 power-domains = <&rpmpd MSM8953_VDDCX>; 1179 operating-points-v2 = <&sdhc1_opp_table>; 1180 1181 pinctrl-names = "default", "sleep"; 1182 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1183 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1184 1185 mmc-hs400-1_8v; 1186 mmc-hs200-1_8v; 1187 mmc-ddr-1_8v; 1188 bus-width = <8>; 1189 non-removable; 1190 1191 status = "disabled"; 1192 1193 sdhc1_opp_table: opp-table-sdhc1 { 1194 compatible = "operating-points-v2"; 1195 1196 opp-25000000 { 1197 opp-hz = /bits/ 64 <25000000>; 1198 required-opps = <&rpmpd_opp_low_svs>; 1199 }; 1200 1201 opp-50000000 { 1202 opp-hz = /bits/ 64 <50000000>; 1203 required-opps = <&rpmpd_opp_svs>; 1204 }; 1205 1206 opp-100000000 { 1207 opp-hz = /bits/ 64 <100000000>; 1208 required-opps = <&rpmpd_opp_svs>; 1209 }; 1210 1211 opp-192000000 { 1212 opp-hz = /bits/ 64 <192000000>; 1213 required-opps = <&rpmpd_opp_nom>; 1214 }; 1215 1216 opp-384000000 { 1217 opp-hz = /bits/ 64 <384000000>; 1218 required-opps = <&rpmpd_opp_nom>; 1219 }; 1220 }; 1221 }; 1222 1223 sdhc_2: mmc@7864900 { 1224 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1225 1226 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1227 reg-names = "hc", "core"; 1228 1229 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "hc_irq", "pwr_irq"; 1232 1233 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1234 <&gcc GCC_SDCC2_APPS_CLK>, 1235 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1236 clock-names = "iface", "core", "xo"; 1237 1238 power-domains = <&rpmpd MSM8953_VDDCX>; 1239 operating-points-v2 = <&sdhc2_opp_table>; 1240 1241 pinctrl-names = "default", "sleep"; 1242 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1243 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1244 1245 bus-width = <4>; 1246 1247 status = "disabled"; 1248 1249 sdhc2_opp_table: opp-table-sdhc2 { 1250 compatible = "operating-points-v2"; 1251 1252 opp-25000000 { 1253 opp-hz = /bits/ 64 <25000000>; 1254 required-opps = <&rpmpd_opp_low_svs>; 1255 }; 1256 1257 opp-50000000 { 1258 opp-hz = /bits/ 64 <50000000>; 1259 required-opps = <&rpmpd_opp_svs>; 1260 }; 1261 1262 opp-100000000 { 1263 opp-hz = /bits/ 64 <100000000>; 1264 required-opps = <&rpmpd_opp_svs>; 1265 }; 1266 1267 opp-177770000 { 1268 opp-hz = /bits/ 64 <177770000>; 1269 required-opps = <&rpmpd_opp_nom>; 1270 }; 1271 1272 opp-200000000 { 1273 opp-hz = /bits/ 64 <200000000>; 1274 required-opps = <&rpmpd_opp_nom>; 1275 }; 1276 }; 1277 }; 1278 1279 uart_0: serial@78af000 { 1280 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1281 reg = <0x078af000 0x200>; 1282 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1284 <&gcc GCC_BLSP1_AHB_CLK>; 1285 clock-names = "core", "iface"; 1286 1287 status = "disabled"; 1288 }; 1289 1290 i2c_1: i2c@78b5000 { 1291 compatible = "qcom,i2c-qup-v2.2.1"; 1292 reg = <0x078b5000 0x600>; 1293 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1294 clock-names = "core", "iface"; 1295 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1296 <&gcc GCC_BLSP1_AHB_CLK>; 1297 1298 pinctrl-names = "default", "sleep"; 1299 pinctrl-0 = <&i2c_1_default>; 1300 pinctrl-1 = <&i2c_1_sleep>; 1301 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 1305 status = "disabled"; 1306 }; 1307 1308 i2c_2: i2c@78b6000 { 1309 compatible = "qcom,i2c-qup-v2.2.1"; 1310 reg = <0x078b6000 0x600>; 1311 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1312 clock-names = "core", "iface"; 1313 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1314 <&gcc GCC_BLSP1_AHB_CLK>; 1315 1316 pinctrl-names = "default", "sleep"; 1317 pinctrl-0 = <&i2c_2_default>; 1318 pinctrl-1 = <&i2c_2_sleep>; 1319 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 1323 status = "disabled"; 1324 }; 1325 1326 i2c_3: i2c@78b7000 { 1327 compatible = "qcom,i2c-qup-v2.2.1"; 1328 reg = <0x078b7000 0x600>; 1329 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1330 clock-names = "core", "iface"; 1331 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1332 <&gcc GCC_BLSP1_AHB_CLK>; 1333 pinctrl-names = "default", "sleep"; 1334 pinctrl-0 = <&i2c_3_default>; 1335 pinctrl-1 = <&i2c_3_sleep>; 1336 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 1340 status = "disabled"; 1341 }; 1342 1343 i2c_4: i2c@78b8000 { 1344 compatible = "qcom,i2c-qup-v2.2.1"; 1345 reg = <0x078b8000 0x600>; 1346 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1347 clock-names = "core", "iface"; 1348 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1349 <&gcc GCC_BLSP1_AHB_CLK>; 1350 pinctrl-names = "default", "sleep"; 1351 pinctrl-0 = <&i2c_4_default>; 1352 pinctrl-1 = <&i2c_4_sleep>; 1353 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 1357 status = "disabled"; 1358 }; 1359 1360 i2c_5: i2c@7af5000 { 1361 compatible = "qcom,i2c-qup-v2.2.1"; 1362 reg = <0x07af5000 0x600>; 1363 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1364 clock-names = "core", "iface"; 1365 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1366 <&gcc GCC_BLSP2_AHB_CLK>; 1367 pinctrl-names = "default", "sleep"; 1368 pinctrl-0 = <&i2c_5_default>; 1369 pinctrl-1 = <&i2c_5_sleep>; 1370 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 1374 status = "disabled"; 1375 }; 1376 1377 i2c_6: i2c@7af6000 { 1378 compatible = "qcom,i2c-qup-v2.2.1"; 1379 reg = <0x07af6000 0x600>; 1380 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1381 clock-names = "core", "iface"; 1382 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1383 <&gcc GCC_BLSP2_AHB_CLK>; 1384 pinctrl-names = "default", "sleep"; 1385 pinctrl-0 = <&i2c_6_default>; 1386 pinctrl-1 = <&i2c_6_sleep>; 1387 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 1391 status = "disabled"; 1392 }; 1393 1394 i2c_7: i2c@7af7000 { 1395 compatible = "qcom,i2c-qup-v2.2.1"; 1396 reg = <0x07af7000 0x600>; 1397 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1398 clock-names = "core", "iface"; 1399 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1400 <&gcc GCC_BLSP2_AHB_CLK>; 1401 pinctrl-names = "default", "sleep"; 1402 pinctrl-0 = <&i2c_7_default>; 1403 pinctrl-1 = <&i2c_7_sleep>; 1404 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 1408 status = "disabled"; 1409 }; 1410 1411 i2c_8: i2c@7af8000 { 1412 compatible = "qcom,i2c-qup-v2.2.1"; 1413 reg = <0x07af8000 0x600>; 1414 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1415 clock-names = "core", "iface"; 1416 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1417 <&gcc GCC_BLSP2_AHB_CLK>; 1418 pinctrl-names = "default", "sleep"; 1419 pinctrl-0 = <&i2c_8_default>; 1420 pinctrl-1 = <&i2c_8_sleep>; 1421 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 1425 status = "disabled"; 1426 }; 1427 1428 wcnss: remoteproc@a21b000 { 1429 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1430 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1431 reg-names = "ccu", "dxe", "pmu"; 1432 1433 memory-region = <&wcnss_fw_mem>; 1434 1435 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1436 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 1437 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 1438 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 1439 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 1440 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1441 1442 power-domains = <&rpmpd MSM8953_VDDCX>, 1443 <&rpmpd MSM8953_VDDMX>; 1444 power-domain-names = "cx", "mx"; 1445 1446 qcom,smem-states = <&smp2p_wcnss_out 0>; 1447 qcom,smem-state-names = "stop"; 1448 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&wcnss_pin_a>; 1451 1452 status = "disabled"; 1453 1454 wcnss_iris: iris { 1455 /* Separate chip, compatible is board-specific */ 1456 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1457 clock-names = "xo"; 1458 }; 1459 1460 smd-edge { 1461 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1462 1463 qcom,ipc = <&apcs 8 17>; 1464 qcom,smd-edge = <6>; 1465 qcom,remote-pid = <4>; 1466 1467 label = "pronto"; 1468 1469 wcnss_ctrl: wcnss { 1470 compatible = "qcom,wcnss"; 1471 qcom,smd-channels = "WCNSS_CTRL"; 1472 1473 qcom,mmio = <&wcnss>; 1474 1475 wcnss_bt: bluetooth { 1476 compatible = "qcom,wcnss-bt"; 1477 }; 1478 1479 wcnss_wifi: wifi { 1480 compatible = "qcom,wcnss-wlan"; 1481 1482 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupt-names = "tx", "rx"; 1485 1486 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1487 qcom,smem-state-names = "tx-enable", 1488 "tx-rings-empty"; 1489 }; 1490 }; 1491 }; 1492 }; 1493 1494 intc: interrupt-controller@b000000 { 1495 compatible = "qcom,msm-qgic2"; 1496 interrupt-controller; 1497 #interrupt-cells = <3>; 1498 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1499 }; 1500 1501 apcs: mailbox@b011000 { 1502 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1503 reg = <0x0b011000 0x1000>; 1504 #mbox-cells = <1>; 1505 }; 1506 1507 timer@b120000 { 1508 compatible = "arm,armv7-timer-mem"; 1509 reg = <0x0b120000 0x1000>; 1510 #address-cells = <0x01>; 1511 #size-cells = <0x01>; 1512 ranges; 1513 1514 frame@b121000 { 1515 frame-number = <0>; 1516 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1518 reg = <0x0b121000 0x1000>, 1519 <0x0b122000 0x1000>; 1520 }; 1521 1522 frame@b123000 { 1523 frame-number = <1>; 1524 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1525 reg = <0x0b123000 0x1000>; 1526 status = "disabled"; 1527 }; 1528 1529 frame@b124000 { 1530 frame-number = <2>; 1531 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1532 reg = <0x0b124000 0x1000>; 1533 status = "disabled"; 1534 }; 1535 1536 frame@b125000 { 1537 frame-number = <3>; 1538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1539 reg = <0x0b125000 0x1000>; 1540 status = "disabled"; 1541 }; 1542 1543 frame@b126000 { 1544 frame-number = <4>; 1545 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1546 reg = <0x0b126000 0x1000>; 1547 status = "disabled"; 1548 }; 1549 1550 frame@b127000 { 1551 frame-number = <5>; 1552 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1553 reg = <0x0b127000 0x1000>; 1554 status = "disabled"; 1555 }; 1556 1557 frame@b128000 { 1558 frame-number = <6>; 1559 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1560 reg = <0x0b128000 0x1000>; 1561 status = "disabled"; 1562 }; 1563 }; 1564 1565 lpass: remoteproc@c200000 { 1566 compatible = "qcom,msm8953-adsp-pil"; 1567 reg = <0x0c200000 0x100>; 1568 1569 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 1570 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1571 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1572 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1573 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1574 interrupt-names = "wdog", "fatal", "ready", 1575 "handover", "stop-ack"; 1576 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1577 clock-names = "xo"; 1578 1579 power-domains = <&rpmpd MSM8953_VDDCX>; 1580 power-domain-names = "cx"; 1581 1582 memory-region = <&adsp_fw_mem>; 1583 1584 qcom,smem-states = <&smp2p_adsp_out 0>; 1585 qcom,smem-state-names = "stop"; 1586 1587 status = "disabled"; 1588 1589 smd-edge { 1590 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1591 1592 label = "lpass"; 1593 mboxes = <&apcs 8>; 1594 qcom,smd-edge = <1>; 1595 qcom,remote-pid = <2>; 1596 1597 apr { 1598 compatible = "qcom,apr-v2"; 1599 qcom,smd-channels = "apr_audio_svc"; 1600 qcom,apr-domain = <APR_DOMAIN_ADSP>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 1604 q6core: service@3 { 1605 reg = <APR_SVC_ADSP_CORE>; 1606 compatible = "qcom,q6core"; 1607 }; 1608 1609 q6afe: service@4 { 1610 compatible = "qcom,q6afe"; 1611 reg = <APR_SVC_AFE>; 1612 q6afedai: dais { 1613 compatible = "qcom,q6afe-dais"; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 #sound-dai-cells = <1>; 1617 1618 dai@16 { 1619 reg = <PRIMARY_MI2S_RX>; 1620 qcom,sd-lines = <0 1>; 1621 }; 1622 dai@20 { 1623 reg = <TERTIARY_MI2S_TX>; 1624 qcom,sd-lines = <0 1>; 1625 }; 1626 dai@127 { 1627 reg = <QUINARY_MI2S_RX>; 1628 qcom,sd-lines = <0>; 1629 }; 1630 }; 1631 1632 q6afecc: clock-controller { 1633 compatible = "qcom,q6afe-clocks"; 1634 #clock-cells = <2>; 1635 }; 1636 }; 1637 1638 q6asm: service@7 { 1639 compatible = "qcom,q6asm"; 1640 reg = <APR_SVC_ASM>; 1641 q6asmdai: dais { 1642 compatible = "qcom,q6asm-dais"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 #sound-dai-cells = <1>; 1646 1647 dai@0 { 1648 reg = <0>; 1649 direction = <Q6ASM_DAI_RX>; 1650 }; 1651 dai@1 { 1652 reg = <1>; 1653 direction = <Q6ASM_DAI_TX>; 1654 }; 1655 dai@2 { 1656 reg = <2>; 1657 direction = <Q6ASM_DAI_RX>; 1658 }; 1659 dai@3 { 1660 reg = <3>; 1661 direction = <Q6ASM_DAI_RX>; 1662 is-compress-dai; 1663 }; 1664 }; 1665 }; 1666 1667 q6adm: service@8 { 1668 compatible = "qcom,q6adm"; 1669 reg = <APR_SVC_ADM>; 1670 q6routing: routing { 1671 compatible = "qcom,q6adm-routing"; 1672 #sound-dai-cells = <0>; 1673 }; 1674 }; 1675 }; 1676 }; 1677 }; 1678 }; 1679 1680 thermal-zones { 1681 cpu0-thermal { 1682 polling-delay-passive = <250>; 1683 polling-delay = <1000>; 1684 thermal-sensors = <&tsens0 9>; 1685 trips { 1686 cpu0_alert: trip-point0 { 1687 temperature = <80000>; 1688 hysteresis = <2000>; 1689 type = "passive"; 1690 }; 1691 cpu0_crit: crit { 1692 temperature = <100000>; 1693 hysteresis = <2000>; 1694 type = "critical"; 1695 }; 1696 }; 1697 cooling-maps { 1698 map0 { 1699 trip = <&cpu0_alert>; 1700 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1701 }; 1702 }; 1703 }; 1704 cpu1-thermal { 1705 polling-delay-passive = <250>; 1706 polling-delay = <1000>; 1707 thermal-sensors = <&tsens0 10>; 1708 trips { 1709 cpu1_alert: trip-point0 { 1710 temperature = <80000>; 1711 hysteresis = <2000>; 1712 type = "passive"; 1713 }; 1714 cpu1_crit: crit { 1715 temperature = <100000>; 1716 hysteresis = <2000>; 1717 type = "critical"; 1718 }; 1719 }; 1720 cooling-maps { 1721 map0 { 1722 trip = <&cpu1_alert>; 1723 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1724 }; 1725 }; 1726 }; 1727 cpu2-thermal { 1728 polling-delay-passive = <250>; 1729 polling-delay = <1000>; 1730 thermal-sensors = <&tsens0 11>; 1731 trips { 1732 cpu2_alert: trip-point0 { 1733 temperature = <80000>; 1734 hysteresis = <2000>; 1735 type = "passive"; 1736 }; 1737 cpu2_crit: crit { 1738 temperature = <100000>; 1739 hysteresis = <2000>; 1740 type = "critical"; 1741 }; 1742 }; 1743 cooling-maps { 1744 map0 { 1745 trip = <&cpu2_alert>; 1746 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1747 }; 1748 }; 1749 }; 1750 cpu3-thermal { 1751 polling-delay-passive = <250>; 1752 polling-delay = <1000>; 1753 thermal-sensors = <&tsens0 12>; 1754 trips { 1755 cpu3_alert: trip-point0 { 1756 temperature = <80000>; 1757 hysteresis = <2000>; 1758 type = "passive"; 1759 }; 1760 cpu3_crit: crit { 1761 temperature = <100000>; 1762 hysteresis = <2000>; 1763 type = "critical"; 1764 }; 1765 }; 1766 cooling-maps { 1767 map0 { 1768 trip = <&cpu3_alert>; 1769 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1770 }; 1771 }; 1772 }; 1773 cpu4-thermal { 1774 polling-delay-passive = <250>; 1775 polling-delay = <1000>; 1776 thermal-sensors = <&tsens0 4>; 1777 trips { 1778 cpu4_alert: trip-point0 { 1779 temperature = <80000>; 1780 hysteresis = <2000>; 1781 type = "passive"; 1782 }; 1783 cpu4_crit: crit { 1784 temperature = <100000>; 1785 hysteresis = <2000>; 1786 type = "critical"; 1787 }; 1788 }; 1789 cooling-maps { 1790 map0 { 1791 trip = <&cpu4_alert>; 1792 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1793 }; 1794 }; 1795 }; 1796 cpu5-thermal { 1797 polling-delay-passive = <250>; 1798 polling-delay = <1000>; 1799 thermal-sensors = <&tsens0 5>; 1800 trips { 1801 cpu5_alert: trip-point0 { 1802 temperature = <80000>; 1803 hysteresis = <2000>; 1804 type = "passive"; 1805 }; 1806 cpu5_crit: crit { 1807 temperature = <100000>; 1808 hysteresis = <2000>; 1809 type = "critical"; 1810 }; 1811 }; 1812 cooling-maps { 1813 map0 { 1814 trip = <&cpu5_alert>; 1815 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1816 }; 1817 }; 1818 }; 1819 cpu6-thermal { 1820 polling-delay-passive = <250>; 1821 polling-delay = <1000>; 1822 thermal-sensors = <&tsens0 6>; 1823 trips { 1824 cpu6_alert: trip-point0 { 1825 temperature = <80000>; 1826 hysteresis = <2000>; 1827 type = "passive"; 1828 }; 1829 cpu6_crit: crit { 1830 temperature = <100000>; 1831 hysteresis = <2000>; 1832 type = "critical"; 1833 }; 1834 }; 1835 cooling-maps { 1836 map0 { 1837 trip = <&cpu6_alert>; 1838 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1839 }; 1840 }; 1841 }; 1842 cpu7-thermal { 1843 polling-delay-passive = <250>; 1844 polling-delay = <1000>; 1845 thermal-sensors = <&tsens0 7>; 1846 trips { 1847 cpu7_alert: trip-point0 { 1848 temperature = <80000>; 1849 hysteresis = <2000>; 1850 type = "passive"; 1851 }; 1852 cpu7_crit: crit { 1853 temperature = <100000>; 1854 hysteresis = <2000>; 1855 type = "critical"; 1856 }; 1857 }; 1858 cooling-maps { 1859 map0 { 1860 trip = <&cpu7_alert>; 1861 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1862 }; 1863 }; 1864 }; 1865 }; 1866 1867 timer { 1868 compatible = "arm,armv8-timer"; 1869 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1870 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1871 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1872 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1873 }; 1874}; 1875