1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,gcc-msm8953.h> 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <32768>; 23 }; 24 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo"; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 capacity-dmips-mhz = <1024>; 43 next-level-cache = <&L2_0>; 44 #cooling-cells = <2>; 45 }; 46 47 CPU1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x1>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <1024>; 53 next-level-cache = <&L2_0>; 54 #cooling-cells = <2>; 55 }; 56 57 CPU2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x2>; 61 enable-method = "psci"; 62 capacity-dmips-mhz = <1024>; 63 next-level-cache = <&L2_0>; 64 #cooling-cells = <2>; 65 }; 66 67 CPU3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x3>; 71 enable-method = "psci"; 72 capacity-dmips-mhz = <1024>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 }; 76 77 CPU4: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <1024>; 83 next-level-cache = <&L2_1>; 84 #cooling-cells = <2>; 85 }; 86 87 CPU5: cpu@101 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x101>; 91 enable-method = "psci"; 92 capacity-dmips-mhz = <1024>; 93 next-level-cache = <&L2_1>; 94 #cooling-cells = <2>; 95 }; 96 97 CPU6: cpu@102 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x102>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <1024>; 103 next-level-cache = <&L2_1>; 104 #cooling-cells = <2>; 105 }; 106 107 CPU7: cpu@103 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a53"; 110 reg = <0x103>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 next-level-cache = <&L2_1>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu-map { 118 cluster0 { 119 core0 { 120 cpu = <&CPU0>; 121 }; 122 core1 { 123 cpu = <&CPU1>; 124 }; 125 core2 { 126 cpu = <&CPU2>; 127 }; 128 core3 { 129 cpu = <&CPU3>; 130 }; 131 }; 132 133 cluster1 { 134 core0 { 135 cpu = <&CPU4>; 136 }; 137 core1 { 138 cpu = <&CPU5>; 139 }; 140 core2 { 141 cpu = <&CPU6>; 142 }; 143 core3 { 144 cpu = <&CPU7>; 145 }; 146 }; 147 }; 148 149 L2_0: l2-cache-0 { 150 compatible = "cache"; 151 cache-level = <2>; 152 }; 153 154 L2_1: l2-cache-1 { 155 compatible = "cache"; 156 cache-level = <2>; 157 }; 158 }; 159 160 firmware { 161 scm: scm { 162 compatible = "qcom,scm-msm8953", "qcom,scm"; 163 clocks = <&gcc GCC_CRYPTO_CLK>, 164 <&gcc GCC_CRYPTO_AXI_CLK>, 165 <&gcc GCC_CRYPTO_AHB_CLK>; 166 clock-names = "core", "bus", "iface"; 167 #reset-cells = <1>; 168 }; 169 }; 170 171 memory { 172 device_type = "memory"; 173 /* We expect the bootloader to fill in the reg */ 174 reg = <0 0 0 0>; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a53-pmu"; 179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 180 }; 181 182 psci { 183 compatible = "arm,psci-1.0"; 184 method = "smc"; 185 }; 186 187 reserved-memory { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 zap_shader_region: zap@81800000 { 193 compatible = "shared-dma-pool"; 194 reg = <0x0 0x81800000 0x0 0x2000>; 195 no-map; 196 }; 197 198 qseecom_mem: qseecom@85b00000 { 199 reg = <0x0 0x85b00000 0x0 0x800000>; 200 no-map; 201 }; 202 203 smem_mem: smem@86300000 { 204 compatible = "qcom,smem"; 205 reg = <0x0 0x86300000 0x0 0x100000>; 206 qcom,rpm-msg-ram = <&rpm_msg_ram>; 207 hwlocks = <&tcsr_mutex 3>; 208 no-map; 209 }; 210 211 reserved@86400000 { 212 reg = <0x0 0x86400000 0x0 0x400000>; 213 no-map; 214 }; 215 216 mpss_mem: mpss@86c00000 { 217 reg = <0x0 0x86c00000 0x0 0x6a00000>; 218 no-map; 219 }; 220 221 adsp_fw_mem: adsp@8d600000 { 222 reg = <0x0 0x8d600000 0x0 0x1100000>; 223 no-map; 224 }; 225 226 wcnss_fw_mem: wcnss@8e700000 { 227 reg = <0x0 0x8e700000 0x0 0x700000>; 228 no-map; 229 }; 230 231 dfps_data_mem: dfps-data@90000000 { 232 reg = <0 0x90000000 0 0x1000>; 233 no-map; 234 }; 235 236 cont_splash_mem: cont-splash@90001000 { 237 reg = <0x0 0x90001000 0x0 0x13ff000>; 238 no-map; 239 }; 240 241 venus_mem: venus@91400000 { 242 reg = <0x0 0x91400000 0x0 0x700000>; 243 no-map; 244 }; 245 246 mba_mem: mba@92000000 { 247 reg = <0x0 0x92000000 0x0 0x100000>; 248 no-map; 249 }; 250 251 rmtfs@f2d00000 { 252 compatible = "qcom,rmtfs-mem"; 253 reg = <0x0 0xf2d00000 0x0 0x180000>; 254 no-map; 255 256 qcom,client-id = <1>; 257 }; 258 }; 259 260 smd { 261 compatible = "qcom,smd"; 262 263 rpm { 264 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 265 qcom,ipc = <&apcs 8 0>; 266 qcom,smd-edge = <15>; 267 268 rpm_requests: rpm-requests { 269 compatible = "qcom,rpm-msm8953"; 270 qcom,smd-channels = "rpm_requests"; 271 272 rpmcc: rpmcc { 273 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 274 clocks = <&xo_board>; 275 clock-names = "xo"; 276 #clock-cells = <1>; 277 }; 278 279 rpmpd: power-controller { 280 compatible = "qcom,msm8953-rpmpd"; 281 #power-domain-cells = <1>; 282 operating-points-v2 = <&rpmpd_opp_table>; 283 284 clocks = <&xo_board>; 285 clock-names = "ref"; 286 287 rpmpd_opp_table: opp-table { 288 compatible = "operating-points-v2"; 289 290 rpmpd_opp_ret: opp1 { 291 opp-level = <RPM_SMD_LEVEL_RETENTION>; 292 }; 293 294 rpmpd_opp_ret_plus: opp2 { 295 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 296 }; 297 298 rpmpd_opp_min_svs: opp3 { 299 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 300 }; 301 302 rpmpd_opp_low_svs: opp4 { 303 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 304 }; 305 306 rpmpd_opp_svs: opp5 { 307 opp-level = <RPM_SMD_LEVEL_SVS>; 308 }; 309 310 rpmpd_opp_svs_plus: opp6 { 311 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 312 }; 313 314 rpmpd_opp_nom: opp7 { 315 opp-level = <RPM_SMD_LEVEL_NOM>; 316 }; 317 318 rpmpd_opp_nom_plus: opp8 { 319 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 320 }; 321 322 rpmpd_opp_turbo: opp9 { 323 opp-level = <RPM_SMD_LEVEL_TURBO>; 324 }; 325 }; 326 }; 327 }; 328 }; 329 }; 330 331 smsm { 332 compatible = "qcom,smsm"; 333 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 qcom,ipc-1 = <&apcs 8 13>; 338 qcom,ipc-3 = <&apcs 8 19>; 339 340 apps_smsm: apps@0 { 341 reg = <0>; 342 343 #qcom,smem-state-cells = <1>; 344 }; 345 }; 346 347 soc: soc@0 { 348 #address-cells = <1>; 349 #size-cells = <1>; 350 ranges = <0 0 0 0xffffffff>; 351 compatible = "simple-bus"; 352 353 rpm_msg_ram: sram@60000 { 354 compatible = "qcom,rpm-msg-ram"; 355 reg = <0x60000 0x8000>; 356 }; 357 358 hsusb_phy: phy@79000 { 359 compatible = "qcom,msm8953-qusb2-phy"; 360 reg = <0x79000 0x180>; 361 #phy-cells = <0>; 362 363 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 364 <&gcc GCC_QUSB_REF_CLK>; 365 clock-names = "cfg_ahb", "ref"; 366 367 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 368 369 resets = <&gcc GCC_QUSB2_PHY_BCR>; 370 371 status = "disabled"; 372 }; 373 374 rng@e3000 { 375 compatible = "qcom,prng"; 376 reg = <0x000e3000 0x1000>; 377 clocks = <&gcc GCC_PRNG_AHB_CLK>; 378 clock-names = "core"; 379 }; 380 381 tsens0: thermal-sensor@4a9000 { 382 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 383 reg = <0x4a9000 0x1000>, /* TM */ 384 <0x4a8000 0x1000>; /* SROT */ 385 #qcom,sensors = <16>; 386 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-names = "uplow", "critical"; 389 #thermal-sensor-cells = <1>; 390 }; 391 392 restart@4ab000 { 393 compatible = "qcom,pshold"; 394 reg = <0x4ab000 0x4>; 395 }; 396 397 tlmm: pinctrl@1000000 { 398 compatible = "qcom,msm8953-pinctrl"; 399 reg = <0x1000000 0x300000>; 400 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 401 gpio-controller; 402 gpio-ranges = <&tlmm 0 0 142>; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 407 uart_console_active: uart-console-active-state { 408 pins = "gpio4", "gpio5"; 409 function = "blsp_uart2"; 410 drive-strength = <2>; 411 bias-disable; 412 }; 413 414 uart_console_sleep: uart-console-sleep-state { 415 pins = "gpio4", "gpio5"; 416 function = "blsp_uart2"; 417 drive-strength = <2>; 418 bias-pull-down; 419 }; 420 421 sdc1_clk_on: sdc1-clk-on-state { 422 pins = "sdc1_clk"; 423 bias-disable; 424 drive-strength = <16>; 425 }; 426 427 sdc1_clk_off: sdc1-clk-off-state { 428 pins = "sdc1_clk"; 429 bias-disable; 430 drive-strength = <2>; 431 }; 432 433 sdc1_cmd_on: sdc1-cmd-on-state { 434 pins = "sdc1_cmd"; 435 bias-disable; 436 drive-strength = <10>; 437 }; 438 439 sdc1_cmd_off: sdc1-cmd-off-state { 440 pins = "sdc1_cmd"; 441 bias-disable; 442 drive-strength = <2>; 443 }; 444 445 sdc1_data_on: sdc1-data-on-state { 446 pins = "sdc1_data"; 447 bias-pull-up; 448 drive-strength = <10>; 449 }; 450 451 sdc1_data_off: sdc1-data-off-state { 452 pins = "sdc1_data"; 453 bias-pull-up; 454 drive-strength = <2>; 455 }; 456 457 sdc1_rclk_on: sdc1-rclk-on-state { 458 pins = "sdc1_rclk"; 459 bias-pull-down; 460 }; 461 462 sdc1_rclk_off: sdc1-rclk-off-state { 463 pins = "sdc1_rclk"; 464 bias-pull-down; 465 }; 466 467 sdc2_clk_on: sdc2-clk-on-state { 468 pins = "sdc2_clk"; 469 drive-strength = <16>; 470 bias-disable; 471 }; 472 473 sdc2_clk_off: sdc2-clk-off-state { 474 pins = "sdc2_clk"; 475 bias-disable; 476 drive-strength = <2>; 477 }; 478 479 sdc2_cmd_on: sdc2-cmd-on-state { 480 pins = "sdc2_cmd"; 481 bias-pull-up; 482 drive-strength = <10>; 483 }; 484 485 sdc2_cmd_off: sdc2-cmd-off-state { 486 pins = "sdc2_cmd"; 487 bias-pull-up; 488 drive-strength = <2>; 489 }; 490 491 sdc2_data_on: sdc2-data-on-state { 492 pins = "sdc2_data"; 493 bias-pull-up; 494 drive-strength = <10>; 495 }; 496 497 sdc2_data_off: sdc2-data-off-state { 498 pins = "sdc2_data"; 499 bias-pull-up; 500 drive-strength = <2>; 501 }; 502 503 sdc2_cd_on: cd-on-state { 504 pins = "gpio133"; 505 function = "gpio"; 506 drive-strength = <2>; 507 bias-pull-up; 508 }; 509 510 sdc2_cd_off: cd-off-state { 511 pins = "gpio133"; 512 function = "gpio"; 513 drive-strength = <2>; 514 bias-disable; 515 }; 516 517 gpio_key_default: gpio-key-default-state { 518 pins = "gpio85"; 519 function = "gpio"; 520 drive-strength = <2>; 521 bias-pull-up; 522 }; 523 524 i2c_1_default: i2c-1-default-state { 525 pins = "gpio2", "gpio3"; 526 function = "blsp_i2c1"; 527 drive-strength = <2>; 528 bias-disable; 529 }; 530 531 i2c_1_sleep: i2c-1-sleep-state { 532 pins = "gpio2", "gpio3"; 533 function = "gpio"; 534 drive-strength = <2>; 535 bias-disable; 536 }; 537 538 i2c_2_default: i2c-2-default-state { 539 pins = "gpio6", "gpio7"; 540 function = "blsp_i2c2"; 541 drive-strength = <2>; 542 bias-disable; 543 }; 544 545 i2c_2_sleep: i2c-2-sleep-state { 546 pins = "gpio6", "gpio7"; 547 function = "gpio"; 548 drive-strength = <2>; 549 bias-disable; 550 }; 551 552 i2c_3_default: i2c-3-default-state { 553 pins = "gpio10", "gpio11"; 554 function = "blsp_i2c3"; 555 drive-strength = <2>; 556 bias-disable; 557 }; 558 559 i2c_3_sleep: i2c-3-sleep-state { 560 pins = "gpio10", "gpio11"; 561 function = "gpio"; 562 drive-strength = <2>; 563 bias-disable; 564 }; 565 566 i2c_4_default: i2c-4-default-state { 567 pins = "gpio14", "gpio15"; 568 function = "blsp_i2c4"; 569 drive-strength = <2>; 570 bias-disable; 571 }; 572 573 i2c_4_sleep: i2c-4-sleep-state { 574 pins = "gpio14", "gpio15"; 575 function = "gpio"; 576 drive-strength = <2>; 577 bias-disable; 578 }; 579 580 i2c_5_default: i2c-5-default-state { 581 pins = "gpio18", "gpio19"; 582 function = "blsp_i2c5"; 583 drive-strength = <2>; 584 bias-disable; 585 }; 586 587 i2c_5_sleep: i2c-5-sleep-state { 588 pins = "gpio18", "gpio19"; 589 function = "gpio"; 590 drive-strength = <2>; 591 bias-disable; 592 }; 593 594 i2c_6_default: i2c-6-default-state { 595 pins = "gpio22", "gpio23"; 596 function = "blsp_i2c6"; 597 drive-strength = <2>; 598 bias-disable; 599 }; 600 601 i2c_6_sleep: i2c-6-sleep-state { 602 pins = "gpio22", "gpio23"; 603 function = "gpio"; 604 drive-strength = <2>; 605 bias-disable; 606 }; 607 608 i2c_7_default: i2c-7-default-state { 609 pins = "gpio135", "gpio136"; 610 function = "blsp_i2c7"; 611 drive-strength = <2>; 612 bias-disable; 613 }; 614 615 i2c_7_sleep: i2c-7-sleep-state { 616 pins = "gpio135", "gpio136"; 617 function = "gpio"; 618 drive-strength = <2>; 619 bias-disable; 620 }; 621 622 i2c_8_default: i2c-8-default-state { 623 pins = "gpio98", "gpio99"; 624 function = "blsp_i2c8"; 625 drive-strength = <2>; 626 bias-disable; 627 }; 628 629 i2c_8_sleep: i2c-8-sleep-state { 630 pins = "gpio98", "gpio99"; 631 function = "gpio"; 632 drive-strength = <2>; 633 bias-disable; 634 }; 635 }; 636 637 gcc: clock-controller@1800000 { 638 compatible = "qcom,gcc-msm8953"; 639 reg = <0x1800000 0x80000>; 640 #clock-cells = <1>; 641 #reset-cells = <1>; 642 #power-domain-cells = <1>; 643 clocks = <&xo_board>, 644 <&sleep_clk>, 645 <0>, 646 <0>, 647 <0>, 648 <0>; 649 clock-names = "xo", 650 "sleep", 651 "dsi0pll", 652 "dsi0pllbyte", 653 "dsi1pll", 654 "dsi1pllbyte"; 655 }; 656 657 tcsr_mutex: hwlock@1905000 { 658 compatible = "qcom,tcsr-mutex"; 659 reg = <0x1905000 0x20000>; 660 #hwlock-cells = <1>; 661 }; 662 663 tcsr: syscon@1937000 { 664 compatible = "qcom,tcsr-msm8953", "syscon"; 665 reg = <0x1937000 0x30000>; 666 }; 667 668 tcsr_phy_clk_scheme_sel: syscon@193f044 { 669 compatible = "qcom,tcsr-msm8953", "syscon"; 670 reg = <0x193f044 0x4>; 671 }; 672 673 mdss: display-subsystem@1a00000 { 674 compatible = "qcom,mdss"; 675 676 reg = <0x1a00000 0x1000>, 677 <0x1ab0000 0x1040>; 678 reg-names = "mdss_phys", 679 "vbif_phys"; 680 681 power-domains = <&gcc MDSS_GDSC>; 682 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 683 684 interrupt-controller; 685 #interrupt-cells = <1>; 686 687 clocks = <&gcc GCC_MDSS_AHB_CLK>, 688 <&gcc GCC_MDSS_AXI_CLK>, 689 <&gcc GCC_MDSS_VSYNC_CLK>, 690 <&gcc GCC_MDSS_MDP_CLK>; 691 clock-names = "iface", 692 "bus", 693 "vsync", 694 "core"; 695 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges; 699 700 status = "disabled"; 701 702 mdp: display-controller@1a01000 { 703 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 704 reg = <0x1a01000 0x89000>; 705 reg-names = "mdp_phys"; 706 707 interrupt-parent = <&mdss>; 708 interrupts = <0>; 709 710 power-domains = <&gcc MDSS_GDSC>; 711 712 clocks = <&gcc GCC_MDSS_AHB_CLK>, 713 <&gcc GCC_MDSS_AXI_CLK>, 714 <&gcc GCC_MDSS_MDP_CLK>, 715 <&gcc GCC_MDSS_VSYNC_CLK>; 716 clock-names = "iface", 717 "bus", 718 "core", 719 "vsync"; 720 721 iommus = <&apps_iommu 0x15>; 722 723 ports { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 727 port@0 { 728 reg = <0>; 729 mdp5_intf1_out: endpoint { 730 remote-endpoint = <&dsi0_in>; 731 }; 732 }; 733 734 port@1 { 735 reg = <1>; 736 mdp5_intf2_out: endpoint { 737 remote-endpoint = <&dsi1_in>; 738 }; 739 }; 740 }; 741 }; 742 743 dsi0: dsi@1a94000 { 744 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 745 reg = <0x1a94000 0x400>; 746 reg-names = "dsi_ctrl"; 747 748 interrupt-parent = <&mdss>; 749 interrupts = <4>; 750 751 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 752 <&gcc PCLK0_CLK_SRC>; 753 assigned-clock-parents = <&dsi0_phy 0>, 754 <&dsi0_phy 1>; 755 756 clocks = <&gcc GCC_MDSS_MDP_CLK>, 757 <&gcc GCC_MDSS_AHB_CLK>, 758 <&gcc GCC_MDSS_AXI_CLK>, 759 <&gcc GCC_MDSS_BYTE0_CLK>, 760 <&gcc GCC_MDSS_PCLK0_CLK>, 761 <&gcc GCC_MDSS_ESC0_CLK>; 762 clock-names = "mdp_core", 763 "iface", 764 "bus", 765 "byte", 766 "pixel", 767 "core"; 768 769 phys = <&dsi0_phy>; 770 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 status = "disabled"; 775 776 ports { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 port@0 { 781 reg = <0>; 782 dsi0_in: endpoint { 783 remote-endpoint = <&mdp5_intf1_out>; 784 }; 785 }; 786 787 port@1 { 788 reg = <1>; 789 dsi0_out: endpoint { 790 }; 791 }; 792 }; 793 }; 794 795 dsi0_phy: phy@1a94400 { 796 compatible = "qcom,dsi-phy-14nm-8953"; 797 reg = <0x1a94400 0x100>, 798 <0x1a94500 0x300>, 799 <0x1a94800 0x188>; 800 reg-names = "dsi_phy", 801 "dsi_phy_lane", 802 "dsi_pll"; 803 804 #clock-cells = <1>; 805 #phy-cells = <0>; 806 807 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; 808 clock-names = "iface", "ref"; 809 810 status = "disabled"; 811 }; 812 813 dsi1: dsi@1a96000 { 814 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 815 reg = <0x1a96000 0x400>; 816 reg-names = "dsi_ctrl"; 817 818 interrupt-parent = <&mdss>; 819 interrupts = <5>; 820 821 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 822 <&gcc PCLK1_CLK_SRC>; 823 assigned-clock-parents = <&dsi1_phy 0>, 824 <&dsi1_phy 1>; 825 826 clocks = <&gcc GCC_MDSS_MDP_CLK>, 827 <&gcc GCC_MDSS_AHB_CLK>, 828 <&gcc GCC_MDSS_AXI_CLK>, 829 <&gcc GCC_MDSS_BYTE1_CLK>, 830 <&gcc GCC_MDSS_PCLK1_CLK>, 831 <&gcc GCC_MDSS_ESC1_CLK>; 832 clock-names = "mdp_core", 833 "iface", 834 "bus", 835 "byte", 836 "pixel", 837 "core"; 838 839 phys = <&dsi1_phy>; 840 841 status = "disabled"; 842 843 ports { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 port@0 { 848 reg = <0>; 849 dsi1_in: endpoint { 850 remote-endpoint = <&mdp5_intf2_out>; 851 }; 852 }; 853 854 port@1 { 855 reg = <1>; 856 dsi1_out: endpoint { 857 }; 858 }; 859 }; 860 }; 861 862 dsi1_phy: phy@1a96400 { 863 compatible = "qcom,dsi-phy-14nm-8953"; 864 reg = <0x1a96400 0x100>, 865 <0x1a96500 0x300>, 866 <0x1a96800 0x188>; 867 reg-names = "dsi_phy", 868 "dsi_phy_lane", 869 "dsi_pll"; 870 871 #clock-cells = <1>; 872 #phy-cells = <0>; 873 874 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; 875 clock-names = "iface", "ref"; 876 877 status = "disabled"; 878 }; 879 }; 880 881 apps_iommu: iommu@1e00000 { 882 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 883 ranges = <0 0x1e20000 0x20000>; 884 885 clocks = <&gcc GCC_SMMU_CFG_CLK>, 886 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 887 clock-names = "iface", "bus"; 888 889 qcom,iommu-secure-id = <17>; 890 891 #address-cells = <1>; 892 #iommu-cells = <1>; 893 #size-cells = <1>; 894 895 /* VFE */ 896 iommu-ctx@14000 { 897 compatible = "qcom,msm-iommu-v1-ns"; 898 reg = <0x14000 0x1000>; 899 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 900 }; 901 902 /* MDP_0 */ 903 iommu-ctx@15000 { 904 compatible = "qcom,msm-iommu-v1-ns"; 905 reg = <0x15000 0x1000>; 906 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 907 }; 908 909 /* VENUS_NS */ 910 iommu-ctx@16000 { 911 compatible = "qcom,msm-iommu-v1-ns"; 912 reg = <0x16000 0x1000>; 913 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 914 }; 915 }; 916 917 spmi_bus: spmi@200f000 { 918 compatible = "qcom,spmi-pmic-arb"; 919 reg = <0x200f000 0x1000>, 920 <0x2400000 0x800000>, 921 <0x2c00000 0x800000>, 922 <0x3800000 0x200000>, 923 <0x200a000 0x2100>; 924 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 925 interrupt-names = "periph_irq"; 926 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 927 qcom,ee = <0>; 928 qcom,channel = <0>; 929 interrupt-controller; 930 931 #interrupt-cells = <4>; 932 #address-cells = <2>; 933 #size-cells = <0>; 934 }; 935 936 usb3: usb@70f8800 { 937 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 938 reg = <0x70f8800 0x400>; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges; 942 943 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 946 947 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 948 <&gcc GCC_USB30_MASTER_CLK>, 949 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 950 <&gcc GCC_USB30_SLEEP_CLK>, 951 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 952 clock-names = "cfg_noc", 953 "core", 954 "iface", 955 "sleep", 956 "mock_utmi"; 957 958 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 959 <&gcc GCC_USB30_MASTER_CLK>; 960 assigned-clock-rates = <19200000>, <133330000>; 961 962 power-domains = <&gcc USB30_GDSC>; 963 964 qcom,select-utmi-as-pipe-clk; 965 966 status = "disabled"; 967 968 usb3_dwc3: usb@7000000 { 969 compatible = "snps,dwc3"; 970 reg = <0x07000000 0xcc00>; 971 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 972 phys = <&hsusb_phy>; 973 phy-names = "usb2-phy"; 974 975 snps,usb2-gadget-lpm-disable; 976 snps,dis-u1-entry-quirk; 977 snps,dis-u2-entry-quirk; 978 snps,is-utmi-l1-suspend; 979 snps,hird-threshold = /bits/ 8 <0x00>; 980 981 maximum-speed = "high-speed"; 982 phy_mode = "utmi"; 983 }; 984 }; 985 986 sdhc_1: mmc@7824900 { 987 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 988 989 reg = <0x7824900 0x500>, <0x7824000 0x800>; 990 reg-names = "hc", "core"; 991 992 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 994 interrupt-names = "hc_irq", "pwr_irq"; 995 996 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 997 <&gcc GCC_SDCC1_APPS_CLK>, 998 <&xo_board>; 999 clock-names = "iface", "core", "xo"; 1000 1001 power-domains = <&rpmpd MSM8953_VDDCX>; 1002 operating-points-v2 = <&sdhc1_opp_table>; 1003 1004 pinctrl-names = "default", "sleep"; 1005 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1006 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1007 1008 mmc-hs400-1_8v; 1009 mmc-hs200-1_8v; 1010 mmc-ddr-1_8v; 1011 bus-width = <8>; 1012 non-removable; 1013 1014 status = "disabled"; 1015 1016 sdhc1_opp_table: opp-table-sdhc1 { 1017 compatible = "operating-points-v2"; 1018 1019 opp-25000000 { 1020 opp-hz = /bits/ 64 <25000000>; 1021 required-opps = <&rpmpd_opp_low_svs>; 1022 }; 1023 1024 opp-50000000 { 1025 opp-hz = /bits/ 64 <50000000>; 1026 required-opps = <&rpmpd_opp_svs>; 1027 }; 1028 1029 opp-100000000 { 1030 opp-hz = /bits/ 64 <100000000>; 1031 required-opps = <&rpmpd_opp_svs>; 1032 }; 1033 1034 opp-192000000 { 1035 opp-hz = /bits/ 64 <192000000>; 1036 required-opps = <&rpmpd_opp_nom>; 1037 }; 1038 1039 opp-384000000 { 1040 opp-hz = /bits/ 64 <384000000>; 1041 required-opps = <&rpmpd_opp_nom>; 1042 }; 1043 }; 1044 }; 1045 1046 sdhc_2: mmc@7864900 { 1047 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1048 1049 reg = <0x7864900 0x500>, <0x7864000 0x800>; 1050 reg-names = "hc", "core"; 1051 1052 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "hc_irq", "pwr_irq"; 1055 1056 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1057 <&gcc GCC_SDCC2_APPS_CLK>, 1058 <&xo_board>; 1059 clock-names = "iface", "core", "xo"; 1060 1061 power-domains = <&rpmpd MSM8953_VDDCX>; 1062 operating-points-v2 = <&sdhc2_opp_table>; 1063 1064 pinctrl-names = "default", "sleep"; 1065 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1066 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1067 1068 bus-width = <4>; 1069 1070 status = "disabled"; 1071 1072 sdhc2_opp_table: opp-table-sdhc2 { 1073 compatible = "operating-points-v2"; 1074 1075 opp-25000000 { 1076 opp-hz = /bits/ 64 <25000000>; 1077 required-opps = <&rpmpd_opp_low_svs>; 1078 }; 1079 1080 opp-50000000 { 1081 opp-hz = /bits/ 64 <50000000>; 1082 required-opps = <&rpmpd_opp_svs>; 1083 }; 1084 1085 opp-100000000 { 1086 opp-hz = /bits/ 64 <100000000>; 1087 required-opps = <&rpmpd_opp_svs>; 1088 }; 1089 1090 opp-177770000 { 1091 opp-hz = /bits/ 64 <177770000>; 1092 required-opps = <&rpmpd_opp_nom>; 1093 }; 1094 1095 opp-200000000 { 1096 opp-hz = /bits/ 64 <200000000>; 1097 required-opps = <&rpmpd_opp_nom>; 1098 }; 1099 }; 1100 }; 1101 1102 uart_0: serial@78af000 { 1103 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1104 reg = <0x78af000 0x200>; 1105 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1107 <&gcc GCC_BLSP1_AHB_CLK>; 1108 clock-names = "core", "iface"; 1109 1110 status = "disabled"; 1111 }; 1112 1113 i2c_1: i2c@78b5000 { 1114 compatible = "qcom,i2c-qup-v2.2.1"; 1115 reg = <0x78b5000 0x600>; 1116 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1117 clock-names = "core", "iface"; 1118 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1119 <&gcc GCC_BLSP1_AHB_CLK>; 1120 1121 pinctrl-names = "default", "sleep"; 1122 pinctrl-0 = <&i2c_1_default>; 1123 pinctrl-1 = <&i2c_1_sleep>; 1124 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 1128 status = "disabled"; 1129 }; 1130 1131 i2c_2: i2c@78b6000 { 1132 compatible = "qcom,i2c-qup-v2.2.1"; 1133 reg = <0x78b6000 0x600>; 1134 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1135 clock-names = "core", "iface"; 1136 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1137 <&gcc GCC_BLSP1_AHB_CLK>; 1138 1139 pinctrl-names = "default", "sleep"; 1140 pinctrl-0 = <&i2c_2_default>; 1141 pinctrl-1 = <&i2c_2_sleep>; 1142 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 status = "disabled"; 1147 }; 1148 1149 i2c_3: i2c@78b7000 { 1150 compatible = "qcom,i2c-qup-v2.2.1"; 1151 reg = <0x78b7000 0x600>; 1152 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1153 clock-names = "core", "iface"; 1154 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1155 <&gcc GCC_BLSP1_AHB_CLK>; 1156 pinctrl-names = "default", "sleep"; 1157 pinctrl-0 = <&i2c_3_default>; 1158 pinctrl-1 = <&i2c_3_sleep>; 1159 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 status = "disabled"; 1164 }; 1165 1166 i2c_4: i2c@78b8000 { 1167 compatible = "qcom,i2c-qup-v2.2.1"; 1168 reg = <0x78b8000 0x600>; 1169 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1170 clock-names = "core", "iface"; 1171 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1172 <&gcc GCC_BLSP1_AHB_CLK>; 1173 pinctrl-names = "default", "sleep"; 1174 pinctrl-0 = <&i2c_4_default>; 1175 pinctrl-1 = <&i2c_4_sleep>; 1176 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 1180 status = "disabled"; 1181 }; 1182 1183 i2c_5: i2c@7af5000 { 1184 compatible = "qcom,i2c-qup-v2.2.1"; 1185 reg = <0x7af5000 0x600>; 1186 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1187 clock-names = "core", "iface"; 1188 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1189 <&gcc GCC_BLSP2_AHB_CLK>; 1190 pinctrl-names = "default", "sleep"; 1191 pinctrl-0 = <&i2c_5_default>; 1192 pinctrl-1 = <&i2c_5_sleep>; 1193 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 1197 status = "disabled"; 1198 }; 1199 1200 i2c_6: i2c@7af6000 { 1201 compatible = "qcom,i2c-qup-v2.2.1"; 1202 reg = <0x7af6000 0x600>; 1203 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1204 clock-names = "core", "iface"; 1205 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1206 <&gcc GCC_BLSP2_AHB_CLK>; 1207 pinctrl-names = "default", "sleep"; 1208 pinctrl-0 = <&i2c_6_default>; 1209 pinctrl-1 = <&i2c_6_sleep>; 1210 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 status = "disabled"; 1215 }; 1216 1217 i2c_7: i2c@7af7000 { 1218 compatible = "qcom,i2c-qup-v2.2.1"; 1219 reg = <0x7af7000 0x600>; 1220 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1221 clock-names = "core", "iface"; 1222 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1223 <&gcc GCC_BLSP2_AHB_CLK>; 1224 pinctrl-names = "default", "sleep"; 1225 pinctrl-0 = <&i2c_7_default>; 1226 pinctrl-1 = <&i2c_7_sleep>; 1227 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 status = "disabled"; 1232 }; 1233 1234 i2c_8: i2c@7af8000 { 1235 compatible = "qcom,i2c-qup-v2.2.1"; 1236 reg = <0x7af8000 0x600>; 1237 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1238 clock-names = "core", "iface"; 1239 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1240 <&gcc GCC_BLSP2_AHB_CLK>; 1241 pinctrl-names = "default", "sleep"; 1242 pinctrl-0 = <&i2c_8_default>; 1243 pinctrl-1 = <&i2c_8_sleep>; 1244 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 intc: interrupt-controller@b000000 { 1252 compatible = "qcom,msm-qgic2"; 1253 interrupt-controller; 1254 #interrupt-cells = <3>; 1255 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1256 }; 1257 1258 apcs: mailbox@b011000 { 1259 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1260 reg = <0xb011000 0x1000>; 1261 #mbox-cells = <1>; 1262 }; 1263 1264 timer@b120000 { 1265 compatible = "arm,armv7-timer-mem"; 1266 reg = <0xb120000 0x1000>; 1267 #address-cells = <0x01>; 1268 #size-cells = <0x01>; 1269 ranges; 1270 1271 frame@b121000 { 1272 frame-number = <0>; 1273 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1275 reg = <0xb121000 0x1000>, 1276 <0xb122000 0x1000>; 1277 }; 1278 1279 frame@b123000 { 1280 frame-number = <1>; 1281 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1282 reg = <0xb123000 0x1000>; 1283 status = "disabled"; 1284 }; 1285 1286 frame@b124000 { 1287 frame-number = <2>; 1288 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1289 reg = <0xb124000 0x1000>; 1290 status = "disabled"; 1291 }; 1292 1293 frame@b125000 { 1294 frame-number = <3>; 1295 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1296 reg = <0xb125000 0x1000>; 1297 status = "disabled"; 1298 }; 1299 1300 frame@b126000 { 1301 frame-number = <4>; 1302 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1303 reg = <0xb126000 0x1000>; 1304 status = "disabled"; 1305 }; 1306 1307 frame@b127000 { 1308 frame-number = <5>; 1309 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1310 reg = <0xb127000 0x1000>; 1311 status = "disabled"; 1312 }; 1313 1314 frame@b128000 { 1315 frame-number = <6>; 1316 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1317 reg = <0xb128000 0x1000>; 1318 status = "disabled"; 1319 }; 1320 }; 1321 }; 1322 1323 thermal-zones { 1324 cpu0-thermal { 1325 polling-delay-passive = <250>; 1326 polling-delay = <1000>; 1327 thermal-sensors = <&tsens0 9>; 1328 trips { 1329 cpu0_alert: trip-point0 { 1330 temperature = <80000>; 1331 hysteresis = <2000>; 1332 type = "passive"; 1333 }; 1334 cpu0_crit: crit { 1335 temperature = <100000>; 1336 hysteresis = <2000>; 1337 type = "critical"; 1338 }; 1339 }; 1340 cooling-maps { 1341 map0 { 1342 trip = <&cpu0_alert>; 1343 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1344 }; 1345 }; 1346 }; 1347 cpu1-thermal { 1348 polling-delay-passive = <250>; 1349 polling-delay = <1000>; 1350 thermal-sensors = <&tsens0 10>; 1351 trips { 1352 cpu1_alert: trip-point0 { 1353 temperature = <80000>; 1354 hysteresis = <2000>; 1355 type = "passive"; 1356 }; 1357 cpu1_crit: crit { 1358 temperature = <100000>; 1359 hysteresis = <2000>; 1360 type = "critical"; 1361 }; 1362 }; 1363 cooling-maps { 1364 map0 { 1365 trip = <&cpu1_alert>; 1366 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1367 }; 1368 }; 1369 }; 1370 cpu2-thermal { 1371 polling-delay-passive = <250>; 1372 polling-delay = <1000>; 1373 thermal-sensors = <&tsens0 11>; 1374 trips { 1375 cpu2_alert: trip-point0 { 1376 temperature = <80000>; 1377 hysteresis = <2000>; 1378 type = "passive"; 1379 }; 1380 cpu2_crit: crit { 1381 temperature = <100000>; 1382 hysteresis = <2000>; 1383 type = "critical"; 1384 }; 1385 }; 1386 cooling-maps { 1387 map0 { 1388 trip = <&cpu2_alert>; 1389 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1390 }; 1391 }; 1392 }; 1393 cpu3-thermal { 1394 polling-delay-passive = <250>; 1395 polling-delay = <1000>; 1396 thermal-sensors = <&tsens0 12>; 1397 trips { 1398 cpu3_alert: trip-point0 { 1399 temperature = <80000>; 1400 hysteresis = <2000>; 1401 type = "passive"; 1402 }; 1403 cpu3_crit: crit { 1404 temperature = <100000>; 1405 hysteresis = <2000>; 1406 type = "critical"; 1407 }; 1408 }; 1409 cooling-maps { 1410 map0 { 1411 trip = <&cpu3_alert>; 1412 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1413 }; 1414 }; 1415 }; 1416 cpu4-thermal { 1417 polling-delay-passive = <250>; 1418 polling-delay = <1000>; 1419 thermal-sensors = <&tsens0 4>; 1420 trips { 1421 cpu4_alert: trip-point0 { 1422 temperature = <80000>; 1423 hysteresis = <2000>; 1424 type = "passive"; 1425 }; 1426 cpu4_crit: crit { 1427 temperature = <100000>; 1428 hysteresis = <2000>; 1429 type = "critical"; 1430 }; 1431 }; 1432 cooling-maps { 1433 map0 { 1434 trip = <&cpu4_alert>; 1435 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1436 }; 1437 }; 1438 }; 1439 cpu5-thermal { 1440 polling-delay-passive = <250>; 1441 polling-delay = <1000>; 1442 thermal-sensors = <&tsens0 5>; 1443 trips { 1444 cpu5_alert: trip-point0 { 1445 temperature = <80000>; 1446 hysteresis = <2000>; 1447 type = "passive"; 1448 }; 1449 cpu5_crit: crit { 1450 temperature = <100000>; 1451 hysteresis = <2000>; 1452 type = "critical"; 1453 }; 1454 }; 1455 cooling-maps { 1456 map0 { 1457 trip = <&cpu5_alert>; 1458 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1459 }; 1460 }; 1461 }; 1462 cpu6-thermal { 1463 polling-delay-passive = <250>; 1464 polling-delay = <1000>; 1465 thermal-sensors = <&tsens0 6>; 1466 trips { 1467 cpu6_alert: trip-point0 { 1468 temperature = <80000>; 1469 hysteresis = <2000>; 1470 type = "passive"; 1471 }; 1472 cpu6_crit: crit { 1473 temperature = <100000>; 1474 hysteresis = <2000>; 1475 type = "critical"; 1476 }; 1477 }; 1478 cooling-maps { 1479 map0 { 1480 trip = <&cpu6_alert>; 1481 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1482 }; 1483 }; 1484 }; 1485 cpu7-thermal { 1486 polling-delay-passive = <250>; 1487 polling-delay = <1000>; 1488 thermal-sensors = <&tsens0 7>; 1489 trips { 1490 cpu7_alert: trip-point0 { 1491 temperature = <80000>; 1492 hysteresis = <2000>; 1493 type = "passive"; 1494 }; 1495 cpu7_crit: crit { 1496 temperature = <100000>; 1497 hysteresis = <2000>; 1498 type = "critical"; 1499 }; 1500 }; 1501 cooling-maps { 1502 map0 { 1503 trip = <&cpu7_alert>; 1504 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1505 }; 1506 }; 1507 }; 1508 }; 1509 1510 timer { 1511 compatible = "arm,armv8-timer"; 1512 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1513 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1514 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1515 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1516 }; 1517}; 1518