1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-msm8939.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8939.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8939.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 /* 19 * Stock LK wants address-cells/size-cells = 2 20 * A number of our drivers want address/size cells = 1 21 * hence the disparity between top-level and /soc below. 22 */ 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32768>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 CPU0: cpu@100 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 enable-method = "spin-table"; 48 reg = <0x100>; 49 next-level-cache = <&L2_1>; 50 qcom,acc = <&acc0>; 51 qcom,saw = <&saw0>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 clocks = <&apcs1_mbox>; 54 #cooling-cells = <2>; 55 L2_1: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 }; 61 62 CPU1: cpu@101 { 63 compatible = "arm,cortex-a53"; 64 device_type = "cpu"; 65 enable-method = "spin-table"; 66 reg = <0x101>; 67 next-level-cache = <&L2_1>; 68 qcom,acc = <&acc1>; 69 qcom,saw = <&saw1>; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 clocks = <&apcs1_mbox>; 72 #cooling-cells = <2>; 73 }; 74 75 CPU2: cpu@102 { 76 compatible = "arm,cortex-a53"; 77 device_type = "cpu"; 78 enable-method = "spin-table"; 79 reg = <0x102>; 80 next-level-cache = <&L2_1>; 81 qcom,acc = <&acc2>; 82 qcom,saw = <&saw2>; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 clocks = <&apcs1_mbox>; 85 #cooling-cells = <2>; 86 }; 87 88 CPU3: cpu@103 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 reg = <0x103>; 93 next-level-cache = <&L2_1>; 94 qcom,acc = <&acc3>; 95 qcom,saw = <&saw3>; 96 cpu-idle-states = <&CPU_SLEEP_0>; 97 clocks = <&apcs1_mbox>; 98 #cooling-cells = <2>; 99 }; 100 101 CPU4: cpu@0 { 102 compatible = "arm,cortex-a53"; 103 device_type = "cpu"; 104 enable-method = "spin-table"; 105 reg = <0x0>; 106 qcom,acc = <&acc4>; 107 qcom,saw = <&saw4>; 108 cpu-idle-states = <&CPU_SLEEP_0>; 109 clocks = <&apcs0_mbox>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_0>; 112 L2_0: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-unified; 116 }; 117 }; 118 119 CPU5: cpu@1 { 120 compatible = "arm,cortex-a53"; 121 device_type = "cpu"; 122 enable-method = "spin-table"; 123 reg = <0x1>; 124 next-level-cache = <&L2_0>; 125 qcom,acc = <&acc5>; 126 qcom,saw = <&saw5>; 127 cpu-idle-states = <&CPU_SLEEP_0>; 128 clocks = <&apcs0_mbox>; 129 #cooling-cells = <2>; 130 }; 131 132 CPU6: cpu@2 { 133 compatible = "arm,cortex-a53"; 134 device_type = "cpu"; 135 enable-method = "spin-table"; 136 reg = <0x2>; 137 next-level-cache = <&L2_0>; 138 qcom,acc = <&acc6>; 139 qcom,saw = <&saw6>; 140 cpu-idle-states = <&CPU_SLEEP_0>; 141 clocks = <&apcs0_mbox>; 142 #cooling-cells = <2>; 143 }; 144 145 CPU7: cpu@3 { 146 compatible = "arm,cortex-a53"; 147 device_type = "cpu"; 148 enable-method = "spin-table"; 149 reg = <0x3>; 150 next-level-cache = <&L2_0>; 151 qcom,acc = <&acc7>; 152 qcom,saw = <&saw7>; 153 cpu-idle-states = <&CPU_SLEEP_0>; 154 clocks = <&apcs0_mbox>; 155 #cooling-cells = <2>; 156 }; 157 158 idle-states { 159 CPU_SLEEP_0: cpu-sleep-0 { 160 compatible = "arm,idle-state"; 161 entry-latency-us = <130>; 162 exit-latency-us = <150>; 163 min-residency-us = <2000>; 164 local-timer-stop; 165 }; 166 }; 167 }; 168 169 /* 170 * MSM8939 has a big.LITTLE heterogeneous computing architecture, 171 * consisting of two clusters of four ARM Cortex-A53s each. The 172 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs 173 * at 1.5-1.7GHz. 174 * 175 * The enable method used here is spin-table which presupposes use 176 * of a 2nd stage boot shim such as lk2nd to have installed a 177 * spin-table, the downstream non-psci/non-spin-table method that 178 * default msm8916/msm8936/msm8939 will not be supported upstream. 179 */ 180 cpu-map { 181 /* LITTLE (efficiency) cluster */ 182 cluster0 { 183 core0 { 184 cpu = <&CPU4>; 185 }; 186 187 core1 { 188 cpu = <&CPU5>; 189 }; 190 191 core2 { 192 cpu = <&CPU6>; 193 }; 194 195 core3 { 196 cpu = <&CPU7>; 197 }; 198 }; 199 200 /* big (performance) cluster */ 201 /* Boot CPU is cluster 1 core 0 */ 202 cluster1 { 203 core0 { 204 cpu = <&CPU0>; 205 }; 206 207 core1 { 208 cpu = <&CPU1>; 209 }; 210 211 core2 { 212 cpu = <&CPU2>; 213 }; 214 215 core3 { 216 cpu = <&CPU3>; 217 }; 218 }; 219 }; 220 221 firmware { 222 scm: scm { 223 compatible = "qcom,scm-msm8916", "qcom,scm"; 224 clocks = <&gcc GCC_CRYPTO_CLK>, 225 <&gcc GCC_CRYPTO_AXI_CLK>, 226 <&gcc GCC_CRYPTO_AHB_CLK>; 227 clock-names = "core", "bus", "iface"; 228 #reset-cells = <1>; 229 230 qcom,dload-mode = <&tcsr 0x6100>; 231 }; 232 }; 233 234 memory@80000000 { 235 device_type = "memory"; 236 /* We expect the bootloader to fill in the reg */ 237 reg = <0x0 0x80000000 0x0 0x0>; 238 }; 239 240 pmu { 241 compatible = "arm,cortex-a53-pmu"; 242 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 243 }; 244 245 rpm: remoteproc { 246 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc"; 247 248 smd-edge { 249 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 250 qcom,ipc = <&apcs1_mbox 8 0>; 251 qcom,smd-edge = <15>; 252 253 rpm_requests: rpm-requests { 254 compatible = "qcom,rpm-msm8936"; 255 qcom,smd-channels = "rpm_requests"; 256 257 rpmcc: clock-controller { 258 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; 259 #clock-cells = <1>; 260 clock-names = "xo"; 261 clocks = <&xo_board>; 262 }; 263 264 rpmpd: power-controller { 265 compatible = "qcom,msm8939-rpmpd"; 266 #power-domain-cells = <1>; 267 operating-points-v2 = <&rpmpd_opp_table>; 268 269 rpmpd_opp_table: opp-table { 270 compatible = "operating-points-v2"; 271 272 rpmpd_opp_ret: opp1 { 273 opp-level = <1>; 274 }; 275 276 rpmpd_opp_svs_krait: opp2 { 277 opp-level = <2>; 278 }; 279 280 rpmpd_opp_svs_soc: opp3 { 281 opp-level = <3>; 282 }; 283 284 rpmpd_opp_nom: opp4 { 285 opp-level = <4>; 286 }; 287 288 rpmpd_opp_turbo: opp5 { 289 opp-level = <5>; 290 }; 291 292 rpmpd_opp_super_turbo: opp6 { 293 opp-level = <6>; 294 }; 295 }; 296 }; 297 }; 298 }; 299 }; 300 301 reserved-memory { 302 #address-cells = <2>; 303 #size-cells = <2>; 304 ranges; 305 306 tz-apps@86000000 { 307 reg = <0x0 0x86000000 0x0 0x300000>; 308 no-map; 309 }; 310 311 smem@86300000 { 312 compatible = "qcom,smem"; 313 reg = <0x0 0x86300000 0x0 0x100000>; 314 no-map; 315 316 hwlocks = <&tcsr_mutex 3>; 317 qcom,rpm-msg-ram = <&rpm_msg_ram>; 318 }; 319 320 hypervisor@86400000 { 321 reg = <0x0 0x86400000 0x0 0x100000>; 322 no-map; 323 }; 324 325 tz@86500000 { 326 reg = <0x0 0x86500000 0x0 0x180000>; 327 no-map; 328 }; 329 330 reserved@86680000 { 331 reg = <0x0 0x86680000 0x0 0x80000>; 332 no-map; 333 }; 334 335 rmtfs@86700000 { 336 compatible = "qcom,rmtfs-mem"; 337 reg = <0x0 0x86700000 0x0 0xe0000>; 338 no-map; 339 340 qcom,client-id = <1>; 341 }; 342 343 rfsa@867e0000 { 344 reg = <0x0 0x867e0000 0x0 0x20000>; 345 no-map; 346 }; 347 348 mpss_mem: mpss@86800000 { 349 reg = <0x0 0x86800000 0x0 0x5500000>; 350 no-map; 351 }; 352 353 wcnss_mem: wcnss@8bd00000 { 354 reg = <0x0 0x8bd00000 0x0 0x600000>; 355 no-map; 356 }; 357 358 venus_mem: venus@8c300000 { 359 reg = <0x0 0x8c300000 0x0 0x800000>; 360 no-map; 361 }; 362 363 mba_mem: mba@8cb00000 { 364 reg = <0x0 0x8cb00000 0x0 0x100000>; 365 no-map; 366 }; 367 }; 368 369 smp2p-hexagon { 370 compatible = "qcom,smp2p"; 371 qcom,smem = <435>, <428>; 372 373 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 374 375 mboxes = <&apcs1_mbox 14>; 376 377 qcom,local-pid = <0>; 378 qcom,remote-pid = <1>; 379 380 hexagon_smp2p_out: master-kernel { 381 qcom,entry-name = "master-kernel"; 382 383 #qcom,smem-state-cells = <1>; 384 }; 385 386 hexagon_smp2p_in: slave-kernel { 387 qcom,entry-name = "slave-kernel"; 388 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 }; 392 }; 393 394 smp2p-wcnss { 395 compatible = "qcom,smp2p"; 396 qcom,smem = <451>, <431>; 397 398 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 399 400 mboxes = <&apcs1_mbox 18>; 401 402 qcom,local-pid = <0>; 403 qcom,remote-pid = <4>; 404 405 wcnss_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 }; 411 412 wcnss_smp2p_out: master-kernel { 413 qcom,entry-name = "master-kernel"; 414 415 #qcom,smem-state-cells = <1>; 416 }; 417 }; 418 419 smsm { 420 compatible = "qcom,smsm"; 421 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 qcom,ipc-1 = <&apcs1_mbox 8 13>; 426 qcom,ipc-3 = <&apcs1_mbox 8 19>; 427 428 apps_smsm: apps@0 { 429 reg = <0>; 430 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 hexagon_smsm: hexagon@1 { 435 reg = <1>; 436 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 437 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 442 wcnss_smsm: wcnss@6 { 443 reg = <6>; 444 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 445 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 }; 449 }; 450 451 soc: soc@0 { 452 compatible = "simple-bus"; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 ranges = <0 0 0 0xffffffff>; 456 457 rng@22000 { 458 compatible = "qcom,prng"; 459 reg = <0x00022000 0x200>; 460 clocks = <&gcc GCC_PRNG_AHB_CLK>; 461 clock-names = "core"; 462 }; 463 464 qfprom: qfprom@5c000 { 465 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 466 reg = <0x0005c000 0x1000>; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 470 tsens_base1: base1@a0 { 471 reg = <0xa0 0x1>; 472 bits = <0 8>; 473 }; 474 475 tsens_s6_p1: s6-p1@a1 { 476 reg = <0xa1 0x1>; 477 bits = <0 6>; 478 }; 479 480 tsens_s6_p2: s6-p2@a1 { 481 reg = <0xa1 0x2>; 482 bits = <6 6>; 483 }; 484 485 tsens_s7_p1: s7-p1@a2 { 486 reg = <0xa2 0x2>; 487 bits = <4 6>; 488 }; 489 490 tsens_s7_p2: s7-p2@a3 { 491 reg = <0xa3 0x1>; 492 bits = <2 6>; 493 }; 494 495 tsens_s8_p1: s8-p1@a4 { 496 reg = <0xa4 0x1>; 497 bits = <0 6>; 498 }; 499 500 tsens_s8_p2: s8-p2@a4 { 501 reg = <0xa4 0x2>; 502 bits = <6 6>; 503 }; 504 505 tsens_s9_p1: s9-p1@a5 { 506 reg = <0xa5 0x2>; 507 bits = <4 6>; 508 }; 509 510 tsens_s9_p2: s9-p2@a6 { 511 reg = <0xa6 0x1>; 512 bits = <2 6>; 513 }; 514 515 tsens_base2: base2@a7 { 516 reg = <0xa7 0x1>; 517 bits = <0 8>; 518 }; 519 520 tsens_mode: mode@d0 { 521 reg = <0xd0 0x1>; 522 bits = <0 3>; 523 }; 524 525 tsens_s0_p1: s0-p1@d0 { 526 reg = <0xd0 0x2>; 527 bits = <3 6>; 528 }; 529 530 tsens_s0_p2: s0-p1@d1 { 531 reg = <0xd1 0x1>; 532 bits = <1 6>; 533 }; 534 535 tsens_s1_p1: s1-p1@d1 { 536 reg = <0xd1 0x2>; 537 bits = <7 6>; 538 }; 539 540 tsens_s1_p2: s1-p2@d2 { 541 reg = <0xd2 0x2>; 542 bits = <5 6>; 543 }; 544 545 tsens_s2_p1: s2-p1@d3 { 546 reg = <0xd3 0x2>; 547 bits = <3 6>; 548 }; 549 550 tsens_s2_p2: s2-p2@d4 { 551 reg = <0xd4 0x1>; 552 bits = <1 6>; 553 }; 554 555 tsens_s3_p1: s3-p1@d4 { 556 reg = <0xd4 0x2>; 557 bits = <7 6>; 558 }; 559 560 tsens_s3_p2: s3-p2@d5 { 561 reg = <0xd5 0x2>; 562 bits = <5 6>; 563 }; 564 565 tsens_s5_p1: s5-p1@d6 { 566 reg = <0xd6 0x2>; 567 bits = <3 6>; 568 }; 569 570 tsens_s5_p2: s5-p2@d7 { 571 reg = <0xd7 0x1>; 572 bits = <1 6>; 573 }; 574 }; 575 576 rpm_msg_ram: sram@60000 { 577 compatible = "qcom,rpm-msg-ram"; 578 reg = <0x00060000 0x8000>; 579 }; 580 581 bimc: interconnect@400000 { 582 compatible = "qcom,msm8939-bimc"; 583 reg = <0x00400000 0x62000>; 584 clock-names = "bus", "bus_a"; 585 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 586 <&rpmcc RPM_SMD_BIMC_A_CLK>; 587 #interconnect-cells = <1>; 588 }; 589 590 tsens: thermal-sensor@4a9000 { 591 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; 592 reg = <0x004a9000 0x1000>, /* TM */ 593 <0x004a8000 0x1000>; /* SROT */ 594 nvmem-cells = <&tsens_mode>, 595 <&tsens_base1>, <&tsens_base2>, 596 <&tsens_s0_p1>, <&tsens_s0_p2>, 597 <&tsens_s1_p1>, <&tsens_s1_p2>, 598 <&tsens_s2_p1>, <&tsens_s2_p2>, 599 <&tsens_s3_p1>, <&tsens_s3_p2>, 600 <&tsens_s5_p1>, <&tsens_s5_p2>, 601 <&tsens_s6_p1>, <&tsens_s6_p2>, 602 <&tsens_s7_p1>, <&tsens_s7_p2>, 603 <&tsens_s8_p1>, <&tsens_s8_p2>, 604 <&tsens_s9_p1>, <&tsens_s9_p2>; 605 nvmem-cell-names = "mode", 606 "base1", "base2", 607 "s0_p1", "s0_p2", 608 "s1_p1", "s1_p2", 609 "s2_p1", "s2_p2", 610 "s3_p1", "s3_p2", 611 "s5_p1", "s5_p2", 612 "s6_p1", "s6_p2", 613 "s7_p1", "s7_p2", 614 "s8_p1", "s8_p2", 615 "s9_p1", "s9_p2"; 616 #qcom,sensors = <9>; 617 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "uplow"; 619 #thermal-sensor-cells = <1>; 620 }; 621 622 restart@4ab000 { 623 compatible = "qcom,pshold"; 624 reg = <0x004ab000 0x4>; 625 }; 626 627 pcnoc: interconnect@500000 { 628 compatible = "qcom,msm8939-pcnoc"; 629 reg = <0x00500000 0x11000>; 630 clock-names = "bus", "bus_a"; 631 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 632 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 633 #interconnect-cells = <1>; 634 }; 635 636 snoc: interconnect@580000 { 637 compatible = "qcom,msm8939-snoc"; 638 reg = <0x00580000 0x14080>; 639 clock-names = "bus", "bus_a"; 640 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 641 <&rpmcc RPM_SMD_SNOC_A_CLK>; 642 #interconnect-cells = <1>; 643 644 snoc_mm: interconnect-snoc { 645 compatible = "qcom,msm8939-snoc-mm"; 646 clock-names = "bus", "bus_a"; 647 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>, 648 <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; 649 #interconnect-cells = <1>; 650 }; 651 }; 652 653 tlmm: pinctrl@1000000 { 654 compatible = "qcom,msm8916-pinctrl"; 655 reg = <0x01000000 0x300000>; 656 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 657 gpio-controller; 658 gpio-ranges = <&tlmm 0 0 122>; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 663 blsp_i2c1_default: blsp-i2c1-default-state { 664 pins = "gpio2", "gpio3"; 665 function = "blsp_i2c1"; 666 drive-strength = <2>; 667 bias-disable; 668 }; 669 670 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 671 pins = "gpio2", "gpio3"; 672 function = "gpio"; 673 drive-strength = <2>; 674 bias-disable; 675 }; 676 677 blsp_i2c2_default: blsp-i2c2-default-state { 678 pins = "gpio6", "gpio7"; 679 function = "blsp_i2c2"; 680 drive-strength = <2>; 681 bias-disable; 682 }; 683 684 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 685 pins = "gpio6", "gpio7"; 686 function = "gpio"; 687 drive-strength = <2>; 688 bias-disable; 689 }; 690 691 blsp_i2c3_default: blsp-i2c3-default-state { 692 pins = "gpio10", "gpio11"; 693 function = "blsp_i2c3"; 694 drive-strength = <2>; 695 bias-disable; 696 }; 697 698 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 699 pins = "gpio10", "gpio11"; 700 function = "gpio"; 701 drive-strength = <2>; 702 bias-disable; 703 }; 704 705 blsp_i2c4_default: blsp-i2c4-default-state { 706 pins = "gpio14", "gpio15"; 707 function = "blsp_i2c4"; 708 drive-strength = <2>; 709 bias-disable; 710 }; 711 712 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 713 pins = "gpio14", "gpio15"; 714 function = "gpio"; 715 drive-strength = <2>; 716 bias-disable; 717 }; 718 719 blsp_i2c5_default: blsp-i2c5-default-state { 720 pins = "gpio18", "gpio19"; 721 function = "blsp_i2c5"; 722 drive-strength = <2>; 723 bias-disable; 724 }; 725 726 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 727 pins = "gpio18", "gpio19"; 728 function = "gpio"; 729 drive-strength = <2>; 730 bias-disable; 731 }; 732 733 blsp_i2c6_default: blsp-i2c6-default-state { 734 pins = "gpio22", "gpio23"; 735 function = "blsp_i2c6"; 736 drive-strength = <2>; 737 bias-disable; 738 }; 739 740 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 741 pins = "gpio22", "gpio23"; 742 function = "gpio"; 743 drive-strength = <2>; 744 bias-disable; 745 }; 746 747 blsp_spi1_default: blsp-spi1-default-state { 748 spi-pins { 749 pins = "gpio0", "gpio1", "gpio3"; 750 function = "blsp_spi1"; 751 drive-strength = <12>; 752 bias-disable; 753 }; 754 755 cs-pins { 756 pins = "gpio2"; 757 function = "gpio"; 758 drive-strength = <16>; 759 bias-disable; 760 output-high; 761 }; 762 }; 763 764 blsp_spi1_sleep: blsp-spi1-sleep-state { 765 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-pull-down; 769 }; 770 771 blsp_spi2_default: blsp-spi2-default-state { 772 spi-pins { 773 pins = "gpio4", "gpio5", "gpio7"; 774 function = "blsp_spi2"; 775 drive-strength = <12>; 776 bias-disable; 777 }; 778 779 cs-pins { 780 pins = "gpio6"; 781 function = "gpio"; 782 drive-strength = <16>; 783 bias-disable; 784 output-high; 785 }; 786 }; 787 788 blsp_spi2_sleep: blsp-spi2-sleep-state { 789 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 790 function = "gpio"; 791 drive-strength = <2>; 792 bias-pull-down; 793 }; 794 795 blsp_spi3_default: blsp-spi3-default-state { 796 spi-pins { 797 pins = "gpio8", "gpio9", "gpio11"; 798 function = "blsp_spi3"; 799 drive-strength = <12>; 800 bias-disable; 801 }; 802 803 cs-pins { 804 pins = "gpio10"; 805 function = "gpio"; 806 drive-strength = <16>; 807 bias-disable; 808 output-high; 809 }; 810 }; 811 812 blsp_spi3_sleep: blsp-spi3-sleep-state { 813 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 814 function = "gpio"; 815 drive-strength = <2>; 816 bias-pull-down; 817 }; 818 819 blsp_spi4_default: blsp-spi4-default-state { 820 spi-pins { 821 pins = "gpio12", "gpio13", "gpio15"; 822 function = "blsp_spi4"; 823 drive-strength = <12>; 824 bias-disable; 825 }; 826 827 cs-pins { 828 pins = "gpio14"; 829 function = "gpio"; 830 drive-strength = <16>; 831 bias-disable; 832 output-high; 833 }; 834 }; 835 836 blsp_spi4_sleep: blsp-spi4-sleep-state { 837 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 838 function = "gpio"; 839 drive-strength = <2>; 840 bias-pull-down; 841 }; 842 843 blsp_spi5_default: blsp-spi5-default-state { 844 spi-pins { 845 pins = "gpio16", "gpio17", "gpio19"; 846 function = "blsp_spi5"; 847 drive-strength = <12>; 848 bias-disable; 849 }; 850 851 cs-pins { 852 pins = "gpio18"; 853 function = "gpio"; 854 drive-strength = <16>; 855 bias-disable; 856 output-high; 857 }; 858 }; 859 860 blsp_spi5_sleep: blsp-spi5-sleep-state { 861 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 862 function = "gpio"; 863 drive-strength = <2>; 864 bias-pull-down; 865 }; 866 867 blsp_spi6_default: blsp-spi6-default-state { 868 spi-pins { 869 pins = "gpio20", "gpio21", "gpio23"; 870 function = "blsp_spi6"; 871 drive-strength = <12>; 872 bias-disable; 873 }; 874 875 cs-pins { 876 pins = "gpio22"; 877 function = "gpio"; 878 drive-strength = <16>; 879 bias-disable; 880 output-high; 881 }; 882 }; 883 884 blsp_spi6_sleep: blsp-spi6-sleep-state { 885 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 886 function = "gpio"; 887 drive-strength = <2>; 888 bias-pull-down; 889 }; 890 891 blsp_uart1_default: blsp-uart1-default-state { 892 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 893 function = "blsp_uart1"; 894 drive-strength = <16>; 895 bias-disable; 896 }; 897 898 blsp_uart1_sleep: blsp-uart1-sleep-state { 899 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 900 function = "gpio"; 901 drive-strength = <2>; 902 bias-pull-down; 903 }; 904 905 blsp_uart2_default: blsp-uart2-default-state { 906 pins = "gpio4", "gpio5"; 907 function = "blsp_uart2"; 908 drive-strength = <16>; 909 bias-disable; 910 }; 911 912 blsp_uart2_sleep: blsp-uart2-sleep-state { 913 pins = "gpio4", "gpio5"; 914 function = "gpio"; 915 drive-strength = <2>; 916 bias-pull-down; 917 }; 918 919 camera_front_default: camera-front-default-state { 920 pwdn-pins { 921 pins = "gpio33"; 922 function = "gpio"; 923 drive-strength = <16>; 924 bias-disable; 925 }; 926 927 rst-pins { 928 pins = "gpio28"; 929 function = "gpio"; 930 drive-strength = <16>; 931 bias-disable; 932 }; 933 934 mclk1-pins { 935 pins = "gpio27"; 936 function = "cam_mclk1"; 937 drive-strength = <16>; 938 bias-disable; 939 }; 940 }; 941 942 camera_rear_default: camera-rear-default-state { 943 pwdn-pins { 944 pins = "gpio34"; 945 function = "gpio"; 946 drive-strength = <16>; 947 bias-disable; 948 }; 949 950 rst-pins { 951 pins = "gpio35"; 952 function = "gpio"; 953 drive-strength = <16>; 954 bias-disable; 955 }; 956 957 mclk0-pins { 958 pins = "gpio26"; 959 function = "cam_mclk0"; 960 drive-strength = <16>; 961 bias-disable; 962 }; 963 }; 964 965 cci0_default: cci0-default-state { 966 pins = "gpio29", "gpio30"; 967 function = "cci_i2c"; 968 drive-strength = <16>; 969 bias-disable; 970 }; 971 972 cdc_dmic_default: cdc-dmic-default-state { 973 clk-pins { 974 pins = "gpio0"; 975 function = "dmic0_clk"; 976 drive-strength = <8>; 977 }; 978 979 data-pins { 980 pins = "gpio1"; 981 function = "dmic0_data"; 982 drive-strength = <8>; 983 }; 984 }; 985 986 cdc_dmic_sleep: cdc-dmic-sleep-state { 987 clk-pins { 988 pins = "gpio0"; 989 function = "dmic0_clk"; 990 drive-strength = <2>; 991 bias-disable; 992 }; 993 994 data-pins { 995 pins = "gpio1"; 996 function = "dmic0_data"; 997 drive-strength = <2>; 998 bias-disable; 999 }; 1000 }; 1001 1002 cdc_pdm_default: cdc-pdm-default-state { 1003 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1004 "gpio67", "gpio68"; 1005 function = "cdc_pdm0"; 1006 drive-strength = <8>; 1007 bias-disable; 1008 }; 1009 1010 cdc_pdm_sleep: cdc-pdm-sleep-state { 1011 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1012 "gpio67", "gpio68"; 1013 function = "cdc_pdm0"; 1014 drive-strength = <2>; 1015 bias-pull-down; 1016 }; 1017 1018 pri_mi2s_default: mi2s-pri-default-state { 1019 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1020 function = "pri_mi2s"; 1021 drive-strength = <8>; 1022 bias-disable; 1023 }; 1024 1025 pri_mi2s_sleep: mi2s-pri-sleep-state { 1026 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1027 function = "pri_mi2s"; 1028 drive-strength = <2>; 1029 bias-disable; 1030 }; 1031 1032 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1033 pins = "gpio116"; 1034 function = "pri_mi2s"; 1035 drive-strength = <8>; 1036 bias-disable; 1037 }; 1038 1039 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1040 pins = "gpio116"; 1041 function = "pri_mi2s"; 1042 drive-strength = <2>; 1043 bias-disable; 1044 }; 1045 1046 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1047 pins = "gpio110"; 1048 function = "pri_mi2s_ws"; 1049 drive-strength = <8>; 1050 bias-disable; 1051 }; 1052 1053 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1054 pins = "gpio110"; 1055 function = "pri_mi2s_ws"; 1056 drive-strength = <2>; 1057 bias-disable; 1058 }; 1059 1060 sec_mi2s_default: mi2s-sec-default-state { 1061 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1062 function = "sec_mi2s"; 1063 drive-strength = <8>; 1064 bias-disable; 1065 }; 1066 1067 sec_mi2s_sleep: mi2s-sec-sleep-state { 1068 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1069 function = "sec_mi2s"; 1070 drive-strength = <2>; 1071 bias-disable; 1072 }; 1073 1074 sdc1_default: sdc1-default-state { 1075 clk-pins { 1076 pins = "sdc1_clk"; 1077 bias-disable; 1078 drive-strength = <16>; 1079 }; 1080 1081 cmd-pins { 1082 pins = "sdc1_cmd"; 1083 bias-pull-up; 1084 drive-strength = <10>; 1085 }; 1086 1087 data-pins { 1088 pins = "sdc1_data"; 1089 bias-pull-up; 1090 drive-strength = <10>; 1091 }; 1092 }; 1093 1094 sdc1_sleep: sdc1-sleep-state { 1095 clk-pins { 1096 pins = "sdc1_clk"; 1097 bias-disable; 1098 drive-strength = <2>; 1099 }; 1100 1101 cmd-pins { 1102 pins = "sdc1_cmd"; 1103 bias-pull-up; 1104 drive-strength = <2>; 1105 }; 1106 1107 data-pins { 1108 pins = "sdc1_data"; 1109 bias-pull-up; 1110 drive-strength = <2>; 1111 }; 1112 }; 1113 1114 sdc2_default: sdc2-default-state { 1115 clk-pins { 1116 pins = "sdc2_clk"; 1117 bias-disable; 1118 drive-strength = <16>; 1119 }; 1120 1121 cmd-pins { 1122 pins = "sdc2_cmd"; 1123 bias-pull-up; 1124 drive-strength = <10>; 1125 }; 1126 1127 data-pins { 1128 pins = "sdc2_data"; 1129 bias-pull-up; 1130 drive-strength = <10>; 1131 }; 1132 }; 1133 1134 sdc2_sleep: sdc2-sleep-state { 1135 clk-pins { 1136 pins = "sdc2_clk"; 1137 bias-disable; 1138 drive-strength = <2>; 1139 }; 1140 1141 cmd-pins { 1142 pins = "sdc2_cmd"; 1143 bias-pull-up; 1144 drive-strength = <2>; 1145 }; 1146 1147 data-pins { 1148 pins = "sdc2_data"; 1149 bias-pull-up; 1150 drive-strength = <2>; 1151 }; 1152 }; 1153 1154 wcss_wlan_default: wcss-wlan-default-state { 1155 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1156 function = "wcss_wlan"; 1157 drive-strength = <6>; 1158 bias-pull-up; 1159 }; 1160 }; 1161 1162 gcc: clock-controller@1800000 { 1163 compatible = "qcom,gcc-msm8939"; 1164 reg = <0x01800000 0x80000>; 1165 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1166 <&sleep_clk>, 1167 <&mdss_dsi0_phy 1>, 1168 <&mdss_dsi0_phy 0>, 1169 <0>, 1170 <0>, 1171 <0>; 1172 clock-names = "xo", 1173 "sleep_clk", 1174 "dsi0pll", 1175 "dsi0pllbyte", 1176 "ext_mclk", 1177 "ext_pri_i2s", 1178 "ext_sec_i2s"; 1179 #clock-cells = <1>; 1180 #reset-cells = <1>; 1181 #power-domain-cells = <1>; 1182 }; 1183 1184 tcsr_mutex: hwlock@1905000 { 1185 compatible = "qcom,tcsr-mutex"; 1186 reg = <0x01905000 0x20000>; 1187 #hwlock-cells = <1>; 1188 }; 1189 1190 tcsr: syscon@1937000 { 1191 compatible = "qcom,tcsr-msm8916", "syscon"; 1192 reg = <0x01937000 0x30000>; 1193 }; 1194 1195 mdss: display-subsystem@1a00000 { 1196 compatible = "qcom,mdss"; 1197 reg = <0x01a00000 0x1000>, 1198 <0x01ac8000 0x3000>; 1199 reg-names = "mdss_phys", "vbif_phys"; 1200 1201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1202 interrupt-controller; 1203 1204 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1205 <&gcc GCC_MDSS_AXI_CLK>, 1206 <&gcc GCC_MDSS_VSYNC_CLK>; 1207 clock-names = "iface", 1208 "bus", 1209 "vsync"; 1210 1211 power-domains = <&gcc MDSS_GDSC>; 1212 1213 #address-cells = <1>; 1214 #size-cells = <1>; 1215 #interrupt-cells = <1>; 1216 ranges; 1217 1218 status = "disabled"; 1219 1220 mdss_mdp: display-controller@1a01000 { 1221 compatible = "qcom,mdp5"; 1222 reg = <0x01a01000 0x89000>; 1223 reg-names = "mdp_phys"; 1224 1225 interrupt-parent = <&mdss>; 1226 interrupts = <0>; 1227 1228 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1229 <&gcc GCC_MDSS_AXI_CLK>, 1230 <&gcc GCC_MDSS_MDP_CLK>, 1231 <&gcc GCC_MDSS_VSYNC_CLK>; 1232 clock-names = "iface", 1233 "bus", 1234 "core", 1235 "vsync"; 1236 1237 iommus = <&apps_iommu 4>; 1238 1239 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1240 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; 1241 interconnect-names = "mdp0-mem", "mdp1-mem"; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 port@0 { 1248 reg = <0>; 1249 mdss_mdp_intf1_out: endpoint { 1250 remote-endpoint = <&mdss_dsi0_in>; 1251 }; 1252 }; 1253 1254 port@1 { 1255 reg = <1>; 1256 mdss_mdp_intf2_out: endpoint { 1257 remote-endpoint = <&mdss_dsi1_in>; 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 mdss_dsi0: dsi@1a98000 { 1264 compatible = "qcom,msm8916-dsi-ctrl", 1265 "qcom,mdss-dsi-ctrl"; 1266 reg = <0x01a98000 0x25c>; 1267 reg-names = "dsi_ctrl"; 1268 1269 interrupt-parent = <&mdss>; 1270 interrupts = <4>; 1271 1272 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1273 <&gcc GCC_MDSS_AHB_CLK>, 1274 <&gcc GCC_MDSS_AXI_CLK>, 1275 <&gcc GCC_MDSS_BYTE0_CLK>, 1276 <&gcc GCC_MDSS_PCLK0_CLK>, 1277 <&gcc GCC_MDSS_ESC0_CLK>; 1278 clock-names = "mdp_core", 1279 "iface", 1280 "bus", 1281 "byte", 1282 "pixel", 1283 "core"; 1284 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1285 <&gcc PCLK0_CLK_SRC>; 1286 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1287 <&mdss_dsi0_phy 1>; 1288 1289 phys = <&mdss_dsi0_phy>; 1290 status = "disabled"; 1291 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 ports { 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 1299 port@0 { 1300 reg = <0>; 1301 mdss_dsi0_in: endpoint { 1302 remote-endpoint = <&mdss_mdp_intf1_out>; 1303 }; 1304 }; 1305 1306 port@1 { 1307 reg = <1>; 1308 mdss_dsi0_out: endpoint { 1309 }; 1310 }; 1311 }; 1312 }; 1313 1314 mdss_dsi0_phy: phy@1a98300 { 1315 compatible = "qcom,dsi-phy-28nm-lp"; 1316 reg = <0x01a98300 0xd4>, 1317 <0x01a98500 0x280>, 1318 <0x01a98780 0x30>; 1319 reg-names = "dsi_pll", 1320 "dsi_phy", 1321 "dsi_phy_regulator"; 1322 1323 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1324 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1325 clock-names = "iface", "ref"; 1326 1327 #clock-cells = <1>; 1328 #phy-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 mdss_dsi1: dsi@1aa0000 { 1333 compatible = "qcom,msm8916-dsi-ctrl", 1334 "qcom,mdss-dsi-ctrl"; 1335 reg = <0x01aa0000 0x25c>; 1336 reg-names = "dsi_ctrl"; 1337 1338 interrupt-parent = <&mdss>; 1339 interrupts = <5>; 1340 1341 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1342 <&gcc GCC_MDSS_AHB_CLK>, 1343 <&gcc GCC_MDSS_AXI_CLK>, 1344 <&gcc GCC_MDSS_BYTE1_CLK>, 1345 <&gcc GCC_MDSS_PCLK1_CLK>, 1346 <&gcc GCC_MDSS_ESC1_CLK>; 1347 clock-names = "mdp_core", 1348 "iface", 1349 "bus", 1350 "byte", 1351 "pixel", 1352 "core"; 1353 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1354 <&gcc PCLK1_CLK_SRC>; 1355 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1356 <&mdss_dsi0_phy 1>; 1357 phys = <&mdss_dsi1_phy>; 1358 status = "disabled"; 1359 1360 ports { 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 port@0 { 1365 reg = <0>; 1366 mdss_dsi1_in: endpoint { 1367 remote-endpoint = <&mdss_mdp_intf2_out>; 1368 }; 1369 }; 1370 1371 port@1 { 1372 reg = <1>; 1373 mdss_dsi1_out: endpoint { 1374 }; 1375 }; 1376 }; 1377 }; 1378 1379 mdss_dsi1_phy: phy@1aa0300 { 1380 compatible = "qcom,dsi-phy-28nm-lp"; 1381 reg = <0x01aa0300 0xd4>, 1382 <0x01aa0500 0x280>, 1383 <0x01aa0780 0x30>; 1384 reg-names = "dsi_pll", 1385 "dsi_phy", 1386 "dsi_phy_regulator"; 1387 1388 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1389 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1390 clock-names = "iface", "ref"; 1391 1392 #clock-cells = <1>; 1393 #phy-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 }; 1397 1398 gpu@1c00000 { 1399 compatible = "qcom,adreno-405.0", "qcom,adreno"; 1400 reg = <0x01c00000 0x10000>; 1401 reg-names = "kgsl_3d0_reg_memory"; 1402 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "kgsl_3d0_irq"; 1404 clock-names = "core", 1405 "iface", 1406 "mem", 1407 "mem_iface", 1408 "alt_mem_iface", 1409 "gfx3d", 1410 "rbbmtimer"; 1411 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1412 <&gcc GCC_OXILI_AHB_CLK>, 1413 <&gcc GCC_OXILI_GMEM_CLK>, 1414 <&gcc GCC_BIMC_GFX_CLK>, 1415 <&gcc GCC_BIMC_GPU_CLK>, 1416 <&gcc GFX3D_CLK_SRC>, 1417 <&gcc GCC_OXILI_TIMER_CLK>; 1418 power-domains = <&gcc OXILI_GDSC>; 1419 operating-points-v2 = <&opp_table>; 1420 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1421 1422 opp_table: opp-table { 1423 compatible = "operating-points-v2"; 1424 1425 opp-550000000 { 1426 opp-hz = /bits/ 64 <550000000>; 1427 }; 1428 1429 opp-465000000 { 1430 opp-hz = /bits/ 64 <465000000>; 1431 }; 1432 1433 opp-400000000 { 1434 opp-hz = /bits/ 64 <400000000>; 1435 }; 1436 1437 opp-220000000 { 1438 opp-hz = /bits/ 64 <220000000>; 1439 }; 1440 1441 opp-19200000 { 1442 opp-hz = /bits/ 64 <19200000>; 1443 }; 1444 }; 1445 }; 1446 1447 apps_iommu: iommu@1ef0000 { 1448 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1449 reg = <0x01ef0000 0x3000>; 1450 ranges = <0 0x01e20000 0x20000>; 1451 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1452 <&gcc GCC_APSS_TCU_CLK>; 1453 clock-names = "iface", "bus"; 1454 #address-cells = <1>; 1455 #size-cells = <1>; 1456 #iommu-cells = <1>; 1457 qcom,iommu-secure-id = <17>; 1458 1459 /* mdp_0: */ 1460 iommu-ctx@4000 { 1461 compatible = "qcom,msm-iommu-v1-ns"; 1462 reg = <0x4000 0x1000>; 1463 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1464 }; 1465 1466 /* venus_ns: */ 1467 iommu-ctx@5000 { 1468 compatible = "qcom,msm-iommu-v1-sec"; 1469 reg = <0x5000 0x1000>; 1470 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1471 }; 1472 }; 1473 1474 gpu_iommu: iommu@1f08000 { 1475 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1476 ranges = <0 0x1f08000 0x10000>; 1477 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1478 <&gcc GCC_GFX_TCU_CLK>, 1479 <&gcc GCC_GFX_TBU_CLK>; 1480 clock-names = "iface", "bus", "tbu"; 1481 #address-cells = <1>; 1482 #size-cells = <1>; 1483 #iommu-cells = <1>; 1484 qcom,iommu-secure-id = <18>; 1485 1486 /* gfx3d_user: */ 1487 iommu-ctx@1000 { 1488 compatible = "qcom,msm-iommu-v1-ns"; 1489 reg = <0x1000 0x1000>; 1490 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1491 }; 1492 1493 /* gfx3d_priv: */ 1494 iommu-ctx@2000 { 1495 compatible = "qcom,msm-iommu-v1-ns"; 1496 reg = <0x2000 0x1000>; 1497 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1498 }; 1499 }; 1500 1501 spmi_bus: spmi@200f000 { 1502 compatible = "qcom,spmi-pmic-arb"; 1503 reg = <0x0200f000 0x001000>, 1504 <0x02400000 0x400000>, 1505 <0x02c00000 0x400000>, 1506 <0x03800000 0x200000>, 1507 <0x0200a000 0x002100>; 1508 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1509 interrupt-names = "periph_irq"; 1510 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1511 qcom,ee = <0>; 1512 qcom,channel = <0>; 1513 #address-cells = <2>; 1514 #size-cells = <0>; 1515 interrupt-controller; 1516 #interrupt-cells = <4>; 1517 }; 1518 1519 mpss: remoteproc@4080000 { 1520 compatible = "qcom,msm8916-mss-pil"; 1521 reg = <0x04080000 0x100>, <0x04020000 0x040>; 1522 reg-names = "qdsp6", "rmb"; 1523 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1524 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1525 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1526 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1527 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1528 interrupt-names = "wdog", 1529 "fatal", 1530 "ready", 1531 "handover", 1532 "stop-ack"; 1533 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1534 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1535 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1536 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1537 clock-names = "iface", 1538 "bus", 1539 "mem", 1540 "xo"; 1541 power-domains = <&rpmpd MSM8939_VDDMDCX>, 1542 <&rpmpd MSM8939_VDDMX>; 1543 power-domain-names = "cx", "mx"; 1544 qcom,smem-states = <&hexagon_smp2p_out 0>; 1545 qcom,smem-state-names = "stop"; 1546 resets = <&scm 0>; 1547 reset-names = "mss_restart"; 1548 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1549 status = "disabled"; 1550 1551 mba { 1552 memory-region = <&mba_mem>; 1553 }; 1554 1555 mpss { 1556 memory-region = <&mpss_mem>; 1557 }; 1558 1559 smd-edge { 1560 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1561 1562 qcom,smd-edge = <0>; 1563 mboxes = <&apcs1_mbox 12>; 1564 qcom,remote-pid = <1>; 1565 1566 label = "hexagon"; 1567 }; 1568 }; 1569 1570 sound: sound@7702000 { 1571 compatible = "qcom,apq8016-sbc-sndcard"; 1572 reg = <0x07702000 0x4>, 1573 <0x07702004 0x4>; 1574 reg-names = "mic-iomux", "spkr-iomux"; 1575 status = "disabled"; 1576 }; 1577 1578 lpass: audio-controller@7708000 { 1579 compatible = "qcom,apq8016-lpass-cpu"; 1580 reg = <0x07708000 0x10000>; 1581 reg-names = "lpass-lpaif"; 1582 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1583 interrupt-names = "lpass-irq-lpaif"; 1584 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1585 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1586 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1587 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1588 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 1589 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1590 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 1591 clock-names = "ahbix-clk", 1592 "mi2s-bit-clk0", 1593 "mi2s-bit-clk1", 1594 "mi2s-bit-clk2", 1595 "mi2s-bit-clk3", 1596 "pcnoc-mport-clk", 1597 "pcnoc-sway-clk"; 1598 #sound-dai-cells = <1>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 lpass_codec: audio-codec@771c000 { 1605 compatible = "qcom,msm8916-wcd-digital-codec"; 1606 reg = <0x0771c000 0x400>; 1607 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1608 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1609 clock-names = "ahbix-clk", "mclk"; 1610 #sound-dai-cells = <1>; 1611 status = "disabled"; 1612 }; 1613 1614 sdhc_1: mmc@7824900 { 1615 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1616 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1617 reg-names = "hc", "core"; 1618 1619 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "hc_irq", "pwr_irq"; 1622 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1623 <&gcc GCC_SDCC1_APPS_CLK>, 1624 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1625 clock-names = "iface", "core", "xo"; 1626 resets = <&gcc GCC_SDCC1_BCR>; 1627 pinctrl-0 = <&sdc1_default>; 1628 pinctrl-1 = <&sdc1_sleep>; 1629 pinctrl-names = "default", "sleep"; 1630 mmc-ddr-1_8v; 1631 bus-width = <8>; 1632 non-removable; 1633 status = "disabled"; 1634 }; 1635 1636 sdhc_2: mmc@7864900 { 1637 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1638 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1639 reg-names = "hc", "core"; 1640 1641 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupt-names = "hc_irq", "pwr_irq"; 1644 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1645 <&gcc GCC_SDCC2_APPS_CLK>, 1646 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1647 clock-names = "iface", "core", "xo"; 1648 resets = <&gcc GCC_SDCC2_BCR>; 1649 pinctrl-0 = <&sdc2_default>; 1650 pinctrl-1 = <&sdc2_sleep>; 1651 pinctrl-names = "default", "sleep"; 1652 bus-width = <4>; 1653 status = "disabled"; 1654 }; 1655 1656 blsp_dma: dma-controller@7884000 { 1657 compatible = "qcom,bam-v1.7.0"; 1658 reg = <0x07884000 0x23000>; 1659 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1661 clock-names = "bam_clk"; 1662 #dma-cells = <1>; 1663 qcom,ee = <0>; 1664 qcom,controlled-remotely; 1665 }; 1666 1667 blsp_uart1: serial@78af000 { 1668 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1669 reg = <0x078af000 0x200>; 1670 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1671 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1672 clock-names = "core", "iface"; 1673 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1674 dma-names = "tx", "rx"; 1675 pinctrl-0 = <&blsp_uart1_default>; 1676 pinctrl-1 = <&blsp_uart1_sleep>; 1677 pinctrl-names = "default", "sleep"; 1678 status = "disabled"; 1679 }; 1680 1681 blsp_uart2: serial@78b0000 { 1682 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1683 reg = <0x078b0000 0x200>; 1684 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1685 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1686 clock-names = "core", "iface"; 1687 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1688 dma-names = "tx", "rx"; 1689 pinctrl-0 = <&blsp_uart2_default>; 1690 pinctrl-1 = <&blsp_uart2_sleep>; 1691 pinctrl-names = "default", "sleep"; 1692 status = "disabled"; 1693 }; 1694 1695 blsp_i2c1: i2c@78b5000 { 1696 compatible = "qcom,i2c-qup-v2.2.1"; 1697 reg = <0x078b5000 0x500>; 1698 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1699 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1700 <&gcc GCC_BLSP1_AHB_CLK>; 1701 clock-names = "core", "iface"; 1702 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1703 dma-names = "tx", "rx"; 1704 pinctrl-0 = <&blsp_i2c1_default>; 1705 pinctrl-1 = <&blsp_i2c1_sleep>; 1706 pinctrl-names = "default", "sleep"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 blsp_spi1: spi@78b5000 { 1713 compatible = "qcom,spi-qup-v2.2.1"; 1714 reg = <0x078b5000 0x500>; 1715 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1716 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1717 <&gcc GCC_BLSP1_AHB_CLK>; 1718 clock-names = "core", "iface"; 1719 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1720 dma-names = "tx", "rx"; 1721 pinctrl-0 = <&blsp_spi1_default>; 1722 pinctrl-1 = <&blsp_spi1_sleep>; 1723 pinctrl-names = "default", "sleep"; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 status = "disabled"; 1727 }; 1728 1729 blsp_i2c2: i2c@78b6000 { 1730 compatible = "qcom,i2c-qup-v2.2.1"; 1731 reg = <0x078b6000 0x500>; 1732 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1734 <&gcc GCC_BLSP1_AHB_CLK>; 1735 clock-names = "core", "iface"; 1736 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1737 dma-names = "tx", "rx"; 1738 pinctrl-0 = <&blsp_i2c2_default>; 1739 pinctrl-1 = <&blsp_i2c2_sleep>; 1740 pinctrl-names = "default", "sleep"; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 status = "disabled"; 1744 }; 1745 1746 blsp_spi2: spi@78b6000 { 1747 compatible = "qcom,spi-qup-v2.2.1"; 1748 reg = <0x078b6000 0x500>; 1749 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1750 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1751 <&gcc GCC_BLSP1_AHB_CLK>; 1752 clock-names = "core", "iface"; 1753 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1754 dma-names = "tx", "rx"; 1755 pinctrl-0 = <&blsp_spi2_default>; 1756 pinctrl-1 = <&blsp_spi2_sleep>; 1757 pinctrl-names = "default", "sleep"; 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 status = "disabled"; 1761 }; 1762 1763 blsp_i2c3: i2c@78b7000 { 1764 compatible = "qcom,i2c-qup-v2.2.1"; 1765 reg = <0x078b7000 0x500>; 1766 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1767 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1768 <&gcc GCC_BLSP1_AHB_CLK>; 1769 clock-names = "core", "iface"; 1770 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1771 dma-names = "tx", "rx"; 1772 pinctrl-0 = <&blsp_i2c3_default>; 1773 pinctrl-1 = <&blsp_i2c3_sleep>; 1774 pinctrl-names = "default", "sleep"; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 status = "disabled"; 1778 }; 1779 1780 blsp_spi3: spi@78b7000 { 1781 compatible = "qcom,spi-qup-v2.2.1"; 1782 reg = <0x078b7000 0x500>; 1783 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1784 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1785 <&gcc GCC_BLSP1_AHB_CLK>; 1786 clock-names = "core", "iface"; 1787 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1788 dma-names = "tx", "rx"; 1789 pinctrl-0 = <&blsp_spi3_default>; 1790 pinctrl-1 = <&blsp_spi3_sleep>; 1791 pinctrl-names = "default", "sleep"; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 status = "disabled"; 1795 }; 1796 1797 blsp_i2c4: i2c@78b8000 { 1798 compatible = "qcom,i2c-qup-v2.2.1"; 1799 reg = <0x078b8000 0x500>; 1800 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1802 <&gcc GCC_BLSP1_AHB_CLK>; 1803 clock-names = "core", "iface"; 1804 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1805 dma-names = "tx", "rx"; 1806 pinctrl-0 = <&blsp_i2c4_default>; 1807 pinctrl-1 = <&blsp_i2c4_sleep>; 1808 pinctrl-names = "default", "sleep"; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 status = "disabled"; 1812 }; 1813 1814 blsp_spi4: spi@78b8000 { 1815 compatible = "qcom,spi-qup-v2.2.1"; 1816 reg = <0x078b8000 0x500>; 1817 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1818 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1819 <&gcc GCC_BLSP1_AHB_CLK>; 1820 clock-names = "core", "iface"; 1821 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1822 dma-names = "tx", "rx"; 1823 pinctrl-0 = <&blsp_spi4_default>; 1824 pinctrl-1 = <&blsp_spi4_sleep>; 1825 pinctrl-names = "default", "sleep"; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 status = "disabled"; 1829 }; 1830 1831 blsp_i2c5: i2c@78b9000 { 1832 compatible = "qcom,i2c-qup-v2.2.1"; 1833 reg = <0x078b9000 0x500>; 1834 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1835 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1836 <&gcc GCC_BLSP1_AHB_CLK>; 1837 clock-names = "core", "iface"; 1838 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1839 dma-names = "tx", "rx"; 1840 pinctrl-0 = <&blsp_i2c5_default>; 1841 pinctrl-1 = <&blsp_i2c5_sleep>; 1842 pinctrl-names = "default", "sleep"; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 }; 1847 1848 blsp_spi5: spi@78b9000 { 1849 compatible = "qcom,spi-qup-v2.2.1"; 1850 reg = <0x078b9000 0x500>; 1851 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1853 <&gcc GCC_BLSP1_AHB_CLK>; 1854 clock-names = "core", "iface"; 1855 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1856 dma-names = "tx", "rx"; 1857 pinctrl-0 = <&blsp_spi5_default>; 1858 pinctrl-1 = <&blsp_spi5_sleep>; 1859 pinctrl-names = "default", "sleep"; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 status = "disabled"; 1863 }; 1864 1865 blsp_i2c6: i2c@78ba000 { 1866 compatible = "qcom,i2c-qup-v2.2.1"; 1867 reg = <0x078ba000 0x500>; 1868 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1869 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1870 <&gcc GCC_BLSP1_AHB_CLK>; 1871 clock-names = "core", "iface"; 1872 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1873 dma-names = "tx", "rx"; 1874 pinctrl-0 = <&blsp_i2c6_default>; 1875 pinctrl-1 = <&blsp_i2c6_sleep>; 1876 pinctrl-names = "default", "sleep"; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 blsp_spi6: spi@78ba000 { 1883 compatible = "qcom,spi-qup-v2.2.1"; 1884 reg = <0x078ba000 0x500>; 1885 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1886 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1887 <&gcc GCC_BLSP1_AHB_CLK>; 1888 clock-names = "core", "iface"; 1889 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1890 dma-names = "tx", "rx"; 1891 pinctrl-0 = <&blsp_spi6_default>; 1892 pinctrl-1 = <&blsp_spi6_sleep>; 1893 pinctrl-names = "default", "sleep"; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 status = "disabled"; 1897 }; 1898 1899 usb: usb@78d9000 { 1900 compatible = "qcom,ci-hdrc"; 1901 reg = <0x078d9000 0x200>, 1902 <0x078d9200 0x200>; 1903 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1905 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1906 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1907 clock-names = "iface", "core"; 1908 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1909 assigned-clock-rates = <80000000>; 1910 resets = <&gcc GCC_USB_HS_BCR>; 1911 reset-names = "core"; 1912 #reset-cells = <1>; 1913 phy_type = "ulpi"; 1914 dr_mode = "otg"; 1915 adp-disable; 1916 hnp-disable; 1917 srp-disable; 1918 ahb-burst-config = <0>; 1919 phy-names = "usb-phy"; 1920 phys = <&usb_hs_phy>; 1921 status = "disabled"; 1922 1923 ulpi { 1924 usb_hs_phy: phy { 1925 compatible = "qcom,usb-hs-phy-msm8916", 1926 "qcom,usb-hs-phy"; 1927 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1928 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1929 clock-names = "ref", "sleep"; 1930 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1931 reset-names = "phy", "por"; 1932 #phy-cells = <0>; 1933 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1934 <0x1 0x6b>, 1935 <0x2 0x24>, 1936 <0x3 0x13>; 1937 }; 1938 }; 1939 }; 1940 1941 wcnss: remoteproc@a204000 { 1942 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1943 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1944 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1945 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1946 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1947 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1948 interrupt-names = "wdog", 1949 "fatal", 1950 "ready", 1951 "handover", 1952 "stop-ack"; 1953 reg = <0x0a204000 0x2000>, 1954 <0x0a202000 0x1000>, 1955 <0x0a21b000 0x3000>; 1956 reg-names = "ccu", "dxe", "pmu"; 1957 1958 memory-region = <&wcnss_mem>; 1959 1960 power-domains = <&rpmpd MSM8939_VDDCX>, 1961 <&rpmpd MSM8939_VDDMX>; 1962 power-domain-names = "cx", "mx"; 1963 1964 qcom,smem-states = <&wcnss_smp2p_out 0>; 1965 qcom,smem-state-names = "stop"; 1966 1967 pinctrl-names = "default"; 1968 pinctrl-0 = <&wcss_wlan_default>; 1969 1970 status = "disabled"; 1971 1972 wcnss_iris: iris { 1973 /* Separate chip, compatible is board-specific */ 1974 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1975 clock-names = "xo"; 1976 }; 1977 1978 smd-edge { 1979 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1980 qcom,ipc = <&apcs1_mbox 8 17>; 1981 qcom,smd-edge = <6>; 1982 qcom,remote-pid = <4>; 1983 1984 label = "pronto"; 1985 1986 wcnss { 1987 compatible = "qcom,wcnss"; 1988 qcom,smd-channels = "WCNSS_CTRL"; 1989 1990 qcom,mmio = <&wcnss>; 1991 1992 wcnss_bt: bluetooth { 1993 compatible = "qcom,wcnss-bt"; 1994 }; 1995 1996 wcnss_wifi: wifi { 1997 compatible = "qcom,wcnss-wlan"; 1998 1999 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2001 interrupt-names = "tx", "rx"; 2002 2003 qcom,smem-states = <&apps_smsm 10>, 2004 <&apps_smsm 9>; 2005 qcom,smem-state-names = "tx-enable", 2006 "tx-rings-empty"; 2007 }; 2008 }; 2009 }; 2010 }; 2011 2012 intc: interrupt-controller@b000000 { 2013 compatible = "qcom,msm-qgic2"; 2014 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2015 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2016 interrupt-controller; 2017 #interrupt-cells = <3>; 2018 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2019 }; 2020 2021 apcs1_mbox: mailbox@b011000 { 2022 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2023 reg = <0x0b011000 0x1000>; 2024 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2025 clock-names = "pll", "aux", "ref"; 2026 #clock-cells = <0>; 2027 assigned-clocks = <&apcs2>; 2028 assigned-clock-rates = <297600000>; 2029 #mbox-cells = <1>; 2030 }; 2031 2032 a53pll_c1: clock@b016000 { 2033 compatible = "qcom,msm8939-a53pll"; 2034 reg = <0x0b016000 0x40>; 2035 #clock-cells = <0>; 2036 }; 2037 2038 acc0: clock-controller@b088000 { 2039 compatible = "qcom,kpss-acc-v2"; 2040 reg = <0x0b088000 0x1000>; 2041 }; 2042 2043 saw0: power-manager@b089000 { 2044 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2045 reg = <0x0b089000 0x1000>; 2046 }; 2047 2048 acc1: clock-controller@b098000 { 2049 compatible = "qcom,kpss-acc-v2"; 2050 reg = <0x0b098000 0x1000>; 2051 }; 2052 2053 saw1: power-manager@b099000 { 2054 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2055 reg = <0x0b099000 0x1000>; 2056 }; 2057 2058 acc2: clock-controller@b0a8000 { 2059 compatible = "qcom,kpss-acc-v2"; 2060 reg = <0x0b0a8000 0x1000>; 2061 }; 2062 2063 saw2: power-manager@b0a9000 { 2064 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2065 reg = <0x0b0a9000 0x1000>; 2066 }; 2067 2068 acc3: clock-controller@b0b8000 { 2069 compatible = "qcom,kpss-acc-v2"; 2070 reg = <0x0b0b8000 0x1000>; 2071 }; 2072 2073 saw3: power-manager@b0b9000 { 2074 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2075 reg = <0x0b0b9000 0x1000>; 2076 }; 2077 2078 apcs0_mbox: mailbox@b111000 { 2079 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2080 reg = <0x0b111000 0x1000>; 2081 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2082 clock-names = "pll", "aux", "ref"; 2083 #clock-cells = <0>; 2084 #mbox-cells = <1>; 2085 }; 2086 2087 a53pll_c0: clock@b116000 { 2088 compatible = "qcom,msm8939-a53pll"; 2089 reg = <0x0b116000 0x40>; 2090 #clock-cells = <0>; 2091 }; 2092 2093 timer@b120000 { 2094 compatible = "arm,armv7-timer-mem"; 2095 reg = <0x0b120000 0x1000>; 2096 #address-cells = <1>; 2097 #size-cells = <1>; 2098 ranges; 2099 2100 frame@b121000 { 2101 reg = <0x0b121000 0x1000>, 2102 <0x0b122000 0x1000>; 2103 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2105 frame-number = <0>; 2106 }; 2107 2108 frame@b123000 { 2109 reg = <0x0b123000 0x1000>; 2110 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2111 frame-number = <1>; 2112 status = "disabled"; 2113 }; 2114 2115 frame@b124000 { 2116 reg = <0x0b124000 0x1000>; 2117 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2118 frame-number = <2>; 2119 status = "disabled"; 2120 }; 2121 2122 frame@b125000 { 2123 reg = <0x0b125000 0x1000>; 2124 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2125 frame-number = <3>; 2126 status = "disabled"; 2127 }; 2128 2129 frame@b126000 { 2130 reg = <0x0b126000 0x1000>; 2131 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2132 frame-number = <4>; 2133 status = "disabled"; 2134 }; 2135 2136 frame@b127000 { 2137 reg = <0x0b127000 0x1000>; 2138 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2139 frame-number = <5>; 2140 status = "disabled"; 2141 }; 2142 2143 frame@b128000 { 2144 reg = <0x0b128000 0x1000>; 2145 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2146 frame-number = <6>; 2147 status = "disabled"; 2148 }; 2149 }; 2150 2151 acc4: clock-controller@b188000 { 2152 compatible = "qcom,kpss-acc-v2"; 2153 reg = <0x0b188000 0x1000>; 2154 }; 2155 2156 saw4: power-manager@b189000 { 2157 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2158 reg = <0x0b189000 0x1000>; 2159 }; 2160 2161 acc5: clock-controller@b198000 { 2162 compatible = "qcom,kpss-acc-v2"; 2163 reg = <0x0b198000 0x1000>; 2164 }; 2165 2166 saw5: power-manager@b199000 { 2167 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2168 reg = <0x0b199000 0x1000>; 2169 }; 2170 2171 acc6: clock-controller@b1a8000 { 2172 compatible = "qcom,kpss-acc-v2"; 2173 reg = <0x0b1a8000 0x1000>; 2174 }; 2175 2176 saw6: power-manager@b1a9000 { 2177 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2178 reg = <0x0b1a9000 0x1000>; 2179 }; 2180 2181 acc7: clock-controller@b1b8000 { 2182 compatible = "qcom,kpss-acc-v2"; 2183 reg = <0x0b1b8000 0x1000>; 2184 }; 2185 2186 saw7: power-manager@b1b9000 { 2187 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2188 reg = <0x0b1b9000 0x1000>; 2189 }; 2190 2191 a53pll_cci: clock@b1d0000 { 2192 compatible = "qcom,msm8939-a53pll"; 2193 reg = <0x0b1d0000 0x40>; 2194 #clock-cells = <0>; 2195 }; 2196 2197 apcs2: mailbox@b1d1000 { 2198 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2199 reg = <0x0b1d1000 0x1000>; 2200 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2201 clock-names = "pll", "aux", "ref"; 2202 #clock-cells = <0>; 2203 #mbox-cells = <1>; 2204 }; 2205 }; 2206 2207 thermal_zones: thermal-zones { 2208 cpu0-thermal { 2209 polling-delay-passive = <250>; 2210 polling-delay = <1000>; 2211 2212 thermal-sensors = <&tsens 5>; 2213 2214 trips { 2215 cpu0_alert: trip0 { 2216 temperature = <75000>; 2217 hysteresis = <2000>; 2218 type = "passive"; 2219 }; 2220 2221 cpu0_crit: trip1 { 2222 temperature = <115000>; 2223 hysteresis = <0>; 2224 type = "critical"; 2225 }; 2226 }; 2227 2228 cooling-maps { 2229 map0 { 2230 trip = <&cpu0_alert>; 2231 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2232 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2233 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2234 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2235 }; 2236 }; 2237 }; 2238 2239 cpu1-thermal { 2240 polling-delay-passive = <250>; 2241 polling-delay = <1000>; 2242 2243 thermal-sensors = <&tsens 6>; 2244 2245 trips { 2246 cpu1_alert: trip0 { 2247 temperature = <75000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 2252 cpu1_crit: trip1 { 2253 temperature = <110000>; 2254 hysteresis = <2000>; 2255 type = "critical"; 2256 }; 2257 }; 2258 2259 cooling-maps { 2260 map0 { 2261 trip = <&cpu1_alert>; 2262 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2263 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2264 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2265 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2266 }; 2267 }; 2268 }; 2269 2270 cpu2-thermal { 2271 polling-delay-passive = <250>; 2272 polling-delay = <1000>; 2273 2274 thermal-sensors = <&tsens 7>; 2275 2276 trips { 2277 cpu2_alert: trip0 { 2278 temperature = <75000>; 2279 hysteresis = <2000>; 2280 type = "passive"; 2281 }; 2282 2283 cpu2_crit: trip1 { 2284 temperature = <110000>; 2285 hysteresis = <2000>; 2286 type = "critical"; 2287 }; 2288 }; 2289 2290 cooling-maps { 2291 map0 { 2292 trip = <&cpu2_alert>; 2293 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2294 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2295 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2296 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2297 }; 2298 }; 2299 }; 2300 2301 cpu3-thermal { 2302 polling-delay-passive = <250>; 2303 polling-delay = <1000>; 2304 2305 thermal-sensors = <&tsens 8>; 2306 2307 trips { 2308 cpu3_alert: trip0 { 2309 temperature = <75000>; 2310 hysteresis = <2000>; 2311 type = "passive"; 2312 }; 2313 2314 cpu3_crit: trip1 { 2315 temperature = <110000>; 2316 hysteresis = <2000>; 2317 type = "critical"; 2318 }; 2319 }; 2320 2321 cooling-maps { 2322 map0 { 2323 trip = <&cpu3_alert>; 2324 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2325 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2326 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2327 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2328 }; 2329 }; 2330 }; 2331 2332 cpu4567-thermal { 2333 polling-delay-passive = <250>; 2334 polling-delay = <1000>; 2335 2336 thermal-sensors = <&tsens 9>; 2337 2338 trips { 2339 cpu4567_alert: trip0 { 2340 temperature = <75000>; 2341 hysteresis = <2000>; 2342 type = "passive"; 2343 }; 2344 2345 cpu4567_crit: trip1 { 2346 temperature = <110000>; 2347 hysteresis = <2000>; 2348 type = "critical"; 2349 }; 2350 }; 2351 2352 cooling-maps { 2353 map0 { 2354 trip = <&cpu4567_alert>; 2355 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2356 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2357 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2358 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2359 }; 2360 }; 2361 }; 2362 2363 gpu-thermal { 2364 polling-delay-passive = <250>; 2365 polling-delay = <1000>; 2366 2367 thermal-sensors = <&tsens 3>; 2368 2369 trips { 2370 gpu_alert0: trip-point0 { 2371 temperature = <75000>; 2372 hysteresis = <2000>; 2373 type = "passive"; 2374 }; 2375 2376 gpu_crit: gpu_crit { 2377 temperature = <95000>; 2378 hysteresis = <2000>; 2379 type = "critical"; 2380 }; 2381 }; 2382 }; 2383 2384 modem1-thermal { 2385 polling-delay-passive = <250>; 2386 polling-delay = <1000>; 2387 2388 thermal-sensors = <&tsens 0>; 2389 2390 trips { 2391 modem1_alert0: trip-point0 { 2392 temperature = <85000>; 2393 hysteresis = <2000>; 2394 type = "hot"; 2395 }; 2396 }; 2397 }; 2398 2399 modem2-thermal { 2400 polling-delay-passive = <250>; 2401 polling-delay = <1000>; 2402 2403 thermal-sensors = <&tsens 2>; 2404 2405 trips { 2406 modem2_alert0: trip-point0 { 2407 temperature = <85000>; 2408 hysteresis = <2000>; 2409 type = "hot"; 2410 }; 2411 }; 2412 }; 2413 2414 camera-thermal { 2415 polling-delay-passive = <250>; 2416 polling-delay = <1000>; 2417 2418 thermal-sensors = <&tsens 1>; 2419 2420 trips { 2421 cam_alert0: trip-point0 { 2422 temperature = <75000>; 2423 hysteresis = <2000>; 2424 type = "hot"; 2425 }; 2426 }; 2427 }; 2428 }; 2429 2430 timer { 2431 compatible = "arm,armv8-timer"; 2432 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2433 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2434 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2435 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2436 }; 2437}; 2438