1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-msm8939.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8939.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8939.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 /* 19 * Stock LK wants address-cells/size-cells = 2 20 * A number of our drivers want address/size cells = 1 21 * hence the disparity between top-level and /soc below. 22 */ 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32768>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 CPU0: cpu@100 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 enable-method = "spin-table"; 48 reg = <0x100>; 49 next-level-cache = <&L2_1>; 50 qcom,acc = <&acc0>; 51 qcom,saw = <&saw0>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 clocks = <&apcs1_mbox>; 54 #cooling-cells = <2>; 55 L2_1: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 }; 59 }; 60 61 CPU1: cpu@101 { 62 compatible = "arm,cortex-a53"; 63 device_type = "cpu"; 64 enable-method = "spin-table"; 65 reg = <0x101>; 66 next-level-cache = <&L2_1>; 67 qcom,acc = <&acc1>; 68 qcom,saw = <&saw1>; 69 cpu-idle-states = <&CPU_SLEEP_0>; 70 clocks = <&apcs1_mbox>; 71 #cooling-cells = <2>; 72 }; 73 74 CPU2: cpu@102 { 75 compatible = "arm,cortex-a53"; 76 device_type = "cpu"; 77 enable-method = "spin-table"; 78 reg = <0x102>; 79 next-level-cache = <&L2_1>; 80 qcom,acc = <&acc2>; 81 qcom,saw = <&saw2>; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 clocks = <&apcs1_mbox>; 84 #cooling-cells = <2>; 85 }; 86 87 CPU3: cpu@103 { 88 compatible = "arm,cortex-a53"; 89 device_type = "cpu"; 90 enable-method = "spin-table"; 91 reg = <0x103>; 92 next-level-cache = <&L2_1>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 cpu-idle-states = <&CPU_SLEEP_0>; 96 clocks = <&apcs1_mbox>; 97 #cooling-cells = <2>; 98 }; 99 100 CPU4: cpu@0 { 101 compatible = "arm,cortex-a53"; 102 device_type = "cpu"; 103 enable-method = "spin-table"; 104 reg = <0x0>; 105 qcom,acc = <&acc4>; 106 qcom,saw = <&saw4>; 107 cpu-idle-states = <&CPU_SLEEP_0>; 108 clocks = <&apcs0_mbox>; 109 #cooling-cells = <2>; 110 next-level-cache = <&L2_0>; 111 L2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 }; 115 }; 116 117 CPU5: cpu@1 { 118 compatible = "arm,cortex-a53"; 119 device_type = "cpu"; 120 enable-method = "spin-table"; 121 reg = <0x1>; 122 next-level-cache = <&L2_0>; 123 qcom,acc = <&acc5>; 124 qcom,saw = <&saw5>; 125 cpu-idle-states = <&CPU_SLEEP_0>; 126 clocks = <&apcs0_mbox>; 127 #cooling-cells = <2>; 128 }; 129 130 CPU6: cpu@2 { 131 compatible = "arm,cortex-a53"; 132 device_type = "cpu"; 133 enable-method = "spin-table"; 134 reg = <0x2>; 135 next-level-cache = <&L2_0>; 136 qcom,acc = <&acc6>; 137 qcom,saw = <&saw6>; 138 cpu-idle-states = <&CPU_SLEEP_0>; 139 clocks = <&apcs0_mbox>; 140 #cooling-cells = <2>; 141 }; 142 143 CPU7: cpu@3 { 144 compatible = "arm,cortex-a53"; 145 device_type = "cpu"; 146 enable-method = "spin-table"; 147 reg = <0x3>; 148 next-level-cache = <&L2_0>; 149 qcom,acc = <&acc7>; 150 qcom,saw = <&saw7>; 151 cpu-idle-states = <&CPU_SLEEP_0>; 152 clocks = <&apcs0_mbox>; 153 #cooling-cells = <2>; 154 }; 155 156 idle-states { 157 CPU_SLEEP_0: cpu-sleep-0 { 158 compatible ="qcom,idle-state-spc", "arm,idle-state"; 159 entry-latency-us = <130>; 160 exit-latency-us = <150>; 161 min-residency-us = <2000>; 162 local-timer-stop; 163 }; 164 }; 165 }; 166 167 /* 168 * MSM8939 has a big.LITTLE heterogeneous computing architecture, 169 * consisting of two clusters of four ARM Cortex-A53s each. The 170 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs 171 * at 1.5-1.7GHz. 172 * 173 * The enable method used here is spin-table which presupposes use 174 * of a 2nd stage boot shim such as lk2nd to have installed a 175 * spin-table, the downstream non-psci/non-spin-table method that 176 * default msm8916/msm8936/msm8939 will not be supported upstream. 177 */ 178 cpu-map { 179 /* LITTLE (efficiency) cluster */ 180 cluster0 { 181 core0 { 182 cpu = <&CPU4>; 183 }; 184 185 core1 { 186 cpu = <&CPU5>; 187 }; 188 189 core2 { 190 cpu = <&CPU6>; 191 }; 192 193 core3 { 194 cpu = <&CPU7>; 195 }; 196 }; 197 198 /* big (performance) cluster */ 199 /* Boot CPU is cluster 1 core 0 */ 200 cluster1 { 201 core0 { 202 cpu = <&CPU0>; 203 }; 204 205 core1 { 206 cpu = <&CPU1>; 207 }; 208 209 core2 { 210 cpu = <&CPU2>; 211 }; 212 213 core3 { 214 cpu = <&CPU3>; 215 }; 216 }; 217 }; 218 219 firmware { 220 scm: scm { 221 compatible = "qcom,scm-msm8916", "qcom,scm"; 222 clocks = <&gcc GCC_CRYPTO_CLK>, 223 <&gcc GCC_CRYPTO_AXI_CLK>, 224 <&gcc GCC_CRYPTO_AHB_CLK>; 225 clock-names = "core", "bus", "iface"; 226 #reset-cells = <1>; 227 228 qcom,dload-mode = <&tcsr 0x6100>; 229 }; 230 }; 231 232 memory@80000000 { 233 device_type = "memory"; 234 /* We expect the bootloader to fill in the reg */ 235 reg = <0x0 0x80000000 0x0 0x0>; 236 }; 237 238 pmu { 239 compatible = "arm,cortex-a53-pmu"; 240 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 241 }; 242 243 reserved-memory { 244 #address-cells = <2>; 245 #size-cells = <2>; 246 ranges; 247 248 tz-apps@86000000 { 249 reg = <0x0 0x86000000 0x0 0x300000>; 250 no-map; 251 }; 252 253 smem@86300000 { 254 compatible = "qcom,smem"; 255 reg = <0x0 0x86300000 0x0 0x100000>; 256 no-map; 257 258 hwlocks = <&tcsr_mutex 3>; 259 qcom,rpm-msg-ram = <&rpm_msg_ram>; 260 }; 261 262 hypervisor@86400000 { 263 reg = <0x0 0x86400000 0x0 0x100000>; 264 no-map; 265 }; 266 267 tz@86500000 { 268 reg = <0x0 0x86500000 0x0 0x180000>; 269 no-map; 270 }; 271 272 reserved@86680000 { 273 reg = <0x0 0x86680000 0x0 0x80000>; 274 no-map; 275 }; 276 277 rmtfs@86700000 { 278 compatible = "qcom,rmtfs-mem"; 279 reg = <0x0 0x86700000 0x0 0xe0000>; 280 no-map; 281 282 qcom,client-id = <1>; 283 }; 284 285 rfsa@867e0000 { 286 reg = <0x0 0x867e0000 0x0 0x20000>; 287 no-map; 288 }; 289 290 mpss_mem: mpss@86800000 { 291 reg = <0x0 0x86800000 0x0 0x5500000>; 292 no-map; 293 }; 294 295 wcnss_mem: wcnss@8bd00000 { 296 reg = <0x0 0x8bd00000 0x0 0x600000>; 297 no-map; 298 }; 299 300 venus_mem: venus@8c300000 { 301 reg = <0x0 0x8c300000 0x0 0x800000>; 302 no-map; 303 }; 304 305 mba_mem: mba@8cb00000 { 306 reg = <0x0 0x8cb00000 0x0 0x100000>; 307 no-map; 308 }; 309 }; 310 311 smd { 312 compatible = "qcom,smd"; 313 314 rpm { 315 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 316 qcom,ipc = <&apcs1_mbox 8 0>; 317 qcom,smd-edge = <15>; 318 319 rpm_requests: rpm-requests { 320 compatible = "qcom,rpm-msm8936"; 321 qcom,smd-channels = "rpm_requests"; 322 323 rpmcc: clock-controller { 324 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; 325 #clock-cells = <1>; 326 clock-names = "xo"; 327 clocks = <&xo_board>; 328 }; 329 330 rpmpd: power-controller { 331 compatible = "qcom,msm8939-rpmpd"; 332 #power-domain-cells = <1>; 333 operating-points-v2 = <&rpmpd_opp_table>; 334 335 rpmpd_opp_table: opp-table { 336 compatible = "operating-points-v2"; 337 338 rpmpd_opp_ret: opp1 { 339 opp-level = <1>; 340 }; 341 342 rpmpd_opp_svs_krait: opp2 { 343 opp-level = <2>; 344 }; 345 346 rpmpd_opp_svs_soc: opp3 { 347 opp-level = <3>; 348 }; 349 350 rpmpd_opp_nom: opp4 { 351 opp-level = <4>; 352 }; 353 354 rpmpd_opp_turbo: opp5 { 355 opp-level = <5>; 356 }; 357 358 rpmpd_opp_super_turbo: opp6 { 359 opp-level = <6>; 360 }; 361 }; 362 }; 363 }; 364 }; 365 }; 366 367 smp2p-hexagon { 368 compatible = "qcom,smp2p"; 369 qcom,smem = <435>, <428>; 370 371 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 372 373 mboxes = <&apcs1_mbox 14>; 374 375 qcom,local-pid = <0>; 376 qcom,remote-pid = <1>; 377 378 hexagon_smp2p_out: master-kernel { 379 qcom,entry-name = "master-kernel"; 380 381 #qcom,smem-state-cells = <1>; 382 }; 383 384 hexagon_smp2p_in: slave-kernel { 385 qcom,entry-name = "slave-kernel"; 386 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 #address-cells = <0>; 390 #size-cells = <0>; 391 }; 392 }; 393 394 smp2p-wcnss { 395 compatible = "qcom,smp2p"; 396 qcom,smem = <451>, <431>; 397 398 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 399 400 mboxes = <&apcs1_mbox 18>; 401 402 qcom,local-pid = <0>; 403 qcom,remote-pid = <4>; 404 405 wcnss_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 }; 411 412 wcnss_smp2p_out: master-kernel { 413 qcom,entry-name = "master-kernel"; 414 415 #qcom,smem-state-cells = <1>; 416 }; 417 }; 418 419 smsm { 420 compatible = "qcom,smsm"; 421 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 qcom,ipc-1 = <&apcs1_mbox 8 13>; 426 qcom,ipc-3 = <&apcs1_mbox 8 19>; 427 428 apps_smsm: apps@0 { 429 reg = <0>; 430 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 hexagon_smsm: hexagon@1 { 435 reg = <1>; 436 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 437 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 442 wcnss_smsm: wcnss@6 { 443 reg = <6>; 444 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 445 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 }; 449 }; 450 451 soc: soc@0 { 452 compatible = "simple-bus"; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 ranges = <0 0 0 0xffffffff>; 456 457 rng@22000 { 458 compatible = "qcom,prng"; 459 reg = <0x00022000 0x200>; 460 clocks = <&gcc GCC_PRNG_AHB_CLK>; 461 clock-names = "core"; 462 }; 463 464 qfprom: qfprom@5c000 { 465 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 466 reg = <0x0005c000 0x1000>; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 470 tsens_base1: base1@a0 { 471 reg = <0xa0 0x1>; 472 bits = <0 8>; 473 }; 474 475 tsens_s6_p1: s6-p1@a1 { 476 reg = <0xa1 0x1>; 477 bits = <0 6>; 478 }; 479 480 tsens_s6_p2: s6-p2@a1 { 481 reg = <0xa1 0x2>; 482 bits = <6 6>; 483 }; 484 485 tsens_s7_p1: s7-p1@a2 { 486 reg = <0xa2 0x2>; 487 bits = <4 6>; 488 }; 489 490 tsens_s7_p2: s7-p2@a3 { 491 reg = <0xa3 0x1>; 492 bits = <2 6>; 493 }; 494 495 tsens_s8_p1: s8-p1@a4 { 496 reg = <0xa4 0x1>; 497 bits = <0 6>; 498 }; 499 500 tsens_s8_p2: s8-p2@a4 { 501 reg = <0xa4 0x2>; 502 bits = <6 6>; 503 }; 504 505 tsens_s9_p1: s9-p1@a5 { 506 reg = <0xa5 0x2>; 507 bits = <4 6>; 508 }; 509 510 tsens_s9_p2: s9-p2@a6 { 511 reg = <0xa6 0x1>; 512 bits = <2 6>; 513 }; 514 515 tsens_base2: base2@a7 { 516 reg = <0xa7 0x1>; 517 bits = <0 8>; 518 }; 519 520 tsens_mode: mode@d0 { 521 reg = <0xd0 0x1>; 522 bits = <0 3>; 523 }; 524 525 tsens_s0_p1: s0-p1@d0 { 526 reg = <0xd0 0x2>; 527 bits = <3 6>; 528 }; 529 530 tsens_s0_p2: s0-p1@d1 { 531 reg = <0xd1 0x1>; 532 bits = <1 6>; 533 }; 534 535 tsens_s1_p1: s1-p1@d1 { 536 reg = <0xd1 0x2>; 537 bits = <7 6>; 538 }; 539 540 tsens_s1_p2: s1-p2@d2 { 541 reg = <0xd2 0x2>; 542 bits = <5 6>; 543 }; 544 545 tsens_s2_p1: s2-p1@d3 { 546 reg = <0xd3 0x2>; 547 bits = <3 6>; 548 }; 549 550 tsens_s2_p2: s2-p2@d4 { 551 reg = <0xd4 0x1>; 552 bits = <1 6>; 553 }; 554 555 tsens_s3_p1: s3-p1@d4 { 556 reg = <0xd4 0x2>; 557 bits = <7 6>; 558 }; 559 560 tsens_s3_p2: s3-p2@d5 { 561 reg = <0xd5 0x2>; 562 bits = <5 6>; 563 }; 564 565 tsens_s5_p1: s5-p1@d6 { 566 reg = <0xd6 0x2>; 567 bits = <3 6>; 568 }; 569 570 tsens_s5_p2: s5-p2@d7 { 571 reg = <0xd7 0x1>; 572 bits = <1 6>; 573 }; 574 }; 575 576 rpm_msg_ram: sram@60000 { 577 compatible = "qcom,rpm-msg-ram"; 578 reg = <0x00060000 0x8000>; 579 }; 580 581 bimc: interconnect@400000 { 582 compatible = "qcom,msm8939-bimc"; 583 reg = <0x00400000 0x62000>; 584 clock-names = "bus", "bus_a"; 585 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 586 <&rpmcc RPM_SMD_BIMC_A_CLK>; 587 #interconnect-cells = <1>; 588 }; 589 590 tsens: thermal-sensor@4a9000 { 591 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; 592 reg = <0x004a9000 0x1000>, /* TM */ 593 <0x004a8000 0x1000>; /* SROT */ 594 nvmem-cells = <&tsens_mode>, 595 <&tsens_base1>, <&tsens_base2>, 596 <&tsens_s0_p1>, <&tsens_s0_p2>, 597 <&tsens_s1_p1>, <&tsens_s1_p2>, 598 <&tsens_s2_p1>, <&tsens_s2_p2>, 599 <&tsens_s3_p1>, <&tsens_s3_p2>, 600 <&tsens_s5_p1>, <&tsens_s5_p2>, 601 <&tsens_s6_p1>, <&tsens_s6_p2>, 602 <&tsens_s7_p1>, <&tsens_s7_p2>, 603 <&tsens_s8_p1>, <&tsens_s8_p2>, 604 <&tsens_s9_p1>, <&tsens_s9_p2>; 605 nvmem-cell-names = "mode", 606 "base1", "base2", 607 "s0_p1", "s0_p2", 608 "s1_p1", "s1_p2", 609 "s2_p1", "s2_p2", 610 "s3_p1", "s3_p2", 611 "s5_p1", "s5_p2", 612 "s6_p1", "s6_p2", 613 "s7_p1", "s7_p2", 614 "s8_p1", "s8_p2", 615 "s9_p1", "s9_p2"; 616 #qcom,sensors = <9>; 617 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "uplow"; 619 #thermal-sensor-cells = <1>; 620 }; 621 622 restart@4ab000 { 623 compatible = "qcom,pshold"; 624 reg = <0x004ab000 0x4>; 625 }; 626 627 pcnoc: interconnect@500000 { 628 compatible = "qcom,msm8939-pcnoc"; 629 reg = <0x00500000 0x11000>; 630 clock-names = "bus", "bus_a"; 631 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 632 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 633 #interconnect-cells = <1>; 634 }; 635 636 snoc: interconnect@580000 { 637 compatible = "qcom,msm8939-snoc"; 638 reg = <0x00580000 0x14080>; 639 clock-names = "bus", "bus_a"; 640 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 641 <&rpmcc RPM_SMD_SNOC_A_CLK>; 642 #interconnect-cells = <1>; 643 644 snoc_mm: interconnect-snoc { 645 compatible = "qcom,msm8939-snoc-mm"; 646 clock-names = "bus", "bus_a"; 647 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>, 648 <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; 649 #interconnect-cells = <1>; 650 }; 651 }; 652 653 tlmm: pinctrl@1000000 { 654 compatible = "qcom,msm8916-pinctrl"; 655 reg = <0x01000000 0x300000>; 656 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 657 gpio-controller; 658 gpio-ranges = <&tlmm 0 0 122>; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 663 blsp_i2c1_default: blsp-i2c1-default-state { 664 pins = "gpio2", "gpio3"; 665 function = "blsp_i2c1"; 666 drive-strength = <2>; 667 bias-disable; 668 }; 669 670 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 671 pins = "gpio2", "gpio3"; 672 function = "gpio"; 673 drive-strength = <2>; 674 bias-disable; 675 }; 676 677 blsp_i2c2_default: blsp-i2c2-default-state { 678 pins = "gpio6", "gpio7"; 679 function = "blsp_i2c2"; 680 drive-strength = <2>; 681 bias-disable; 682 }; 683 684 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 685 pins = "gpio6", "gpio7"; 686 function = "gpio"; 687 drive-strength = <2>; 688 bias-disable; 689 }; 690 691 blsp_i2c3_default: blsp-i2c3-default-state { 692 pins = "gpio10", "gpio11"; 693 function = "blsp_i2c3"; 694 drive-strength = <2>; 695 bias-disable; 696 }; 697 698 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 699 pins = "gpio10", "gpio11"; 700 function = "gpio"; 701 drive-strength = <2>; 702 bias-disable; 703 }; 704 705 blsp_i2c4_default: blsp-i2c4-default-state { 706 pins = "gpio14", "gpio15"; 707 function = "blsp_i2c4"; 708 drive-strength = <2>; 709 bias-disable; 710 }; 711 712 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 713 pins = "gpio14", "gpio15"; 714 function = "gpio"; 715 drive-strength = <2>; 716 bias-disable; 717 }; 718 719 blsp_i2c5_default: blsp-i2c5-default-state { 720 pins = "gpio18", "gpio19"; 721 function = "blsp_i2c5"; 722 drive-strength = <2>; 723 bias-disable; 724 }; 725 726 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 727 pins = "gpio18", "gpio19"; 728 function = "gpio"; 729 drive-strength = <2>; 730 bias-disable; 731 }; 732 733 blsp_i2c6_default: blsp-i2c6-default-state { 734 pins = "gpio22", "gpio23"; 735 function = "blsp_i2c6"; 736 drive-strength = <2>; 737 bias-disable; 738 }; 739 740 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 741 pins = "gpio22", "gpio23"; 742 function = "gpio"; 743 drive-strength = <2>; 744 bias-disable; 745 }; 746 747 blsp_spi1_default: blsp-spi1-default-state { 748 spi-pins { 749 pins = "gpio0", "gpio1", "gpio3"; 750 function = "blsp_spi1"; 751 drive-strength = <12>; 752 bias-disable; 753 }; 754 755 cs-pins { 756 pins = "gpio2"; 757 function = "gpio"; 758 drive-strength = <16>; 759 bias-disable; 760 output-high; 761 }; 762 }; 763 764 blsp_spi1_sleep: blsp-spi1-sleep-state { 765 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-pull-down; 769 }; 770 771 blsp_spi2_default: blsp-spi2-default-state { 772 spi-pins { 773 pins = "gpio4", "gpio5", "gpio7"; 774 function = "blsp_spi2"; 775 drive-strength = <12>; 776 bias-disable; 777 }; 778 779 cs-pins { 780 pins = "gpio6"; 781 function = "gpio"; 782 drive-strength = <16>; 783 bias-disable; 784 output-high; 785 }; 786 }; 787 788 blsp_spi2_sleep: blsp-spi2-sleep-state { 789 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 790 function = "gpio"; 791 drive-strength = <2>; 792 bias-pull-down; 793 }; 794 795 blsp_spi3_default: blsp-spi3-default-state { 796 spi-pins { 797 pins = "gpio8", "gpio9", "gpio11"; 798 function = "blsp_spi3"; 799 drive-strength = <12>; 800 bias-disable; 801 }; 802 803 cs-pins { 804 pins = "gpio10"; 805 function = "gpio"; 806 drive-strength = <16>; 807 bias-disable; 808 output-high; 809 }; 810 }; 811 812 blsp_spi3_sleep: blsp-spi3-sleep-state { 813 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 814 function = "gpio"; 815 drive-strength = <2>; 816 bias-pull-down; 817 }; 818 819 blsp_spi4_default: blsp-spi4-default-state { 820 spi-pins { 821 pins = "gpio12", "gpio13", "gpio15"; 822 function = "blsp_spi4"; 823 drive-strength = <12>; 824 bias-disable; 825 }; 826 827 cs-pins { 828 pins = "gpio14"; 829 function = "gpio"; 830 drive-strength = <16>; 831 bias-disable; 832 output-high; 833 }; 834 }; 835 836 blsp_spi4_sleep: blsp-spi4-sleep-state { 837 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 838 function = "gpio"; 839 drive-strength = <2>; 840 bias-pull-down; 841 }; 842 843 blsp_spi5_default: blsp-spi5-default-state { 844 spi-pins { 845 pins = "gpio16", "gpio17", "gpio19"; 846 function = "blsp_spi5"; 847 drive-strength = <12>; 848 bias-disable; 849 }; 850 851 cs-pins { 852 pins = "gpio18"; 853 function = "gpio"; 854 drive-strength = <16>; 855 bias-disable; 856 output-high; 857 }; 858 }; 859 860 blsp_spi5_sleep: blsp-spi5-sleep-state { 861 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 862 function = "gpio"; 863 drive-strength = <2>; 864 bias-pull-down; 865 }; 866 867 blsp_spi6_default: blsp-spi6-default-state { 868 spi-pins { 869 pins = "gpio20", "gpio21", "gpio23"; 870 function = "blsp_spi6"; 871 drive-strength = <12>; 872 bias-disable; 873 }; 874 875 cs-pins { 876 pins = "gpio22"; 877 function = "gpio"; 878 drive-strength = <16>; 879 bias-disable; 880 output-high; 881 }; 882 }; 883 884 blsp_spi6_sleep: blsp-spi6-sleep-state { 885 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 886 function = "gpio"; 887 drive-strength = <2>; 888 bias-pull-down; 889 }; 890 891 blsp_uart1_default: blsp-uart1-default-state { 892 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 893 function = "blsp_uart1"; 894 drive-strength = <16>; 895 bias-disable; 896 }; 897 898 blsp_uart1_sleep: blsp-uart1-sleep-state { 899 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 900 function = "gpio"; 901 drive-strength = <2>; 902 bias-pull-down; 903 }; 904 905 blsp_uart2_default: blsp-uart2-default-state { 906 pins = "gpio4", "gpio5"; 907 function = "blsp_uart2"; 908 drive-strength = <16>; 909 bias-disable; 910 }; 911 912 blsp_uart2_sleep: blsp-uart2-sleep-state { 913 pins = "gpio4", "gpio5"; 914 function = "gpio"; 915 drive-strength = <2>; 916 bias-pull-down; 917 }; 918 919 camera_front_default: camera-front-default-state { 920 pwdn-pins { 921 pins = "gpio33"; 922 function = "gpio"; 923 drive-strength = <16>; 924 bias-disable; 925 }; 926 927 rst-pins { 928 pins = "gpio28"; 929 function = "gpio"; 930 drive-strength = <16>; 931 bias-disable; 932 }; 933 934 mclk1-pins { 935 pins = "gpio27"; 936 function = "cam_mclk1"; 937 drive-strength = <16>; 938 bias-disable; 939 }; 940 }; 941 942 camera_rear_default: camera-rear-default-state { 943 pwdn-pins { 944 pins = "gpio34"; 945 function = "gpio"; 946 drive-strength = <16>; 947 bias-disable; 948 }; 949 950 rst-pins { 951 pins = "gpio35"; 952 function = "gpio"; 953 drive-strength = <16>; 954 bias-disable; 955 }; 956 957 mclk0-pins { 958 pins = "gpio26"; 959 function = "cam_mclk0"; 960 drive-strength = <16>; 961 bias-disable; 962 }; 963 }; 964 965 cci0_default: cci0-default-state { 966 pins = "gpio29", "gpio30"; 967 function = "cci_i2c"; 968 drive-strength = <16>; 969 bias-disable; 970 }; 971 972 cdc_dmic_default: cdc-dmic-default-state { 973 clk-pins { 974 pins = "gpio0"; 975 function = "dmic0_clk"; 976 drive-strength = <8>; 977 }; 978 979 data-pins { 980 pins = "gpio1"; 981 function = "dmic0_data"; 982 drive-strength = <8>; 983 }; 984 }; 985 986 cdc_dmic_sleep: cdc-dmic-sleep-state { 987 clk-pins { 988 pins = "gpio0"; 989 function = "dmic0_clk"; 990 drive-strength = <2>; 991 bias-disable; 992 }; 993 994 data-pins { 995 pins = "gpio1"; 996 function = "dmic0_data"; 997 drive-strength = <2>; 998 bias-disable; 999 }; 1000 }; 1001 1002 cdc_pdm_default: cdc-pdm-default-state { 1003 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1004 "gpio67", "gpio68"; 1005 function = "cdc_pdm0"; 1006 drive-strength = <8>; 1007 bias-disable; 1008 }; 1009 1010 cdc_pdm_sleep: cdc-pdm-sleep-state { 1011 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1012 "gpio67", "gpio68"; 1013 function = "cdc_pdm0"; 1014 drive-strength = <2>; 1015 bias-pull-down; 1016 }; 1017 1018 pri_mi2s_default: mi2s-pri-default-state { 1019 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1020 function = "pri_mi2s"; 1021 drive-strength = <8>; 1022 bias-disable; 1023 }; 1024 1025 pri_mi2s_sleep: mi2s-pri-sleep-state { 1026 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1027 function = "pri_mi2s"; 1028 drive-strength = <2>; 1029 bias-disable; 1030 }; 1031 1032 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1033 pins = "gpio116"; 1034 function = "pri_mi2s"; 1035 drive-strength = <8>; 1036 bias-disable; 1037 }; 1038 1039 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1040 pins = "gpio116"; 1041 function = "pri_mi2s"; 1042 drive-strength = <2>; 1043 bias-disable; 1044 }; 1045 1046 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1047 pins = "gpio110"; 1048 function = "pri_mi2s_ws"; 1049 drive-strength = <8>; 1050 bias-disable; 1051 }; 1052 1053 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1054 pins = "gpio110"; 1055 function = "pri_mi2s_ws"; 1056 drive-strength = <2>; 1057 bias-disable; 1058 }; 1059 1060 sec_mi2s_default: mi2s-sec-default-state { 1061 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1062 function = "sec_mi2s"; 1063 drive-strength = <8>; 1064 bias-disable; 1065 }; 1066 1067 sec_mi2s_sleep: mi2s-sec-sleep-state { 1068 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1069 function = "sec_mi2s"; 1070 drive-strength = <2>; 1071 bias-disable; 1072 }; 1073 1074 sdc1_default: sdc1-default-state { 1075 clk-pins { 1076 pins = "sdc1_clk"; 1077 bias-disable; 1078 drive-strength = <16>; 1079 }; 1080 1081 cmd-pins { 1082 pins = "sdc1_cmd"; 1083 bias-pull-up; 1084 drive-strength = <10>; 1085 }; 1086 1087 data-pins { 1088 pins = "sdc1_data"; 1089 bias-pull-up; 1090 drive-strength = <10>; 1091 }; 1092 }; 1093 1094 sdc1_sleep: sdc1-sleep-state { 1095 clk-pins { 1096 pins = "sdc1_clk"; 1097 bias-disable; 1098 drive-strength = <2>; 1099 }; 1100 1101 cmd-pins { 1102 pins = "sdc1_cmd"; 1103 bias-pull-up; 1104 drive-strength = <2>; 1105 }; 1106 1107 data-pins { 1108 pins = "sdc1_data"; 1109 bias-pull-up; 1110 drive-strength = <2>; 1111 }; 1112 }; 1113 1114 sdc2_default: sdc2-default-state { 1115 clk-pins { 1116 pins = "sdc2_clk"; 1117 bias-disable; 1118 drive-strength = <16>; 1119 }; 1120 1121 cmd-pins { 1122 pins = "sdc2_cmd"; 1123 bias-pull-up; 1124 drive-strength = <10>; 1125 }; 1126 1127 data-pins { 1128 pins = "sdc2_data"; 1129 bias-pull-up; 1130 drive-strength = <10>; 1131 }; 1132 }; 1133 1134 sdc2_sleep: sdc2-sleep-state { 1135 clk-pins { 1136 pins = "sdc2_clk"; 1137 bias-disable; 1138 drive-strength = <2>; 1139 }; 1140 1141 cmd-pins { 1142 pins = "sdc2_cmd"; 1143 bias-pull-up; 1144 drive-strength = <2>; 1145 }; 1146 1147 data-pins { 1148 pins = "sdc2_data"; 1149 bias-pull-up; 1150 drive-strength = <2>; 1151 }; 1152 }; 1153 1154 wcss_wlan_default: wcss-wlan-default-state { 1155 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1156 function = "wcss_wlan"; 1157 drive-strength = <6>; 1158 bias-pull-up; 1159 }; 1160 }; 1161 1162 gcc: clock-controller@1800000 { 1163 compatible = "qcom,gcc-msm8939"; 1164 reg = <0x01800000 0x80000>; 1165 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1166 <&sleep_clk>, 1167 <&mdss_dsi0_phy 1>, 1168 <&mdss_dsi0_phy 0>, 1169 <0>, 1170 <0>, 1171 <0>; 1172 clock-names = "xo", 1173 "sleep_clk", 1174 "dsi0pll", 1175 "dsi0pllbyte", 1176 "ext_mclk", 1177 "ext_pri_i2s", 1178 "ext_sec_i2s"; 1179 #clock-cells = <1>; 1180 #reset-cells = <1>; 1181 #power-domain-cells = <1>; 1182 }; 1183 1184 tcsr_mutex: hwlock@1905000 { 1185 compatible = "qcom,tcsr-mutex"; 1186 reg = <0x01905000 0x20000>; 1187 #hwlock-cells = <1>; 1188 }; 1189 1190 tcsr: syscon@1937000 { 1191 compatible = "qcom,tcsr-msm8916", "syscon"; 1192 reg = <0x01937000 0x30000>; 1193 }; 1194 1195 mdss: display-subsystem@1a00000 { 1196 compatible = "qcom,mdss"; 1197 reg = <0x01a00000 0x1000>, 1198 <0x01ac8000 0x3000>; 1199 reg-names = "mdss_phys", "vbif_phys"; 1200 1201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1202 interrupt-controller; 1203 1204 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1205 <&gcc GCC_MDSS_AXI_CLK>, 1206 <&gcc GCC_MDSS_VSYNC_CLK>; 1207 clock-names = "iface", 1208 "bus", 1209 "vsync"; 1210 1211 power-domains = <&gcc MDSS_GDSC>; 1212 1213 #address-cells = <1>; 1214 #size-cells = <1>; 1215 #interrupt-cells = <1>; 1216 ranges; 1217 1218 status = "disabled"; 1219 1220 mdss_mdp: display-controller@1a01000 { 1221 compatible = "qcom,mdp5"; 1222 reg = <0x01a01000 0x89000>; 1223 reg-names = "mdp_phys"; 1224 1225 interrupt-parent = <&mdss>; 1226 interrupts = <0>; 1227 1228 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1229 <&gcc GCC_MDSS_AXI_CLK>, 1230 <&gcc GCC_MDSS_MDP_CLK>, 1231 <&gcc GCC_MDSS_VSYNC_CLK>; 1232 clock-names = "iface", 1233 "bus", 1234 "core", 1235 "vsync"; 1236 1237 iommus = <&apps_iommu 4>; 1238 1239 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1240 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; 1241 interconnect-names = "mdp0-mem", "mdp1-mem"; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 port@0 { 1248 reg = <0>; 1249 mdss_mdp_intf1_out: endpoint { 1250 remote-endpoint = <&mdss_dsi0_in>; 1251 }; 1252 }; 1253 1254 port@1 { 1255 reg = <1>; 1256 mdss_mdp_intf2_out: endpoint { 1257 remote-endpoint = <&mdss_dsi1_in>; 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 mdss_dsi0: dsi@1a98000 { 1264 compatible = "qcom,msm8916-dsi-ctrl", 1265 "qcom,mdss-dsi-ctrl"; 1266 reg = <0x01a98000 0x25c>; 1267 reg-names = "dsi_ctrl"; 1268 1269 interrupt-parent = <&mdss>; 1270 interrupts = <4>; 1271 1272 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1273 <&gcc GCC_MDSS_AHB_CLK>, 1274 <&gcc GCC_MDSS_AXI_CLK>, 1275 <&gcc GCC_MDSS_BYTE0_CLK>, 1276 <&gcc GCC_MDSS_PCLK0_CLK>, 1277 <&gcc GCC_MDSS_ESC0_CLK>; 1278 clock-names = "mdp_core", 1279 "iface", 1280 "bus", 1281 "byte", 1282 "pixel", 1283 "core"; 1284 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1285 <&gcc PCLK0_CLK_SRC>; 1286 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1287 <&mdss_dsi0_phy 1>; 1288 1289 phys = <&mdss_dsi0_phy>; 1290 status = "disabled"; 1291 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 ports { 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 1299 port@0 { 1300 reg = <0>; 1301 mdss_dsi0_in: endpoint { 1302 remote-endpoint = <&mdss_mdp_intf1_out>; 1303 }; 1304 }; 1305 1306 port@1 { 1307 reg = <1>; 1308 mdss_dsi0_out: endpoint { 1309 }; 1310 }; 1311 }; 1312 }; 1313 1314 mdss_dsi0_phy: phy@1a98300 { 1315 compatible = "qcom,dsi-phy-28nm-lp"; 1316 reg = <0x01a98300 0xd4>, 1317 <0x01a98500 0x280>, 1318 <0x01a98780 0x30>; 1319 reg-names = "dsi_pll", 1320 "dsi_phy", 1321 "dsi_phy_regulator"; 1322 1323 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1324 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1325 clock-names = "iface", "ref"; 1326 1327 #clock-cells = <1>; 1328 #phy-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 mdss_dsi1: dsi@1aa0000 { 1333 compatible = "qcom,msm8916-dsi-ctrl", 1334 "qcom,mdss-dsi-ctrl"; 1335 reg = <0x01aa0000 0x25c>; 1336 reg-names = "dsi_ctrl"; 1337 1338 interrupt-parent = <&mdss>; 1339 interrupts = <5>; 1340 1341 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1342 <&gcc GCC_MDSS_AHB_CLK>, 1343 <&gcc GCC_MDSS_AXI_CLK>, 1344 <&gcc GCC_MDSS_BYTE1_CLK>, 1345 <&gcc GCC_MDSS_PCLK1_CLK>, 1346 <&gcc GCC_MDSS_ESC1_CLK>; 1347 clock-names = "mdp_core", 1348 "iface", 1349 "bus", 1350 "byte", 1351 "pixel", 1352 "core"; 1353 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1354 <&gcc PCLK1_CLK_SRC>; 1355 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1356 <&mdss_dsi0_phy 1>; 1357 phys = <&mdss_dsi1_phy>; 1358 status = "disabled"; 1359 1360 ports { 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 port@0 { 1365 reg = <0>; 1366 mdss_dsi1_in: endpoint { 1367 remote-endpoint = <&mdss_mdp_intf2_out>; 1368 }; 1369 }; 1370 1371 port@1 { 1372 reg = <1>; 1373 mdss_dsi1_out: endpoint { 1374 }; 1375 }; 1376 }; 1377 }; 1378 1379 mdss_dsi1_phy: phy@1aa0300 { 1380 compatible = "qcom,dsi-phy-28nm-lp"; 1381 reg = <0x01aa0300 0xd4>, 1382 <0x01aa0500 0x280>, 1383 <0x01aa0780 0x30>; 1384 reg-names = "dsi_pll", 1385 "dsi_phy", 1386 "dsi_phy_regulator"; 1387 1388 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1389 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1390 clock-names = "iface", "ref"; 1391 1392 #clock-cells = <1>; 1393 #phy-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 }; 1397 1398 gpu@1c00000 { 1399 compatible = "qcom,adreno-405.0", "qcom,adreno"; 1400 reg = <0x01c00000 0x10000>; 1401 reg-names = "kgsl_3d0_reg_memory"; 1402 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "kgsl_3d0_irq"; 1404 clock-names = "core", 1405 "iface", 1406 "mem", 1407 "mem_iface", 1408 "alt_mem_iface", 1409 "gfx3d", 1410 "rbbmtimer"; 1411 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1412 <&gcc GCC_OXILI_AHB_CLK>, 1413 <&gcc GCC_OXILI_GMEM_CLK>, 1414 <&gcc GCC_BIMC_GFX_CLK>, 1415 <&gcc GCC_BIMC_GPU_CLK>, 1416 <&gcc GFX3D_CLK_SRC>, 1417 <&gcc GCC_OXILI_TIMER_CLK>; 1418 power-domains = <&gcc OXILI_GDSC>; 1419 operating-points-v2 = <&opp_table>; 1420 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1421 1422 opp_table: opp-table { 1423 compatible = "operating-points-v2"; 1424 1425 opp-550000000 { 1426 opp-hz = /bits/ 64 <550000000>; 1427 }; 1428 1429 opp-465000000 { 1430 opp-hz = /bits/ 64 <465000000>; 1431 }; 1432 1433 opp-400000000 { 1434 opp-hz = /bits/ 64 <400000000>; 1435 }; 1436 1437 opp-220000000 { 1438 opp-hz = /bits/ 64 <220000000>; 1439 }; 1440 1441 opp-19200000 { 1442 opp-hz = /bits/ 64 <19200000>; 1443 }; 1444 }; 1445 }; 1446 1447 apps_iommu: iommu@1ef0000 { 1448 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1449 reg = <0x01ef0000 0x3000>; 1450 ranges = <0 0x01e20000 0x40000>; 1451 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1452 <&gcc GCC_APSS_TCU_CLK>; 1453 clock-names = "iface", "bus"; 1454 #address-cells = <1>; 1455 #size-cells = <1>; 1456 #iommu-cells = <1>; 1457 qcom,iommu-secure-id = <17>; 1458 1459 /* mdp_0: */ 1460 iommu-ctx@4000 { 1461 compatible = "qcom,msm-iommu-v1-ns"; 1462 reg = <0x4000 0x1000>; 1463 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1464 }; 1465 1466 /* venus_ns: */ 1467 iommu-ctx@5000 { 1468 compatible = "qcom,msm-iommu-v1-sec"; 1469 reg = <0x5000 0x1000>; 1470 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1471 }; 1472 }; 1473 1474 gpu_iommu: iommu@1f08000 { 1475 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1476 ranges = <0 0x1f08000 0x10000>; 1477 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1478 <&gcc GCC_GFX_TCU_CLK>, 1479 <&gcc GCC_GFX_TBU_CLK>; 1480 clock-names = "iface", "bus", "tbu"; 1481 #address-cells = <1>; 1482 #size-cells = <1>; 1483 #iommu-cells = <1>; 1484 qcom,iommu-secure-id = <18>; 1485 1486 /* gfx3d_user: */ 1487 iommu-ctx@1000 { 1488 compatible = "qcom,msm-iommu-v1-ns"; 1489 reg = <0x1000 0x1000>; 1490 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1491 }; 1492 1493 /* gfx3d_priv: */ 1494 iommu-ctx@2000 { 1495 compatible = "qcom,msm-iommu-v1-ns"; 1496 reg = <0x2000 0x1000>; 1497 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1498 }; 1499 }; 1500 1501 spmi_bus: spmi@200f000 { 1502 compatible = "qcom,spmi-pmic-arb"; 1503 reg = <0x0200f000 0x001000>, 1504 <0x02400000 0x400000>, 1505 <0x02c00000 0x400000>, 1506 <0x03800000 0x200000>, 1507 <0x0200a000 0x002100>; 1508 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1509 interrupt-names = "periph_irq"; 1510 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1511 qcom,ee = <0>; 1512 qcom,channel = <0>; 1513 #address-cells = <2>; 1514 #size-cells = <0>; 1515 interrupt-controller; 1516 #interrupt-cells = <4>; 1517 }; 1518 1519 mpss: remoteproc@4080000 { 1520 compatible = "qcom,msm8916-mss-pil"; 1521 reg = <0x04080000 0x100>, <0x04020000 0x040>; 1522 reg-names = "qdsp6", "rmb"; 1523 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1524 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1525 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1526 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1527 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1528 interrupt-names = "wdog", 1529 "fatal", 1530 "ready", 1531 "handover", 1532 "stop-ack"; 1533 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1534 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1535 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1536 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1537 clock-names = "iface", 1538 "bus", 1539 "mem", 1540 "xo"; 1541 power-domains = <&rpmpd MSM8939_VDDMDCX>, 1542 <&rpmpd MSM8939_VDDMX>; 1543 power-domain-names = "cx", "mx"; 1544 qcom,smem-states = <&hexagon_smp2p_out 0>; 1545 qcom,smem-state-names = "stop"; 1546 resets = <&scm 0>; 1547 reset-names = "mss_restart"; 1548 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1549 status = "disabled"; 1550 1551 mba { 1552 memory-region = <&mba_mem>; 1553 }; 1554 1555 mpss { 1556 memory-region = <&mpss_mem>; 1557 }; 1558 1559 smd-edge { 1560 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1561 1562 qcom,smd-edge = <0>; 1563 mboxes = <&apcs1_mbox 12>; 1564 qcom,remote-pid = <1>; 1565 1566 label = "hexagon"; 1567 }; 1568 }; 1569 1570 sound: sound@7702000 { 1571 compatible = "qcom,apq8016-sbc-sndcard"; 1572 reg = <0x07702000 0x4>, 1573 <0x07702004 0x4>; 1574 reg-names = "mic-iomux", "spkr-iomux"; 1575 status = "disabled"; 1576 }; 1577 1578 lpass: audio-controller@7708000 { 1579 compatible = "qcom,apq8016-lpass-cpu"; 1580 reg = <0x07708000 0x10000>; 1581 reg-names = "lpass-lpaif"; 1582 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1583 interrupt-names = "lpass-irq-lpaif"; 1584 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1585 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1586 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1587 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1588 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 1589 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1590 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 1591 clock-names = "ahbix-clk", 1592 "mi2s-bit-clk0", 1593 "mi2s-bit-clk1", 1594 "mi2s-bit-clk2", 1595 "mi2s-bit-clk3", 1596 "pcnoc-mport-clk", 1597 "pcnoc-sway-clk"; 1598 #sound-dai-cells = <1>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 lpass_codec: audio-codec@771c000 { 1605 compatible = "qcom,msm8916-wcd-digital-codec"; 1606 reg = <0x0771c000 0x400>; 1607 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1608 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1609 clock-names = "ahbix-clk", "mclk"; 1610 #sound-dai-cells = <1>; 1611 status = "disabled"; 1612 }; 1613 1614 sdhc_1: mmc@7824900 { 1615 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1616 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1617 reg-names = "hc", "core"; 1618 1619 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "hc_irq", "pwr_irq"; 1622 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1623 <&gcc GCC_SDCC1_APPS_CLK>, 1624 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1625 clock-names = "iface", "core", "xo"; 1626 resets = <&gcc GCC_SDCC1_BCR>; 1627 pinctrl-0 = <&sdc1_default>; 1628 pinctrl-1 = <&sdc1_sleep>; 1629 pinctrl-names = "default", "sleep"; 1630 mmc-ddr-1_8v; 1631 bus-width = <8>; 1632 non-removable; 1633 status = "disabled"; 1634 }; 1635 1636 sdhc_2: mmc@7864900 { 1637 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1638 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1639 reg-names = "hc", "core"; 1640 1641 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupt-names = "hc_irq", "pwr_irq"; 1644 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1645 <&gcc GCC_SDCC2_APPS_CLK>, 1646 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1647 clock-names = "iface", "core", "xo"; 1648 resets = <&gcc GCC_SDCC2_BCR>; 1649 pinctrl-0 = <&sdc2_default>; 1650 pinctrl-1 = <&sdc2_sleep>; 1651 pinctrl-names = "default", "sleep"; 1652 bus-width = <4>; 1653 status = "disabled"; 1654 }; 1655 1656 blsp_dma: dma-controller@7884000 { 1657 compatible = "qcom,bam-v1.7.0"; 1658 reg = <0x07884000 0x23000>; 1659 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1661 clock-names = "bam_clk"; 1662 #dma-cells = <1>; 1663 qcom,ee = <0>; 1664 }; 1665 1666 blsp_uart1: serial@78af000 { 1667 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1668 reg = <0x078af000 0x200>; 1669 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1671 clock-names = "core", "iface"; 1672 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1673 dma-names = "tx", "rx"; 1674 pinctrl-0 = <&blsp_uart1_default>; 1675 pinctrl-1 = <&blsp_uart1_sleep>; 1676 pinctrl-names = "default", "sleep"; 1677 status = "disabled"; 1678 }; 1679 1680 blsp_uart2: serial@78b0000 { 1681 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1682 reg = <0x078b0000 0x200>; 1683 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1684 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1685 clock-names = "core", "iface"; 1686 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1687 dma-names = "tx", "rx"; 1688 pinctrl-0 = <&blsp_uart2_default>; 1689 pinctrl-1 = <&blsp_uart2_sleep>; 1690 pinctrl-names = "default", "sleep"; 1691 status = "disabled"; 1692 }; 1693 1694 blsp_i2c1: i2c@78b5000 { 1695 compatible = "qcom,i2c-qup-v2.2.1"; 1696 reg = <0x078b5000 0x500>; 1697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1698 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1699 <&gcc GCC_BLSP1_AHB_CLK>; 1700 clock-names = "core", "iface"; 1701 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1702 dma-names = "tx", "rx"; 1703 pinctrl-0 = <&blsp_i2c1_default>; 1704 pinctrl-1 = <&blsp_i2c1_sleep>; 1705 pinctrl-names = "default", "sleep"; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 status = "disabled"; 1709 }; 1710 1711 blsp_spi1: spi@78b5000 { 1712 compatible = "qcom,spi-qup-v2.2.1"; 1713 reg = <0x078b5000 0x500>; 1714 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1716 <&gcc GCC_BLSP1_AHB_CLK>; 1717 clock-names = "core", "iface"; 1718 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1719 dma-names = "tx", "rx"; 1720 pinctrl-0 = <&blsp_spi1_default>; 1721 pinctrl-1 = <&blsp_spi1_sleep>; 1722 pinctrl-names = "default", "sleep"; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 blsp_i2c2: i2c@78b6000 { 1729 compatible = "qcom,i2c-qup-v2.2.1"; 1730 reg = <0x078b6000 0x500>; 1731 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1733 <&gcc GCC_BLSP1_AHB_CLK>; 1734 clock-names = "core", "iface"; 1735 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1736 dma-names = "tx", "rx"; 1737 pinctrl-0 = <&blsp_i2c2_default>; 1738 pinctrl-1 = <&blsp_i2c2_sleep>; 1739 pinctrl-names = "default", "sleep"; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 status = "disabled"; 1743 }; 1744 1745 blsp_spi2: spi@78b6000 { 1746 compatible = "qcom,spi-qup-v2.2.1"; 1747 reg = <0x078b6000 0x500>; 1748 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1750 <&gcc GCC_BLSP1_AHB_CLK>; 1751 clock-names = "core", "iface"; 1752 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1753 dma-names = "tx", "rx"; 1754 pinctrl-0 = <&blsp_spi2_default>; 1755 pinctrl-1 = <&blsp_spi2_sleep>; 1756 pinctrl-names = "default", "sleep"; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 status = "disabled"; 1760 }; 1761 1762 blsp_i2c3: i2c@78b7000 { 1763 compatible = "qcom,i2c-qup-v2.2.1"; 1764 reg = <0x078b7000 0x500>; 1765 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1766 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1767 <&gcc GCC_BLSP1_AHB_CLK>; 1768 clock-names = "core", "iface"; 1769 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1770 dma-names = "tx", "rx"; 1771 pinctrl-0 = <&blsp_i2c3_default>; 1772 pinctrl-1 = <&blsp_i2c3_sleep>; 1773 pinctrl-names = "default", "sleep"; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 status = "disabled"; 1777 }; 1778 1779 blsp_spi3: spi@78b7000 { 1780 compatible = "qcom,spi-qup-v2.2.1"; 1781 reg = <0x078b7000 0x500>; 1782 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1784 <&gcc GCC_BLSP1_AHB_CLK>; 1785 clock-names = "core", "iface"; 1786 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1787 dma-names = "tx", "rx"; 1788 pinctrl-0 = <&blsp_spi3_default>; 1789 pinctrl-1 = <&blsp_spi3_sleep>; 1790 pinctrl-names = "default", "sleep"; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 status = "disabled"; 1794 }; 1795 1796 blsp_i2c4: i2c@78b8000 { 1797 compatible = "qcom,i2c-qup-v2.2.1"; 1798 reg = <0x078b8000 0x500>; 1799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1801 <&gcc GCC_BLSP1_AHB_CLK>; 1802 clock-names = "core", "iface"; 1803 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1804 dma-names = "tx", "rx"; 1805 pinctrl-0 = <&blsp_i2c4_default>; 1806 pinctrl-1 = <&blsp_i2c4_sleep>; 1807 pinctrl-names = "default", "sleep"; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 status = "disabled"; 1811 }; 1812 1813 blsp_spi4: spi@78b8000 { 1814 compatible = "qcom,spi-qup-v2.2.1"; 1815 reg = <0x078b8000 0x500>; 1816 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1818 <&gcc GCC_BLSP1_AHB_CLK>; 1819 clock-names = "core", "iface"; 1820 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1821 dma-names = "tx", "rx"; 1822 pinctrl-0 = <&blsp_spi4_default>; 1823 pinctrl-1 = <&blsp_spi4_sleep>; 1824 pinctrl-names = "default", "sleep"; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 status = "disabled"; 1828 }; 1829 1830 blsp_i2c5: i2c@78b9000 { 1831 compatible = "qcom,i2c-qup-v2.2.1"; 1832 reg = <0x078b9000 0x500>; 1833 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1835 <&gcc GCC_BLSP1_AHB_CLK>; 1836 clock-names = "core", "iface"; 1837 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1838 dma-names = "tx", "rx"; 1839 pinctrl-0 = <&blsp_i2c5_default>; 1840 pinctrl-1 = <&blsp_i2c5_sleep>; 1841 pinctrl-names = "default", "sleep"; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 status = "disabled"; 1845 }; 1846 1847 blsp_spi5: spi@78b9000 { 1848 compatible = "qcom,spi-qup-v2.2.1"; 1849 reg = <0x078b9000 0x500>; 1850 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1851 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1852 <&gcc GCC_BLSP1_AHB_CLK>; 1853 clock-names = "core", "iface"; 1854 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1855 dma-names = "tx", "rx"; 1856 pinctrl-0 = <&blsp_spi5_default>; 1857 pinctrl-1 = <&blsp_spi5_sleep>; 1858 pinctrl-names = "default", "sleep"; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 status = "disabled"; 1862 }; 1863 1864 blsp_i2c6: i2c@78ba000 { 1865 compatible = "qcom,i2c-qup-v2.2.1"; 1866 reg = <0x078ba000 0x500>; 1867 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1868 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1869 <&gcc GCC_BLSP1_AHB_CLK>; 1870 clock-names = "core", "iface"; 1871 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1872 dma-names = "tx", "rx"; 1873 pinctrl-0 = <&blsp_i2c6_default>; 1874 pinctrl-1 = <&blsp_i2c6_sleep>; 1875 pinctrl-names = "default", "sleep"; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 status = "disabled"; 1879 }; 1880 1881 blsp_spi6: spi@78ba000 { 1882 compatible = "qcom,spi-qup-v2.2.1"; 1883 reg = <0x078ba000 0x500>; 1884 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1885 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1886 <&gcc GCC_BLSP1_AHB_CLK>; 1887 clock-names = "core", "iface"; 1888 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1889 dma-names = "tx", "rx"; 1890 pinctrl-0 = <&blsp_spi6_default>; 1891 pinctrl-1 = <&blsp_spi6_sleep>; 1892 pinctrl-names = "default", "sleep"; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 status = "disabled"; 1896 }; 1897 1898 usb: usb@78d9000 { 1899 compatible = "qcom,ci-hdrc"; 1900 reg = <0x078d9000 0x200>, 1901 <0x078d9200 0x200>; 1902 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1905 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1906 clock-names = "iface", "core"; 1907 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1908 assigned-clock-rates = <80000000>; 1909 resets = <&gcc GCC_USB_HS_BCR>; 1910 reset-names = "core"; 1911 #reset-cells = <1>; 1912 phy_type = "ulpi"; 1913 dr_mode = "otg"; 1914 adp-disable; 1915 hnp-disable; 1916 srp-disable; 1917 ahb-burst-config = <0>; 1918 phy-names = "usb-phy"; 1919 phys = <&usb_hs_phy>; 1920 status = "disabled"; 1921 1922 ulpi { 1923 usb_hs_phy: phy { 1924 compatible = "qcom,usb-hs-phy-msm8916", 1925 "qcom,usb-hs-phy"; 1926 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1927 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1928 clock-names = "ref", "sleep"; 1929 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1930 reset-names = "phy", "por"; 1931 #phy-cells = <0>; 1932 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1933 <0x1 0x6b>, 1934 <0x2 0x24>, 1935 <0x3 0x13>; 1936 }; 1937 }; 1938 }; 1939 1940 wcnss: remoteproc@a204000 { 1941 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1942 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1943 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1944 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1945 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1946 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1947 interrupt-names = "wdog", 1948 "fatal", 1949 "ready", 1950 "handover", 1951 "stop-ack"; 1952 reg = <0x0a204000 0x2000>, 1953 <0x0a202000 0x1000>, 1954 <0x0a21b000 0x3000>; 1955 reg-names = "ccu", "dxe", "pmu"; 1956 1957 memory-region = <&wcnss_mem>; 1958 1959 power-domains = <&rpmpd MSM8939_VDDCX>, 1960 <&rpmpd MSM8939_VDDMX>; 1961 power-domain-names = "cx", "mx"; 1962 1963 qcom,smem-states = <&wcnss_smp2p_out 0>; 1964 qcom,smem-state-names = "stop"; 1965 1966 pinctrl-names = "default"; 1967 pinctrl-0 = <&wcss_wlan_default>; 1968 1969 status = "disabled"; 1970 1971 wcnss_iris: iris { 1972 /* Separate chip, compatible is board-specific */ 1973 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1974 clock-names = "xo"; 1975 }; 1976 1977 smd-edge { 1978 interrupts = <GIC_SPI 142 1>; 1979 qcom,ipc = <&apcs1_mbox 8 17>; 1980 qcom,smd-edge = <6>; 1981 qcom,remote-pid = <4>; 1982 1983 label = "pronto"; 1984 1985 wcnss { 1986 compatible = "qcom,wcnss"; 1987 qcom,smd-channels = "WCNSS_CTRL"; 1988 1989 qcom,mmio = <&wcnss>; 1990 1991 wcnss_bt: bluetooth { 1992 compatible = "qcom,wcnss-bt"; 1993 }; 1994 1995 wcnss_wifi: wifi { 1996 compatible = "qcom,wcnss-wlan"; 1997 1998 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2000 interrupt-names = "tx", "rx"; 2001 2002 qcom,smem-states = <&apps_smsm 10>, 2003 <&apps_smsm 9>; 2004 qcom,smem-state-names = "tx-enable", 2005 "tx-rings-empty"; 2006 }; 2007 }; 2008 }; 2009 }; 2010 2011 intc: interrupt-controller@b000000 { 2012 compatible = "qcom,msm-qgic2"; 2013 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2014 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2015 interrupt-controller; 2016 #interrupt-cells = <3>; 2017 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2018 }; 2019 2020 apcs1_mbox: mailbox@b011000 { 2021 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2022 reg = <0x0b011000 0x1000>; 2023 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2024 clock-names = "pll", "aux", "ref"; 2025 #clock-cells = <0>; 2026 assigned-clocks = <&apcs2>; 2027 assigned-clock-rates = <297600000>; 2028 #mbox-cells = <1>; 2029 }; 2030 2031 a53pll_c1: clock@b016000 { 2032 compatible = "qcom,msm8939-a53pll"; 2033 reg = <0x0b016000 0x40>; 2034 #clock-cells = <0>; 2035 }; 2036 2037 acc0: clock-controller@b088000 { 2038 compatible = "qcom,kpss-acc-v2"; 2039 reg = <0x0b088000 0x1000>; 2040 }; 2041 2042 saw0: power-manager@b089000 { 2043 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2044 reg = <0x0b089000 0x1000>; 2045 }; 2046 2047 acc1: clock-controller@b098000 { 2048 compatible = "qcom,kpss-acc-v2"; 2049 reg = <0x0b098000 0x1000>; 2050 }; 2051 2052 saw1: power-manager@b099000 { 2053 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2054 reg = <0x0b099000 0x1000>; 2055 }; 2056 2057 acc2: clock-controller@b0a8000 { 2058 compatible = "qcom,kpss-acc-v2"; 2059 reg = <0x0b0a8000 0x1000>; 2060 }; 2061 2062 saw2: power-manager@b0a9000 { 2063 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2064 reg = <0x0b0a9000 0x1000>; 2065 }; 2066 2067 acc3: clock-controller@b0b8000 { 2068 compatible = "qcom,kpss-acc-v2"; 2069 reg = <0x0b0b8000 0x1000>; 2070 }; 2071 2072 saw3: power-manager@b0b9000 { 2073 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2074 reg = <0x0b0b9000 0x1000>; 2075 }; 2076 2077 apcs0_mbox: mailbox@b111000 { 2078 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2079 reg = <0x0b111000 0x1000>; 2080 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2081 clock-names = "pll", "aux", "ref"; 2082 #clock-cells = <0>; 2083 #mbox-cells = <1>; 2084 }; 2085 2086 a53pll_c0: clock@b116000 { 2087 compatible = "qcom,msm8939-a53pll"; 2088 reg = <0x0b116000 0x40>; 2089 #clock-cells = <0>; 2090 }; 2091 2092 timer@b120000 { 2093 compatible = "arm,armv7-timer-mem"; 2094 reg = <0x0b120000 0x1000>; 2095 #address-cells = <1>; 2096 #size-cells = <1>; 2097 ranges; 2098 2099 frame@b121000 { 2100 reg = <0x0b121000 0x1000>, 2101 <0x0b122000 0x1000>; 2102 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2104 frame-number = <0>; 2105 }; 2106 2107 frame@b123000 { 2108 reg = <0x0b123000 0x1000>; 2109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2110 frame-number = <1>; 2111 status = "disabled"; 2112 }; 2113 2114 frame@b124000 { 2115 reg = <0x0b124000 0x1000>; 2116 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2117 frame-number = <2>; 2118 status = "disabled"; 2119 }; 2120 2121 frame@b125000 { 2122 reg = <0x0b125000 0x1000>; 2123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2124 frame-number = <3>; 2125 status = "disabled"; 2126 }; 2127 2128 frame@b126000 { 2129 reg = <0x0b126000 0x1000>; 2130 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2131 frame-number = <4>; 2132 status = "disabled"; 2133 }; 2134 2135 frame@b127000 { 2136 reg = <0x0b127000 0x1000>; 2137 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2138 frame-number = <5>; 2139 status = "disabled"; 2140 }; 2141 2142 frame@b128000 { 2143 reg = <0x0b128000 0x1000>; 2144 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2145 frame-number = <6>; 2146 status = "disabled"; 2147 }; 2148 }; 2149 2150 acc4: clock-controller@b188000 { 2151 compatible = "qcom,kpss-acc-v2"; 2152 reg = <0x0b188000 0x1000>; 2153 }; 2154 2155 saw4: power-manager@b189000 { 2156 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2157 reg = <0x0b189000 0x1000>; 2158 }; 2159 2160 acc5: clock-controller@b198000 { 2161 compatible = "qcom,kpss-acc-v2"; 2162 reg = <0x0b198000 0x1000>; 2163 }; 2164 2165 saw5: power-manager@b199000 { 2166 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2167 reg = <0x0b199000 0x1000>; 2168 }; 2169 2170 acc6: clock-controller@b1a8000 { 2171 compatible = "qcom,kpss-acc-v2"; 2172 reg = <0x0b1a8000 0x1000>; 2173 }; 2174 2175 saw6: power-manager@b1a9000 { 2176 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2177 reg = <0x0b1a9000 0x1000>; 2178 }; 2179 2180 acc7: clock-controller@b1b8000 { 2181 compatible = "qcom,kpss-acc-v2"; 2182 reg = <0x0b1b8000 0x1000>; 2183 }; 2184 2185 saw7: power-manager@b1b9000 { 2186 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2187 reg = <0x0b1b9000 0x1000>; 2188 }; 2189 2190 a53pll_cci: clock@b1d0000 { 2191 compatible = "qcom,msm8939-a53pll"; 2192 reg = <0x0b1d0000 0x40>; 2193 #clock-cells = <0>; 2194 }; 2195 2196 apcs2: mailbox@b1d1000 { 2197 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2198 reg = <0x0b1d1000 0x1000>; 2199 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2200 clock-names = "pll", "aux", "ref"; 2201 #clock-cells = <0>; 2202 #mbox-cells = <1>; 2203 }; 2204 }; 2205 2206 thermal_zones: thermal-zones { 2207 cpu0-thermal { 2208 polling-delay-passive = <250>; 2209 polling-delay = <1000>; 2210 2211 thermal-sensors = <&tsens 5>; 2212 2213 trips { 2214 cpu0_alert: trip0 { 2215 temperature = <75000>; 2216 hysteresis = <2000>; 2217 type = "passive"; 2218 }; 2219 2220 cpu0_crit: trip1 { 2221 temperature = <115000>; 2222 hysteresis = <0>; 2223 type = "critical"; 2224 }; 2225 }; 2226 2227 cooling-maps { 2228 map0 { 2229 trip = <&cpu0_alert>; 2230 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2231 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2232 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2233 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2234 }; 2235 }; 2236 }; 2237 2238 cpu1-thermal { 2239 polling-delay-passive = <250>; 2240 polling-delay = <1000>; 2241 2242 thermal-sensors = <&tsens 6>; 2243 2244 trips { 2245 cpu1_alert: trip0 { 2246 temperature = <75000>; 2247 hysteresis = <2000>; 2248 type = "passive"; 2249 }; 2250 2251 cpu1_crit: trip1 { 2252 temperature = <110000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 2258 cooling-maps { 2259 map0 { 2260 trip = <&cpu1_alert>; 2261 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2262 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2263 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2264 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2265 }; 2266 }; 2267 }; 2268 2269 cpu2-thermal { 2270 polling-delay-passive = <250>; 2271 polling-delay = <1000>; 2272 2273 thermal-sensors = <&tsens 7>; 2274 2275 trips { 2276 cpu2_alert: trip0 { 2277 temperature = <75000>; 2278 hysteresis = <2000>; 2279 type = "passive"; 2280 }; 2281 2282 cpu2_crit: trip1 { 2283 temperature = <110000>; 2284 hysteresis = <2000>; 2285 type = "critical"; 2286 }; 2287 }; 2288 2289 cooling-maps { 2290 map0 { 2291 trip = <&cpu2_alert>; 2292 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2293 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2294 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2295 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2296 }; 2297 }; 2298 }; 2299 2300 cpu3-thermal { 2301 polling-delay-passive = <250>; 2302 polling-delay = <1000>; 2303 2304 thermal-sensors = <&tsens 8>; 2305 2306 trips { 2307 cpu3_alert: trip0 { 2308 temperature = <75000>; 2309 hysteresis = <2000>; 2310 type = "passive"; 2311 }; 2312 2313 cpu3_crit: trip1 { 2314 temperature = <110000>; 2315 hysteresis = <2000>; 2316 type = "critical"; 2317 }; 2318 }; 2319 2320 cooling-maps { 2321 map0 { 2322 trip = <&cpu3_alert>; 2323 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2324 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2325 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2326 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2327 }; 2328 }; 2329 }; 2330 2331 cpu4567-thermal { 2332 polling-delay-passive = <250>; 2333 polling-delay = <1000>; 2334 2335 thermal-sensors = <&tsens 9>; 2336 2337 trips { 2338 cpu4567_alert: trip0 { 2339 temperature = <75000>; 2340 hysteresis = <2000>; 2341 type = "passive"; 2342 }; 2343 2344 cpu4567_crit: trip1 { 2345 temperature = <110000>; 2346 hysteresis = <2000>; 2347 type = "critical"; 2348 }; 2349 }; 2350 2351 cooling-maps { 2352 map0 { 2353 trip = <&cpu4567_alert>; 2354 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2355 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2356 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2357 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2358 }; 2359 }; 2360 }; 2361 2362 gpu-thermal { 2363 polling-delay-passive = <250>; 2364 polling-delay = <1000>; 2365 2366 thermal-sensors = <&tsens 3>; 2367 2368 trips { 2369 gpu_alert0: trip-point0 { 2370 temperature = <75000>; 2371 hysteresis = <2000>; 2372 type = "passive"; 2373 }; 2374 2375 gpu_crit: gpu_crit { 2376 temperature = <95000>; 2377 hysteresis = <2000>; 2378 type = "critical"; 2379 }; 2380 }; 2381 }; 2382 2383 modem1-thermal { 2384 polling-delay-passive = <250>; 2385 polling-delay = <1000>; 2386 2387 thermal-sensors = <&tsens 0>; 2388 2389 trips { 2390 modem1_alert0: trip-point0 { 2391 temperature = <85000>; 2392 hysteresis = <2000>; 2393 type = "hot"; 2394 }; 2395 }; 2396 }; 2397 2398 modem2-thermal { 2399 polling-delay-passive = <250>; 2400 polling-delay = <1000>; 2401 2402 thermal-sensors = <&tsens 2>; 2403 2404 trips { 2405 modem2_alert0: trip-point0 { 2406 temperature = <85000>; 2407 hysteresis = <2000>; 2408 type = "hot"; 2409 }; 2410 }; 2411 }; 2412 2413 camera-thermal { 2414 polling-delay-passive = <250>; 2415 polling-delay = <1000>; 2416 2417 thermal-sensors = <&tsens 1>; 2418 2419 trips { 2420 cam_alert0: trip-point0 { 2421 temperature = <75000>; 2422 hysteresis = <2000>; 2423 type = "hot"; 2424 }; 2425 }; 2426 }; 2427 }; 2428 2429 timer { 2430 compatible = "arm,armv8-timer"; 2431 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2432 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2433 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2434 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2435 }; 2436}; 2437