1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sdhc_1; /* SDC1 eMMC slot */ 23 mmc1 = &sdhc_2; /* SDC2 SD card slot */ 24 }; 25 26 chosen { }; 27 28 memory@80000000 { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0x80000000 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 tz-apps@86000000 { 40 reg = <0x0 0x86000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 smem@86300000 { 45 compatible = "qcom,smem"; 46 reg = <0x0 0x86300000 0x0 0x100000>; 47 no-map; 48 49 hwlocks = <&tcsr_mutex 3>; 50 qcom,rpm-msg-ram = <&rpm_msg_ram>; 51 }; 52 53 hypervisor@86400000 { 54 reg = <0x0 0x86400000 0x0 0x100000>; 55 no-map; 56 }; 57 58 tz@86500000 { 59 reg = <0x0 0x86500000 0x0 0x180000>; 60 no-map; 61 }; 62 63 reserved@86680000 { 64 reg = <0x0 0x86680000 0x0 0x80000>; 65 no-map; 66 }; 67 68 rmtfs@86700000 { 69 compatible = "qcom,rmtfs-mem"; 70 reg = <0x0 0x86700000 0x0 0xe0000>; 71 no-map; 72 73 qcom,client-id = <1>; 74 }; 75 76 rfsa@867e0000 { 77 reg = <0x0 0x867e0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 mpss_mem: mpss@86800000 { 82 reg = <0x0 0x86800000 0x0 0x2b00000>; 83 no-map; 84 }; 85 86 wcnss_mem: wcnss@89300000 { 87 reg = <0x0 0x89300000 0x0 0x600000>; 88 no-map; 89 }; 90 91 venus_mem: venus@89900000 { 92 reg = <0x0 0x89900000 0x0 0x600000>; 93 no-map; 94 }; 95 96 mba_mem: mba@8ea00000 { 97 no-map; 98 reg = <0 0x8ea00000 0 0x100000>; 99 }; 100 }; 101 102 clocks { 103 xo_board: xo-board { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <19200000>; 107 }; 108 109 sleep_clk: sleep-clk { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <32768>; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 CPU0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x0>; 124 next-level-cache = <&L2_0>; 125 enable-method = "psci"; 126 clocks = <&apcs>; 127 operating-points-v2 = <&cpu_opp_table>; 128 #cooling-cells = <2>; 129 power-domains = <&CPU_PD0>; 130 power-domain-names = "psci"; 131 qcom,acc = <&cpu0_acc>; 132 qcom,saw = <&cpu0_saw>; 133 }; 134 135 CPU1: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x1>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 clocks = <&apcs>; 142 operating-points-v2 = <&cpu_opp_table>; 143 #cooling-cells = <2>; 144 power-domains = <&CPU_PD1>; 145 power-domain-names = "psci"; 146 qcom,acc = <&cpu1_acc>; 147 qcom,saw = <&cpu1_saw>; 148 }; 149 150 CPU2: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x2>; 154 next-level-cache = <&L2_0>; 155 enable-method = "psci"; 156 clocks = <&apcs>; 157 operating-points-v2 = <&cpu_opp_table>; 158 #cooling-cells = <2>; 159 power-domains = <&CPU_PD2>; 160 power-domain-names = "psci"; 161 qcom,acc = <&cpu2_acc>; 162 qcom,saw = <&cpu2_saw>; 163 }; 164 165 CPU3: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x3>; 169 next-level-cache = <&L2_0>; 170 enable-method = "psci"; 171 clocks = <&apcs>; 172 operating-points-v2 = <&cpu_opp_table>; 173 #cooling-cells = <2>; 174 power-domains = <&CPU_PD3>; 175 power-domain-names = "psci"; 176 qcom,acc = <&cpu3_acc>; 177 qcom,saw = <&cpu3_saw>; 178 }; 179 180 L2_0: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 }; 184 185 idle-states { 186 entry-method = "psci"; 187 188 CPU_SLEEP_0: cpu-sleep-0 { 189 compatible = "arm,idle-state"; 190 idle-state-name = "standalone-power-collapse"; 191 arm,psci-suspend-param = <0x40000002>; 192 entry-latency-us = <130>; 193 exit-latency-us = <150>; 194 min-residency-us = <2000>; 195 local-timer-stop; 196 }; 197 }; 198 199 domain-idle-states { 200 201 CLUSTER_RET: cluster-retention { 202 compatible = "domain-idle-state"; 203 arm,psci-suspend-param = <0x41000012>; 204 entry-latency-us = <500>; 205 exit-latency-us = <500>; 206 min-residency-us = <2000>; 207 }; 208 209 CLUSTER_PWRDN: cluster-gdhs { 210 compatible = "domain-idle-state"; 211 arm,psci-suspend-param = <0x41000032>; 212 entry-latency-us = <2000>; 213 exit-latency-us = <2000>; 214 min-residency-us = <6000>; 215 }; 216 }; 217 }; 218 219 cpu_opp_table: opp-table-cpu { 220 compatible = "operating-points-v2"; 221 opp-shared; 222 223 opp-200000000 { 224 opp-hz = /bits/ 64 <200000000>; 225 }; 226 opp-400000000 { 227 opp-hz = /bits/ 64 <400000000>; 228 }; 229 opp-800000000 { 230 opp-hz = /bits/ 64 <800000000>; 231 }; 232 opp-998400000 { 233 opp-hz = /bits/ 64 <998400000>; 234 }; 235 }; 236 237 firmware { 238 scm: scm { 239 compatible = "qcom,scm-msm8916", "qcom,scm"; 240 clocks = <&gcc GCC_CRYPTO_CLK>, 241 <&gcc GCC_CRYPTO_AXI_CLK>, 242 <&gcc GCC_CRYPTO_AHB_CLK>; 243 clock-names = "core", "bus", "iface"; 244 #reset-cells = <1>; 245 246 qcom,dload-mode = <&tcsr 0x6100>; 247 }; 248 }; 249 250 pmu { 251 compatible = "arm,cortex-a53-pmu"; 252 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 253 }; 254 255 psci { 256 compatible = "arm,psci-1.0"; 257 method = "smc"; 258 259 CPU_PD0: power-domain-cpu0 { 260 #power-domain-cells = <0>; 261 power-domains = <&CLUSTER_PD>; 262 domain-idle-states = <&CPU_SLEEP_0>; 263 }; 264 265 CPU_PD1: power-domain-cpu1 { 266 #power-domain-cells = <0>; 267 power-domains = <&CLUSTER_PD>; 268 domain-idle-states = <&CPU_SLEEP_0>; 269 }; 270 271 CPU_PD2: power-domain-cpu2 { 272 #power-domain-cells = <0>; 273 power-domains = <&CLUSTER_PD>; 274 domain-idle-states = <&CPU_SLEEP_0>; 275 }; 276 277 CPU_PD3: power-domain-cpu3 { 278 #power-domain-cells = <0>; 279 power-domains = <&CLUSTER_PD>; 280 domain-idle-states = <&CPU_SLEEP_0>; 281 }; 282 283 CLUSTER_PD: power-domain-cluster { 284 #power-domain-cells = <0>; 285 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 286 }; 287 }; 288 289 smd { 290 compatible = "qcom,smd"; 291 292 rpm { 293 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 294 qcom,ipc = <&apcs 8 0>; 295 qcom,smd-edge = <15>; 296 297 rpm_requests: rpm-requests { 298 compatible = "qcom,rpm-msm8916"; 299 qcom,smd-channels = "rpm_requests"; 300 301 rpmcc: clock-controller { 302 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 303 #clock-cells = <1>; 304 clocks = <&xo_board>; 305 clock-names = "xo"; 306 }; 307 308 rpmpd: power-controller { 309 compatible = "qcom,msm8916-rpmpd"; 310 #power-domain-cells = <1>; 311 operating-points-v2 = <&rpmpd_opp_table>; 312 313 rpmpd_opp_table: opp-table { 314 compatible = "operating-points-v2"; 315 316 rpmpd_opp_ret: opp1 { 317 opp-level = <1>; 318 }; 319 rpmpd_opp_svs_krait: opp2 { 320 opp-level = <2>; 321 }; 322 rpmpd_opp_svs_soc: opp3 { 323 opp-level = <3>; 324 }; 325 rpmpd_opp_nom: opp4 { 326 opp-level = <4>; 327 }; 328 rpmpd_opp_turbo: opp5 { 329 opp-level = <5>; 330 }; 331 rpmpd_opp_super_turbo: opp6 { 332 opp-level = <6>; 333 }; 334 }; 335 }; 336 }; 337 }; 338 }; 339 340 smp2p-hexagon { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <435>, <428>; 343 344 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 345 346 qcom,ipc = <&apcs 8 14>; 347 348 qcom,local-pid = <0>; 349 qcom,remote-pid = <1>; 350 351 hexagon_smp2p_out: master-kernel { 352 qcom,entry-name = "master-kernel"; 353 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 hexagon_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 }; 363 }; 364 365 smp2p-wcnss { 366 compatible = "qcom,smp2p"; 367 qcom,smem = <451>, <431>; 368 369 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 370 371 qcom,ipc = <&apcs 8 18>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <4>; 375 376 wcnss_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 379 #qcom,smem-state-cells = <1>; 380 }; 381 382 wcnss_smp2p_in: slave-kernel { 383 qcom,entry-name = "slave-kernel"; 384 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 }; 388 }; 389 390 smsm { 391 compatible = "qcom,smsm"; 392 393 #address-cells = <1>; 394 #size-cells = <0>; 395 396 qcom,ipc-1 = <&apcs 8 13>; 397 qcom,ipc-3 = <&apcs 8 19>; 398 399 apps_smsm: apps@0 { 400 reg = <0>; 401 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 hexagon_smsm: hexagon@1 { 406 reg = <1>; 407 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 408 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 }; 412 413 wcnss_smsm: wcnss@6 { 414 reg = <6>; 415 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 416 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 }; 421 422 soc: soc@0 { 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0 0 0 0xffffffff>; 426 compatible = "simple-bus"; 427 428 rng@22000 { 429 compatible = "qcom,prng"; 430 reg = <0x00022000 0x200>; 431 clocks = <&gcc GCC_PRNG_AHB_CLK>; 432 clock-names = "core"; 433 }; 434 435 restart@4ab000 { 436 compatible = "qcom,pshold"; 437 reg = <0x004ab000 0x4>; 438 }; 439 440 qfprom: qfprom@5c000 { 441 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 442 reg = <0x0005c000 0x1000>; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 tsens_caldata: caldata@d0 { 446 reg = <0xd0 0x8>; 447 }; 448 tsens_calsel: calsel@ec { 449 reg = <0xec 0x4>; 450 }; 451 }; 452 453 rpm_msg_ram: sram@60000 { 454 compatible = "qcom,rpm-msg-ram"; 455 reg = <0x00060000 0x8000>; 456 }; 457 458 sram@290000 { 459 compatible = "qcom,msm8916-rpm-stats"; 460 reg = <0x00290000 0x10000>; 461 }; 462 463 bimc: interconnect@400000 { 464 compatible = "qcom,msm8916-bimc"; 465 reg = <0x00400000 0x62000>; 466 #interconnect-cells = <1>; 467 clock-names = "bus", "bus_a"; 468 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 469 <&rpmcc RPM_SMD_BIMC_A_CLK>; 470 }; 471 472 tsens: thermal-sensor@4a9000 { 473 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 474 reg = <0x004a9000 0x1000>, /* TM */ 475 <0x004a8000 0x1000>; /* SROT */ 476 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 477 nvmem-cell-names = "calib", "calib_sel"; 478 #qcom,sensors = <5>; 479 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 480 interrupt-names = "uplow"; 481 #thermal-sensor-cells = <1>; 482 }; 483 484 pcnoc: interconnect@500000 { 485 compatible = "qcom,msm8916-pcnoc"; 486 reg = <0x00500000 0x11000>; 487 #interconnect-cells = <1>; 488 clock-names = "bus", "bus_a"; 489 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 490 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 491 }; 492 493 snoc: interconnect@580000 { 494 compatible = "qcom,msm8916-snoc"; 495 reg = <0x00580000 0x14000>; 496 #interconnect-cells = <1>; 497 clock-names = "bus", "bus_a"; 498 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 499 <&rpmcc RPM_SMD_SNOC_A_CLK>; 500 }; 501 502 stm: stm@802000 { 503 compatible = "arm,coresight-stm", "arm,primecell"; 504 reg = <0x00802000 0x1000>, 505 <0x09280000 0x180000>; 506 reg-names = "stm-base", "stm-stimulus-base"; 507 508 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 509 clock-names = "apb_pclk", "atclk"; 510 511 status = "disabled"; 512 513 out-ports { 514 port { 515 stm_out: endpoint { 516 remote-endpoint = <&funnel0_in7>; 517 }; 518 }; 519 }; 520 }; 521 522 /* System CTIs */ 523 /* CTI 0 - TMC connections */ 524 cti0: cti@810000 { 525 compatible = "arm,coresight-cti", "arm,primecell"; 526 reg = <0x00810000 0x1000>; 527 528 clocks = <&rpmcc RPM_QDSS_CLK>; 529 clock-names = "apb_pclk"; 530 531 status = "disabled"; 532 }; 533 534 /* CTI 1 - TPIU connections */ 535 cti1: cti@811000 { 536 compatible = "arm,coresight-cti", "arm,primecell"; 537 reg = <0x00811000 0x1000>; 538 539 clocks = <&rpmcc RPM_QDSS_CLK>; 540 clock-names = "apb_pclk"; 541 542 status = "disabled"; 543 }; 544 545 /* CTIs 2-11 - no information - not instantiated */ 546 547 tpiu: tpiu@820000 { 548 compatible = "arm,coresight-tpiu", "arm,primecell"; 549 reg = <0x00820000 0x1000>; 550 551 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 552 clock-names = "apb_pclk", "atclk"; 553 554 status = "disabled"; 555 556 in-ports { 557 port { 558 tpiu_in: endpoint { 559 remote-endpoint = <&replicator_out1>; 560 }; 561 }; 562 }; 563 }; 564 565 funnel0: funnel@821000 { 566 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 567 reg = <0x00821000 0x1000>; 568 569 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 570 clock-names = "apb_pclk", "atclk"; 571 572 status = "disabled"; 573 574 in-ports { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 578 /* 579 * Not described input ports: 580 * 0 - connected to Resource and Power Manger CPU ETM 581 * 1 - not-connected 582 * 2 - connected to Modem CPU ETM 583 * 3 - not-connected 584 * 5 - not-connected 585 * 6 - connected trought funnel to Wireless CPU ETM 586 * 7 - connected to STM component 587 */ 588 589 port@4 { 590 reg = <4>; 591 funnel0_in4: endpoint { 592 remote-endpoint = <&funnel1_out>; 593 }; 594 }; 595 596 port@7 { 597 reg = <7>; 598 funnel0_in7: endpoint { 599 remote-endpoint = <&stm_out>; 600 }; 601 }; 602 }; 603 604 out-ports { 605 port { 606 funnel0_out: endpoint { 607 remote-endpoint = <&etf_in>; 608 }; 609 }; 610 }; 611 }; 612 613 replicator: replicator@824000 { 614 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 615 reg = <0x00824000 0x1000>; 616 617 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 618 clock-names = "apb_pclk", "atclk"; 619 620 status = "disabled"; 621 622 out-ports { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 port@0 { 627 reg = <0>; 628 replicator_out0: endpoint { 629 remote-endpoint = <&etr_in>; 630 }; 631 }; 632 port@1 { 633 reg = <1>; 634 replicator_out1: endpoint { 635 remote-endpoint = <&tpiu_in>; 636 }; 637 }; 638 }; 639 640 in-ports { 641 port { 642 replicator_in: endpoint { 643 remote-endpoint = <&etf_out>; 644 }; 645 }; 646 }; 647 }; 648 649 etf: etf@825000 { 650 compatible = "arm,coresight-tmc", "arm,primecell"; 651 reg = <0x00825000 0x1000>; 652 653 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 654 clock-names = "apb_pclk", "atclk"; 655 656 status = "disabled"; 657 658 in-ports { 659 port { 660 etf_in: endpoint { 661 remote-endpoint = <&funnel0_out>; 662 }; 663 }; 664 }; 665 666 out-ports { 667 port { 668 etf_out: endpoint { 669 remote-endpoint = <&replicator_in>; 670 }; 671 }; 672 }; 673 }; 674 675 etr: etr@826000 { 676 compatible = "arm,coresight-tmc", "arm,primecell"; 677 reg = <0x00826000 0x1000>; 678 679 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 680 clock-names = "apb_pclk", "atclk"; 681 682 status = "disabled"; 683 684 in-ports { 685 port { 686 etr_in: endpoint { 687 remote-endpoint = <&replicator_out0>; 688 }; 689 }; 690 }; 691 }; 692 693 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 695 reg = <0x00841000 0x1000>; 696 697 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 698 clock-names = "apb_pclk", "atclk"; 699 700 status = "disabled"; 701 702 in-ports { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 port@0 { 707 reg = <0>; 708 funnel1_in0: endpoint { 709 remote-endpoint = <&etm0_out>; 710 }; 711 }; 712 port@1 { 713 reg = <1>; 714 funnel1_in1: endpoint { 715 remote-endpoint = <&etm1_out>; 716 }; 717 }; 718 port@2 { 719 reg = <2>; 720 funnel1_in2: endpoint { 721 remote-endpoint = <&etm2_out>; 722 }; 723 }; 724 port@3 { 725 reg = <3>; 726 funnel1_in3: endpoint { 727 remote-endpoint = <&etm3_out>; 728 }; 729 }; 730 }; 731 732 out-ports { 733 port { 734 funnel1_out: endpoint { 735 remote-endpoint = <&funnel0_in4>; 736 }; 737 }; 738 }; 739 }; 740 741 debug0: debug@850000 { 742 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 743 reg = <0x00850000 0x1000>; 744 clocks = <&rpmcc RPM_QDSS_CLK>; 745 clock-names = "apb_pclk"; 746 cpu = <&CPU0>; 747 status = "disabled"; 748 }; 749 750 debug1: debug@852000 { 751 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 752 reg = <0x00852000 0x1000>; 753 clocks = <&rpmcc RPM_QDSS_CLK>; 754 clock-names = "apb_pclk"; 755 cpu = <&CPU1>; 756 status = "disabled"; 757 }; 758 759 debug2: debug@854000 { 760 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 761 reg = <0x00854000 0x1000>; 762 clocks = <&rpmcc RPM_QDSS_CLK>; 763 clock-names = "apb_pclk"; 764 cpu = <&CPU2>; 765 status = "disabled"; 766 }; 767 768 debug3: debug@856000 { 769 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 770 reg = <0x00856000 0x1000>; 771 clocks = <&rpmcc RPM_QDSS_CLK>; 772 clock-names = "apb_pclk"; 773 cpu = <&CPU3>; 774 status = "disabled"; 775 }; 776 777 /* Core CTIs; CTIs 12-15 */ 778 /* CTI - CPU-0 */ 779 cti12: cti@858000 { 780 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 781 "arm,primecell"; 782 reg = <0x00858000 0x1000>; 783 784 clocks = <&rpmcc RPM_QDSS_CLK>; 785 clock-names = "apb_pclk"; 786 787 cpu = <&CPU0>; 788 arm,cs-dev-assoc = <&etm0>; 789 790 status = "disabled"; 791 }; 792 793 /* CTI - CPU-1 */ 794 cti13: cti@859000 { 795 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 796 "arm,primecell"; 797 reg = <0x00859000 0x1000>; 798 799 clocks = <&rpmcc RPM_QDSS_CLK>; 800 clock-names = "apb_pclk"; 801 802 cpu = <&CPU1>; 803 arm,cs-dev-assoc = <&etm1>; 804 805 status = "disabled"; 806 }; 807 808 /* CTI - CPU-2 */ 809 cti14: cti@85a000 { 810 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 811 "arm,primecell"; 812 reg = <0x0085a000 0x1000>; 813 814 clocks = <&rpmcc RPM_QDSS_CLK>; 815 clock-names = "apb_pclk"; 816 817 cpu = <&CPU2>; 818 arm,cs-dev-assoc = <&etm2>; 819 820 status = "disabled"; 821 }; 822 823 /* CTI - CPU-3 */ 824 cti15: cti@85b000 { 825 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 826 "arm,primecell"; 827 reg = <0x0085b000 0x1000>; 828 829 clocks = <&rpmcc RPM_QDSS_CLK>; 830 clock-names = "apb_pclk"; 831 832 cpu = <&CPU3>; 833 arm,cs-dev-assoc = <&etm3>; 834 835 status = "disabled"; 836 }; 837 838 etm0: etm@85c000 { 839 compatible = "arm,coresight-etm4x", "arm,primecell"; 840 reg = <0x0085c000 0x1000>; 841 842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 843 clock-names = "apb_pclk", "atclk"; 844 arm,coresight-loses-context-with-cpu; 845 846 cpu = <&CPU0>; 847 848 status = "disabled"; 849 850 out-ports { 851 port { 852 etm0_out: endpoint { 853 remote-endpoint = <&funnel1_in0>; 854 }; 855 }; 856 }; 857 }; 858 859 etm1: etm@85d000 { 860 compatible = "arm,coresight-etm4x", "arm,primecell"; 861 reg = <0x0085d000 0x1000>; 862 863 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 864 clock-names = "apb_pclk", "atclk"; 865 arm,coresight-loses-context-with-cpu; 866 867 cpu = <&CPU1>; 868 869 status = "disabled"; 870 871 out-ports { 872 port { 873 etm1_out: endpoint { 874 remote-endpoint = <&funnel1_in1>; 875 }; 876 }; 877 }; 878 }; 879 880 etm2: etm@85e000 { 881 compatible = "arm,coresight-etm4x", "arm,primecell"; 882 reg = <0x0085e000 0x1000>; 883 884 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 885 clock-names = "apb_pclk", "atclk"; 886 arm,coresight-loses-context-with-cpu; 887 888 cpu = <&CPU2>; 889 890 status = "disabled"; 891 892 out-ports { 893 port { 894 etm2_out: endpoint { 895 remote-endpoint = <&funnel1_in2>; 896 }; 897 }; 898 }; 899 }; 900 901 etm3: etm@85f000 { 902 compatible = "arm,coresight-etm4x", "arm,primecell"; 903 reg = <0x0085f000 0x1000>; 904 905 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 906 clock-names = "apb_pclk", "atclk"; 907 arm,coresight-loses-context-with-cpu; 908 909 cpu = <&CPU3>; 910 911 status = "disabled"; 912 913 out-ports { 914 port { 915 etm3_out: endpoint { 916 remote-endpoint = <&funnel1_in3>; 917 }; 918 }; 919 }; 920 }; 921 922 msmgpio: pinctrl@1000000 { 923 compatible = "qcom,msm8916-pinctrl"; 924 reg = <0x01000000 0x300000>; 925 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 926 gpio-controller; 927 gpio-ranges = <&msmgpio 0 0 122>; 928 #gpio-cells = <2>; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 }; 932 933 gcc: clock-controller@1800000 { 934 compatible = "qcom,gcc-msm8916"; 935 #clock-cells = <1>; 936 #reset-cells = <1>; 937 #power-domain-cells = <1>; 938 reg = <0x01800000 0x80000>; 939 clocks = <&xo_board>, 940 <&sleep_clk>, 941 <&dsi_phy0 1>, 942 <&dsi_phy0 0>, 943 <0>, 944 <0>, 945 <0>; 946 clock-names = "xo", 947 "sleep_clk", 948 "dsi0pll", 949 "dsi0pllbyte", 950 "ext_mclk", 951 "ext_pri_i2s", 952 "ext_sec_i2s"; 953 }; 954 955 tcsr_mutex: hwlock@1905000 { 956 compatible = "qcom,tcsr-mutex"; 957 reg = <0x01905000 0x20000>; 958 #hwlock-cells = <1>; 959 }; 960 961 tcsr: syscon@1937000 { 962 compatible = "qcom,tcsr-msm8916", "syscon"; 963 reg = <0x01937000 0x30000>; 964 }; 965 966 mdss: mdss@1a00000 { 967 status = "disabled"; 968 compatible = "qcom,mdss"; 969 reg = <0x01a00000 0x1000>, 970 <0x01ac8000 0x3000>; 971 reg-names = "mdss_phys", "vbif_phys"; 972 973 power-domains = <&gcc MDSS_GDSC>; 974 975 clocks = <&gcc GCC_MDSS_AHB_CLK>, 976 <&gcc GCC_MDSS_AXI_CLK>, 977 <&gcc GCC_MDSS_VSYNC_CLK>; 978 clock-names = "iface", 979 "bus", 980 "vsync"; 981 982 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 983 984 interrupt-controller; 985 #interrupt-cells = <1>; 986 987 #address-cells = <1>; 988 #size-cells = <1>; 989 ranges; 990 991 mdp: mdp@1a01000 { 992 compatible = "qcom,mdp5"; 993 reg = <0x01a01000 0x89000>; 994 reg-names = "mdp_phys"; 995 996 interrupt-parent = <&mdss>; 997 interrupts = <0>; 998 999 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1000 <&gcc GCC_MDSS_AXI_CLK>, 1001 <&gcc GCC_MDSS_MDP_CLK>, 1002 <&gcc GCC_MDSS_VSYNC_CLK>; 1003 clock-names = "iface", 1004 "bus", 1005 "core", 1006 "vsync"; 1007 1008 iommus = <&apps_iommu 4>; 1009 1010 ports { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 1014 port@0 { 1015 reg = <0>; 1016 mdp5_intf1_out: endpoint { 1017 remote-endpoint = <&dsi0_in>; 1018 }; 1019 }; 1020 }; 1021 }; 1022 1023 dsi0: dsi@1a98000 { 1024 compatible = "qcom,mdss-dsi-ctrl"; 1025 reg = <0x01a98000 0x25c>; 1026 reg-names = "dsi_ctrl"; 1027 1028 interrupt-parent = <&mdss>; 1029 interrupts = <4>; 1030 1031 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1032 <&gcc PCLK0_CLK_SRC>; 1033 assigned-clock-parents = <&dsi_phy0 0>, 1034 <&dsi_phy0 1>; 1035 1036 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1037 <&gcc GCC_MDSS_AHB_CLK>, 1038 <&gcc GCC_MDSS_AXI_CLK>, 1039 <&gcc GCC_MDSS_BYTE0_CLK>, 1040 <&gcc GCC_MDSS_PCLK0_CLK>, 1041 <&gcc GCC_MDSS_ESC0_CLK>; 1042 clock-names = "mdp_core", 1043 "iface", 1044 "bus", 1045 "byte", 1046 "pixel", 1047 "core"; 1048 phys = <&dsi_phy0>; 1049 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 ports { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 port@0 { 1058 reg = <0>; 1059 dsi0_in: endpoint { 1060 remote-endpoint = <&mdp5_intf1_out>; 1061 }; 1062 }; 1063 1064 port@1 { 1065 reg = <1>; 1066 dsi0_out: endpoint { 1067 }; 1068 }; 1069 }; 1070 }; 1071 1072 dsi_phy0: phy@1a98300 { 1073 compatible = "qcom,dsi-phy-28nm-lp"; 1074 reg = <0x01a98300 0xd4>, 1075 <0x01a98500 0x280>, 1076 <0x01a98780 0x30>; 1077 reg-names = "dsi_pll", 1078 "dsi_phy", 1079 "dsi_phy_regulator"; 1080 1081 #clock-cells = <1>; 1082 #phy-cells = <0>; 1083 1084 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1085 <&xo_board>; 1086 clock-names = "iface", "ref"; 1087 }; 1088 }; 1089 1090 camss: camss@1b00000 { 1091 compatible = "qcom,msm8916-camss"; 1092 reg = <0x01b0ac00 0x200>, 1093 <0x01b00030 0x4>, 1094 <0x01b0b000 0x200>, 1095 <0x01b00038 0x4>, 1096 <0x01b08000 0x100>, 1097 <0x01b08400 0x100>, 1098 <0x01b0a000 0x500>, 1099 <0x01b00020 0x10>, 1100 <0x01b10000 0x1000>; 1101 reg-names = "csiphy0", 1102 "csiphy0_clk_mux", 1103 "csiphy1", 1104 "csiphy1_clk_mux", 1105 "csid0", 1106 "csid1", 1107 "ispif", 1108 "csi_clk_mux", 1109 "vfe0"; 1110 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1111 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1112 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1113 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1114 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1115 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1116 interrupt-names = "csiphy0", 1117 "csiphy1", 1118 "csid0", 1119 "csid1", 1120 "ispif", 1121 "vfe0"; 1122 power-domains = <&gcc VFE_GDSC>; 1123 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1124 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1125 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1126 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1127 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1128 <&gcc GCC_CAMSS_CSI0_CLK>, 1129 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1130 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1131 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1132 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1133 <&gcc GCC_CAMSS_CSI1_CLK>, 1134 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1135 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1136 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1137 <&gcc GCC_CAMSS_AHB_CLK>, 1138 <&gcc GCC_CAMSS_VFE0_CLK>, 1139 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1140 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1141 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1142 clock-names = "top_ahb", 1143 "ispif_ahb", 1144 "csiphy0_timer", 1145 "csiphy1_timer", 1146 "csi0_ahb", 1147 "csi0", 1148 "csi0_phy", 1149 "csi0_pix", 1150 "csi0_rdi", 1151 "csi1_ahb", 1152 "csi1", 1153 "csi1_phy", 1154 "csi1_pix", 1155 "csi1_rdi", 1156 "ahb", 1157 "vfe0", 1158 "csi_vfe0", 1159 "vfe_ahb", 1160 "vfe_axi"; 1161 iommus = <&apps_iommu 3>; 1162 status = "disabled"; 1163 ports { 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 }; 1167 }; 1168 1169 cci: cci@1b0c000 { 1170 compatible = "qcom,msm8916-cci"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 reg = <0x01b0c000 0x1000>; 1174 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1175 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1176 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1177 <&gcc GCC_CAMSS_CCI_CLK>, 1178 <&gcc GCC_CAMSS_AHB_CLK>; 1179 clock-names = "camss_top_ahb", "cci_ahb", 1180 "cci", "camss_ahb"; 1181 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1182 <&gcc GCC_CAMSS_CCI_CLK>; 1183 assigned-clock-rates = <80000000>, <19200000>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&cci0_default>; 1186 status = "disabled"; 1187 1188 cci_i2c0: i2c-bus@0 { 1189 reg = <0>; 1190 clock-frequency = <400000>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 }; 1194 }; 1195 1196 gpu@1c00000 { 1197 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1198 reg = <0x01c00000 0x20000>; 1199 reg-names = "kgsl_3d0_reg_memory"; 1200 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "kgsl_3d0_irq"; 1202 clock-names = 1203 "core", 1204 "iface", 1205 "mem", 1206 "mem_iface", 1207 "alt_mem_iface", 1208 "gfx3d"; 1209 clocks = 1210 <&gcc GCC_OXILI_GFX3D_CLK>, 1211 <&gcc GCC_OXILI_AHB_CLK>, 1212 <&gcc GCC_OXILI_GMEM_CLK>, 1213 <&gcc GCC_BIMC_GFX_CLK>, 1214 <&gcc GCC_BIMC_GPU_CLK>, 1215 <&gcc GFX3D_CLK_SRC>; 1216 power-domains = <&gcc OXILI_GDSC>; 1217 operating-points-v2 = <&gpu_opp_table>; 1218 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1219 1220 gpu_opp_table: opp-table { 1221 compatible = "operating-points-v2"; 1222 1223 opp-400000000 { 1224 opp-hz = /bits/ 64 <400000000>; 1225 }; 1226 opp-19200000 { 1227 opp-hz = /bits/ 64 <19200000>; 1228 }; 1229 }; 1230 }; 1231 1232 venus: video-codec@1d00000 { 1233 compatible = "qcom,msm8916-venus"; 1234 reg = <0x01d00000 0xff000>; 1235 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&gcc VENUS_GDSC>; 1237 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1238 <&gcc GCC_VENUS0_AHB_CLK>, 1239 <&gcc GCC_VENUS0_AXI_CLK>; 1240 clock-names = "core", "iface", "bus"; 1241 iommus = <&apps_iommu 5>; 1242 memory-region = <&venus_mem>; 1243 status = "okay"; 1244 1245 video-decoder { 1246 compatible = "venus-decoder"; 1247 }; 1248 1249 video-encoder { 1250 compatible = "venus-encoder"; 1251 }; 1252 }; 1253 1254 apps_iommu: iommu@1ef0000 { 1255 #address-cells = <1>; 1256 #size-cells = <1>; 1257 #iommu-cells = <1>; 1258 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1259 ranges = <0 0x01e20000 0x40000>; 1260 reg = <0x01ef0000 0x3000>; 1261 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1262 <&gcc GCC_APSS_TCU_CLK>; 1263 clock-names = "iface", "bus"; 1264 qcom,iommu-secure-id = <17>; 1265 1266 /* VFE */ 1267 iommu-ctx@3000 { 1268 compatible = "qcom,msm-iommu-v1-sec"; 1269 reg = <0x3000 0x1000>; 1270 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1271 }; 1272 1273 /* MDP_0 */ 1274 iommu-ctx@4000 { 1275 compatible = "qcom,msm-iommu-v1-ns"; 1276 reg = <0x4000 0x1000>; 1277 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1278 }; 1279 1280 /* VENUS_NS */ 1281 iommu-ctx@5000 { 1282 compatible = "qcom,msm-iommu-v1-sec"; 1283 reg = <0x5000 0x1000>; 1284 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1285 }; 1286 }; 1287 1288 gpu_iommu: iommu@1f08000 { 1289 #address-cells = <1>; 1290 #size-cells = <1>; 1291 #iommu-cells = <1>; 1292 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1293 ranges = <0 0x01f08000 0x10000>; 1294 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1295 <&gcc GCC_GFX_TCU_CLK>; 1296 clock-names = "iface", "bus"; 1297 qcom,iommu-secure-id = <18>; 1298 1299 /* GFX3D_USER */ 1300 iommu-ctx@1000 { 1301 compatible = "qcom,msm-iommu-v1-ns"; 1302 reg = <0x1000 0x1000>; 1303 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1304 }; 1305 1306 /* GFX3D_PRIV */ 1307 iommu-ctx@2000 { 1308 compatible = "qcom,msm-iommu-v1-ns"; 1309 reg = <0x2000 0x1000>; 1310 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1311 }; 1312 }; 1313 1314 spmi_bus: spmi@200f000 { 1315 compatible = "qcom,spmi-pmic-arb"; 1316 reg = <0x0200f000 0x001000>, 1317 <0x02400000 0x400000>, 1318 <0x02c00000 0x400000>, 1319 <0x03800000 0x200000>, 1320 <0x0200a000 0x002100>; 1321 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1322 interrupt-names = "periph_irq"; 1323 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1324 qcom,ee = <0>; 1325 qcom,channel = <0>; 1326 #address-cells = <2>; 1327 #size-cells = <0>; 1328 interrupt-controller; 1329 #interrupt-cells = <4>; 1330 }; 1331 1332 bam_dmux_dma: dma-controller@4044000 { 1333 compatible = "qcom,bam-v1.7.0"; 1334 reg = <0x04044000 0x19000>; 1335 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1336 #dma-cells = <1>; 1337 qcom,ee = <0>; 1338 1339 num-channels = <6>; 1340 qcom,num-ees = <1>; 1341 qcom,powered-remotely; 1342 1343 status = "disabled"; 1344 }; 1345 1346 mpss: remoteproc@4080000 { 1347 compatible = "qcom,msm8916-mss-pil"; 1348 reg = <0x04080000 0x100>, 1349 <0x04020000 0x040>; 1350 1351 reg-names = "qdsp6", "rmb"; 1352 1353 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1354 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1355 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1356 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1357 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1358 interrupt-names = "wdog", "fatal", "ready", 1359 "handover", "stop-ack"; 1360 1361 power-domains = <&rpmpd MSM8916_VDDCX>, 1362 <&rpmpd MSM8916_VDDMX>; 1363 power-domain-names = "cx", "mx"; 1364 1365 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1366 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1367 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1368 <&xo_board>; 1369 clock-names = "iface", "bus", "mem", "xo"; 1370 1371 qcom,smem-states = <&hexagon_smp2p_out 0>; 1372 qcom,smem-state-names = "stop"; 1373 1374 resets = <&scm 0>; 1375 reset-names = "mss_restart"; 1376 1377 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1378 1379 status = "disabled"; 1380 1381 mba { 1382 memory-region = <&mba_mem>; 1383 }; 1384 1385 mpss { 1386 memory-region = <&mpss_mem>; 1387 }; 1388 1389 bam_dmux: bam-dmux { 1390 compatible = "qcom,bam-dmux"; 1391 1392 interrupt-parent = <&hexagon_smsm>; 1393 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1394 interrupt-names = "pc", "pc-ack"; 1395 1396 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1397 qcom,smem-state-names = "pc", "pc-ack"; 1398 1399 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1400 dma-names = "tx", "rx"; 1401 1402 status = "disabled"; 1403 }; 1404 1405 smd-edge { 1406 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1407 1408 qcom,smd-edge = <0>; 1409 qcom,ipc = <&apcs 8 12>; 1410 qcom,remote-pid = <1>; 1411 1412 label = "hexagon"; 1413 1414 fastrpc { 1415 compatible = "qcom,fastrpc"; 1416 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1417 label = "adsp"; 1418 qcom,non-secure-domain; 1419 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 1423 cb@1 { 1424 compatible = "qcom,fastrpc-compute-cb"; 1425 reg = <1>; 1426 }; 1427 }; 1428 }; 1429 }; 1430 1431 sound: sound@7702000 { 1432 status = "disabled"; 1433 compatible = "qcom,apq8016-sbc-sndcard"; 1434 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1435 reg-names = "mic-iomux", "spkr-iomux"; 1436 }; 1437 1438 lpass: audio-controller@7708000 { 1439 status = "disabled"; 1440 compatible = "qcom,apq8016-lpass-cpu"; 1441 1442 /* 1443 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1444 * is actually only used by Tertiary MI2S while 1445 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1446 */ 1447 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1448 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1449 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 1450 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1451 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1452 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1453 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 1454 1455 clock-names = "ahbix-clk", 1456 "pcnoc-mport-clk", 1457 "pcnoc-sway-clk", 1458 "mi2s-bit-clk0", 1459 "mi2s-bit-clk1", 1460 "mi2s-bit-clk2", 1461 "mi2s-bit-clk3"; 1462 #sound-dai-cells = <1>; 1463 1464 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1465 interrupt-names = "lpass-irq-lpaif"; 1466 reg = <0x07708000 0x10000>; 1467 reg-names = "lpass-lpaif"; 1468 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 }; 1472 1473 lpass_codec: audio-codec@771c000 { 1474 compatible = "qcom,msm8916-wcd-digital-codec"; 1475 reg = <0x0771c000 0x400>; 1476 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1477 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1478 clock-names = "ahbix-clk", "mclk"; 1479 #sound-dai-cells = <1>; 1480 }; 1481 1482 sdhc_1: mmc@7824000 { 1483 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1484 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1485 reg-names = "hc", "core"; 1486 1487 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1489 interrupt-names = "hc_irq", "pwr_irq"; 1490 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1491 <&gcc GCC_SDCC1_APPS_CLK>, 1492 <&xo_board>; 1493 clock-names = "iface", "core", "xo"; 1494 mmc-ddr-1_8v; 1495 bus-width = <8>; 1496 non-removable; 1497 status = "disabled"; 1498 }; 1499 1500 sdhc_2: mmc@7864000 { 1501 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1502 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1503 reg-names = "hc", "core"; 1504 1505 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1507 interrupt-names = "hc_irq", "pwr_irq"; 1508 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1509 <&gcc GCC_SDCC2_APPS_CLK>, 1510 <&xo_board>; 1511 clock-names = "iface", "core", "xo"; 1512 bus-width = <4>; 1513 status = "disabled"; 1514 }; 1515 1516 blsp_dma: dma-controller@7884000 { 1517 compatible = "qcom,bam-v1.7.0"; 1518 reg = <0x07884000 0x23000>; 1519 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1521 clock-names = "bam_clk"; 1522 #dma-cells = <1>; 1523 qcom,ee = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 blsp1_uart1: serial@78af000 { 1528 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1529 reg = <0x078af000 0x200>; 1530 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1532 clock-names = "core", "iface"; 1533 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1534 dma-names = "tx", "rx"; 1535 pinctrl-names = "default", "sleep"; 1536 pinctrl-0 = <&blsp1_uart1_default>; 1537 pinctrl-1 = <&blsp1_uart1_sleep>; 1538 status = "disabled"; 1539 }; 1540 1541 blsp1_uart2: serial@78b0000 { 1542 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1543 reg = <0x078b0000 0x200>; 1544 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1545 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1546 clock-names = "core", "iface"; 1547 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1548 dma-names = "tx", "rx"; 1549 pinctrl-names = "default", "sleep"; 1550 pinctrl-0 = <&blsp1_uart2_default>; 1551 pinctrl-1 = <&blsp1_uart2_sleep>; 1552 status = "disabled"; 1553 }; 1554 1555 blsp_i2c1: i2c@78b5000 { 1556 compatible = "qcom,i2c-qup-v2.2.1"; 1557 reg = <0x078b5000 0x500>; 1558 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1560 <&gcc GCC_BLSP1_AHB_CLK>; 1561 clock-names = "core", "iface"; 1562 pinctrl-names = "default", "sleep"; 1563 pinctrl-0 = <&i2c1_default>; 1564 pinctrl-1 = <&i2c1_sleep>; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 status = "disabled"; 1568 }; 1569 1570 blsp_spi1: spi@78b5000 { 1571 compatible = "qcom,spi-qup-v2.2.1"; 1572 reg = <0x078b5000 0x500>; 1573 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1574 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1575 <&gcc GCC_BLSP1_AHB_CLK>; 1576 clock-names = "core", "iface"; 1577 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1578 dma-names = "tx", "rx"; 1579 pinctrl-names = "default", "sleep"; 1580 pinctrl-0 = <&spi1_default>; 1581 pinctrl-1 = <&spi1_sleep>; 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 blsp_i2c2: i2c@78b6000 { 1588 compatible = "qcom,i2c-qup-v2.2.1"; 1589 reg = <0x078b6000 0x500>; 1590 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1592 <&gcc GCC_BLSP1_AHB_CLK>; 1593 clock-names = "core", "iface"; 1594 pinctrl-names = "default", "sleep"; 1595 pinctrl-0 = <&i2c2_default>; 1596 pinctrl-1 = <&i2c2_sleep>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 status = "disabled"; 1600 }; 1601 1602 blsp_spi2: spi@78b6000 { 1603 compatible = "qcom,spi-qup-v2.2.1"; 1604 reg = <0x078b6000 0x500>; 1605 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1607 <&gcc GCC_BLSP1_AHB_CLK>; 1608 clock-names = "core", "iface"; 1609 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1610 dma-names = "tx", "rx"; 1611 pinctrl-names = "default", "sleep"; 1612 pinctrl-0 = <&spi2_default>; 1613 pinctrl-1 = <&spi2_sleep>; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 blsp_i2c3: i2c@78b7000 { 1620 compatible = "qcom,i2c-qup-v2.2.1"; 1621 reg = <0x078b7000 0x500>; 1622 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1624 <&gcc GCC_BLSP1_AHB_CLK>; 1625 clock-names = "core", "iface"; 1626 pinctrl-names = "default", "sleep"; 1627 pinctrl-0 = <&i2c3_default>; 1628 pinctrl-1 = <&i2c3_sleep>; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 status = "disabled"; 1632 }; 1633 1634 blsp_spi3: spi@78b7000 { 1635 compatible = "qcom,spi-qup-v2.2.1"; 1636 reg = <0x078b7000 0x500>; 1637 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1639 <&gcc GCC_BLSP1_AHB_CLK>; 1640 clock-names = "core", "iface"; 1641 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1642 dma-names = "tx", "rx"; 1643 pinctrl-names = "default", "sleep"; 1644 pinctrl-0 = <&spi3_default>; 1645 pinctrl-1 = <&spi3_sleep>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 }; 1650 1651 blsp_i2c4: i2c@78b8000 { 1652 compatible = "qcom,i2c-qup-v2.2.1"; 1653 reg = <0x078b8000 0x500>; 1654 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1655 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1656 <&gcc GCC_BLSP1_AHB_CLK>; 1657 clock-names = "core", "iface"; 1658 pinctrl-names = "default", "sleep"; 1659 pinctrl-0 = <&i2c4_default>; 1660 pinctrl-1 = <&i2c4_sleep>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 blsp_spi4: spi@78b8000 { 1667 compatible = "qcom,spi-qup-v2.2.1"; 1668 reg = <0x078b8000 0x500>; 1669 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1671 <&gcc GCC_BLSP1_AHB_CLK>; 1672 clock-names = "core", "iface"; 1673 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1674 dma-names = "tx", "rx"; 1675 pinctrl-names = "default", "sleep"; 1676 pinctrl-0 = <&spi4_default>; 1677 pinctrl-1 = <&spi4_sleep>; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 status = "disabled"; 1681 }; 1682 1683 blsp_i2c5: i2c@78b9000 { 1684 compatible = "qcom,i2c-qup-v2.2.1"; 1685 reg = <0x078b9000 0x500>; 1686 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1687 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1688 <&gcc GCC_BLSP1_AHB_CLK>; 1689 clock-names = "core", "iface"; 1690 pinctrl-names = "default", "sleep"; 1691 pinctrl-0 = <&i2c5_default>; 1692 pinctrl-1 = <&i2c5_sleep>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 }; 1697 1698 blsp_spi5: spi@78b9000 { 1699 compatible = "qcom,spi-qup-v2.2.1"; 1700 reg = <0x078b9000 0x500>; 1701 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1703 <&gcc GCC_BLSP1_AHB_CLK>; 1704 clock-names = "core", "iface"; 1705 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1706 dma-names = "tx", "rx"; 1707 pinctrl-names = "default", "sleep"; 1708 pinctrl-0 = <&spi5_default>; 1709 pinctrl-1 = <&spi5_sleep>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 blsp_i2c6: i2c@78ba000 { 1716 compatible = "qcom,i2c-qup-v2.2.1"; 1717 reg = <0x078ba000 0x500>; 1718 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1719 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1720 <&gcc GCC_BLSP1_AHB_CLK>; 1721 clock-names = "core", "iface"; 1722 pinctrl-names = "default", "sleep"; 1723 pinctrl-0 = <&i2c6_default>; 1724 pinctrl-1 = <&i2c6_sleep>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 blsp_spi6: spi@78ba000 { 1731 compatible = "qcom,spi-qup-v2.2.1"; 1732 reg = <0x078ba000 0x500>; 1733 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1735 <&gcc GCC_BLSP1_AHB_CLK>; 1736 clock-names = "core", "iface"; 1737 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1738 dma-names = "tx", "rx"; 1739 pinctrl-names = "default", "sleep"; 1740 pinctrl-0 = <&spi6_default>; 1741 pinctrl-1 = <&spi6_sleep>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 status = "disabled"; 1745 }; 1746 1747 usb: usb@78d9000 { 1748 compatible = "qcom,ci-hdrc"; 1749 reg = <0x078d9000 0x200>, 1750 <0x078d9200 0x200>; 1751 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1753 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1754 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1755 clock-names = "iface", "core"; 1756 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1757 assigned-clock-rates = <80000000>; 1758 resets = <&gcc GCC_USB_HS_BCR>; 1759 reset-names = "core"; 1760 phy_type = "ulpi"; 1761 dr_mode = "otg"; 1762 hnp-disable; 1763 srp-disable; 1764 adp-disable; 1765 ahb-burst-config = <0>; 1766 phy-names = "usb-phy"; 1767 phys = <&usb_hs_phy>; 1768 status = "disabled"; 1769 #reset-cells = <1>; 1770 1771 ulpi { 1772 usb_hs_phy: phy { 1773 compatible = "qcom,usb-hs-phy-msm8916", 1774 "qcom,usb-hs-phy"; 1775 #phy-cells = <0>; 1776 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1777 clock-names = "ref", "sleep"; 1778 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1779 reset-names = "phy", "por"; 1780 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1781 <0x1 0x6b>, 1782 <0x2 0x24>, 1783 <0x3 0x13>; 1784 }; 1785 }; 1786 }; 1787 1788 pronto: remoteproc@a21b000 { 1789 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1790 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1791 reg-names = "ccu", "dxe", "pmu"; 1792 1793 memory-region = <&wcnss_mem>; 1794 1795 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1796 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1797 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1798 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1799 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1800 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1801 1802 power-domains = <&rpmpd MSM8916_VDDCX>, 1803 <&rpmpd MSM8916_VDDMX>; 1804 power-domain-names = "cx", "mx"; 1805 1806 qcom,smem-states = <&wcnss_smp2p_out 0>; 1807 qcom,smem-state-names = "stop"; 1808 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&wcnss_pin_a>; 1811 1812 status = "disabled"; 1813 1814 iris { 1815 compatible = "qcom,wcn3620"; 1816 1817 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1818 clock-names = "xo"; 1819 }; 1820 1821 smd-edge { 1822 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1823 1824 qcom,ipc = <&apcs 8 17>; 1825 qcom,smd-edge = <6>; 1826 qcom,remote-pid = <4>; 1827 1828 label = "pronto"; 1829 1830 wcnss_ctrl: wcnss { 1831 compatible = "qcom,wcnss"; 1832 qcom,smd-channels = "WCNSS_CTRL"; 1833 1834 qcom,mmio = <&pronto>; 1835 1836 bluetooth { 1837 compatible = "qcom,wcnss-bt"; 1838 }; 1839 1840 wifi { 1841 compatible = "qcom,wcnss-wlan"; 1842 1843 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1845 interrupt-names = "tx", "rx"; 1846 1847 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1848 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1849 }; 1850 }; 1851 }; 1852 }; 1853 1854 intc: interrupt-controller@b000000 { 1855 compatible = "qcom,msm-qgic2"; 1856 interrupt-controller; 1857 #interrupt-cells = <3>; 1858 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 1859 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 1860 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1861 }; 1862 1863 apcs: mailbox@b011000 { 1864 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 1865 reg = <0x0b011000 0x1000>; 1866 #mbox-cells = <1>; 1867 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 1868 clock-names = "pll", "aux"; 1869 #clock-cells = <0>; 1870 }; 1871 1872 a53pll: clock@b016000 { 1873 compatible = "qcom,msm8916-a53pll"; 1874 reg = <0x0b016000 0x40>; 1875 #clock-cells = <0>; 1876 clocks = <&xo_board>; 1877 clock-names = "xo"; 1878 }; 1879 1880 timer@b020000 { 1881 #address-cells = <1>; 1882 #size-cells = <1>; 1883 ranges; 1884 compatible = "arm,armv7-timer-mem"; 1885 reg = <0x0b020000 0x1000>; 1886 clock-frequency = <19200000>; 1887 1888 frame@b021000 { 1889 frame-number = <0>; 1890 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1892 reg = <0x0b021000 0x1000>, 1893 <0x0b022000 0x1000>; 1894 }; 1895 1896 frame@b023000 { 1897 frame-number = <1>; 1898 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1899 reg = <0x0b023000 0x1000>; 1900 status = "disabled"; 1901 }; 1902 1903 frame@b024000 { 1904 frame-number = <2>; 1905 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1906 reg = <0x0b024000 0x1000>; 1907 status = "disabled"; 1908 }; 1909 1910 frame@b025000 { 1911 frame-number = <3>; 1912 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1913 reg = <0x0b025000 0x1000>; 1914 status = "disabled"; 1915 }; 1916 1917 frame@b026000 { 1918 frame-number = <4>; 1919 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1920 reg = <0x0b026000 0x1000>; 1921 status = "disabled"; 1922 }; 1923 1924 frame@b027000 { 1925 frame-number = <5>; 1926 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1927 reg = <0x0b027000 0x1000>; 1928 status = "disabled"; 1929 }; 1930 1931 frame@b028000 { 1932 frame-number = <6>; 1933 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1934 reg = <0x0b028000 0x1000>; 1935 status = "disabled"; 1936 }; 1937 }; 1938 1939 cpu0_acc: power-manager@b088000 { 1940 compatible = "qcom,msm8916-acc"; 1941 reg = <0x0b088000 0x1000>; 1942 status = "reserved"; /* Controlled by PSCI firmware */ 1943 }; 1944 1945 cpu0_saw: power-manager@b089000 { 1946 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1947 reg = <0x0b089000 0x1000>; 1948 status = "reserved"; /* Controlled by PSCI firmware */ 1949 }; 1950 1951 cpu1_acc: power-manager@b098000 { 1952 compatible = "qcom,msm8916-acc"; 1953 reg = <0x0b098000 0x1000>; 1954 status = "reserved"; /* Controlled by PSCI firmware */ 1955 }; 1956 1957 cpu1_saw: power-manager@b099000 { 1958 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1959 reg = <0x0b099000 0x1000>; 1960 status = "reserved"; /* Controlled by PSCI firmware */ 1961 }; 1962 1963 cpu2_acc: power-manager@b0a8000 { 1964 compatible = "qcom,msm8916-acc"; 1965 reg = <0x0b0a8000 0x1000>; 1966 status = "reserved"; /* Controlled by PSCI firmware */ 1967 }; 1968 1969 cpu2_saw: power-manager@b0a9000 { 1970 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1971 reg = <0x0b0a9000 0x1000>; 1972 status = "reserved"; /* Controlled by PSCI firmware */ 1973 }; 1974 1975 cpu3_acc: power-manager@b0b8000 { 1976 compatible = "qcom,msm8916-acc"; 1977 reg = <0x0b0b8000 0x1000>; 1978 status = "reserved"; /* Controlled by PSCI firmware */ 1979 }; 1980 1981 cpu3_saw: power-manager@b0b9000 { 1982 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1983 reg = <0x0b0b9000 0x1000>; 1984 status = "reserved"; /* Controlled by PSCI firmware */ 1985 }; 1986 }; 1987 1988 thermal-zones { 1989 cpu0-1-thermal { 1990 polling-delay-passive = <250>; 1991 polling-delay = <1000>; 1992 1993 thermal-sensors = <&tsens 5>; 1994 1995 trips { 1996 cpu0_1_alert0: trip-point0 { 1997 temperature = <75000>; 1998 hysteresis = <2000>; 1999 type = "passive"; 2000 }; 2001 cpu0_1_crit: cpu_crit { 2002 temperature = <110000>; 2003 hysteresis = <2000>; 2004 type = "critical"; 2005 }; 2006 }; 2007 2008 cooling-maps { 2009 map0 { 2010 trip = <&cpu0_1_alert0>; 2011 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2012 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2013 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2014 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2015 }; 2016 }; 2017 }; 2018 2019 cpu2-3-thermal { 2020 polling-delay-passive = <250>; 2021 polling-delay = <1000>; 2022 2023 thermal-sensors = <&tsens 4>; 2024 2025 trips { 2026 cpu2_3_alert0: trip-point0 { 2027 temperature = <75000>; 2028 hysteresis = <2000>; 2029 type = "passive"; 2030 }; 2031 cpu2_3_crit: cpu_crit { 2032 temperature = <110000>; 2033 hysteresis = <2000>; 2034 type = "critical"; 2035 }; 2036 }; 2037 2038 cooling-maps { 2039 map0 { 2040 trip = <&cpu2_3_alert0>; 2041 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2042 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2043 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2044 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2045 }; 2046 }; 2047 }; 2048 2049 gpu-thermal { 2050 polling-delay-passive = <250>; 2051 polling-delay = <1000>; 2052 2053 thermal-sensors = <&tsens 2>; 2054 2055 trips { 2056 gpu_alert0: trip-point0 { 2057 temperature = <75000>; 2058 hysteresis = <2000>; 2059 type = "passive"; 2060 }; 2061 gpu_crit: gpu_crit { 2062 temperature = <95000>; 2063 hysteresis = <2000>; 2064 type = "critical"; 2065 }; 2066 }; 2067 }; 2068 2069 camera-thermal { 2070 polling-delay-passive = <250>; 2071 polling-delay = <1000>; 2072 2073 thermal-sensors = <&tsens 1>; 2074 2075 trips { 2076 cam_alert0: trip-point0 { 2077 temperature = <75000>; 2078 hysteresis = <2000>; 2079 type = "hot"; 2080 }; 2081 }; 2082 }; 2083 2084 modem-thermal { 2085 polling-delay-passive = <250>; 2086 polling-delay = <1000>; 2087 2088 thermal-sensors = <&tsens 0>; 2089 2090 trips { 2091 modem_alert0: trip-point0 { 2092 temperature = <85000>; 2093 hysteresis = <2000>; 2094 type = "hot"; 2095 }; 2096 }; 2097 }; 2098 2099 }; 2100 2101 timer { 2102 compatible = "arm,armv8-timer"; 2103 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2104 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2105 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2106 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2107 }; 2108}; 2109 2110#include "msm8916-pins.dtsi" 2111