1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sdhc_1; /* SDC1 eMMC slot */ 23 mmc1 = &sdhc_2; /* SDC2 SD card slot */ 24 }; 25 26 chosen { }; 27 28 memory@80000000 { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0x80000000 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 tz-apps@86000000 { 40 reg = <0x0 0x86000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 smem@86300000 { 45 compatible = "qcom,smem"; 46 reg = <0x0 0x86300000 0x0 0x100000>; 47 no-map; 48 49 hwlocks = <&tcsr_mutex 3>; 50 qcom,rpm-msg-ram = <&rpm_msg_ram>; 51 }; 52 53 hypervisor@86400000 { 54 reg = <0x0 0x86400000 0x0 0x100000>; 55 no-map; 56 }; 57 58 tz@86500000 { 59 reg = <0x0 0x86500000 0x0 0x180000>; 60 no-map; 61 }; 62 63 reserved@86680000 { 64 reg = <0x0 0x86680000 0x0 0x80000>; 65 no-map; 66 }; 67 68 rmtfs@86700000 { 69 compatible = "qcom,rmtfs-mem"; 70 reg = <0x0 0x86700000 0x0 0xe0000>; 71 no-map; 72 73 qcom,client-id = <1>; 74 }; 75 76 rfsa@867e0000 { 77 reg = <0x0 0x867e0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 mpss_mem: mpss@86800000 { 82 reg = <0x0 0x86800000 0x0 0x2b00000>; 83 no-map; 84 }; 85 86 wcnss_mem: wcnss@89300000 { 87 reg = <0x0 0x89300000 0x0 0x600000>; 88 no-map; 89 }; 90 91 venus_mem: venus@89900000 { 92 reg = <0x0 0x89900000 0x0 0x600000>; 93 no-map; 94 }; 95 96 mba_mem: mba@8ea00000 { 97 no-map; 98 reg = <0 0x8ea00000 0 0x100000>; 99 }; 100 }; 101 102 clocks { 103 xo_board: xo-board { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <19200000>; 107 }; 108 109 sleep_clk: sleep-clk { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <32768>; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 CPU0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x0>; 124 next-level-cache = <&L2_0>; 125 enable-method = "psci"; 126 clocks = <&apcs>; 127 operating-points-v2 = <&cpu_opp_table>; 128 #cooling-cells = <2>; 129 power-domains = <&CPU_PD0>; 130 power-domain-names = "psci"; 131 qcom,acc = <&cpu0_acc>; 132 qcom,saw = <&cpu0_saw>; 133 }; 134 135 CPU1: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x1>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 clocks = <&apcs>; 142 operating-points-v2 = <&cpu_opp_table>; 143 #cooling-cells = <2>; 144 power-domains = <&CPU_PD1>; 145 power-domain-names = "psci"; 146 qcom,acc = <&cpu1_acc>; 147 qcom,saw = <&cpu1_saw>; 148 }; 149 150 CPU2: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x2>; 154 next-level-cache = <&L2_0>; 155 enable-method = "psci"; 156 clocks = <&apcs>; 157 operating-points-v2 = <&cpu_opp_table>; 158 #cooling-cells = <2>; 159 power-domains = <&CPU_PD2>; 160 power-domain-names = "psci"; 161 qcom,acc = <&cpu2_acc>; 162 qcom,saw = <&cpu2_saw>; 163 }; 164 165 CPU3: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x3>; 169 next-level-cache = <&L2_0>; 170 enable-method = "psci"; 171 clocks = <&apcs>; 172 operating-points-v2 = <&cpu_opp_table>; 173 #cooling-cells = <2>; 174 power-domains = <&CPU_PD3>; 175 power-domain-names = "psci"; 176 qcom,acc = <&cpu3_acc>; 177 qcom,saw = <&cpu3_saw>; 178 }; 179 180 L2_0: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 }; 184 185 idle-states { 186 entry-method = "psci"; 187 188 CPU_SLEEP_0: cpu-sleep-0 { 189 compatible = "arm,idle-state"; 190 idle-state-name = "standalone-power-collapse"; 191 arm,psci-suspend-param = <0x40000002>; 192 entry-latency-us = <130>; 193 exit-latency-us = <150>; 194 min-residency-us = <2000>; 195 local-timer-stop; 196 }; 197 }; 198 199 domain-idle-states { 200 201 CLUSTER_RET: cluster-retention { 202 compatible = "domain-idle-state"; 203 arm,psci-suspend-param = <0x41000012>; 204 entry-latency-us = <500>; 205 exit-latency-us = <500>; 206 min-residency-us = <2000>; 207 }; 208 209 CLUSTER_PWRDN: cluster-gdhs { 210 compatible = "domain-idle-state"; 211 arm,psci-suspend-param = <0x41000032>; 212 entry-latency-us = <2000>; 213 exit-latency-us = <2000>; 214 min-residency-us = <6000>; 215 }; 216 }; 217 }; 218 219 cpu_opp_table: opp-table-cpu { 220 compatible = "operating-points-v2"; 221 opp-shared; 222 223 opp-200000000 { 224 opp-hz = /bits/ 64 <200000000>; 225 }; 226 opp-400000000 { 227 opp-hz = /bits/ 64 <400000000>; 228 }; 229 opp-800000000 { 230 opp-hz = /bits/ 64 <800000000>; 231 }; 232 opp-998400000 { 233 opp-hz = /bits/ 64 <998400000>; 234 }; 235 }; 236 237 firmware { 238 scm: scm { 239 compatible = "qcom,scm-msm8916", "qcom,scm"; 240 clocks = <&gcc GCC_CRYPTO_CLK>, 241 <&gcc GCC_CRYPTO_AXI_CLK>, 242 <&gcc GCC_CRYPTO_AHB_CLK>; 243 clock-names = "core", "bus", "iface"; 244 #reset-cells = <1>; 245 246 qcom,dload-mode = <&tcsr 0x6100>; 247 }; 248 }; 249 250 pmu { 251 compatible = "arm,cortex-a53-pmu"; 252 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 253 }; 254 255 psci { 256 compatible = "arm,psci-1.0"; 257 method = "smc"; 258 259 CPU_PD0: power-domain-cpu0 { 260 #power-domain-cells = <0>; 261 power-domains = <&CLUSTER_PD>; 262 domain-idle-states = <&CPU_SLEEP_0>; 263 }; 264 265 CPU_PD1: power-domain-cpu1 { 266 #power-domain-cells = <0>; 267 power-domains = <&CLUSTER_PD>; 268 domain-idle-states = <&CPU_SLEEP_0>; 269 }; 270 271 CPU_PD2: power-domain-cpu2 { 272 #power-domain-cells = <0>; 273 power-domains = <&CLUSTER_PD>; 274 domain-idle-states = <&CPU_SLEEP_0>; 275 }; 276 277 CPU_PD3: power-domain-cpu3 { 278 #power-domain-cells = <0>; 279 power-domains = <&CLUSTER_PD>; 280 domain-idle-states = <&CPU_SLEEP_0>; 281 }; 282 283 CLUSTER_PD: power-domain-cluster { 284 #power-domain-cells = <0>; 285 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 286 }; 287 }; 288 289 smd { 290 compatible = "qcom,smd"; 291 292 rpm { 293 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 294 qcom,ipc = <&apcs 8 0>; 295 qcom,smd-edge = <15>; 296 297 rpm_requests: rpm-requests { 298 compatible = "qcom,rpm-msm8916"; 299 qcom,smd-channels = "rpm_requests"; 300 301 rpmcc: clock-controller { 302 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 303 #clock-cells = <1>; 304 clocks = <&xo_board>; 305 clock-names = "xo"; 306 }; 307 308 rpmpd: power-controller { 309 compatible = "qcom,msm8916-rpmpd"; 310 #power-domain-cells = <1>; 311 operating-points-v2 = <&rpmpd_opp_table>; 312 313 rpmpd_opp_table: opp-table { 314 compatible = "operating-points-v2"; 315 316 rpmpd_opp_ret: opp1 { 317 opp-level = <1>; 318 }; 319 rpmpd_opp_svs_krait: opp2 { 320 opp-level = <2>; 321 }; 322 rpmpd_opp_svs_soc: opp3 { 323 opp-level = <3>; 324 }; 325 rpmpd_opp_nom: opp4 { 326 opp-level = <4>; 327 }; 328 rpmpd_opp_turbo: opp5 { 329 opp-level = <5>; 330 }; 331 rpmpd_opp_super_turbo: opp6 { 332 opp-level = <6>; 333 }; 334 }; 335 }; 336 }; 337 }; 338 }; 339 340 smp2p-hexagon { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <435>, <428>; 343 344 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 345 346 qcom,ipc = <&apcs 8 14>; 347 348 qcom,local-pid = <0>; 349 qcom,remote-pid = <1>; 350 351 hexagon_smp2p_out: master-kernel { 352 qcom,entry-name = "master-kernel"; 353 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 hexagon_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 }; 363 }; 364 365 smp2p-wcnss { 366 compatible = "qcom,smp2p"; 367 qcom,smem = <451>, <431>; 368 369 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 370 371 qcom,ipc = <&apcs 8 18>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <4>; 375 376 wcnss_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 379 #qcom,smem-state-cells = <1>; 380 }; 381 382 wcnss_smp2p_in: slave-kernel { 383 qcom,entry-name = "slave-kernel"; 384 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 }; 388 }; 389 390 smsm { 391 compatible = "qcom,smsm"; 392 393 #address-cells = <1>; 394 #size-cells = <0>; 395 396 qcom,ipc-1 = <&apcs 8 13>; 397 qcom,ipc-3 = <&apcs 8 19>; 398 399 apps_smsm: apps@0 { 400 reg = <0>; 401 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 hexagon_smsm: hexagon@1 { 406 reg = <1>; 407 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 408 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 }; 412 413 wcnss_smsm: wcnss@6 { 414 reg = <6>; 415 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 416 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 }; 421 422 soc: soc@0 { 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0 0 0 0xffffffff>; 426 compatible = "simple-bus"; 427 428 rng@22000 { 429 compatible = "qcom,prng"; 430 reg = <0x00022000 0x200>; 431 clocks = <&gcc GCC_PRNG_AHB_CLK>; 432 clock-names = "core"; 433 }; 434 435 restart@4ab000 { 436 compatible = "qcom,pshold"; 437 reg = <0x004ab000 0x4>; 438 }; 439 440 qfprom: qfprom@5c000 { 441 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 442 reg = <0x0005c000 0x1000>; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 446 tsens_base1: base1@d0 { 447 reg = <0xd0 0x1>; 448 bits = <0 7>; 449 }; 450 451 tsens_s0_p1: s0-p1@d0 { 452 reg = <0xd0 0x2>; 453 bits = <7 5>; 454 }; 455 456 tsens_s0_p2: s0-p2@d1 { 457 reg = <0xd1 0x2>; 458 bits = <4 5>; 459 }; 460 461 tsens_s1_p1: s1-p1@d2 { 462 reg = <0xd2 0x1>; 463 bits = <1 5>; 464 }; 465 tsens_s1_p2: s1-p2@d2 { 466 reg = <0xd2 0x2>; 467 bits = <6 5>; 468 }; 469 tsens_s2_p1: s2-p1@d3 { 470 reg = <0xd3 0x1>; 471 bits = <3 5>; 472 }; 473 474 tsens_s2_p2: s2-p2@d4 { 475 reg = <0xd4 0x1>; 476 bits = <0 5>; 477 }; 478 479 // no tsens with hw_id 3 480 481 tsens_s4_p1: s4-p1@d4 { 482 reg = <0xd4 0x2>; 483 bits = <5 5>; 484 }; 485 486 tsens_s4_p2: s4-p2@d5 { 487 reg = <0xd5 0x1>; 488 bits = <2 5>; 489 }; 490 491 tsens_s5_p1: s5-p1@d5 { 492 reg = <0xd5 0x2>; 493 bits = <7 5>; 494 }; 495 496 tsens_s5_p2: s5-p2@d6 { 497 reg = <0xd6 0x2>; 498 bits = <4 5>; 499 }; 500 501 tsens_base2: base2@d7 { 502 reg = <0xd7 0x1>; 503 bits = <1 7>; 504 }; 505 506 tsens_mode: mode@ec { 507 reg = <0xef 0x1>; 508 bits = <5 3>; 509 }; 510 }; 511 512 rpm_msg_ram: sram@60000 { 513 compatible = "qcom,rpm-msg-ram"; 514 reg = <0x00060000 0x8000>; 515 }; 516 517 sram@290000 { 518 compatible = "qcom,msm8916-rpm-stats"; 519 reg = <0x00290000 0x10000>; 520 }; 521 522 bimc: interconnect@400000 { 523 compatible = "qcom,msm8916-bimc"; 524 reg = <0x00400000 0x62000>; 525 #interconnect-cells = <1>; 526 clock-names = "bus", "bus_a"; 527 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 528 <&rpmcc RPM_SMD_BIMC_A_CLK>; 529 }; 530 531 tsens: thermal-sensor@4a9000 { 532 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 533 reg = <0x004a9000 0x1000>, /* TM */ 534 <0x004a8000 0x1000>; /* SROT */ 535 536 // no hw_id 3 537 nvmem-cells = <&tsens_mode>, 538 <&tsens_base1>, <&tsens_base2>, 539 <&tsens_s0_p1>, <&tsens_s0_p2>, 540 <&tsens_s1_p1>, <&tsens_s1_p2>, 541 <&tsens_s2_p1>, <&tsens_s2_p2>, 542 <&tsens_s4_p1>, <&tsens_s4_p2>, 543 <&tsens_s5_p1>, <&tsens_s5_p2>; 544 nvmem-cell-names = "mode", 545 "base1", "base2", 546 "s0_p1", "s0_p2", 547 "s1_p1", "s1_p2", 548 "s2_p1", "s2_p2", 549 "s4_p1", "s4_p2", 550 "s5_p1", "s5_p2"; 551 #qcom,sensors = <5>; 552 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-names = "uplow"; 554 #thermal-sensor-cells = <1>; 555 }; 556 557 pcnoc: interconnect@500000 { 558 compatible = "qcom,msm8916-pcnoc"; 559 reg = <0x00500000 0x11000>; 560 #interconnect-cells = <1>; 561 clock-names = "bus", "bus_a"; 562 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 563 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 564 }; 565 566 snoc: interconnect@580000 { 567 compatible = "qcom,msm8916-snoc"; 568 reg = <0x00580000 0x14000>; 569 #interconnect-cells = <1>; 570 clock-names = "bus", "bus_a"; 571 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 572 <&rpmcc RPM_SMD_SNOC_A_CLK>; 573 }; 574 575 stm: stm@802000 { 576 compatible = "arm,coresight-stm", "arm,primecell"; 577 reg = <0x00802000 0x1000>, 578 <0x09280000 0x180000>; 579 reg-names = "stm-base", "stm-stimulus-base"; 580 581 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 582 clock-names = "apb_pclk", "atclk"; 583 584 status = "disabled"; 585 586 out-ports { 587 port { 588 stm_out: endpoint { 589 remote-endpoint = <&funnel0_in7>; 590 }; 591 }; 592 }; 593 }; 594 595 /* System CTIs */ 596 /* CTI 0 - TMC connections */ 597 cti0: cti@810000 { 598 compatible = "arm,coresight-cti", "arm,primecell"; 599 reg = <0x00810000 0x1000>; 600 601 clocks = <&rpmcc RPM_QDSS_CLK>; 602 clock-names = "apb_pclk"; 603 604 status = "disabled"; 605 }; 606 607 /* CTI 1 - TPIU connections */ 608 cti1: cti@811000 { 609 compatible = "arm,coresight-cti", "arm,primecell"; 610 reg = <0x00811000 0x1000>; 611 612 clocks = <&rpmcc RPM_QDSS_CLK>; 613 clock-names = "apb_pclk"; 614 615 status = "disabled"; 616 }; 617 618 /* CTIs 2-11 - no information - not instantiated */ 619 620 tpiu: tpiu@820000 { 621 compatible = "arm,coresight-tpiu", "arm,primecell"; 622 reg = <0x00820000 0x1000>; 623 624 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 625 clock-names = "apb_pclk", "atclk"; 626 627 status = "disabled"; 628 629 in-ports { 630 port { 631 tpiu_in: endpoint { 632 remote-endpoint = <&replicator_out1>; 633 }; 634 }; 635 }; 636 }; 637 638 funnel0: funnel@821000 { 639 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 640 reg = <0x00821000 0x1000>; 641 642 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 643 clock-names = "apb_pclk", "atclk"; 644 645 status = "disabled"; 646 647 in-ports { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 651 /* 652 * Not described input ports: 653 * 0 - connected to Resource and Power Manger CPU ETM 654 * 1 - not-connected 655 * 2 - connected to Modem CPU ETM 656 * 3 - not-connected 657 * 5 - not-connected 658 * 6 - connected trought funnel to Wireless CPU ETM 659 * 7 - connected to STM component 660 */ 661 662 port@4 { 663 reg = <4>; 664 funnel0_in4: endpoint { 665 remote-endpoint = <&funnel1_out>; 666 }; 667 }; 668 669 port@7 { 670 reg = <7>; 671 funnel0_in7: endpoint { 672 remote-endpoint = <&stm_out>; 673 }; 674 }; 675 }; 676 677 out-ports { 678 port { 679 funnel0_out: endpoint { 680 remote-endpoint = <&etf_in>; 681 }; 682 }; 683 }; 684 }; 685 686 replicator: replicator@824000 { 687 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 688 reg = <0x00824000 0x1000>; 689 690 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 691 clock-names = "apb_pclk", "atclk"; 692 693 status = "disabled"; 694 695 out-ports { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 port@0 { 700 reg = <0>; 701 replicator_out0: endpoint { 702 remote-endpoint = <&etr_in>; 703 }; 704 }; 705 port@1 { 706 reg = <1>; 707 replicator_out1: endpoint { 708 remote-endpoint = <&tpiu_in>; 709 }; 710 }; 711 }; 712 713 in-ports { 714 port { 715 replicator_in: endpoint { 716 remote-endpoint = <&etf_out>; 717 }; 718 }; 719 }; 720 }; 721 722 etf: etf@825000 { 723 compatible = "arm,coresight-tmc", "arm,primecell"; 724 reg = <0x00825000 0x1000>; 725 726 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 727 clock-names = "apb_pclk", "atclk"; 728 729 status = "disabled"; 730 731 in-ports { 732 port { 733 etf_in: endpoint { 734 remote-endpoint = <&funnel0_out>; 735 }; 736 }; 737 }; 738 739 out-ports { 740 port { 741 etf_out: endpoint { 742 remote-endpoint = <&replicator_in>; 743 }; 744 }; 745 }; 746 }; 747 748 etr: etr@826000 { 749 compatible = "arm,coresight-tmc", "arm,primecell"; 750 reg = <0x00826000 0x1000>; 751 752 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 753 clock-names = "apb_pclk", "atclk"; 754 755 status = "disabled"; 756 757 in-ports { 758 port { 759 etr_in: endpoint { 760 remote-endpoint = <&replicator_out0>; 761 }; 762 }; 763 }; 764 }; 765 766 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 767 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 768 reg = <0x00841000 0x1000>; 769 770 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 771 clock-names = "apb_pclk", "atclk"; 772 773 status = "disabled"; 774 775 in-ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@0 { 780 reg = <0>; 781 funnel1_in0: endpoint { 782 remote-endpoint = <&etm0_out>; 783 }; 784 }; 785 port@1 { 786 reg = <1>; 787 funnel1_in1: endpoint { 788 remote-endpoint = <&etm1_out>; 789 }; 790 }; 791 port@2 { 792 reg = <2>; 793 funnel1_in2: endpoint { 794 remote-endpoint = <&etm2_out>; 795 }; 796 }; 797 port@3 { 798 reg = <3>; 799 funnel1_in3: endpoint { 800 remote-endpoint = <&etm3_out>; 801 }; 802 }; 803 }; 804 805 out-ports { 806 port { 807 funnel1_out: endpoint { 808 remote-endpoint = <&funnel0_in4>; 809 }; 810 }; 811 }; 812 }; 813 814 debug0: debug@850000 { 815 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 816 reg = <0x00850000 0x1000>; 817 clocks = <&rpmcc RPM_QDSS_CLK>; 818 clock-names = "apb_pclk"; 819 cpu = <&CPU0>; 820 status = "disabled"; 821 }; 822 823 debug1: debug@852000 { 824 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 825 reg = <0x00852000 0x1000>; 826 clocks = <&rpmcc RPM_QDSS_CLK>; 827 clock-names = "apb_pclk"; 828 cpu = <&CPU1>; 829 status = "disabled"; 830 }; 831 832 debug2: debug@854000 { 833 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 834 reg = <0x00854000 0x1000>; 835 clocks = <&rpmcc RPM_QDSS_CLK>; 836 clock-names = "apb_pclk"; 837 cpu = <&CPU2>; 838 status = "disabled"; 839 }; 840 841 debug3: debug@856000 { 842 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 843 reg = <0x00856000 0x1000>; 844 clocks = <&rpmcc RPM_QDSS_CLK>; 845 clock-names = "apb_pclk"; 846 cpu = <&CPU3>; 847 status = "disabled"; 848 }; 849 850 /* Core CTIs; CTIs 12-15 */ 851 /* CTI - CPU-0 */ 852 cti12: cti@858000 { 853 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 854 "arm,primecell"; 855 reg = <0x00858000 0x1000>; 856 857 clocks = <&rpmcc RPM_QDSS_CLK>; 858 clock-names = "apb_pclk"; 859 860 cpu = <&CPU0>; 861 arm,cs-dev-assoc = <&etm0>; 862 863 status = "disabled"; 864 }; 865 866 /* CTI - CPU-1 */ 867 cti13: cti@859000 { 868 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 869 "arm,primecell"; 870 reg = <0x00859000 0x1000>; 871 872 clocks = <&rpmcc RPM_QDSS_CLK>; 873 clock-names = "apb_pclk"; 874 875 cpu = <&CPU1>; 876 arm,cs-dev-assoc = <&etm1>; 877 878 status = "disabled"; 879 }; 880 881 /* CTI - CPU-2 */ 882 cti14: cti@85a000 { 883 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 884 "arm,primecell"; 885 reg = <0x0085a000 0x1000>; 886 887 clocks = <&rpmcc RPM_QDSS_CLK>; 888 clock-names = "apb_pclk"; 889 890 cpu = <&CPU2>; 891 arm,cs-dev-assoc = <&etm2>; 892 893 status = "disabled"; 894 }; 895 896 /* CTI - CPU-3 */ 897 cti15: cti@85b000 { 898 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 899 "arm,primecell"; 900 reg = <0x0085b000 0x1000>; 901 902 clocks = <&rpmcc RPM_QDSS_CLK>; 903 clock-names = "apb_pclk"; 904 905 cpu = <&CPU3>; 906 arm,cs-dev-assoc = <&etm3>; 907 908 status = "disabled"; 909 }; 910 911 etm0: etm@85c000 { 912 compatible = "arm,coresight-etm4x", "arm,primecell"; 913 reg = <0x0085c000 0x1000>; 914 915 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 916 clock-names = "apb_pclk", "atclk"; 917 arm,coresight-loses-context-with-cpu; 918 919 cpu = <&CPU0>; 920 921 status = "disabled"; 922 923 out-ports { 924 port { 925 etm0_out: endpoint { 926 remote-endpoint = <&funnel1_in0>; 927 }; 928 }; 929 }; 930 }; 931 932 etm1: etm@85d000 { 933 compatible = "arm,coresight-etm4x", "arm,primecell"; 934 reg = <0x0085d000 0x1000>; 935 936 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 937 clock-names = "apb_pclk", "atclk"; 938 arm,coresight-loses-context-with-cpu; 939 940 cpu = <&CPU1>; 941 942 status = "disabled"; 943 944 out-ports { 945 port { 946 etm1_out: endpoint { 947 remote-endpoint = <&funnel1_in1>; 948 }; 949 }; 950 }; 951 }; 952 953 etm2: etm@85e000 { 954 compatible = "arm,coresight-etm4x", "arm,primecell"; 955 reg = <0x0085e000 0x1000>; 956 957 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 958 clock-names = "apb_pclk", "atclk"; 959 arm,coresight-loses-context-with-cpu; 960 961 cpu = <&CPU2>; 962 963 status = "disabled"; 964 965 out-ports { 966 port { 967 etm2_out: endpoint { 968 remote-endpoint = <&funnel1_in2>; 969 }; 970 }; 971 }; 972 }; 973 974 etm3: etm@85f000 { 975 compatible = "arm,coresight-etm4x", "arm,primecell"; 976 reg = <0x0085f000 0x1000>; 977 978 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 979 clock-names = "apb_pclk", "atclk"; 980 arm,coresight-loses-context-with-cpu; 981 982 cpu = <&CPU3>; 983 984 status = "disabled"; 985 986 out-ports { 987 port { 988 etm3_out: endpoint { 989 remote-endpoint = <&funnel1_in3>; 990 }; 991 }; 992 }; 993 }; 994 995 msmgpio: pinctrl@1000000 { 996 compatible = "qcom,msm8916-pinctrl"; 997 reg = <0x01000000 0x300000>; 998 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 999 gpio-controller; 1000 gpio-ranges = <&msmgpio 0 0 122>; 1001 #gpio-cells = <2>; 1002 interrupt-controller; 1003 #interrupt-cells = <2>; 1004 }; 1005 1006 gcc: clock-controller@1800000 { 1007 compatible = "qcom,gcc-msm8916"; 1008 #clock-cells = <1>; 1009 #reset-cells = <1>; 1010 #power-domain-cells = <1>; 1011 reg = <0x01800000 0x80000>; 1012 clocks = <&xo_board>, 1013 <&sleep_clk>, 1014 <&dsi_phy0 1>, 1015 <&dsi_phy0 0>, 1016 <0>, 1017 <0>, 1018 <0>; 1019 clock-names = "xo", 1020 "sleep_clk", 1021 "dsi0pll", 1022 "dsi0pllbyte", 1023 "ext_mclk", 1024 "ext_pri_i2s", 1025 "ext_sec_i2s"; 1026 }; 1027 1028 tcsr_mutex: hwlock@1905000 { 1029 compatible = "qcom,tcsr-mutex"; 1030 reg = <0x01905000 0x20000>; 1031 #hwlock-cells = <1>; 1032 }; 1033 1034 tcsr: syscon@1937000 { 1035 compatible = "qcom,tcsr-msm8916", "syscon"; 1036 reg = <0x01937000 0x30000>; 1037 }; 1038 1039 mdss: display-subsystem@1a00000 { 1040 status = "disabled"; 1041 compatible = "qcom,mdss"; 1042 reg = <0x01a00000 0x1000>, 1043 <0x01ac8000 0x3000>; 1044 reg-names = "mdss_phys", "vbif_phys"; 1045 1046 power-domains = <&gcc MDSS_GDSC>; 1047 1048 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1049 <&gcc GCC_MDSS_AXI_CLK>, 1050 <&gcc GCC_MDSS_VSYNC_CLK>; 1051 clock-names = "iface", 1052 "bus", 1053 "vsync"; 1054 1055 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1056 1057 interrupt-controller; 1058 #interrupt-cells = <1>; 1059 1060 #address-cells = <1>; 1061 #size-cells = <1>; 1062 ranges; 1063 1064 mdp: display-controller@1a01000 { 1065 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1066 reg = <0x01a01000 0x89000>; 1067 reg-names = "mdp_phys"; 1068 1069 interrupt-parent = <&mdss>; 1070 interrupts = <0>; 1071 1072 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1073 <&gcc GCC_MDSS_AXI_CLK>, 1074 <&gcc GCC_MDSS_MDP_CLK>, 1075 <&gcc GCC_MDSS_VSYNC_CLK>; 1076 clock-names = "iface", 1077 "bus", 1078 "core", 1079 "vsync"; 1080 1081 iommus = <&apps_iommu 4>; 1082 1083 ports { 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 port@0 { 1088 reg = <0>; 1089 mdp5_intf1_out: endpoint { 1090 remote-endpoint = <&dsi0_in>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 1096 dsi0: dsi@1a98000 { 1097 compatible = "qcom,msm8916-dsi-ctrl", 1098 "qcom,mdss-dsi-ctrl"; 1099 reg = <0x01a98000 0x25c>; 1100 reg-names = "dsi_ctrl"; 1101 1102 interrupt-parent = <&mdss>; 1103 interrupts = <4>; 1104 1105 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1106 <&gcc PCLK0_CLK_SRC>; 1107 assigned-clock-parents = <&dsi_phy0 0>, 1108 <&dsi_phy0 1>; 1109 1110 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1111 <&gcc GCC_MDSS_AHB_CLK>, 1112 <&gcc GCC_MDSS_AXI_CLK>, 1113 <&gcc GCC_MDSS_BYTE0_CLK>, 1114 <&gcc GCC_MDSS_PCLK0_CLK>, 1115 <&gcc GCC_MDSS_ESC0_CLK>; 1116 clock-names = "mdp_core", 1117 "iface", 1118 "bus", 1119 "byte", 1120 "pixel", 1121 "core"; 1122 phys = <&dsi_phy0>; 1123 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 1127 ports { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 1131 port@0 { 1132 reg = <0>; 1133 dsi0_in: endpoint { 1134 remote-endpoint = <&mdp5_intf1_out>; 1135 }; 1136 }; 1137 1138 port@1 { 1139 reg = <1>; 1140 dsi0_out: endpoint { 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 dsi_phy0: phy@1a98300 { 1147 compatible = "qcom,dsi-phy-28nm-lp"; 1148 reg = <0x01a98300 0xd4>, 1149 <0x01a98500 0x280>, 1150 <0x01a98780 0x30>; 1151 reg-names = "dsi_pll", 1152 "dsi_phy", 1153 "dsi_phy_regulator"; 1154 1155 #clock-cells = <1>; 1156 #phy-cells = <0>; 1157 1158 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1159 <&xo_board>; 1160 clock-names = "iface", "ref"; 1161 }; 1162 }; 1163 1164 camss: camss@1b00000 { 1165 compatible = "qcom,msm8916-camss"; 1166 reg = <0x01b0ac00 0x200>, 1167 <0x01b00030 0x4>, 1168 <0x01b0b000 0x200>, 1169 <0x01b00038 0x4>, 1170 <0x01b08000 0x100>, 1171 <0x01b08400 0x100>, 1172 <0x01b0a000 0x500>, 1173 <0x01b00020 0x10>, 1174 <0x01b10000 0x1000>; 1175 reg-names = "csiphy0", 1176 "csiphy0_clk_mux", 1177 "csiphy1", 1178 "csiphy1_clk_mux", 1179 "csid0", 1180 "csid1", 1181 "ispif", 1182 "csi_clk_mux", 1183 "vfe0"; 1184 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1185 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1186 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1187 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1188 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1189 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1190 interrupt-names = "csiphy0", 1191 "csiphy1", 1192 "csid0", 1193 "csid1", 1194 "ispif", 1195 "vfe0"; 1196 power-domains = <&gcc VFE_GDSC>; 1197 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1198 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1199 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1200 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1201 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1202 <&gcc GCC_CAMSS_CSI0_CLK>, 1203 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1204 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1205 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1206 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1207 <&gcc GCC_CAMSS_CSI1_CLK>, 1208 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1209 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1210 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1211 <&gcc GCC_CAMSS_AHB_CLK>, 1212 <&gcc GCC_CAMSS_VFE0_CLK>, 1213 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1214 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1215 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1216 clock-names = "top_ahb", 1217 "ispif_ahb", 1218 "csiphy0_timer", 1219 "csiphy1_timer", 1220 "csi0_ahb", 1221 "csi0", 1222 "csi0_phy", 1223 "csi0_pix", 1224 "csi0_rdi", 1225 "csi1_ahb", 1226 "csi1", 1227 "csi1_phy", 1228 "csi1_pix", 1229 "csi1_rdi", 1230 "ahb", 1231 "vfe0", 1232 "csi_vfe0", 1233 "vfe_ahb", 1234 "vfe_axi"; 1235 iommus = <&apps_iommu 3>; 1236 status = "disabled"; 1237 ports { 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 }; 1241 }; 1242 1243 cci: cci@1b0c000 { 1244 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 reg = <0x01b0c000 0x1000>; 1248 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1249 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1250 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1251 <&gcc GCC_CAMSS_CCI_CLK>, 1252 <&gcc GCC_CAMSS_AHB_CLK>; 1253 clock-names = "camss_top_ahb", "cci_ahb", 1254 "cci", "camss_ahb"; 1255 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1256 <&gcc GCC_CAMSS_CCI_CLK>; 1257 assigned-clock-rates = <80000000>, <19200000>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&cci0_default>; 1260 status = "disabled"; 1261 1262 cci_i2c0: i2c-bus@0 { 1263 reg = <0>; 1264 clock-frequency = <400000>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 }; 1268 }; 1269 1270 gpu@1c00000 { 1271 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1272 reg = <0x01c00000 0x20000>; 1273 reg-names = "kgsl_3d0_reg_memory"; 1274 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "kgsl_3d0_irq"; 1276 clock-names = 1277 "core", 1278 "iface", 1279 "mem", 1280 "mem_iface", 1281 "alt_mem_iface", 1282 "gfx3d"; 1283 clocks = 1284 <&gcc GCC_OXILI_GFX3D_CLK>, 1285 <&gcc GCC_OXILI_AHB_CLK>, 1286 <&gcc GCC_OXILI_GMEM_CLK>, 1287 <&gcc GCC_BIMC_GFX_CLK>, 1288 <&gcc GCC_BIMC_GPU_CLK>, 1289 <&gcc GFX3D_CLK_SRC>; 1290 power-domains = <&gcc OXILI_GDSC>; 1291 operating-points-v2 = <&gpu_opp_table>; 1292 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1293 1294 gpu_opp_table: opp-table { 1295 compatible = "operating-points-v2"; 1296 1297 opp-400000000 { 1298 opp-hz = /bits/ 64 <400000000>; 1299 }; 1300 opp-19200000 { 1301 opp-hz = /bits/ 64 <19200000>; 1302 }; 1303 }; 1304 }; 1305 1306 venus: video-codec@1d00000 { 1307 compatible = "qcom,msm8916-venus"; 1308 reg = <0x01d00000 0xff000>; 1309 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1310 power-domains = <&gcc VENUS_GDSC>; 1311 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1312 <&gcc GCC_VENUS0_AHB_CLK>, 1313 <&gcc GCC_VENUS0_AXI_CLK>; 1314 clock-names = "core", "iface", "bus"; 1315 iommus = <&apps_iommu 5>; 1316 memory-region = <&venus_mem>; 1317 status = "okay"; 1318 1319 video-decoder { 1320 compatible = "venus-decoder"; 1321 }; 1322 1323 video-encoder { 1324 compatible = "venus-encoder"; 1325 }; 1326 }; 1327 1328 apps_iommu: iommu@1ef0000 { 1329 #address-cells = <1>; 1330 #size-cells = <1>; 1331 #iommu-cells = <1>; 1332 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1333 ranges = <0 0x01e20000 0x40000>; 1334 reg = <0x01ef0000 0x3000>; 1335 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1336 <&gcc GCC_APSS_TCU_CLK>; 1337 clock-names = "iface", "bus"; 1338 qcom,iommu-secure-id = <17>; 1339 1340 /* VFE */ 1341 iommu-ctx@3000 { 1342 compatible = "qcom,msm-iommu-v1-sec"; 1343 reg = <0x3000 0x1000>; 1344 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1345 }; 1346 1347 /* MDP_0 */ 1348 iommu-ctx@4000 { 1349 compatible = "qcom,msm-iommu-v1-ns"; 1350 reg = <0x4000 0x1000>; 1351 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1352 }; 1353 1354 /* VENUS_NS */ 1355 iommu-ctx@5000 { 1356 compatible = "qcom,msm-iommu-v1-sec"; 1357 reg = <0x5000 0x1000>; 1358 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1359 }; 1360 }; 1361 1362 gpu_iommu: iommu@1f08000 { 1363 #address-cells = <1>; 1364 #size-cells = <1>; 1365 #iommu-cells = <1>; 1366 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1367 ranges = <0 0x01f08000 0x10000>; 1368 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1369 <&gcc GCC_GFX_TCU_CLK>; 1370 clock-names = "iface", "bus"; 1371 qcom,iommu-secure-id = <18>; 1372 1373 /* GFX3D_USER */ 1374 iommu-ctx@1000 { 1375 compatible = "qcom,msm-iommu-v1-ns"; 1376 reg = <0x1000 0x1000>; 1377 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1378 }; 1379 1380 /* GFX3D_PRIV */ 1381 iommu-ctx@2000 { 1382 compatible = "qcom,msm-iommu-v1-ns"; 1383 reg = <0x2000 0x1000>; 1384 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1385 }; 1386 }; 1387 1388 spmi_bus: spmi@200f000 { 1389 compatible = "qcom,spmi-pmic-arb"; 1390 reg = <0x0200f000 0x001000>, 1391 <0x02400000 0x400000>, 1392 <0x02c00000 0x400000>, 1393 <0x03800000 0x200000>, 1394 <0x0200a000 0x002100>; 1395 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1396 interrupt-names = "periph_irq"; 1397 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1398 qcom,ee = <0>; 1399 qcom,channel = <0>; 1400 #address-cells = <2>; 1401 #size-cells = <0>; 1402 interrupt-controller; 1403 #interrupt-cells = <4>; 1404 }; 1405 1406 bam_dmux_dma: dma-controller@4044000 { 1407 compatible = "qcom,bam-v1.7.0"; 1408 reg = <0x04044000 0x19000>; 1409 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1410 #dma-cells = <1>; 1411 qcom,ee = <0>; 1412 1413 num-channels = <6>; 1414 qcom,num-ees = <1>; 1415 qcom,powered-remotely; 1416 1417 status = "disabled"; 1418 }; 1419 1420 mpss: remoteproc@4080000 { 1421 compatible = "qcom,msm8916-mss-pil"; 1422 reg = <0x04080000 0x100>, 1423 <0x04020000 0x040>; 1424 1425 reg-names = "qdsp6", "rmb"; 1426 1427 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1428 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1429 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1430 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1431 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1432 interrupt-names = "wdog", "fatal", "ready", 1433 "handover", "stop-ack"; 1434 1435 power-domains = <&rpmpd MSM8916_VDDCX>, 1436 <&rpmpd MSM8916_VDDMX>; 1437 power-domain-names = "cx", "mx"; 1438 1439 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1440 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1441 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1442 <&xo_board>; 1443 clock-names = "iface", "bus", "mem", "xo"; 1444 1445 qcom,smem-states = <&hexagon_smp2p_out 0>; 1446 qcom,smem-state-names = "stop"; 1447 1448 resets = <&scm 0>; 1449 reset-names = "mss_restart"; 1450 1451 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1452 1453 status = "disabled"; 1454 1455 mba { 1456 memory-region = <&mba_mem>; 1457 }; 1458 1459 mpss { 1460 memory-region = <&mpss_mem>; 1461 }; 1462 1463 bam_dmux: bam-dmux { 1464 compatible = "qcom,bam-dmux"; 1465 1466 interrupt-parent = <&hexagon_smsm>; 1467 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1468 interrupt-names = "pc", "pc-ack"; 1469 1470 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1471 qcom,smem-state-names = "pc", "pc-ack"; 1472 1473 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1474 dma-names = "tx", "rx"; 1475 1476 status = "disabled"; 1477 }; 1478 1479 smd-edge { 1480 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1481 1482 qcom,smd-edge = <0>; 1483 qcom,ipc = <&apcs 8 12>; 1484 qcom,remote-pid = <1>; 1485 1486 label = "hexagon"; 1487 1488 fastrpc { 1489 compatible = "qcom,fastrpc"; 1490 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1491 label = "adsp"; 1492 qcom,non-secure-domain; 1493 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 1497 cb@1 { 1498 compatible = "qcom,fastrpc-compute-cb"; 1499 reg = <1>; 1500 }; 1501 }; 1502 }; 1503 }; 1504 1505 sound: sound@7702000 { 1506 status = "disabled"; 1507 compatible = "qcom,apq8016-sbc-sndcard"; 1508 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1509 reg-names = "mic-iomux", "spkr-iomux"; 1510 }; 1511 1512 lpass: audio-controller@7708000 { 1513 status = "disabled"; 1514 compatible = "qcom,apq8016-lpass-cpu"; 1515 1516 /* 1517 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1518 * is actually only used by Tertiary MI2S while 1519 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1520 */ 1521 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1522 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1523 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 1524 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1525 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1526 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1527 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 1528 1529 clock-names = "ahbix-clk", 1530 "pcnoc-mport-clk", 1531 "pcnoc-sway-clk", 1532 "mi2s-bit-clk0", 1533 "mi2s-bit-clk1", 1534 "mi2s-bit-clk2", 1535 "mi2s-bit-clk3"; 1536 #sound-dai-cells = <1>; 1537 1538 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1539 interrupt-names = "lpass-irq-lpaif"; 1540 reg = <0x07708000 0x10000>; 1541 reg-names = "lpass-lpaif"; 1542 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 }; 1546 1547 lpass_codec: audio-codec@771c000 { 1548 compatible = "qcom,msm8916-wcd-digital-codec"; 1549 reg = <0x0771c000 0x400>; 1550 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1551 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1552 clock-names = "ahbix-clk", "mclk"; 1553 #sound-dai-cells = <1>; 1554 }; 1555 1556 sdhc_1: mmc@7824000 { 1557 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1558 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1559 reg-names = "hc", "core"; 1560 1561 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1563 interrupt-names = "hc_irq", "pwr_irq"; 1564 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1565 <&gcc GCC_SDCC1_APPS_CLK>, 1566 <&xo_board>; 1567 clock-names = "iface", "core", "xo"; 1568 mmc-ddr-1_8v; 1569 bus-width = <8>; 1570 non-removable; 1571 status = "disabled"; 1572 }; 1573 1574 sdhc_2: mmc@7864000 { 1575 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1576 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1577 reg-names = "hc", "core"; 1578 1579 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1581 interrupt-names = "hc_irq", "pwr_irq"; 1582 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1583 <&gcc GCC_SDCC2_APPS_CLK>, 1584 <&xo_board>; 1585 clock-names = "iface", "core", "xo"; 1586 bus-width = <4>; 1587 status = "disabled"; 1588 }; 1589 1590 blsp_dma: dma-controller@7884000 { 1591 compatible = "qcom,bam-v1.7.0"; 1592 reg = <0x07884000 0x23000>; 1593 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1595 clock-names = "bam_clk"; 1596 #dma-cells = <1>; 1597 qcom,ee = <0>; 1598 }; 1599 1600 blsp1_uart1: serial@78af000 { 1601 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1602 reg = <0x078af000 0x200>; 1603 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1604 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1605 clock-names = "core", "iface"; 1606 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1607 dma-names = "tx", "rx"; 1608 pinctrl-names = "default", "sleep"; 1609 pinctrl-0 = <&blsp1_uart1_default>; 1610 pinctrl-1 = <&blsp1_uart1_sleep>; 1611 status = "disabled"; 1612 }; 1613 1614 blsp1_uart2: serial@78b0000 { 1615 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1616 reg = <0x078b0000 0x200>; 1617 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1619 clock-names = "core", "iface"; 1620 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1621 dma-names = "tx", "rx"; 1622 pinctrl-names = "default", "sleep"; 1623 pinctrl-0 = <&blsp1_uart2_default>; 1624 pinctrl-1 = <&blsp1_uart2_sleep>; 1625 status = "disabled"; 1626 }; 1627 1628 blsp_i2c1: i2c@78b5000 { 1629 compatible = "qcom,i2c-qup-v2.2.1"; 1630 reg = <0x078b5000 0x500>; 1631 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1632 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1633 <&gcc GCC_BLSP1_AHB_CLK>; 1634 clock-names = "core", "iface"; 1635 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1636 dma-names = "tx", "rx"; 1637 pinctrl-names = "default", "sleep"; 1638 pinctrl-0 = <&i2c1_default>; 1639 pinctrl-1 = <&i2c1_sleep>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 blsp_spi1: spi@78b5000 { 1646 compatible = "qcom,spi-qup-v2.2.1"; 1647 reg = <0x078b5000 0x500>; 1648 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1650 <&gcc GCC_BLSP1_AHB_CLK>; 1651 clock-names = "core", "iface"; 1652 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1653 dma-names = "tx", "rx"; 1654 pinctrl-names = "default", "sleep"; 1655 pinctrl-0 = <&spi1_default>; 1656 pinctrl-1 = <&spi1_sleep>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 blsp_i2c2: i2c@78b6000 { 1663 compatible = "qcom,i2c-qup-v2.2.1"; 1664 reg = <0x078b6000 0x500>; 1665 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1666 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1667 <&gcc GCC_BLSP1_AHB_CLK>; 1668 clock-names = "core", "iface"; 1669 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1670 dma-names = "tx", "rx"; 1671 pinctrl-names = "default", "sleep"; 1672 pinctrl-0 = <&i2c2_default>; 1673 pinctrl-1 = <&i2c2_sleep>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 blsp_spi2: spi@78b6000 { 1680 compatible = "qcom,spi-qup-v2.2.1"; 1681 reg = <0x078b6000 0x500>; 1682 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1684 <&gcc GCC_BLSP1_AHB_CLK>; 1685 clock-names = "core", "iface"; 1686 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1687 dma-names = "tx", "rx"; 1688 pinctrl-names = "default", "sleep"; 1689 pinctrl-0 = <&spi2_default>; 1690 pinctrl-1 = <&spi2_sleep>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 blsp_i2c3: i2c@78b7000 { 1697 compatible = "qcom,i2c-qup-v2.2.1"; 1698 reg = <0x078b7000 0x500>; 1699 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1700 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1701 <&gcc GCC_BLSP1_AHB_CLK>; 1702 clock-names = "core", "iface"; 1703 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1704 dma-names = "tx", "rx"; 1705 pinctrl-names = "default", "sleep"; 1706 pinctrl-0 = <&i2c3_default>; 1707 pinctrl-1 = <&i2c3_sleep>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 status = "disabled"; 1711 }; 1712 1713 blsp_spi3: spi@78b7000 { 1714 compatible = "qcom,spi-qup-v2.2.1"; 1715 reg = <0x078b7000 0x500>; 1716 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1717 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1718 <&gcc GCC_BLSP1_AHB_CLK>; 1719 clock-names = "core", "iface"; 1720 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1721 dma-names = "tx", "rx"; 1722 pinctrl-names = "default", "sleep"; 1723 pinctrl-0 = <&spi3_default>; 1724 pinctrl-1 = <&spi3_sleep>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 blsp_i2c4: i2c@78b8000 { 1731 compatible = "qcom,i2c-qup-v2.2.1"; 1732 reg = <0x078b8000 0x500>; 1733 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1735 <&gcc GCC_BLSP1_AHB_CLK>; 1736 clock-names = "core", "iface"; 1737 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1738 dma-names = "tx", "rx"; 1739 pinctrl-names = "default", "sleep"; 1740 pinctrl-0 = <&i2c4_default>; 1741 pinctrl-1 = <&i2c4_sleep>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 status = "disabled"; 1745 }; 1746 1747 blsp_spi4: spi@78b8000 { 1748 compatible = "qcom,spi-qup-v2.2.1"; 1749 reg = <0x078b8000 0x500>; 1750 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1751 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1752 <&gcc GCC_BLSP1_AHB_CLK>; 1753 clock-names = "core", "iface"; 1754 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1755 dma-names = "tx", "rx"; 1756 pinctrl-names = "default", "sleep"; 1757 pinctrl-0 = <&spi4_default>; 1758 pinctrl-1 = <&spi4_sleep>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 1764 blsp_i2c5: i2c@78b9000 { 1765 compatible = "qcom,i2c-qup-v2.2.1"; 1766 reg = <0x078b9000 0x500>; 1767 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1768 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1769 <&gcc GCC_BLSP1_AHB_CLK>; 1770 clock-names = "core", "iface"; 1771 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1772 dma-names = "tx", "rx"; 1773 pinctrl-names = "default", "sleep"; 1774 pinctrl-0 = <&i2c5_default>; 1775 pinctrl-1 = <&i2c5_sleep>; 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 status = "disabled"; 1779 }; 1780 1781 blsp_spi5: spi@78b9000 { 1782 compatible = "qcom,spi-qup-v2.2.1"; 1783 reg = <0x078b9000 0x500>; 1784 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1785 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1786 <&gcc GCC_BLSP1_AHB_CLK>; 1787 clock-names = "core", "iface"; 1788 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1789 dma-names = "tx", "rx"; 1790 pinctrl-names = "default", "sleep"; 1791 pinctrl-0 = <&spi5_default>; 1792 pinctrl-1 = <&spi5_sleep>; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 status = "disabled"; 1796 }; 1797 1798 blsp_i2c6: i2c@78ba000 { 1799 compatible = "qcom,i2c-qup-v2.2.1"; 1800 reg = <0x078ba000 0x500>; 1801 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1802 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1803 <&gcc GCC_BLSP1_AHB_CLK>; 1804 clock-names = "core", "iface"; 1805 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1806 dma-names = "tx", "rx"; 1807 pinctrl-names = "default", "sleep"; 1808 pinctrl-0 = <&i2c6_default>; 1809 pinctrl-1 = <&i2c6_sleep>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 status = "disabled"; 1813 }; 1814 1815 blsp_spi6: spi@78ba000 { 1816 compatible = "qcom,spi-qup-v2.2.1"; 1817 reg = <0x078ba000 0x500>; 1818 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1820 <&gcc GCC_BLSP1_AHB_CLK>; 1821 clock-names = "core", "iface"; 1822 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1823 dma-names = "tx", "rx"; 1824 pinctrl-names = "default", "sleep"; 1825 pinctrl-0 = <&spi6_default>; 1826 pinctrl-1 = <&spi6_sleep>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 usb: usb@78d9000 { 1833 compatible = "qcom,ci-hdrc"; 1834 reg = <0x078d9000 0x200>, 1835 <0x078d9200 0x200>; 1836 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1839 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1840 clock-names = "iface", "core"; 1841 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1842 assigned-clock-rates = <80000000>; 1843 resets = <&gcc GCC_USB_HS_BCR>; 1844 reset-names = "core"; 1845 phy_type = "ulpi"; 1846 dr_mode = "otg"; 1847 hnp-disable; 1848 srp-disable; 1849 adp-disable; 1850 ahb-burst-config = <0>; 1851 phy-names = "usb-phy"; 1852 phys = <&usb_hs_phy>; 1853 status = "disabled"; 1854 #reset-cells = <1>; 1855 1856 ulpi { 1857 usb_hs_phy: phy { 1858 compatible = "qcom,usb-hs-phy-msm8916", 1859 "qcom,usb-hs-phy"; 1860 #phy-cells = <0>; 1861 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1862 clock-names = "ref", "sleep"; 1863 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1864 reset-names = "phy", "por"; 1865 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1866 <0x1 0x6b>, 1867 <0x2 0x24>, 1868 <0x3 0x13>; 1869 }; 1870 }; 1871 }; 1872 1873 pronto: remoteproc@a21b000 { 1874 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1875 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1876 reg-names = "ccu", "dxe", "pmu"; 1877 1878 memory-region = <&wcnss_mem>; 1879 1880 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1881 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1882 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1883 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1884 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1885 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1886 1887 power-domains = <&rpmpd MSM8916_VDDCX>, 1888 <&rpmpd MSM8916_VDDMX>; 1889 power-domain-names = "cx", "mx"; 1890 1891 qcom,smem-states = <&wcnss_smp2p_out 0>; 1892 qcom,smem-state-names = "stop"; 1893 1894 pinctrl-names = "default"; 1895 pinctrl-0 = <&wcnss_pin_a>; 1896 1897 status = "disabled"; 1898 1899 iris { 1900 compatible = "qcom,wcn3620"; 1901 1902 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1903 clock-names = "xo"; 1904 }; 1905 1906 smd-edge { 1907 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1908 1909 qcom,ipc = <&apcs 8 17>; 1910 qcom,smd-edge = <6>; 1911 qcom,remote-pid = <4>; 1912 1913 label = "pronto"; 1914 1915 wcnss_ctrl: wcnss { 1916 compatible = "qcom,wcnss"; 1917 qcom,smd-channels = "WCNSS_CTRL"; 1918 1919 qcom,mmio = <&pronto>; 1920 1921 bluetooth { 1922 compatible = "qcom,wcnss-bt"; 1923 }; 1924 1925 wifi { 1926 compatible = "qcom,wcnss-wlan"; 1927 1928 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1930 interrupt-names = "tx", "rx"; 1931 1932 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1933 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1934 }; 1935 }; 1936 }; 1937 }; 1938 1939 intc: interrupt-controller@b000000 { 1940 compatible = "qcom,msm-qgic2"; 1941 interrupt-controller; 1942 #interrupt-cells = <3>; 1943 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 1944 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 1945 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1946 }; 1947 1948 apcs: mailbox@b011000 { 1949 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 1950 reg = <0x0b011000 0x1000>; 1951 #mbox-cells = <1>; 1952 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 1953 clock-names = "pll", "aux"; 1954 #clock-cells = <0>; 1955 }; 1956 1957 a53pll: clock@b016000 { 1958 compatible = "qcom,msm8916-a53pll"; 1959 reg = <0x0b016000 0x40>; 1960 #clock-cells = <0>; 1961 clocks = <&xo_board>; 1962 clock-names = "xo"; 1963 }; 1964 1965 timer@b020000 { 1966 #address-cells = <1>; 1967 #size-cells = <1>; 1968 ranges; 1969 compatible = "arm,armv7-timer-mem"; 1970 reg = <0x0b020000 0x1000>; 1971 clock-frequency = <19200000>; 1972 1973 frame@b021000 { 1974 frame-number = <0>; 1975 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1977 reg = <0x0b021000 0x1000>, 1978 <0x0b022000 0x1000>; 1979 }; 1980 1981 frame@b023000 { 1982 frame-number = <1>; 1983 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1984 reg = <0x0b023000 0x1000>; 1985 status = "disabled"; 1986 }; 1987 1988 frame@b024000 { 1989 frame-number = <2>; 1990 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1991 reg = <0x0b024000 0x1000>; 1992 status = "disabled"; 1993 }; 1994 1995 frame@b025000 { 1996 frame-number = <3>; 1997 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1998 reg = <0x0b025000 0x1000>; 1999 status = "disabled"; 2000 }; 2001 2002 frame@b026000 { 2003 frame-number = <4>; 2004 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2005 reg = <0x0b026000 0x1000>; 2006 status = "disabled"; 2007 }; 2008 2009 frame@b027000 { 2010 frame-number = <5>; 2011 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2012 reg = <0x0b027000 0x1000>; 2013 status = "disabled"; 2014 }; 2015 2016 frame@b028000 { 2017 frame-number = <6>; 2018 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2019 reg = <0x0b028000 0x1000>; 2020 status = "disabled"; 2021 }; 2022 }; 2023 2024 cpu0_acc: power-manager@b088000 { 2025 compatible = "qcom,msm8916-acc"; 2026 reg = <0x0b088000 0x1000>; 2027 status = "reserved"; /* Controlled by PSCI firmware */ 2028 }; 2029 2030 cpu0_saw: power-manager@b089000 { 2031 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2032 reg = <0x0b089000 0x1000>; 2033 status = "reserved"; /* Controlled by PSCI firmware */ 2034 }; 2035 2036 cpu1_acc: power-manager@b098000 { 2037 compatible = "qcom,msm8916-acc"; 2038 reg = <0x0b098000 0x1000>; 2039 status = "reserved"; /* Controlled by PSCI firmware */ 2040 }; 2041 2042 cpu1_saw: power-manager@b099000 { 2043 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2044 reg = <0x0b099000 0x1000>; 2045 status = "reserved"; /* Controlled by PSCI firmware */ 2046 }; 2047 2048 cpu2_acc: power-manager@b0a8000 { 2049 compatible = "qcom,msm8916-acc"; 2050 reg = <0x0b0a8000 0x1000>; 2051 status = "reserved"; /* Controlled by PSCI firmware */ 2052 }; 2053 2054 cpu2_saw: power-manager@b0a9000 { 2055 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2056 reg = <0x0b0a9000 0x1000>; 2057 status = "reserved"; /* Controlled by PSCI firmware */ 2058 }; 2059 2060 cpu3_acc: power-manager@b0b8000 { 2061 compatible = "qcom,msm8916-acc"; 2062 reg = <0x0b0b8000 0x1000>; 2063 status = "reserved"; /* Controlled by PSCI firmware */ 2064 }; 2065 2066 cpu3_saw: power-manager@b0b9000 { 2067 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2068 reg = <0x0b0b9000 0x1000>; 2069 status = "reserved"; /* Controlled by PSCI firmware */ 2070 }; 2071 }; 2072 2073 thermal-zones { 2074 cpu0-1-thermal { 2075 polling-delay-passive = <250>; 2076 polling-delay = <1000>; 2077 2078 thermal-sensors = <&tsens 5>; 2079 2080 trips { 2081 cpu0_1_alert0: trip-point0 { 2082 temperature = <75000>; 2083 hysteresis = <2000>; 2084 type = "passive"; 2085 }; 2086 cpu0_1_crit: cpu-crit { 2087 temperature = <110000>; 2088 hysteresis = <2000>; 2089 type = "critical"; 2090 }; 2091 }; 2092 2093 cooling-maps { 2094 map0 { 2095 trip = <&cpu0_1_alert0>; 2096 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2097 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2098 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2099 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2100 }; 2101 }; 2102 }; 2103 2104 cpu2-3-thermal { 2105 polling-delay-passive = <250>; 2106 polling-delay = <1000>; 2107 2108 thermal-sensors = <&tsens 4>; 2109 2110 trips { 2111 cpu2_3_alert0: trip-point0 { 2112 temperature = <75000>; 2113 hysteresis = <2000>; 2114 type = "passive"; 2115 }; 2116 cpu2_3_crit: cpu-crit { 2117 temperature = <110000>; 2118 hysteresis = <2000>; 2119 type = "critical"; 2120 }; 2121 }; 2122 2123 cooling-maps { 2124 map0 { 2125 trip = <&cpu2_3_alert0>; 2126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2130 }; 2131 }; 2132 }; 2133 2134 gpu-thermal { 2135 polling-delay-passive = <250>; 2136 polling-delay = <1000>; 2137 2138 thermal-sensors = <&tsens 2>; 2139 2140 trips { 2141 gpu_alert0: trip-point0 { 2142 temperature = <75000>; 2143 hysteresis = <2000>; 2144 type = "passive"; 2145 }; 2146 gpu_crit: gpu-crit { 2147 temperature = <95000>; 2148 hysteresis = <2000>; 2149 type = "critical"; 2150 }; 2151 }; 2152 }; 2153 2154 camera-thermal { 2155 polling-delay-passive = <250>; 2156 polling-delay = <1000>; 2157 2158 thermal-sensors = <&tsens 1>; 2159 2160 trips { 2161 cam_alert0: trip-point0 { 2162 temperature = <75000>; 2163 hysteresis = <2000>; 2164 type = "hot"; 2165 }; 2166 }; 2167 }; 2168 2169 modem-thermal { 2170 polling-delay-passive = <250>; 2171 polling-delay = <1000>; 2172 2173 thermal-sensors = <&tsens 0>; 2174 2175 trips { 2176 modem_alert0: trip-point0 { 2177 temperature = <85000>; 2178 hysteresis = <2000>; 2179 type = "hot"; 2180 }; 2181 }; 2182 }; 2183 2184 }; 2185 2186 timer { 2187 compatible = "arm,armv8-timer"; 2188 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2189 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2190 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2192 }; 2193}; 2194 2195#include "msm8916-pins.dtsi" 2196