1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/reset/qcom,gcc-msm8916.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 20 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 21 }; 22 23 chosen { }; 24 25 memory { 26 device_type = "memory"; 27 /* We expect the bootloader to fill in the reg */ 28 reg = <0 0 0 0>; 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 tz-apps@86000000 { 37 reg = <0x0 0x86000000 0x0 0x300000>; 38 no-map; 39 }; 40 41 smem_mem: smem_region@86300000 { 42 reg = <0x0 0x86300000 0x0 0x100000>; 43 no-map; 44 }; 45 46 hypervisor@86400000 { 47 reg = <0x0 0x86400000 0x0 0x100000>; 48 no-map; 49 }; 50 51 tz@86500000 { 52 reg = <0x0 0x86500000 0x0 0x180000>; 53 no-map; 54 }; 55 56 reserved@8668000 { 57 reg = <0x0 0x86680000 0x0 0x80000>; 58 no-map; 59 }; 60 61 rmtfs@86700000 { 62 compatible = "qcom,rmtfs-mem"; 63 reg = <0x0 0x86700000 0x0 0xe0000>; 64 no-map; 65 66 qcom,client-id = <1>; 67 }; 68 69 rfsa@867e00000 { 70 reg = <0x0 0x867e0000 0x0 0x20000>; 71 no-map; 72 }; 73 74 mpss_mem: mpss@86800000 { 75 reg = <0x0 0x86800000 0x0 0x2b00000>; 76 no-map; 77 }; 78 79 wcnss_mem: wcnss@89300000 { 80 reg = <0x0 0x89300000 0x0 0x600000>; 81 no-map; 82 }; 83 84 venus_mem: venus@89900000 { 85 reg = <0x0 0x89900000 0x0 0x600000>; 86 no-map; 87 }; 88 89 mba_mem: mba@8ea00000 { 90 no-map; 91 reg = <0 0x8ea00000 0 0x100000>; 92 }; 93 }; 94 95 cpus { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 CPU0: cpu@0 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0>; 103 next-level-cache = <&L2_0>; 104 enable-method = "psci"; 105 cpu-idle-states = <&CPU_SLEEP_0>; 106 clocks = <&apcs>; 107 operating-points-v2 = <&cpu_opp_table>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU1: cpu@1 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x1>; 115 next-level-cache = <&L2_0>; 116 enable-method = "psci"; 117 cpu-idle-states = <&CPU_SLEEP_0>; 118 clocks = <&apcs>; 119 operating-points-v2 = <&cpu_opp_table>; 120 #cooling-cells = <2>; 121 }; 122 123 CPU2: cpu@2 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53"; 126 reg = <0x2>; 127 next-level-cache = <&L2_0>; 128 enable-method = "psci"; 129 cpu-idle-states = <&CPU_SLEEP_0>; 130 clocks = <&apcs>; 131 operating-points-v2 = <&cpu_opp_table>; 132 #cooling-cells = <2>; 133 }; 134 135 CPU3: cpu@3 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x3>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 cpu-idle-states = <&CPU_SLEEP_0>; 142 clocks = <&apcs>; 143 operating-points-v2 = <&cpu_opp_table>; 144 #cooling-cells = <2>; 145 }; 146 147 L2_0: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 }; 151 152 idle-states { 153 entry-method = "psci"; 154 155 CPU_SLEEP_0: cpu-sleep-0 { 156 compatible = "arm,idle-state"; 157 idle-state-name = "standalone-power-collapse"; 158 arm,psci-suspend-param = <0x40000002>; 159 entry-latency-us = <130>; 160 exit-latency-us = <150>; 161 min-residency-us = <2000>; 162 local-timer-stop; 163 }; 164 }; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 pmu { 173 compatible = "arm,cortex-a53-pmu"; 174 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 175 }; 176 177 thermal-zones { 178 cpu0_1-thermal { 179 polling-delay-passive = <250>; 180 polling-delay = <1000>; 181 182 thermal-sensors = <&tsens 5>; 183 184 trips { 185 cpu0_1_alert0: trip-point@0 { 186 temperature = <75000>; 187 hysteresis = <2000>; 188 type = "passive"; 189 }; 190 cpu0_1_crit: cpu_crit { 191 temperature = <110000>; 192 hysteresis = <2000>; 193 type = "critical"; 194 }; 195 }; 196 197 cooling-maps { 198 map0 { 199 trip = <&cpu0_1_alert0>; 200 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 201 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 202 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 203 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 204 }; 205 }; 206 }; 207 208 cpu2_3-thermal { 209 polling-delay-passive = <250>; 210 polling-delay = <1000>; 211 212 thermal-sensors = <&tsens 4>; 213 214 trips { 215 cpu2_3_alert0: trip-point@0 { 216 temperature = <75000>; 217 hysteresis = <2000>; 218 type = "passive"; 219 }; 220 cpu2_3_crit: cpu_crit { 221 temperature = <110000>; 222 hysteresis = <2000>; 223 type = "critical"; 224 }; 225 }; 226 227 cooling-maps { 228 map0 { 229 trip = <&cpu2_3_alert0>; 230 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 231 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 232 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 233 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 234 }; 235 }; 236 }; 237 238 gpu-thermal { 239 polling-delay-passive = <250>; 240 polling-delay = <1000>; 241 242 thermal-sensors = <&tsens 2>; 243 244 trips { 245 gpu_alert0: trip-point@0 { 246 temperature = <75000>; 247 hysteresis = <2000>; 248 type = "passive"; 249 }; 250 gpu_crit: gpu_crit { 251 temperature = <95000>; 252 hysteresis = <2000>; 253 type = "critical"; 254 }; 255 }; 256 }; 257 258 camera-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <1000>; 261 262 thermal-sensors = <&tsens 1>; 263 264 trips { 265 cam_alert0: trip-point@0 { 266 temperature = <75000>; 267 hysteresis = <2000>; 268 type = "hot"; 269 }; 270 }; 271 }; 272 273 modem-thermal { 274 polling-delay-passive = <250>; 275 polling-delay = <1000>; 276 277 thermal-sensors = <&tsens 0>; 278 279 trips { 280 modem_alert0: trip-point@0 { 281 temperature = <85000>; 282 hysteresis = <2000>; 283 type = "hot"; 284 }; 285 }; 286 }; 287 288 }; 289 290 cpu_opp_table: cpu_opp_table { 291 compatible = "operating-points-v2"; 292 opp-shared; 293 294 opp-200000000 { 295 opp-hz = /bits/ 64 <200000000>; 296 }; 297 opp-400000000 { 298 opp-hz = /bits/ 64 <400000000>; 299 }; 300 opp-800000000 { 301 opp-hz = /bits/ 64 <800000000>; 302 }; 303 opp-998400000 { 304 opp-hz = /bits/ 64 <998400000>; 305 }; 306 }; 307 308 gpu_opp_table: opp_table { 309 compatible = "operating-points-v2"; 310 311 opp-400000000 { 312 opp-hz = /bits/ 64 <400000000>; 313 }; 314 opp-19200000 { 315 opp-hz = /bits/ 64 <19200000>; 316 }; 317 }; 318 319 timer { 320 compatible = "arm,armv8-timer"; 321 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 322 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 323 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 324 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 325 }; 326 327 clocks { 328 xo_board: xo_board { 329 compatible = "fixed-clock"; 330 #clock-cells = <0>; 331 clock-frequency = <19200000>; 332 }; 333 334 sleep_clk: sleep_clk { 335 compatible = "fixed-clock"; 336 #clock-cells = <0>; 337 clock-frequency = <32768>; 338 }; 339 }; 340 341 smem { 342 compatible = "qcom,smem"; 343 344 memory-region = <&smem_mem>; 345 qcom,rpm-msg-ram = <&rpm_msg_ram>; 346 347 hwlocks = <&tcsr_mutex 3>; 348 }; 349 350 firmware { 351 scm: scm { 352 compatible = "qcom,scm"; 353 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 354 clock-names = "core", "bus", "iface"; 355 #reset-cells = <1>; 356 357 qcom,dload-mode = <&tcsr 0x6100>; 358 }; 359 }; 360 361 soc: soc { 362 #address-cells = <1>; 363 #size-cells = <1>; 364 ranges = <0 0 0 0xffffffff>; 365 compatible = "simple-bus"; 366 367 restart@4ab000 { 368 compatible = "qcom,pshold"; 369 reg = <0x4ab000 0x4>; 370 }; 371 372 msmgpio: pinctrl@1000000 { 373 compatible = "qcom,msm8916-pinctrl"; 374 reg = <0x1000000 0x300000>; 375 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 382 gcc: clock-controller@1800000 { 383 compatible = "qcom,gcc-msm8916"; 384 #clock-cells = <1>; 385 #reset-cells = <1>; 386 #power-domain-cells = <1>; 387 reg = <0x1800000 0x80000>; 388 }; 389 390 tcsr_mutex_regs: syscon@1905000 { 391 compatible = "syscon"; 392 reg = <0x1905000 0x20000>; 393 }; 394 395 tcsr: syscon@1937000 { 396 compatible = "qcom,tcsr-msm8916", "syscon"; 397 reg = <0x1937000 0x30000>; 398 }; 399 400 tcsr_mutex: hwlock { 401 compatible = "qcom,tcsr-mutex"; 402 syscon = <&tcsr_mutex_regs 0 0x1000>; 403 #hwlock-cells = <1>; 404 }; 405 406 rpm_msg_ram: memory@60000 { 407 compatible = "qcom,rpm-msg-ram"; 408 reg = <0x60000 0x8000>; 409 }; 410 411 blsp1_uart1: serial@78af000 { 412 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 413 reg = <0x78af000 0x200>; 414 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 416 clock-names = "core", "iface"; 417 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 418 dma-names = "rx", "tx"; 419 status = "disabled"; 420 }; 421 422 a53pll: clock@b016000 { 423 compatible = "qcom,msm8916-a53pll"; 424 reg = <0xb016000 0x40>; 425 #clock-cells = <0>; 426 }; 427 428 apcs: mailbox@b011000 { 429 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 430 reg = <0xb011000 0x1000>; 431 #mbox-cells = <1>; 432 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 433 clock-names = "pll", "aux"; 434 #clock-cells = <0>; 435 }; 436 437 blsp1_uart2: serial@78b0000 { 438 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 439 reg = <0x78b0000 0x200>; 440 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 442 clock-names = "core", "iface"; 443 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 blsp_dma: dma@7884000 { 449 compatible = "qcom,bam-v1.7.0"; 450 reg = <0x07884000 0x23000>; 451 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 453 clock-names = "bam_clk"; 454 #dma-cells = <1>; 455 qcom,ee = <0>; 456 status = "disabled"; 457 }; 458 459 blsp_spi1: spi@78b5000 { 460 compatible = "qcom,spi-qup-v2.2.1"; 461 reg = <0x078b5000 0x500>; 462 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 464 <&gcc GCC_BLSP1_AHB_CLK>; 465 clock-names = "core", "iface"; 466 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 467 dma-names = "rx", "tx"; 468 pinctrl-names = "default", "sleep"; 469 pinctrl-0 = <&spi1_default>; 470 pinctrl-1 = <&spi1_sleep>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 blsp_spi2: spi@78b6000 { 477 compatible = "qcom,spi-qup-v2.2.1"; 478 reg = <0x078b6000 0x500>; 479 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 481 <&gcc GCC_BLSP1_AHB_CLK>; 482 clock-names = "core", "iface"; 483 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 484 dma-names = "rx", "tx"; 485 pinctrl-names = "default", "sleep"; 486 pinctrl-0 = <&spi2_default>; 487 pinctrl-1 = <&spi2_sleep>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 blsp_spi3: spi@78b7000 { 494 compatible = "qcom,spi-qup-v2.2.1"; 495 reg = <0x078b7000 0x500>; 496 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 498 <&gcc GCC_BLSP1_AHB_CLK>; 499 clock-names = "core", "iface"; 500 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 501 dma-names = "rx", "tx"; 502 pinctrl-names = "default", "sleep"; 503 pinctrl-0 = <&spi3_default>; 504 pinctrl-1 = <&spi3_sleep>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 blsp_spi4: spi@78b8000 { 511 compatible = "qcom,spi-qup-v2.2.1"; 512 reg = <0x078b8000 0x500>; 513 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 515 <&gcc GCC_BLSP1_AHB_CLK>; 516 clock-names = "core", "iface"; 517 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 518 dma-names = "rx", "tx"; 519 pinctrl-names = "default", "sleep"; 520 pinctrl-0 = <&spi4_default>; 521 pinctrl-1 = <&spi4_sleep>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 blsp_spi5: spi@78b9000 { 528 compatible = "qcom,spi-qup-v2.2.1"; 529 reg = <0x078b9000 0x500>; 530 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 532 <&gcc GCC_BLSP1_AHB_CLK>; 533 clock-names = "core", "iface"; 534 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 535 dma-names = "rx", "tx"; 536 pinctrl-names = "default", "sleep"; 537 pinctrl-0 = <&spi5_default>; 538 pinctrl-1 = <&spi5_sleep>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 blsp_spi6: spi@78ba000 { 545 compatible = "qcom,spi-qup-v2.2.1"; 546 reg = <0x078ba000 0x500>; 547 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 549 <&gcc GCC_BLSP1_AHB_CLK>; 550 clock-names = "core", "iface"; 551 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 552 dma-names = "rx", "tx"; 553 pinctrl-names = "default", "sleep"; 554 pinctrl-0 = <&spi6_default>; 555 pinctrl-1 = <&spi6_sleep>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 blsp_i2c2: i2c@78b6000 { 562 compatible = "qcom,i2c-qup-v2.2.1"; 563 reg = <0x078b6000 0x500>; 564 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 566 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 567 clock-names = "iface", "core"; 568 pinctrl-names = "default", "sleep"; 569 pinctrl-0 = <&i2c2_default>; 570 pinctrl-1 = <&i2c2_sleep>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 blsp_i2c4: i2c@78b8000 { 577 compatible = "qcom,i2c-qup-v2.2.1"; 578 reg = <0x078b8000 0x500>; 579 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 581 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 582 clock-names = "iface", "core"; 583 pinctrl-names = "default", "sleep"; 584 pinctrl-0 = <&i2c4_default>; 585 pinctrl-1 = <&i2c4_sleep>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 blsp_i2c6: i2c@78ba000 { 592 compatible = "qcom,i2c-qup-v2.2.1"; 593 reg = <0x078ba000 0x500>; 594 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 596 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 597 clock-names = "iface", "core"; 598 pinctrl-names = "default", "sleep"; 599 pinctrl-0 = <&i2c6_default>; 600 pinctrl-1 = <&i2c6_sleep>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 lpass: lpass@7708000 { 607 status = "disabled"; 608 compatible = "qcom,lpass-cpu-apq8016"; 609 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 610 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 611 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 612 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 613 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 614 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 615 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 616 617 clock-names = "ahbix-clk", 618 "pcnoc-mport-clk", 619 "pcnoc-sway-clk", 620 "mi2s-bit-clk0", 621 "mi2s-bit-clk1", 622 "mi2s-bit-clk2", 623 "mi2s-bit-clk3"; 624 #sound-dai-cells = <1>; 625 626 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "lpass-irq-lpaif"; 628 reg = <0x07708000 0x10000>; 629 reg-names = "lpass-lpaif"; 630 }; 631 632 lpass_codec: codec{ 633 compatible = "qcom,msm8916-wcd-digital-codec"; 634 reg = <0x0771c000 0x400>; 635 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 636 <&gcc GCC_CODEC_DIGCODEC_CLK>; 637 clock-names = "ahbix-clk", "mclk"; 638 #sound-dai-cells = <1>; 639 }; 640 641 sdhc_1: sdhci@7824000 { 642 compatible = "qcom,sdhci-msm-v4"; 643 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 644 reg-names = "hc_mem", "core_mem"; 645 646 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "hc_irq", "pwr_irq"; 648 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 649 <&gcc GCC_SDCC1_AHB_CLK>, 650 <&xo_board>; 651 clock-names = "core", "iface", "xo"; 652 mmc-ddr-1_8v; 653 bus-width = <8>; 654 non-removable; 655 status = "disabled"; 656 }; 657 658 sdhc_2: sdhci@7864000 { 659 compatible = "qcom,sdhci-msm-v4"; 660 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 661 reg-names = "hc_mem", "core_mem"; 662 663 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-names = "hc_irq", "pwr_irq"; 665 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 666 <&gcc GCC_SDCC2_AHB_CLK>, 667 <&xo_board>; 668 clock-names = "core", "iface", "xo"; 669 bus-width = <4>; 670 status = "disabled"; 671 }; 672 673 otg: usb@78d9000 { 674 compatible = "qcom,ci-hdrc"; 675 reg = <0x78d9000 0x200>, 676 <0x78d9200 0x200>; 677 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 680 <&gcc GCC_USB_HS_SYSTEM_CLK>; 681 clock-names = "iface", "core"; 682 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 683 assigned-clock-rates = <80000000>; 684 resets = <&gcc GCC_USB_HS_BCR>; 685 reset-names = "core"; 686 phy_type = "ulpi"; 687 dr_mode = "otg"; 688 ahb-burst-config = <0>; 689 phy-names = "usb-phy"; 690 phys = <&usb_hs_phy>; 691 status = "disabled"; 692 #reset-cells = <1>; 693 694 ulpi { 695 usb_hs_phy: phy { 696 compatible = "qcom,usb-hs-phy-msm8916", 697 "qcom,usb-hs-phy"; 698 #phy-cells = <0>; 699 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 700 clock-names = "ref", "sleep"; 701 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 702 reset-names = "phy", "por"; 703 qcom,init-seq = /bits/ 8 <0x0 0x44 704 0x1 0x6b 0x2 0x24 0x3 0x13>; 705 }; 706 }; 707 }; 708 709 intc: interrupt-controller@b000000 { 710 compatible = "qcom,msm-qgic2"; 711 interrupt-controller; 712 #interrupt-cells = <3>; 713 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 714 }; 715 716 timer@b020000 { 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges; 720 compatible = "arm,armv7-timer-mem"; 721 reg = <0xb020000 0x1000>; 722 clock-frequency = <19200000>; 723 724 frame@b021000 { 725 frame-number = <0>; 726 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 728 reg = <0xb021000 0x1000>, 729 <0xb022000 0x1000>; 730 }; 731 732 frame@b023000 { 733 frame-number = <1>; 734 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 735 reg = <0xb023000 0x1000>; 736 status = "disabled"; 737 }; 738 739 frame@b024000 { 740 frame-number = <2>; 741 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 742 reg = <0xb024000 0x1000>; 743 status = "disabled"; 744 }; 745 746 frame@b025000 { 747 frame-number = <3>; 748 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 749 reg = <0xb025000 0x1000>; 750 status = "disabled"; 751 }; 752 753 frame@b026000 { 754 frame-number = <4>; 755 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 756 reg = <0xb026000 0x1000>; 757 status = "disabled"; 758 }; 759 760 frame@b027000 { 761 frame-number = <5>; 762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 763 reg = <0xb027000 0x1000>; 764 status = "disabled"; 765 }; 766 767 frame@b028000 { 768 frame-number = <6>; 769 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 770 reg = <0xb028000 0x1000>; 771 status = "disabled"; 772 }; 773 }; 774 775 spmi_bus: spmi@200f000 { 776 compatible = "qcom,spmi-pmic-arb"; 777 reg = <0x200f000 0x001000>, 778 <0x2400000 0x400000>, 779 <0x2c00000 0x400000>, 780 <0x3800000 0x200000>, 781 <0x200a000 0x002100>; 782 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 783 interrupt-names = "periph_irq"; 784 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 785 qcom,ee = <0>; 786 qcom,channel = <0>; 787 #address-cells = <2>; 788 #size-cells = <0>; 789 interrupt-controller; 790 #interrupt-cells = <4>; 791 }; 792 793 rng@22000 { 794 compatible = "qcom,prng"; 795 reg = <0x00022000 0x200>; 796 clocks = <&gcc GCC_PRNG_AHB_CLK>; 797 clock-names = "core"; 798 }; 799 800 qfprom: qfprom@5c000 { 801 compatible = "qcom,qfprom"; 802 reg = <0x5c000 0x1000>; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 tsens_caldata: caldata@d0 { 806 reg = <0xd0 0x8>; 807 }; 808 tsens_calsel: calsel@ec { 809 reg = <0xec 0x4>; 810 }; 811 }; 812 813 tsens: thermal-sensor@4a9000 { 814 compatible = "qcom,msm8916-tsens"; 815 reg = <0x4a9000 0x1000>, /* TM */ 816 <0x4a8000 0x1000>; /* SROT */ 817 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 818 nvmem-cell-names = "calib", "calib_sel"; 819 #qcom,sensors = <5>; 820 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 821 interrupt-names = "uplow"; 822 #thermal-sensor-cells = <1>; 823 }; 824 825 apps_iommu: iommu@1ef0000 { 826 #address-cells = <1>; 827 #size-cells = <1>; 828 #iommu-cells = <1>; 829 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 830 ranges = <0 0x1e20000 0x40000>; 831 reg = <0x1ef0000 0x3000>; 832 clocks = <&gcc GCC_SMMU_CFG_CLK>, 833 <&gcc GCC_APSS_TCU_CLK>; 834 clock-names = "iface", "bus"; 835 qcom,iommu-secure-id = <17>; 836 837 // vfe: 838 iommu-ctx@3000 { 839 compatible = "qcom,msm-iommu-v1-sec"; 840 reg = <0x3000 0x1000>; 841 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 842 }; 843 844 // mdp_0: 845 iommu-ctx@4000 { 846 compatible = "qcom,msm-iommu-v1-ns"; 847 reg = <0x4000 0x1000>; 848 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 849 }; 850 851 // venus_ns: 852 iommu-ctx@5000 { 853 compatible = "qcom,msm-iommu-v1-sec"; 854 reg = <0x5000 0x1000>; 855 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 856 }; 857 }; 858 859 gpu_iommu: iommu@1f08000 { 860 #address-cells = <1>; 861 #size-cells = <1>; 862 #iommu-cells = <1>; 863 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 864 ranges = <0 0x1f08000 0x10000>; 865 clocks = <&gcc GCC_SMMU_CFG_CLK>, 866 <&gcc GCC_GFX_TCU_CLK>; 867 clock-names = "iface", "bus"; 868 qcom,iommu-secure-id = <18>; 869 870 // gfx3d_user: 871 iommu-ctx@1000 { 872 compatible = "qcom,msm-iommu-v1-ns"; 873 reg = <0x1000 0x1000>; 874 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 875 }; 876 877 // gfx3d_priv: 878 iommu-ctx@2000 { 879 compatible = "qcom,msm-iommu-v1-ns"; 880 reg = <0x2000 0x1000>; 881 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 882 }; 883 }; 884 885 gpu@1c00000 { 886 compatible = "qcom,adreno-306.0", "qcom,adreno"; 887 reg = <0x01c00000 0x20000>; 888 reg-names = "kgsl_3d0_reg_memory"; 889 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 890 interrupt-names = "kgsl_3d0_irq"; 891 clock-names = 892 "core", 893 "iface", 894 "mem", 895 "mem_iface", 896 "alt_mem_iface", 897 "gfx3d"; 898 clocks = 899 <&gcc GCC_OXILI_GFX3D_CLK>, 900 <&gcc GCC_OXILI_AHB_CLK>, 901 <&gcc GCC_OXILI_GMEM_CLK>, 902 <&gcc GCC_BIMC_GFX_CLK>, 903 <&gcc GCC_BIMC_GPU_CLK>, 904 <&gcc GFX3D_CLK_SRC>; 905 power-domains = <&gcc OXILI_GDSC>; 906 operating-points-v2 = <&gpu_opp_table>; 907 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 908 }; 909 910 mdss: mdss@1a00000 { 911 compatible = "qcom,mdss"; 912 reg = <0x1a00000 0x1000>, 913 <0x1ac8000 0x3000>; 914 reg-names = "mdss_phys", "vbif_phys"; 915 916 power-domains = <&gcc MDSS_GDSC>; 917 918 clocks = <&gcc GCC_MDSS_AHB_CLK>, 919 <&gcc GCC_MDSS_AXI_CLK>, 920 <&gcc GCC_MDSS_VSYNC_CLK>; 921 clock-names = "iface", 922 "bus", 923 "vsync"; 924 925 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 926 927 interrupt-controller; 928 #interrupt-cells = <1>; 929 930 #address-cells = <1>; 931 #size-cells = <1>; 932 ranges; 933 934 mdp: mdp@1a01000 { 935 compatible = "qcom,mdp5"; 936 reg = <0x1a01000 0x89000>; 937 reg-names = "mdp_phys"; 938 939 interrupt-parent = <&mdss>; 940 interrupts = <0 0>; 941 942 clocks = <&gcc GCC_MDSS_AHB_CLK>, 943 <&gcc GCC_MDSS_AXI_CLK>, 944 <&gcc GCC_MDSS_MDP_CLK>, 945 <&gcc GCC_MDSS_VSYNC_CLK>; 946 clock-names = "iface", 947 "bus", 948 "core", 949 "vsync"; 950 951 iommus = <&apps_iommu 4>; 952 953 ports { 954 #address-cells = <1>; 955 #size-cells = <0>; 956 957 port@0 { 958 reg = <0>; 959 mdp5_intf1_out: endpoint { 960 remote-endpoint = <&dsi0_in>; 961 }; 962 }; 963 }; 964 }; 965 966 dsi0: dsi@1a98000 { 967 compatible = "qcom,mdss-dsi-ctrl"; 968 reg = <0x1a98000 0x25c>; 969 reg-names = "dsi_ctrl"; 970 971 interrupt-parent = <&mdss>; 972 interrupts = <4 0>; 973 974 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 975 <&gcc PCLK0_CLK_SRC>; 976 assigned-clock-parents = <&dsi_phy0 0>, 977 <&dsi_phy0 1>; 978 979 clocks = <&gcc GCC_MDSS_MDP_CLK>, 980 <&gcc GCC_MDSS_AHB_CLK>, 981 <&gcc GCC_MDSS_AXI_CLK>, 982 <&gcc GCC_MDSS_BYTE0_CLK>, 983 <&gcc GCC_MDSS_PCLK0_CLK>, 984 <&gcc GCC_MDSS_ESC0_CLK>; 985 clock-names = "mdp_core", 986 "iface", 987 "bus", 988 "byte", 989 "pixel", 990 "core"; 991 phys = <&dsi_phy0>; 992 phy-names = "dsi-phy"; 993 994 ports { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 port@0 { 999 reg = <0>; 1000 dsi0_in: endpoint { 1001 remote-endpoint = <&mdp5_intf1_out>; 1002 }; 1003 }; 1004 1005 port@1 { 1006 reg = <1>; 1007 dsi0_out: endpoint { 1008 }; 1009 }; 1010 }; 1011 }; 1012 1013 dsi_phy0: dsi-phy@1a98300 { 1014 compatible = "qcom,dsi-phy-28nm-lp"; 1015 reg = <0x1a98300 0xd4>, 1016 <0x1a98500 0x280>, 1017 <0x1a98780 0x30>; 1018 reg-names = "dsi_pll", 1019 "dsi_phy", 1020 "dsi_phy_regulator"; 1021 1022 #clock-cells = <1>; 1023 #phy-cells = <0>; 1024 1025 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1026 <&xo_board>; 1027 clock-names = "iface", "ref"; 1028 }; 1029 }; 1030 1031 1032 hexagon@4080000 { 1033 compatible = "qcom,q6v5-pil"; 1034 reg = <0x04080000 0x100>, 1035 <0x04020000 0x040>; 1036 1037 reg-names = "qdsp6", "rmb"; 1038 1039 interrupts-extended = <&intc 0 24 1>, 1040 <&hexagon_smp2p_in 0 0>, 1041 <&hexagon_smp2p_in 1 0>, 1042 <&hexagon_smp2p_in 2 0>, 1043 <&hexagon_smp2p_in 3 0>; 1044 interrupt-names = "wdog", "fatal", "ready", 1045 "handover", "stop-ack"; 1046 1047 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1048 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1049 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1050 <&xo_board>; 1051 clock-names = "iface", "bus", "mem", "xo"; 1052 1053 qcom,smem-states = <&hexagon_smp2p_out 0>; 1054 qcom,smem-state-names = "stop"; 1055 1056 resets = <&scm 0>; 1057 reset-names = "mss_restart"; 1058 1059 cx-supply = <&pm8916_s1>; 1060 mx-supply = <&pm8916_l3>; 1061 pll-supply = <&pm8916_l7>; 1062 1063 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1064 1065 status = "disabled"; 1066 1067 mba { 1068 memory-region = <&mba_mem>; 1069 }; 1070 1071 mpss { 1072 memory-region = <&mpss_mem>; 1073 }; 1074 1075 smd-edge { 1076 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1077 1078 qcom,smd-edge = <0>; 1079 qcom,ipc = <&apcs 8 12>; 1080 qcom,remote-pid = <1>; 1081 1082 label = "hexagon"; 1083 }; 1084 }; 1085 1086 pronto: wcnss@a21b000 { 1087 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1088 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1089 reg-names = "ccu", "dxe", "pmu"; 1090 1091 memory-region = <&wcnss_mem>; 1092 1093 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, 1094 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1095 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1096 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1097 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1098 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1099 1100 vddmx-supply = <&pm8916_l3>; 1101 vddpx-supply = <&pm8916_l7>; 1102 1103 qcom,state = <&wcnss_smp2p_out 0>; 1104 qcom,state-names = "stop"; 1105 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&wcnss_pin_a>; 1108 1109 status = "disabled"; 1110 1111 iris { 1112 compatible = "qcom,wcn3620"; 1113 1114 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1115 clock-names = "xo"; 1116 1117 vddxo-supply = <&pm8916_l7>; 1118 vddrfa-supply = <&pm8916_s3>; 1119 vddpa-supply = <&pm8916_l9>; 1120 vdddig-supply = <&pm8916_l5>; 1121 }; 1122 1123 smd-edge { 1124 interrupts = <0 142 1>; 1125 1126 qcom,ipc = <&apcs 8 17>; 1127 qcom,smd-edge = <6>; 1128 qcom,remote-pid = <4>; 1129 1130 label = "pronto"; 1131 1132 wcnss { 1133 compatible = "qcom,wcnss"; 1134 qcom,smd-channels = "WCNSS_CTRL"; 1135 1136 qcom,mmio = <&pronto>; 1137 1138 bt { 1139 compatible = "qcom,wcnss-bt"; 1140 }; 1141 1142 wifi { 1143 compatible = "qcom,wcnss-wlan"; 1144 1145 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, 1146 <0 146 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "tx", "rx"; 1148 1149 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1150 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1151 }; 1152 }; 1153 }; 1154 }; 1155 1156 tpiu@820000 { 1157 compatible = "arm,coresight-tpiu", "arm,primecell"; 1158 reg = <0x820000 0x1000>; 1159 1160 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1161 clock-names = "apb_pclk", "atclk"; 1162 1163 in-ports { 1164 port { 1165 tpiu_in: endpoint { 1166 remote-endpoint = <&replicator_out1>; 1167 }; 1168 }; 1169 }; 1170 }; 1171 1172 funnel@821000 { 1173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1174 reg = <0x821000 0x1000>; 1175 1176 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1177 clock-names = "apb_pclk", "atclk"; 1178 1179 in-ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 /* 1184 * Not described input ports: 1185 * 0 - connected to Resource and Power Manger CPU ETM 1186 * 1 - not-connected 1187 * 2 - connected to Modem CPU ETM 1188 * 3 - not-connected 1189 * 5 - not-connected 1190 * 6 - connected trought funnel to Wireless CPU ETM 1191 * 7 - connected to STM component 1192 */ 1193 1194 port@4 { 1195 reg = <4>; 1196 funnel0_in4: endpoint { 1197 remote-endpoint = <&funnel1_out>; 1198 }; 1199 }; 1200 }; 1201 1202 out-ports { 1203 port { 1204 funnel0_out: endpoint { 1205 remote-endpoint = <&etf_in>; 1206 }; 1207 }; 1208 }; 1209 }; 1210 1211 replicator@824000 { 1212 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1213 reg = <0x824000 0x1000>; 1214 1215 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1216 clock-names = "apb_pclk", "atclk"; 1217 1218 out-ports { 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 port@0 { 1223 reg = <0>; 1224 replicator_out0: endpoint { 1225 remote-endpoint = <&etr_in>; 1226 }; 1227 }; 1228 port@1 { 1229 reg = <1>; 1230 replicator_out1: endpoint { 1231 remote-endpoint = <&tpiu_in>; 1232 }; 1233 }; 1234 }; 1235 1236 in-ports { 1237 port { 1238 replicator_in: endpoint { 1239 remote-endpoint = <&etf_out>; 1240 }; 1241 }; 1242 }; 1243 }; 1244 1245 etf@825000 { 1246 compatible = "arm,coresight-tmc", "arm,primecell"; 1247 reg = <0x825000 0x1000>; 1248 1249 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1250 clock-names = "apb_pclk", "atclk"; 1251 1252 in-ports { 1253 port { 1254 etf_in: endpoint { 1255 remote-endpoint = <&funnel0_out>; 1256 }; 1257 }; 1258 }; 1259 1260 out-ports { 1261 port { 1262 etf_out: endpoint { 1263 remote-endpoint = <&replicator_in>; 1264 }; 1265 }; 1266 }; 1267 }; 1268 1269 etr@826000 { 1270 compatible = "arm,coresight-tmc", "arm,primecell"; 1271 reg = <0x826000 0x1000>; 1272 1273 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1274 clock-names = "apb_pclk", "atclk"; 1275 1276 in-ports { 1277 port { 1278 etr_in: endpoint { 1279 remote-endpoint = <&replicator_out0>; 1280 }; 1281 }; 1282 }; 1283 }; 1284 1285 funnel@841000 { /* APSS funnel only 4 inputs are used */ 1286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1287 reg = <0x841000 0x1000>; 1288 1289 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1290 clock-names = "apb_pclk", "atclk"; 1291 1292 in-ports { 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 port@0 { 1297 reg = <0>; 1298 funnel1_in0: endpoint { 1299 remote-endpoint = <&etm0_out>; 1300 }; 1301 }; 1302 port@1 { 1303 reg = <1>; 1304 funnel1_in1: endpoint { 1305 remote-endpoint = <&etm1_out>; 1306 }; 1307 }; 1308 port@2 { 1309 reg = <2>; 1310 funnel1_in2: endpoint { 1311 remote-endpoint = <&etm2_out>; 1312 }; 1313 }; 1314 port@3 { 1315 reg = <3>; 1316 funnel1_in3: endpoint { 1317 remote-endpoint = <&etm3_out>; 1318 }; 1319 }; 1320 }; 1321 1322 out-ports { 1323 port { 1324 funnel1_out: endpoint { 1325 remote-endpoint = <&funnel0_in4>; 1326 }; 1327 }; 1328 }; 1329 }; 1330 1331 debug@850000 { 1332 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1333 reg = <0x850000 0x1000>; 1334 clocks = <&rpmcc RPM_QDSS_CLK>; 1335 clock-names = "apb_pclk"; 1336 cpu = <&CPU0>; 1337 }; 1338 1339 debug@852000 { 1340 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1341 reg = <0x852000 0x1000>; 1342 clocks = <&rpmcc RPM_QDSS_CLK>; 1343 clock-names = "apb_pclk"; 1344 cpu = <&CPU1>; 1345 }; 1346 1347 debug@854000 { 1348 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1349 reg = <0x854000 0x1000>; 1350 clocks = <&rpmcc RPM_QDSS_CLK>; 1351 clock-names = "apb_pclk"; 1352 cpu = <&CPU2>; 1353 }; 1354 1355 debug@856000 { 1356 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1357 reg = <0x856000 0x1000>; 1358 clocks = <&rpmcc RPM_QDSS_CLK>; 1359 clock-names = "apb_pclk"; 1360 cpu = <&CPU3>; 1361 }; 1362 1363 etm@85c000 { 1364 compatible = "arm,coresight-etm4x", "arm,primecell"; 1365 reg = <0x85c000 0x1000>; 1366 1367 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1368 clock-names = "apb_pclk", "atclk"; 1369 1370 cpu = <&CPU0>; 1371 1372 out-ports { 1373 port { 1374 etm0_out: endpoint { 1375 remote-endpoint = <&funnel1_in0>; 1376 }; 1377 }; 1378 }; 1379 }; 1380 1381 etm@85d000 { 1382 compatible = "arm,coresight-etm4x", "arm,primecell"; 1383 reg = <0x85d000 0x1000>; 1384 1385 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1386 clock-names = "apb_pclk", "atclk"; 1387 1388 cpu = <&CPU1>; 1389 1390 out-ports { 1391 port { 1392 etm1_out: endpoint { 1393 remote-endpoint = <&funnel1_in1>; 1394 }; 1395 }; 1396 }; 1397 }; 1398 1399 etm@85e000 { 1400 compatible = "arm,coresight-etm4x", "arm,primecell"; 1401 reg = <0x85e000 0x1000>; 1402 1403 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1404 clock-names = "apb_pclk", "atclk"; 1405 1406 cpu = <&CPU2>; 1407 1408 out-ports { 1409 port { 1410 etm2_out: endpoint { 1411 remote-endpoint = <&funnel1_in2>; 1412 }; 1413 }; 1414 }; 1415 }; 1416 1417 etm@85f000 { 1418 compatible = "arm,coresight-etm4x", "arm,primecell"; 1419 reg = <0x85f000 0x1000>; 1420 1421 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1422 clock-names = "apb_pclk", "atclk"; 1423 1424 cpu = <&CPU3>; 1425 1426 out-ports { 1427 port { 1428 etm3_out: endpoint { 1429 remote-endpoint = <&funnel1_in3>; 1430 }; 1431 }; 1432 }; 1433 }; 1434 1435 venus: video-codec@1d00000 { 1436 compatible = "qcom,msm8916-venus"; 1437 reg = <0x01d00000 0xff000>; 1438 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1439 power-domains = <&gcc VENUS_GDSC>; 1440 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1441 <&gcc GCC_VENUS0_AHB_CLK>, 1442 <&gcc GCC_VENUS0_AXI_CLK>; 1443 clock-names = "core", "iface", "bus"; 1444 iommus = <&apps_iommu 5>; 1445 memory-region = <&venus_mem>; 1446 status = "okay"; 1447 1448 video-decoder { 1449 compatible = "venus-decoder"; 1450 }; 1451 1452 video-encoder { 1453 compatible = "venus-encoder"; 1454 }; 1455 }; 1456 1457 camss: camss@1b00000 { 1458 compatible = "qcom,msm8916-camss"; 1459 reg = <0x1b0ac00 0x200>, 1460 <0x1b00030 0x4>, 1461 <0x1b0b000 0x200>, 1462 <0x1b00038 0x4>, 1463 <0x1b08000 0x100>, 1464 <0x1b08400 0x100>, 1465 <0x1b0a000 0x500>, 1466 <0x1b00020 0x10>, 1467 <0x1b10000 0x1000>; 1468 reg-names = "csiphy0", 1469 "csiphy0_clk_mux", 1470 "csiphy1", 1471 "csiphy1_clk_mux", 1472 "csid0", 1473 "csid1", 1474 "ispif", 1475 "csi_clk_mux", 1476 "vfe0"; 1477 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1478 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1479 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1480 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1481 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1482 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1483 interrupt-names = "csiphy0", 1484 "csiphy1", 1485 "csid0", 1486 "csid1", 1487 "ispif", 1488 "vfe0"; 1489 power-domains = <&gcc VFE_GDSC>; 1490 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1491 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1492 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1493 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1494 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1495 <&gcc GCC_CAMSS_CSI0_CLK>, 1496 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1497 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1498 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1499 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1500 <&gcc GCC_CAMSS_CSI1_CLK>, 1501 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1502 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1503 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1504 <&gcc GCC_CAMSS_AHB_CLK>, 1505 <&gcc GCC_CAMSS_VFE0_CLK>, 1506 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1507 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1508 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1509 clock-names = "top_ahb", 1510 "ispif_ahb", 1511 "csiphy0_timer", 1512 "csiphy1_timer", 1513 "csi0_ahb", 1514 "csi0", 1515 "csi0_phy", 1516 "csi0_pix", 1517 "csi0_rdi", 1518 "csi1_ahb", 1519 "csi1", 1520 "csi1_phy", 1521 "csi1_pix", 1522 "csi1_rdi", 1523 "ahb", 1524 "vfe0", 1525 "csi_vfe0", 1526 "vfe_ahb", 1527 "vfe_axi"; 1528 vdda-supply = <&pm8916_l2>; 1529 iommus = <&apps_iommu 3>; 1530 status = "disabled"; 1531 ports { 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 }; 1535 }; 1536 }; 1537 1538 smd { 1539 compatible = "qcom,smd"; 1540 1541 rpm { 1542 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1543 qcom,ipc = <&apcs 8 0>; 1544 qcom,smd-edge = <15>; 1545 1546 rpm_requests { 1547 compatible = "qcom,rpm-msm8916"; 1548 qcom,smd-channels = "rpm_requests"; 1549 1550 rpmcc: qcom,rpmcc { 1551 compatible = "qcom,rpmcc-msm8916"; 1552 #clock-cells = <1>; 1553 }; 1554 1555 smd_rpm_regulators: pm8916-regulators { 1556 compatible = "qcom,rpm-pm8916-regulators"; 1557 1558 pm8916_s1: s1 {}; 1559 pm8916_s3: s3 {}; 1560 pm8916_s4: s4 {}; 1561 1562 pm8916_l1: l1 {}; 1563 pm8916_l2: l2 {}; 1564 pm8916_l3: l3 {}; 1565 pm8916_l4: l4 {}; 1566 pm8916_l5: l5 {}; 1567 pm8916_l6: l6 {}; 1568 pm8916_l7: l7 {}; 1569 pm8916_l8: l8 {}; 1570 pm8916_l9: l9 {}; 1571 pm8916_l10: l10 {}; 1572 pm8916_l11: l11 {}; 1573 pm8916_l12: l12 {}; 1574 pm8916_l13: l13 {}; 1575 pm8916_l14: l14 {}; 1576 pm8916_l15: l15 {}; 1577 pm8916_l16: l16 {}; 1578 pm8916_l17: l17 {}; 1579 pm8916_l18: l18 {}; 1580 }; 1581 }; 1582 }; 1583 }; 1584 1585 hexagon-smp2p { 1586 compatible = "qcom,smp2p"; 1587 qcom,smem = <435>, <428>; 1588 1589 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 1590 1591 qcom,ipc = <&apcs 8 14>; 1592 1593 qcom,local-pid = <0>; 1594 qcom,remote-pid = <1>; 1595 1596 hexagon_smp2p_out: master-kernel { 1597 qcom,entry-name = "master-kernel"; 1598 1599 #qcom,smem-state-cells = <1>; 1600 }; 1601 1602 hexagon_smp2p_in: slave-kernel { 1603 qcom,entry-name = "slave-kernel"; 1604 1605 interrupt-controller; 1606 #interrupt-cells = <2>; 1607 }; 1608 }; 1609 1610 wcnss-smp2p { 1611 compatible = "qcom,smp2p"; 1612 qcom,smem = <451>, <431>; 1613 1614 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 1615 1616 qcom,ipc = <&apcs 8 18>; 1617 1618 qcom,local-pid = <0>; 1619 qcom,remote-pid = <4>; 1620 1621 wcnss_smp2p_out: master-kernel { 1622 qcom,entry-name = "master-kernel"; 1623 1624 #qcom,smem-state-cells = <1>; 1625 }; 1626 1627 wcnss_smp2p_in: slave-kernel { 1628 qcom,entry-name = "slave-kernel"; 1629 1630 interrupt-controller; 1631 #interrupt-cells = <2>; 1632 }; 1633 }; 1634 1635 smsm { 1636 compatible = "qcom,smsm"; 1637 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 qcom,ipc-1 = <&apcs 8 13>; 1642 qcom,ipc-3 = <&apcs 8 19>; 1643 1644 apps_smsm: apps@0 { 1645 reg = <0>; 1646 1647 #qcom,smem-state-cells = <1>; 1648 }; 1649 1650 hexagon_smsm: hexagon@1 { 1651 reg = <1>; 1652 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 1653 1654 interrupt-controller; 1655 #interrupt-cells = <2>; 1656 }; 1657 1658 wcnss_smsm: wcnss@6 { 1659 reg = <6>; 1660 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 1661 1662 interrupt-controller; 1663 #interrupt-cells = <2>; 1664 }; 1665 }; 1666}; 1667 1668#include "msm8916-pins.dtsi" 1669