1/* 2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-msm8916.h> 16#include <dt-bindings/reset/qcom,gcc-msm8916.h> 17#include <dt-bindings/clock/qcom,rpmcc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 28 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 29 }; 30 31 chosen { }; 32 33 memory { 34 device_type = "memory"; 35 /* We expect the bootloader to fill in the reg */ 36 reg = <0 0 0 0>; 37 }; 38 39 reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 tz-apps@86000000 { 45 reg = <0x0 0x86000000 0x0 0x300000>; 46 no-map; 47 }; 48 49 smem_mem: smem_region@86300000 { 50 reg = <0x0 0x86300000 0x0 0x100000>; 51 no-map; 52 }; 53 54 hypervisor@86400000 { 55 reg = <0x0 0x86400000 0x0 0x100000>; 56 no-map; 57 }; 58 59 tz@86500000 { 60 reg = <0x0 0x86500000 0x0 0x180000>; 61 no-map; 62 }; 63 64 reserved@8668000 { 65 reg = <0x0 0x86680000 0x0 0x80000>; 66 no-map; 67 }; 68 69 rmtfs@86700000 { 70 compatible = "qcom,rmtfs-mem"; 71 reg = <0x0 0x86700000 0x0 0xe0000>; 72 no-map; 73 74 qcom,client-id = <1>; 75 }; 76 77 rfsa@867e00000 { 78 reg = <0x0 0x867e0000 0x0 0x20000>; 79 no-map; 80 }; 81 82 mpss_mem: mpss@86800000 { 83 reg = <0x0 0x86800000 0x0 0x2b00000>; 84 no-map; 85 }; 86 87 wcnss_mem: wcnss@89300000 { 88 reg = <0x0 0x89300000 0x0 0x600000>; 89 no-map; 90 }; 91 92 venus_mem: venus@89900000 { 93 reg = <0x0 0x89900000 0x0 0x600000>; 94 no-map; 95 }; 96 97 mba_mem: mba@8ea00000 { 98 no-map; 99 reg = <0 0x8ea00000 0 0x100000>; 100 }; 101 }; 102 103 cpus { 104 #address-cells = <1>; 105 #size-cells = <0>; 106 107 CPU0: cpu@0 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a53", "arm,armv8"; 110 reg = <0x0>; 111 next-level-cache = <&L2_0>; 112 enable-method = "psci"; 113 cpu-idle-states = <&CPU_SPC>; 114 clocks = <&apcs 0>; 115 operating-points-v2 = <&cpu_opp_table>; 116 #cooling-cells = <2>; 117 }; 118 119 CPU1: cpu@1 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 reg = <0x1>; 123 next-level-cache = <&L2_0>; 124 enable-method = "psci"; 125 cpu-idle-states = <&CPU_SPC>; 126 clocks = <&apcs 0>; 127 operating-points-v2 = <&cpu_opp_table>; 128 #cooling-cells = <2>; 129 }; 130 131 CPU2: cpu@2 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a53", "arm,armv8"; 134 reg = <0x2>; 135 next-level-cache = <&L2_0>; 136 enable-method = "psci"; 137 cpu-idle-states = <&CPU_SPC>; 138 clocks = <&apcs 0>; 139 operating-points-v2 = <&cpu_opp_table>; 140 #cooling-cells = <2>; 141 }; 142 143 CPU3: cpu@3 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53", "arm,armv8"; 146 reg = <0x3>; 147 next-level-cache = <&L2_0>; 148 enable-method = "psci"; 149 cpu-idle-states = <&CPU_SPC>; 150 clocks = <&apcs 0>; 151 operating-points-v2 = <&cpu_opp_table>; 152 #cooling-cells = <2>; 153 }; 154 155 L2_0: l2-cache { 156 compatible = "cache"; 157 cache-level = <2>; 158 }; 159 160 idle-states { 161 CPU_SPC: spc { 162 compatible = "arm,idle-state"; 163 arm,psci-suspend-param = <0x40000002>; 164 entry-latency-us = <130>; 165 exit-latency-us = <150>; 166 min-residency-us = <2000>; 167 local-timer-stop; 168 }; 169 }; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a53-pmu"; 179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 180 }; 181 182 thermal-zones { 183 cpu-thermal0 { 184 polling-delay-passive = <250>; 185 polling-delay = <1000>; 186 187 thermal-sensors = <&tsens 4>; 188 189 trips { 190 cpu_alert0: trip0 { 191 temperature = <75000>; 192 hysteresis = <2000>; 193 type = "passive"; 194 }; 195 cpu_crit0: trip1 { 196 temperature = <110000>; 197 hysteresis = <2000>; 198 type = "critical"; 199 }; 200 }; 201 202 cooling-maps { 203 map0 { 204 trip = <&cpu_alert0>; 205 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 213 cpu-thermal1 { 214 polling-delay-passive = <250>; 215 polling-delay = <1000>; 216 217 thermal-sensors = <&tsens 3>; 218 219 trips { 220 cpu_alert1: trip0 { 221 temperature = <75000>; 222 hysteresis = <2000>; 223 type = "passive"; 224 }; 225 cpu_crit1: trip1 { 226 temperature = <110000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 232 cooling-maps { 233 map0 { 234 trip = <&cpu_alert1>; 235 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 239 }; 240 }; 241 }; 242 243 gpu-thermal { 244 polling-delay-passive = <250>; 245 polling-delay = <1000>; 246 247 thermal-sensors = <&tsens 2>; 248 249 trips { 250 gpu_alert: trip0 { 251 temperature = <75000>; 252 hysteresis = <2000>; 253 type = "passive"; 254 }; 255 gpu_crit: trip1 { 256 temperature = <95000>; 257 hysteresis = <2000>; 258 type = "critical"; 259 }; 260 }; 261 }; 262 263 camera-thermal { 264 polling-delay-passive = <250>; 265 polling-delay = <1000>; 266 267 thermal-sensors = <&tsens 1>; 268 269 trips { 270 cam_alert: trip0 { 271 temperature = <75000>; 272 hysteresis = <2000>; 273 type = "passive"; 274 }; 275 cam_crit: trip1 { 276 temperature = <95000>; 277 hysteresis = <2000>; 278 type = "critical"; 279 }; 280 }; 281 282 }; 283 284 }; 285 286 cpu_opp_table: cpu_opp_table { 287 compatible = "operating-points-v2"; 288 opp-shared; 289 290 opp-200000000 { 291 opp-hz = /bits/ 64 <200000000>; 292 }; 293 opp-400000000 { 294 opp-hz = /bits/ 64 <400000000>; 295 }; 296 opp-800000000 { 297 opp-hz = /bits/ 64 <800000000>; 298 }; 299 opp-998400000 { 300 opp-hz = /bits/ 64 <998400000>; 301 }; 302 }; 303 304 gpu_opp_table: opp_table { 305 compatible = "operating-points-v2"; 306 307 opp-400000000 { 308 opp-hz = /bits/ 64 <400000000>; 309 }; 310 opp-19200000 { 311 opp-hz = /bits/ 64 <19200000>; 312 }; 313 }; 314 315 timer { 316 compatible = "arm,armv8-timer"; 317 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 318 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 319 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 320 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 321 }; 322 323 clocks { 324 xo_board: xo_board { 325 compatible = "fixed-clock"; 326 #clock-cells = <0>; 327 clock-frequency = <19200000>; 328 }; 329 330 sleep_clk: sleep_clk { 331 compatible = "fixed-clock"; 332 #clock-cells = <0>; 333 clock-frequency = <32768>; 334 }; 335 }; 336 337 smem { 338 compatible = "qcom,smem"; 339 340 memory-region = <&smem_mem>; 341 qcom,rpm-msg-ram = <&rpm_msg_ram>; 342 343 hwlocks = <&tcsr_mutex 3>; 344 }; 345 346 firmware { 347 scm: scm { 348 compatible = "qcom,scm"; 349 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 350 clock-names = "core", "bus", "iface"; 351 #reset-cells = <1>; 352 353 qcom,dload-mode = <&tcsr 0x6100>; 354 }; 355 }; 356 357 soc: soc { 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0 0 0 0xffffffff>; 361 compatible = "simple-bus"; 362 363 restart@4ab000 { 364 compatible = "qcom,pshold"; 365 reg = <0x4ab000 0x4>; 366 }; 367 368 msmgpio: pinctrl@1000000 { 369 compatible = "qcom,msm8916-pinctrl"; 370 reg = <0x1000000 0x300000>; 371 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 }; 377 378 gcc: clock-controller@1800000 { 379 compatible = "qcom,gcc-msm8916"; 380 #clock-cells = <1>; 381 #reset-cells = <1>; 382 #power-domain-cells = <1>; 383 reg = <0x1800000 0x80000>; 384 }; 385 386 tcsr_mutex_regs: syscon@1905000 { 387 compatible = "syscon"; 388 reg = <0x1905000 0x20000>; 389 }; 390 391 tcsr: syscon@1937000 { 392 compatible = "qcom,tcsr-msm8916", "syscon"; 393 reg = <0x1937000 0x30000>; 394 }; 395 396 tcsr_mutex: hwlock { 397 compatible = "qcom,tcsr-mutex"; 398 syscon = <&tcsr_mutex_regs 0 0x1000>; 399 #hwlock-cells = <1>; 400 }; 401 402 rpm_msg_ram: memory@60000 { 403 compatible = "qcom,rpm-msg-ram"; 404 reg = <0x60000 0x8000>; 405 }; 406 407 blsp1_uart1: serial@78af000 { 408 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 409 reg = <0x78af000 0x200>; 410 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 412 clock-names = "core", "iface"; 413 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 414 dma-names = "rx", "tx"; 415 status = "disabled"; 416 }; 417 418 a53pll: clock@b016000 { 419 compatible = "qcom,msm8916-a53pll"; 420 reg = <0xb016000 0x40>; 421 #clock-cells = <0>; 422 }; 423 424 apcs: mailbox@b011000 { 425 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 426 reg = <0xb011000 0x1000>; 427 #mbox-cells = <1>; 428 clocks = <&a53pll>; 429 #clock-cells = <0>; 430 }; 431 432 blsp1_uart2: serial@78b0000 { 433 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 434 reg = <0x78b0000 0x200>; 435 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 437 clock-names = "core", "iface"; 438 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 439 dma-names = "rx", "tx"; 440 status = "disabled"; 441 }; 442 443 blsp_dma: dma@7884000 { 444 compatible = "qcom,bam-v1.7.0"; 445 reg = <0x07884000 0x23000>; 446 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 448 clock-names = "bam_clk"; 449 #dma-cells = <1>; 450 qcom,ee = <0>; 451 status = "disabled"; 452 }; 453 454 blsp_spi1: spi@78b5000 { 455 compatible = "qcom,spi-qup-v2.2.1"; 456 reg = <0x078b5000 0x500>; 457 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 459 <&gcc GCC_BLSP1_AHB_CLK>; 460 clock-names = "core", "iface"; 461 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 462 dma-names = "rx", "tx"; 463 pinctrl-names = "default", "sleep"; 464 pinctrl-0 = <&spi1_default>; 465 pinctrl-1 = <&spi1_sleep>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 status = "disabled"; 469 }; 470 471 blsp_spi2: spi@78b6000 { 472 compatible = "qcom,spi-qup-v2.2.1"; 473 reg = <0x078b6000 0x500>; 474 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 476 <&gcc GCC_BLSP1_AHB_CLK>; 477 clock-names = "core", "iface"; 478 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 479 dma-names = "rx", "tx"; 480 pinctrl-names = "default", "sleep"; 481 pinctrl-0 = <&spi2_default>; 482 pinctrl-1 = <&spi2_sleep>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 blsp_spi3: spi@78b7000 { 489 compatible = "qcom,spi-qup-v2.2.1"; 490 reg = <0x078b7000 0x500>; 491 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 493 <&gcc GCC_BLSP1_AHB_CLK>; 494 clock-names = "core", "iface"; 495 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 496 dma-names = "rx", "tx"; 497 pinctrl-names = "default", "sleep"; 498 pinctrl-0 = <&spi3_default>; 499 pinctrl-1 = <&spi3_sleep>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 status = "disabled"; 503 }; 504 505 blsp_spi4: spi@78b8000 { 506 compatible = "qcom,spi-qup-v2.2.1"; 507 reg = <0x078b8000 0x500>; 508 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 510 <&gcc GCC_BLSP1_AHB_CLK>; 511 clock-names = "core", "iface"; 512 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 513 dma-names = "rx", "tx"; 514 pinctrl-names = "default", "sleep"; 515 pinctrl-0 = <&spi4_default>; 516 pinctrl-1 = <&spi4_sleep>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 blsp_spi5: spi@78b9000 { 523 compatible = "qcom,spi-qup-v2.2.1"; 524 reg = <0x078b9000 0x500>; 525 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 527 <&gcc GCC_BLSP1_AHB_CLK>; 528 clock-names = "core", "iface"; 529 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 530 dma-names = "rx", "tx"; 531 pinctrl-names = "default", "sleep"; 532 pinctrl-0 = <&spi5_default>; 533 pinctrl-1 = <&spi5_sleep>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 539 blsp_spi6: spi@78ba000 { 540 compatible = "qcom,spi-qup-v2.2.1"; 541 reg = <0x078ba000 0x500>; 542 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 547 dma-names = "rx", "tx"; 548 pinctrl-names = "default", "sleep"; 549 pinctrl-0 = <&spi6_default>; 550 pinctrl-1 = <&spi6_sleep>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 blsp_i2c2: i2c@78b6000 { 557 compatible = "qcom,i2c-qup-v2.2.1"; 558 reg = <0x078b6000 0x500>; 559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 561 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 562 clock-names = "iface", "core"; 563 pinctrl-names = "default", "sleep"; 564 pinctrl-0 = <&i2c2_default>; 565 pinctrl-1 = <&i2c2_sleep>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 blsp_i2c4: i2c@78b8000 { 572 compatible = "qcom,i2c-qup-v2.2.1"; 573 reg = <0x078b8000 0x500>; 574 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 576 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 577 clock-names = "iface", "core"; 578 pinctrl-names = "default", "sleep"; 579 pinctrl-0 = <&i2c4_default>; 580 pinctrl-1 = <&i2c4_sleep>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 status = "disabled"; 584 }; 585 586 blsp_i2c6: i2c@78ba000 { 587 compatible = "qcom,i2c-qup-v2.2.1"; 588 reg = <0x078ba000 0x500>; 589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 591 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 592 clock-names = "iface", "core"; 593 pinctrl-names = "default", "sleep"; 594 pinctrl-0 = <&i2c6_default>; 595 pinctrl-1 = <&i2c6_sleep>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 lpass: lpass@7708000 { 602 status = "disabled"; 603 compatible = "qcom,lpass-cpu-apq8016"; 604 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 605 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 606 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 607 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 608 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 609 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 610 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 611 612 clock-names = "ahbix-clk", 613 "pcnoc-mport-clk", 614 "pcnoc-sway-clk", 615 "mi2s-bit-clk0", 616 "mi2s-bit-clk1", 617 "mi2s-bit-clk2", 618 "mi2s-bit-clk3"; 619 #sound-dai-cells = <1>; 620 621 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "lpass-irq-lpaif"; 623 reg = <0x07708000 0x10000>; 624 reg-names = "lpass-lpaif"; 625 }; 626 627 lpass_codec: codec{ 628 compatible = "qcom,msm8916-wcd-digital-codec"; 629 reg = <0x0771c000 0x400>; 630 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 631 <&gcc GCC_CODEC_DIGCODEC_CLK>; 632 clock-names = "ahbix-clk", "mclk"; 633 #sound-dai-cells = <1>; 634 }; 635 636 sdhc_1: sdhci@7824000 { 637 compatible = "qcom,sdhci-msm-v4"; 638 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 639 reg-names = "hc_mem", "core_mem"; 640 641 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "hc_irq", "pwr_irq"; 643 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 644 <&gcc GCC_SDCC1_AHB_CLK>, 645 <&xo_board>; 646 clock-names = "core", "iface", "xo"; 647 mmc-ddr-1_8v; 648 bus-width = <8>; 649 non-removable; 650 status = "disabled"; 651 }; 652 653 sdhc_2: sdhci@7864000 { 654 compatible = "qcom,sdhci-msm-v4"; 655 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 656 reg-names = "hc_mem", "core_mem"; 657 658 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "hc_irq", "pwr_irq"; 660 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 661 <&gcc GCC_SDCC2_AHB_CLK>, 662 <&xo_board>; 663 clock-names = "core", "iface", "xo"; 664 bus-width = <4>; 665 status = "disabled"; 666 }; 667 668 otg: usb@78d9000 { 669 compatible = "qcom,ci-hdrc"; 670 reg = <0x78d9000 0x200>, 671 <0x78d9200 0x200>; 672 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 675 <&gcc GCC_USB_HS_SYSTEM_CLK>; 676 clock-names = "iface", "core"; 677 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 678 assigned-clock-rates = <80000000>; 679 resets = <&gcc GCC_USB_HS_BCR>; 680 reset-names = "core"; 681 phy_type = "ulpi"; 682 dr_mode = "otg"; 683 ahb-burst-config = <0>; 684 phy-names = "usb-phy"; 685 phys = <&usb_hs_phy>; 686 status = "disabled"; 687 #reset-cells = <1>; 688 689 ulpi { 690 usb_hs_phy: phy { 691 compatible = "qcom,usb-hs-phy-msm8916", 692 "qcom,usb-hs-phy"; 693 #phy-cells = <0>; 694 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 695 clock-names = "ref", "sleep"; 696 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 697 reset-names = "phy", "por"; 698 qcom,init-seq = /bits/ 8 <0x0 0x44 699 0x1 0x6b 0x2 0x24 0x3 0x13>; 700 }; 701 }; 702 }; 703 704 intc: interrupt-controller@b000000 { 705 compatible = "qcom,msm-qgic2"; 706 interrupt-controller; 707 #interrupt-cells = <3>; 708 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 709 }; 710 711 timer@b020000 { 712 #address-cells = <1>; 713 #size-cells = <1>; 714 ranges; 715 compatible = "arm,armv7-timer-mem"; 716 reg = <0xb020000 0x1000>; 717 clock-frequency = <19200000>; 718 719 frame@b021000 { 720 frame-number = <0>; 721 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 723 reg = <0xb021000 0x1000>, 724 <0xb022000 0x1000>; 725 }; 726 727 frame@b023000 { 728 frame-number = <1>; 729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 730 reg = <0xb023000 0x1000>; 731 status = "disabled"; 732 }; 733 734 frame@b024000 { 735 frame-number = <2>; 736 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 737 reg = <0xb024000 0x1000>; 738 status = "disabled"; 739 }; 740 741 frame@b025000 { 742 frame-number = <3>; 743 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 744 reg = <0xb025000 0x1000>; 745 status = "disabled"; 746 }; 747 748 frame@b026000 { 749 frame-number = <4>; 750 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 751 reg = <0xb026000 0x1000>; 752 status = "disabled"; 753 }; 754 755 frame@b027000 { 756 frame-number = <5>; 757 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 758 reg = <0xb027000 0x1000>; 759 status = "disabled"; 760 }; 761 762 frame@b028000 { 763 frame-number = <6>; 764 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 765 reg = <0xb028000 0x1000>; 766 status = "disabled"; 767 }; 768 }; 769 770 spmi_bus: spmi@200f000 { 771 compatible = "qcom,spmi-pmic-arb"; 772 reg = <0x200f000 0x001000>, 773 <0x2400000 0x400000>, 774 <0x2c00000 0x400000>, 775 <0x3800000 0x200000>, 776 <0x200a000 0x002100>; 777 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 778 interrupt-names = "periph_irq"; 779 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 780 qcom,ee = <0>; 781 qcom,channel = <0>; 782 #address-cells = <2>; 783 #size-cells = <0>; 784 interrupt-controller; 785 #interrupt-cells = <4>; 786 }; 787 788 rng@22000 { 789 compatible = "qcom,prng"; 790 reg = <0x00022000 0x200>; 791 clocks = <&gcc GCC_PRNG_AHB_CLK>; 792 clock-names = "core"; 793 }; 794 795 qfprom: qfprom@5c000 { 796 compatible = "qcom,qfprom"; 797 reg = <0x5c000 0x1000>; 798 #address-cells = <1>; 799 #size-cells = <1>; 800 tsens_caldata: caldata@d0 { 801 reg = <0xd0 0x8>; 802 }; 803 tsens_calsel: calsel@ec { 804 reg = <0xec 0x4>; 805 }; 806 }; 807 808 tsens: thermal-sensor@4a9000 { 809 compatible = "qcom,msm8916-tsens"; 810 reg = <0x4a9000 0x1000>, /* TM */ 811 <0x4a8000 0x1000>; /* SROT */ 812 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 813 nvmem-cell-names = "calib", "calib_sel"; 814 #qcom,sensors = <5>; 815 #thermal-sensor-cells = <1>; 816 }; 817 818 apps_iommu: iommu@1ef0000 { 819 #address-cells = <1>; 820 #size-cells = <1>; 821 #iommu-cells = <1>; 822 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 823 ranges = <0 0x1e20000 0x40000>; 824 reg = <0x1ef0000 0x3000>; 825 clocks = <&gcc GCC_SMMU_CFG_CLK>, 826 <&gcc GCC_APSS_TCU_CLK>; 827 clock-names = "iface", "bus"; 828 qcom,iommu-secure-id = <17>; 829 830 // vfe: 831 iommu-ctx@3000 { 832 compatible = "qcom,msm-iommu-v1-sec"; 833 reg = <0x3000 0x1000>; 834 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 835 }; 836 837 // mdp_0: 838 iommu-ctx@4000 { 839 compatible = "qcom,msm-iommu-v1-ns"; 840 reg = <0x4000 0x1000>; 841 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 842 }; 843 844 // venus_ns: 845 iommu-ctx@5000 { 846 compatible = "qcom,msm-iommu-v1-sec"; 847 reg = <0x5000 0x1000>; 848 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 849 }; 850 }; 851 852 gpu_iommu: iommu@1f08000 { 853 #address-cells = <1>; 854 #size-cells = <1>; 855 #iommu-cells = <1>; 856 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 857 ranges = <0 0x1f08000 0x10000>; 858 clocks = <&gcc GCC_SMMU_CFG_CLK>, 859 <&gcc GCC_GFX_TCU_CLK>; 860 clock-names = "iface", "bus"; 861 qcom,iommu-secure-id = <18>; 862 863 // gfx3d_user: 864 iommu-ctx@1000 { 865 compatible = "qcom,msm-iommu-v1-ns"; 866 reg = <0x1000 0x1000>; 867 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 868 }; 869 870 // gfx3d_priv: 871 iommu-ctx@2000 { 872 compatible = "qcom,msm-iommu-v1-ns"; 873 reg = <0x2000 0x1000>; 874 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 875 }; 876 }; 877 878 gpu@1c00000 { 879 compatible = "qcom,adreno-306.0", "qcom,adreno"; 880 reg = <0x01c00000 0x20000>; 881 reg-names = "kgsl_3d0_reg_memory"; 882 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "kgsl_3d0_irq"; 884 clock-names = 885 "core", 886 "iface", 887 "mem", 888 "mem_iface", 889 "alt_mem_iface", 890 "gfx3d"; 891 clocks = 892 <&gcc GCC_OXILI_GFX3D_CLK>, 893 <&gcc GCC_OXILI_AHB_CLK>, 894 <&gcc GCC_OXILI_GMEM_CLK>, 895 <&gcc GCC_BIMC_GFX_CLK>, 896 <&gcc GCC_BIMC_GPU_CLK>, 897 <&gcc GFX3D_CLK_SRC>; 898 power-domains = <&gcc OXILI_GDSC>; 899 operating-points-v2 = <&gpu_opp_table>; 900 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 901 }; 902 903 mdss: mdss@1a00000 { 904 compatible = "qcom,mdss"; 905 reg = <0x1a00000 0x1000>, 906 <0x1ac8000 0x3000>; 907 reg-names = "mdss_phys", "vbif_phys"; 908 909 power-domains = <&gcc MDSS_GDSC>; 910 911 clocks = <&gcc GCC_MDSS_AHB_CLK>, 912 <&gcc GCC_MDSS_AXI_CLK>, 913 <&gcc GCC_MDSS_VSYNC_CLK>; 914 clock-names = "iface", 915 "bus", 916 "vsync"; 917 918 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 919 920 interrupt-controller; 921 #interrupt-cells = <1>; 922 923 #address-cells = <1>; 924 #size-cells = <1>; 925 ranges; 926 927 mdp: mdp@1a01000 { 928 compatible = "qcom,mdp5"; 929 reg = <0x1a01000 0x89000>; 930 reg-names = "mdp_phys"; 931 932 interrupt-parent = <&mdss>; 933 interrupts = <0 0>; 934 935 clocks = <&gcc GCC_MDSS_AHB_CLK>, 936 <&gcc GCC_MDSS_AXI_CLK>, 937 <&gcc GCC_MDSS_MDP_CLK>, 938 <&gcc GCC_MDSS_VSYNC_CLK>; 939 clock-names = "iface", 940 "bus", 941 "core", 942 "vsync"; 943 944 iommus = <&apps_iommu 4>; 945 946 ports { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 port@0 { 951 reg = <0>; 952 mdp5_intf1_out: endpoint { 953 remote-endpoint = <&dsi0_in>; 954 }; 955 }; 956 }; 957 }; 958 959 dsi0: dsi@1a98000 { 960 compatible = "qcom,mdss-dsi-ctrl"; 961 reg = <0x1a98000 0x25c>; 962 reg-names = "dsi_ctrl"; 963 964 interrupt-parent = <&mdss>; 965 interrupts = <4 0>; 966 967 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 968 <&gcc PCLK0_CLK_SRC>; 969 assigned-clock-parents = <&dsi_phy0 0>, 970 <&dsi_phy0 1>; 971 972 clocks = <&gcc GCC_MDSS_MDP_CLK>, 973 <&gcc GCC_MDSS_AHB_CLK>, 974 <&gcc GCC_MDSS_AXI_CLK>, 975 <&gcc GCC_MDSS_BYTE0_CLK>, 976 <&gcc GCC_MDSS_PCLK0_CLK>, 977 <&gcc GCC_MDSS_ESC0_CLK>; 978 clock-names = "mdp_core", 979 "iface", 980 "bus", 981 "byte", 982 "pixel", 983 "core"; 984 phys = <&dsi_phy0>; 985 phy-names = "dsi-phy"; 986 987 ports { 988 #address-cells = <1>; 989 #size-cells = <0>; 990 991 port@0 { 992 reg = <0>; 993 dsi0_in: endpoint { 994 remote-endpoint = <&mdp5_intf1_out>; 995 }; 996 }; 997 998 port@1 { 999 reg = <1>; 1000 dsi0_out: endpoint { 1001 }; 1002 }; 1003 }; 1004 }; 1005 1006 dsi_phy0: dsi-phy@1a98300 { 1007 compatible = "qcom,dsi-phy-28nm-lp"; 1008 reg = <0x1a98300 0xd4>, 1009 <0x1a98500 0x280>, 1010 <0x1a98780 0x30>; 1011 reg-names = "dsi_pll", 1012 "dsi_phy", 1013 "dsi_phy_regulator"; 1014 1015 #clock-cells = <1>; 1016 #phy-cells = <0>; 1017 1018 clocks = <&gcc GCC_MDSS_AHB_CLK>; 1019 clock-names = "iface"; 1020 }; 1021 }; 1022 1023 1024 hexagon@4080000 { 1025 compatible = "qcom,q6v5-pil"; 1026 reg = <0x04080000 0x100>, 1027 <0x04020000 0x040>; 1028 1029 reg-names = "qdsp6", "rmb"; 1030 1031 interrupts-extended = <&intc 0 24 1>, 1032 <&hexagon_smp2p_in 0 0>, 1033 <&hexagon_smp2p_in 1 0>, 1034 <&hexagon_smp2p_in 2 0>, 1035 <&hexagon_smp2p_in 3 0>; 1036 interrupt-names = "wdog", "fatal", "ready", 1037 "handover", "stop-ack"; 1038 1039 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1040 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1041 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1042 <&xo_board>; 1043 clock-names = "iface", "bus", "mem", "xo"; 1044 1045 qcom,smem-states = <&hexagon_smp2p_out 0>; 1046 qcom,smem-state-names = "stop"; 1047 1048 resets = <&scm 0>; 1049 reset-names = "mss_restart"; 1050 1051 cx-supply = <&pm8916_s1>; 1052 mx-supply = <&pm8916_l3>; 1053 pll-supply = <&pm8916_l7>; 1054 1055 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1056 1057 status = "disabled"; 1058 1059 mba { 1060 memory-region = <&mba_mem>; 1061 }; 1062 1063 mpss { 1064 memory-region = <&mpss_mem>; 1065 }; 1066 1067 smd-edge { 1068 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1069 1070 qcom,smd-edge = <0>; 1071 qcom,ipc = <&apcs 8 12>; 1072 qcom,remote-pid = <1>; 1073 1074 label = "hexagon"; 1075 }; 1076 }; 1077 1078 pronto: wcnss@a21b000 { 1079 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1080 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1081 reg-names = "ccu", "dxe", "pmu"; 1082 1083 memory-region = <&wcnss_mem>; 1084 1085 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, 1086 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1087 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1088 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1089 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1090 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1091 1092 vddmx-supply = <&pm8916_l3>; 1093 vddpx-supply = <&pm8916_l7>; 1094 1095 qcom,state = <&wcnss_smp2p_out 0>; 1096 qcom,state-names = "stop"; 1097 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&wcnss_pin_a>; 1100 1101 status = "disabled"; 1102 1103 iris { 1104 compatible = "qcom,wcn3620"; 1105 1106 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1107 clock-names = "xo"; 1108 1109 vddxo-supply = <&pm8916_l7>; 1110 vddrfa-supply = <&pm8916_s3>; 1111 vddpa-supply = <&pm8916_l9>; 1112 vdddig-supply = <&pm8916_l5>; 1113 }; 1114 1115 smd-edge { 1116 interrupts = <0 142 1>; 1117 1118 qcom,ipc = <&apcs 8 17>; 1119 qcom,smd-edge = <6>; 1120 qcom,remote-pid = <4>; 1121 1122 label = "pronto"; 1123 1124 wcnss { 1125 compatible = "qcom,wcnss"; 1126 qcom,smd-channels = "WCNSS_CTRL"; 1127 1128 qcom,mmio = <&pronto>; 1129 1130 bt { 1131 compatible = "qcom,wcnss-bt"; 1132 }; 1133 1134 wifi { 1135 compatible = "qcom,wcnss-wlan"; 1136 1137 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, 1138 <0 146 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "tx", "rx"; 1140 1141 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1142 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1143 }; 1144 }; 1145 }; 1146 }; 1147 1148 tpiu@820000 { 1149 compatible = "arm,coresight-tpiu", "arm,primecell"; 1150 reg = <0x820000 0x1000>; 1151 1152 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1153 clock-names = "apb_pclk", "atclk"; 1154 1155 in-ports { 1156 port { 1157 tpiu_in: endpoint { 1158 remote-endpoint = <&replicator_out1>; 1159 }; 1160 }; 1161 }; 1162 }; 1163 1164 funnel@821000 { 1165 compatible = "arm,coresight-funnel", "arm,primecell"; 1166 reg = <0x821000 0x1000>; 1167 1168 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1169 clock-names = "apb_pclk", "atclk"; 1170 1171 in-ports { 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 /* 1176 * Not described input ports: 1177 * 0 - connected to Resource and Power Manger CPU ETM 1178 * 1 - not-connected 1179 * 2 - connected to Modem CPU ETM 1180 * 3 - not-connected 1181 * 5 - not-connected 1182 * 6 - connected trought funnel to Wireless CPU ETM 1183 * 7 - connected to STM component 1184 */ 1185 1186 port@4 { 1187 reg = <4>; 1188 funnel0_in4: endpoint { 1189 remote-endpoint = <&funnel1_out>; 1190 }; 1191 }; 1192 }; 1193 1194 out-ports { 1195 port { 1196 funnel0_out: endpoint { 1197 remote-endpoint = <&etf_in>; 1198 }; 1199 }; 1200 }; 1201 }; 1202 1203 replicator@824000 { 1204 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1205 reg = <0x824000 0x1000>; 1206 1207 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1208 clock-names = "apb_pclk", "atclk"; 1209 1210 out-ports { 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 port@0 { 1215 reg = <0>; 1216 replicator_out0: endpoint { 1217 remote-endpoint = <&etr_in>; 1218 }; 1219 }; 1220 port@1 { 1221 reg = <1>; 1222 replicator_out1: endpoint { 1223 remote-endpoint = <&tpiu_in>; 1224 }; 1225 }; 1226 }; 1227 1228 in-ports { 1229 port { 1230 replicator_in: endpoint { 1231 remote-endpoint = <&etf_out>; 1232 }; 1233 }; 1234 }; 1235 }; 1236 1237 etf@825000 { 1238 compatible = "arm,coresight-tmc", "arm,primecell"; 1239 reg = <0x825000 0x1000>; 1240 1241 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1242 clock-names = "apb_pclk", "atclk"; 1243 1244 in-ports { 1245 port { 1246 etf_in: endpoint { 1247 remote-endpoint = <&funnel0_out>; 1248 }; 1249 }; 1250 }; 1251 1252 out-ports { 1253 port { 1254 etf_out: endpoint { 1255 remote-endpoint = <&replicator_in>; 1256 }; 1257 }; 1258 }; 1259 }; 1260 1261 etr@826000 { 1262 compatible = "arm,coresight-tmc", "arm,primecell"; 1263 reg = <0x826000 0x1000>; 1264 1265 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1266 clock-names = "apb_pclk", "atclk"; 1267 1268 in-ports { 1269 port { 1270 etr_in: endpoint { 1271 remote-endpoint = <&replicator_out0>; 1272 }; 1273 }; 1274 }; 1275 }; 1276 1277 funnel@841000 { /* APSS funnel only 4 inputs are used */ 1278 compatible = "arm,coresight-funnel", "arm,primecell"; 1279 reg = <0x841000 0x1000>; 1280 1281 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1282 clock-names = "apb_pclk", "atclk"; 1283 1284 in-ports { 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 1288 port@0 { 1289 reg = <0>; 1290 funnel1_in0: endpoint { 1291 remote-endpoint = <&etm0_out>; 1292 }; 1293 }; 1294 port@1 { 1295 reg = <1>; 1296 funnel1_in1: endpoint { 1297 remote-endpoint = <&etm1_out>; 1298 }; 1299 }; 1300 port@2 { 1301 reg = <2>; 1302 funnel1_in2: endpoint { 1303 remote-endpoint = <&etm2_out>; 1304 }; 1305 }; 1306 port@3 { 1307 reg = <3>; 1308 funnel1_in3: endpoint { 1309 remote-endpoint = <&etm3_out>; 1310 }; 1311 }; 1312 }; 1313 1314 out-ports { 1315 port { 1316 funnel1_out: endpoint { 1317 remote-endpoint = <&funnel0_in4>; 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 debug@850000 { 1324 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1325 reg = <0x850000 0x1000>; 1326 clocks = <&rpmcc RPM_QDSS_CLK>; 1327 clock-names = "apb_pclk"; 1328 cpu = <&CPU0>; 1329 }; 1330 1331 debug@852000 { 1332 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1333 reg = <0x852000 0x1000>; 1334 clocks = <&rpmcc RPM_QDSS_CLK>; 1335 clock-names = "apb_pclk"; 1336 cpu = <&CPU1>; 1337 }; 1338 1339 debug@854000 { 1340 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1341 reg = <0x854000 0x1000>; 1342 clocks = <&rpmcc RPM_QDSS_CLK>; 1343 clock-names = "apb_pclk"; 1344 cpu = <&CPU2>; 1345 }; 1346 1347 debug@856000 { 1348 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1349 reg = <0x856000 0x1000>; 1350 clocks = <&rpmcc RPM_QDSS_CLK>; 1351 clock-names = "apb_pclk"; 1352 cpu = <&CPU3>; 1353 }; 1354 1355 etm@85c000 { 1356 compatible = "arm,coresight-etm4x", "arm,primecell"; 1357 reg = <0x85c000 0x1000>; 1358 1359 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1360 clock-names = "apb_pclk", "atclk"; 1361 1362 cpu = <&CPU0>; 1363 1364 out-ports { 1365 port { 1366 etm0_out: endpoint { 1367 remote-endpoint = <&funnel1_in0>; 1368 }; 1369 }; 1370 }; 1371 }; 1372 1373 etm@85d000 { 1374 compatible = "arm,coresight-etm4x", "arm,primecell"; 1375 reg = <0x85d000 0x1000>; 1376 1377 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1378 clock-names = "apb_pclk", "atclk"; 1379 1380 cpu = <&CPU1>; 1381 1382 out-ports { 1383 port { 1384 etm1_out: endpoint { 1385 remote-endpoint = <&funnel1_in1>; 1386 }; 1387 }; 1388 }; 1389 }; 1390 1391 etm@85e000 { 1392 compatible = "arm,coresight-etm4x", "arm,primecell"; 1393 reg = <0x85e000 0x1000>; 1394 1395 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1396 clock-names = "apb_pclk", "atclk"; 1397 1398 cpu = <&CPU2>; 1399 1400 out-ports { 1401 port { 1402 etm2_out: endpoint { 1403 remote-endpoint = <&funnel1_in2>; 1404 }; 1405 }; 1406 }; 1407 }; 1408 1409 etm@85f000 { 1410 compatible = "arm,coresight-etm4x", "arm,primecell"; 1411 reg = <0x85f000 0x1000>; 1412 1413 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1414 clock-names = "apb_pclk", "atclk"; 1415 1416 cpu = <&CPU3>; 1417 1418 out-ports { 1419 port { 1420 etm3_out: endpoint { 1421 remote-endpoint = <&funnel1_in3>; 1422 }; 1423 }; 1424 }; 1425 }; 1426 1427 venus: video-codec@1d00000 { 1428 compatible = "qcom,msm8916-venus"; 1429 reg = <0x01d00000 0xff000>; 1430 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1431 power-domains = <&gcc VENUS_GDSC>; 1432 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1433 <&gcc GCC_VENUS0_AHB_CLK>, 1434 <&gcc GCC_VENUS0_AXI_CLK>; 1435 clock-names = "core", "iface", "bus"; 1436 iommus = <&apps_iommu 5>; 1437 memory-region = <&venus_mem>; 1438 status = "okay"; 1439 1440 video-decoder { 1441 compatible = "venus-decoder"; 1442 }; 1443 1444 video-encoder { 1445 compatible = "venus-encoder"; 1446 }; 1447 }; 1448 1449 camss: camss@1b00000 { 1450 compatible = "qcom,msm8916-camss"; 1451 reg = <0x1b0ac00 0x200>, 1452 <0x1b00030 0x4>, 1453 <0x1b0b000 0x200>, 1454 <0x1b00038 0x4>, 1455 <0x1b08000 0x100>, 1456 <0x1b08400 0x100>, 1457 <0x1b0a000 0x500>, 1458 <0x1b00020 0x10>, 1459 <0x1b10000 0x1000>; 1460 reg-names = "csiphy0", 1461 "csiphy0_clk_mux", 1462 "csiphy1", 1463 "csiphy1_clk_mux", 1464 "csid0", 1465 "csid1", 1466 "ispif", 1467 "csi_clk_mux", 1468 "vfe0"; 1469 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1470 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1471 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1472 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1473 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1474 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1475 interrupt-names = "csiphy0", 1476 "csiphy1", 1477 "csid0", 1478 "csid1", 1479 "ispif", 1480 "vfe0"; 1481 power-domains = <&gcc VFE_GDSC>; 1482 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1483 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1484 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1485 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1486 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1487 <&gcc GCC_CAMSS_CSI0_CLK>, 1488 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1489 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1490 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1491 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1492 <&gcc GCC_CAMSS_CSI1_CLK>, 1493 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1494 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1495 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1496 <&gcc GCC_CAMSS_AHB_CLK>, 1497 <&gcc GCC_CAMSS_VFE0_CLK>, 1498 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1499 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1500 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1501 clock-names = "top_ahb", 1502 "ispif_ahb", 1503 "csiphy0_timer", 1504 "csiphy1_timer", 1505 "csi0_ahb", 1506 "csi0", 1507 "csi0_phy", 1508 "csi0_pix", 1509 "csi0_rdi", 1510 "csi1_ahb", 1511 "csi1", 1512 "csi1_phy", 1513 "csi1_pix", 1514 "csi1_rdi", 1515 "ahb", 1516 "vfe0", 1517 "csi_vfe0", 1518 "vfe_ahb", 1519 "vfe_axi"; 1520 vdda-supply = <&pm8916_l2>; 1521 iommus = <&apps_iommu 3>; 1522 status = "disabled"; 1523 ports { 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 }; 1527 }; 1528 }; 1529 1530 smd { 1531 compatible = "qcom,smd"; 1532 1533 rpm { 1534 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1535 qcom,ipc = <&apcs 8 0>; 1536 qcom,smd-edge = <15>; 1537 1538 rpm_requests { 1539 compatible = "qcom,rpm-msm8916"; 1540 qcom,smd-channels = "rpm_requests"; 1541 1542 rpmcc: qcom,rpmcc { 1543 compatible = "qcom,rpmcc-msm8916"; 1544 #clock-cells = <1>; 1545 }; 1546 1547 smd_rpm_regulators: pm8916-regulators { 1548 compatible = "qcom,rpm-pm8916-regulators"; 1549 1550 pm8916_s1: s1 {}; 1551 pm8916_s3: s3 {}; 1552 pm8916_s4: s4 {}; 1553 1554 pm8916_l1: l1 {}; 1555 pm8916_l2: l2 {}; 1556 pm8916_l3: l3 {}; 1557 pm8916_l4: l4 {}; 1558 pm8916_l5: l5 {}; 1559 pm8916_l6: l6 {}; 1560 pm8916_l7: l7 {}; 1561 pm8916_l8: l8 {}; 1562 pm8916_l9: l9 {}; 1563 pm8916_l10: l10 {}; 1564 pm8916_l11: l11 {}; 1565 pm8916_l12: l12 {}; 1566 pm8916_l13: l13 {}; 1567 pm8916_l14: l14 {}; 1568 pm8916_l15: l15 {}; 1569 pm8916_l16: l16 {}; 1570 pm8916_l17: l17 {}; 1571 pm8916_l18: l18 {}; 1572 }; 1573 }; 1574 }; 1575 }; 1576 1577 hexagon-smp2p { 1578 compatible = "qcom,smp2p"; 1579 qcom,smem = <435>, <428>; 1580 1581 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 1582 1583 qcom,ipc = <&apcs 8 14>; 1584 1585 qcom,local-pid = <0>; 1586 qcom,remote-pid = <1>; 1587 1588 hexagon_smp2p_out: master-kernel { 1589 qcom,entry-name = "master-kernel"; 1590 1591 #qcom,smem-state-cells = <1>; 1592 }; 1593 1594 hexagon_smp2p_in: slave-kernel { 1595 qcom,entry-name = "slave-kernel"; 1596 1597 interrupt-controller; 1598 #interrupt-cells = <2>; 1599 }; 1600 }; 1601 1602 wcnss-smp2p { 1603 compatible = "qcom,smp2p"; 1604 qcom,smem = <451>, <431>; 1605 1606 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 1607 1608 qcom,ipc = <&apcs 8 18>; 1609 1610 qcom,local-pid = <0>; 1611 qcom,remote-pid = <4>; 1612 1613 wcnss_smp2p_out: master-kernel { 1614 qcom,entry-name = "master-kernel"; 1615 1616 #qcom,smem-state-cells = <1>; 1617 }; 1618 1619 wcnss_smp2p_in: slave-kernel { 1620 qcom,entry-name = "slave-kernel"; 1621 1622 interrupt-controller; 1623 #interrupt-cells = <2>; 1624 }; 1625 }; 1626 1627 smsm { 1628 compatible = "qcom,smsm"; 1629 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 1633 qcom,ipc-1 = <&apcs 8 13>; 1634 qcom,ipc-3 = <&apcs 8 19>; 1635 1636 apps_smsm: apps@0 { 1637 reg = <0>; 1638 1639 #qcom,smem-state-cells = <1>; 1640 }; 1641 1642 hexagon_smsm: hexagon@1 { 1643 reg = <1>; 1644 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 1645 1646 interrupt-controller; 1647 #interrupt-cells = <2>; 1648 }; 1649 1650 wcnss_smsm: wcnss@6 { 1651 reg = <6>; 1652 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 1653 1654 interrupt-controller; 1655 #interrupt-cells = <2>; 1656 }; 1657 }; 1658}; 1659 1660#include "msm8916-pins.dtsi" 1661