1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* We expect the bootloader to fill in the reg */ 26 reg = <0 0x80000000 0 0>; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 tz-apps@86000000 { 35 reg = <0x0 0x86000000 0x0 0x300000>; 36 no-map; 37 }; 38 39 smem@86300000 { 40 compatible = "qcom,smem"; 41 reg = <0x0 0x86300000 0x0 0x100000>; 42 no-map; 43 44 hwlocks = <&tcsr_mutex 3>; 45 qcom,rpm-msg-ram = <&rpm_msg_ram>; 46 }; 47 48 hypervisor@86400000 { 49 reg = <0x0 0x86400000 0x0 0x100000>; 50 no-map; 51 }; 52 53 tz@86500000 { 54 reg = <0x0 0x86500000 0x0 0x180000>; 55 no-map; 56 }; 57 58 reserved@86680000 { 59 reg = <0x0 0x86680000 0x0 0x80000>; 60 no-map; 61 }; 62 63 rmtfs@86700000 { 64 compatible = "qcom,rmtfs-mem"; 65 reg = <0x0 0x86700000 0x0 0xe0000>; 66 no-map; 67 68 qcom,client-id = <1>; 69 }; 70 71 rfsa@867e0000 { 72 reg = <0x0 0x867e0000 0x0 0x20000>; 73 no-map; 74 }; 75 76 mpss_mem: mpss@86800000 { 77 reg = <0x0 0x86800000 0x0 0x2b00000>; 78 no-map; 79 }; 80 81 wcnss_mem: wcnss@89300000 { 82 reg = <0x0 0x89300000 0x0 0x600000>; 83 no-map; 84 }; 85 86 venus_mem: venus@89900000 { 87 reg = <0x0 0x89900000 0x0 0x600000>; 88 no-map; 89 }; 90 91 mba_mem: mba@8ea00000 { 92 no-map; 93 reg = <0 0x8ea00000 0 0x100000>; 94 }; 95 }; 96 97 clocks { 98 xo_board: xo-board { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <19200000>; 102 }; 103 104 sleep_clk: sleep-clk { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 }; 109 }; 110 111 cpus { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 115 CPU0: cpu@0 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x0>; 119 next-level-cache = <&L2_0>; 120 enable-method = "psci"; 121 clocks = <&apcs>; 122 operating-points-v2 = <&cpu_opp_table>; 123 #cooling-cells = <2>; 124 power-domains = <&CPU_PD0>; 125 power-domain-names = "psci"; 126 qcom,acc = <&cpu0_acc>; 127 qcom,saw = <&cpu0_saw>; 128 }; 129 130 CPU1: cpu@1 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 reg = <0x1>; 134 next-level-cache = <&L2_0>; 135 enable-method = "psci"; 136 clocks = <&apcs>; 137 operating-points-v2 = <&cpu_opp_table>; 138 #cooling-cells = <2>; 139 power-domains = <&CPU_PD1>; 140 power-domain-names = "psci"; 141 qcom,acc = <&cpu1_acc>; 142 qcom,saw = <&cpu1_saw>; 143 }; 144 145 CPU2: cpu@2 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a53"; 148 reg = <0x2>; 149 next-level-cache = <&L2_0>; 150 enable-method = "psci"; 151 clocks = <&apcs>; 152 operating-points-v2 = <&cpu_opp_table>; 153 #cooling-cells = <2>; 154 power-domains = <&CPU_PD2>; 155 power-domain-names = "psci"; 156 qcom,acc = <&cpu2_acc>; 157 qcom,saw = <&cpu2_saw>; 158 }; 159 160 CPU3: cpu@3 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a53"; 163 reg = <0x3>; 164 next-level-cache = <&L2_0>; 165 enable-method = "psci"; 166 clocks = <&apcs>; 167 operating-points-v2 = <&cpu_opp_table>; 168 #cooling-cells = <2>; 169 power-domains = <&CPU_PD3>; 170 power-domain-names = "psci"; 171 qcom,acc = <&cpu3_acc>; 172 qcom,saw = <&cpu3_saw>; 173 }; 174 175 L2_0: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 }; 179 180 idle-states { 181 entry-method = "psci"; 182 183 CPU_SLEEP_0: cpu-sleep-0 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "standalone-power-collapse"; 186 arm,psci-suspend-param = <0x40000002>; 187 entry-latency-us = <130>; 188 exit-latency-us = <150>; 189 min-residency-us = <2000>; 190 local-timer-stop; 191 }; 192 }; 193 194 domain-idle-states { 195 196 CLUSTER_RET: cluster-retention { 197 compatible = "domain-idle-state"; 198 arm,psci-suspend-param = <0x41000012>; 199 entry-latency-us = <500>; 200 exit-latency-us = <500>; 201 min-residency-us = <2000>; 202 }; 203 204 CLUSTER_PWRDN: cluster-gdhs { 205 compatible = "domain-idle-state"; 206 arm,psci-suspend-param = <0x41000032>; 207 entry-latency-us = <2000>; 208 exit-latency-us = <2000>; 209 min-residency-us = <6000>; 210 }; 211 }; 212 }; 213 214 cpu_opp_table: opp-table-cpu { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-200000000 { 219 opp-hz = /bits/ 64 <200000000>; 220 }; 221 opp-400000000 { 222 opp-hz = /bits/ 64 <400000000>; 223 }; 224 opp-800000000 { 225 opp-hz = /bits/ 64 <800000000>; 226 }; 227 opp-998400000 { 228 opp-hz = /bits/ 64 <998400000>; 229 }; 230 }; 231 232 firmware { 233 scm: scm { 234 compatible = "qcom,scm-msm8916", "qcom,scm"; 235 clocks = <&gcc GCC_CRYPTO_CLK>, 236 <&gcc GCC_CRYPTO_AXI_CLK>, 237 <&gcc GCC_CRYPTO_AHB_CLK>; 238 clock-names = "core", "bus", "iface"; 239 #reset-cells = <1>; 240 241 qcom,dload-mode = <&tcsr 0x6100>; 242 }; 243 }; 244 245 pmu { 246 compatible = "arm,cortex-a53-pmu"; 247 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 248 }; 249 250 psci { 251 compatible = "arm,psci-1.0"; 252 method = "smc"; 253 254 CPU_PD0: power-domain-cpu0 { 255 #power-domain-cells = <0>; 256 power-domains = <&CLUSTER_PD>; 257 domain-idle-states = <&CPU_SLEEP_0>; 258 }; 259 260 CPU_PD1: power-domain-cpu1 { 261 #power-domain-cells = <0>; 262 power-domains = <&CLUSTER_PD>; 263 domain-idle-states = <&CPU_SLEEP_0>; 264 }; 265 266 CPU_PD2: power-domain-cpu2 { 267 #power-domain-cells = <0>; 268 power-domains = <&CLUSTER_PD>; 269 domain-idle-states = <&CPU_SLEEP_0>; 270 }; 271 272 CPU_PD3: power-domain-cpu3 { 273 #power-domain-cells = <0>; 274 power-domains = <&CLUSTER_PD>; 275 domain-idle-states = <&CPU_SLEEP_0>; 276 }; 277 278 CLUSTER_PD: power-domain-cluster { 279 #power-domain-cells = <0>; 280 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 281 }; 282 }; 283 284 smd { 285 compatible = "qcom,smd"; 286 287 rpm { 288 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 289 qcom,ipc = <&apcs 8 0>; 290 qcom,smd-edge = <15>; 291 292 rpm_requests: rpm-requests { 293 compatible = "qcom,rpm-msm8916"; 294 qcom,smd-channels = "rpm_requests"; 295 296 rpmcc: clock-controller { 297 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 298 #clock-cells = <1>; 299 clocks = <&xo_board>; 300 clock-names = "xo"; 301 }; 302 303 rpmpd: power-controller { 304 compatible = "qcom,msm8916-rpmpd"; 305 #power-domain-cells = <1>; 306 operating-points-v2 = <&rpmpd_opp_table>; 307 308 rpmpd_opp_table: opp-table { 309 compatible = "operating-points-v2"; 310 311 rpmpd_opp_ret: opp1 { 312 opp-level = <1>; 313 }; 314 rpmpd_opp_svs_krait: opp2 { 315 opp-level = <2>; 316 }; 317 rpmpd_opp_svs_soc: opp3 { 318 opp-level = <3>; 319 }; 320 rpmpd_opp_nom: opp4 { 321 opp-level = <4>; 322 }; 323 rpmpd_opp_turbo: opp5 { 324 opp-level = <5>; 325 }; 326 rpmpd_opp_super_turbo: opp6 { 327 opp-level = <6>; 328 }; 329 }; 330 }; 331 }; 332 }; 333 }; 334 335 smp2p-hexagon { 336 compatible = "qcom,smp2p"; 337 qcom,smem = <435>, <428>; 338 339 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 340 341 qcom,ipc = <&apcs 8 14>; 342 343 qcom,local-pid = <0>; 344 qcom,remote-pid = <1>; 345 346 hexagon_smp2p_out: master-kernel { 347 qcom,entry-name = "master-kernel"; 348 349 #qcom,smem-state-cells = <1>; 350 }; 351 352 hexagon_smp2p_in: slave-kernel { 353 qcom,entry-name = "slave-kernel"; 354 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 }; 358 }; 359 360 smp2p-wcnss { 361 compatible = "qcom,smp2p"; 362 qcom,smem = <451>, <431>; 363 364 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 365 366 qcom,ipc = <&apcs 8 18>; 367 368 qcom,local-pid = <0>; 369 qcom,remote-pid = <4>; 370 371 wcnss_smp2p_out: master-kernel { 372 qcom,entry-name = "master-kernel"; 373 374 #qcom,smem-state-cells = <1>; 375 }; 376 377 wcnss_smp2p_in: slave-kernel { 378 qcom,entry-name = "slave-kernel"; 379 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 }; 384 385 smsm { 386 compatible = "qcom,smsm"; 387 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 qcom,ipc-1 = <&apcs 8 13>; 392 qcom,ipc-3 = <&apcs 8 19>; 393 394 apps_smsm: apps@0 { 395 reg = <0>; 396 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 hexagon_smsm: hexagon@1 { 401 reg = <1>; 402 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 403 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 408 wcnss_smsm: wcnss@6 { 409 reg = <6>; 410 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 411 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 }; 416 417 soc: soc@0 { 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0 0 0 0xffffffff>; 421 compatible = "simple-bus"; 422 423 rng@22000 { 424 compatible = "qcom,prng"; 425 reg = <0x00022000 0x200>; 426 clocks = <&gcc GCC_PRNG_AHB_CLK>; 427 clock-names = "core"; 428 }; 429 430 restart@4ab000 { 431 compatible = "qcom,pshold"; 432 reg = <0x004ab000 0x4>; 433 }; 434 435 qfprom: qfprom@5c000 { 436 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 437 reg = <0x0005c000 0x1000>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 441 tsens_base1: base1@d0 { 442 reg = <0xd0 0x1>; 443 bits = <0 7>; 444 }; 445 446 tsens_s0_p1: s0-p1@d0 { 447 reg = <0xd0 0x2>; 448 bits = <7 5>; 449 }; 450 451 tsens_s0_p2: s0-p2@d1 { 452 reg = <0xd1 0x2>; 453 bits = <4 5>; 454 }; 455 456 tsens_s1_p1: s1-p1@d2 { 457 reg = <0xd2 0x1>; 458 bits = <1 5>; 459 }; 460 tsens_s1_p2: s1-p2@d2 { 461 reg = <0xd2 0x2>; 462 bits = <6 5>; 463 }; 464 tsens_s2_p1: s2-p1@d3 { 465 reg = <0xd3 0x1>; 466 bits = <3 5>; 467 }; 468 469 tsens_s2_p2: s2-p2@d4 { 470 reg = <0xd4 0x1>; 471 bits = <0 5>; 472 }; 473 474 // no tsens with hw_id 3 475 476 tsens_s4_p1: s4-p1@d4 { 477 reg = <0xd4 0x2>; 478 bits = <5 5>; 479 }; 480 481 tsens_s4_p2: s4-p2@d5 { 482 reg = <0xd5 0x1>; 483 bits = <2 5>; 484 }; 485 486 tsens_s5_p1: s5-p1@d5 { 487 reg = <0xd5 0x2>; 488 bits = <7 5>; 489 }; 490 491 tsens_s5_p2: s5-p2@d6 { 492 reg = <0xd6 0x2>; 493 bits = <4 5>; 494 }; 495 496 tsens_base2: base2@d7 { 497 reg = <0xd7 0x1>; 498 bits = <1 7>; 499 }; 500 501 tsens_mode: mode@ef { 502 reg = <0xef 0x1>; 503 bits = <5 3>; 504 }; 505 }; 506 507 rpm_msg_ram: sram@60000 { 508 compatible = "qcom,rpm-msg-ram"; 509 reg = <0x00060000 0x8000>; 510 }; 511 512 sram@290000 { 513 compatible = "qcom,msm8916-rpm-stats"; 514 reg = <0x00290000 0x10000>; 515 }; 516 517 bimc: interconnect@400000 { 518 compatible = "qcom,msm8916-bimc"; 519 reg = <0x00400000 0x62000>; 520 #interconnect-cells = <1>; 521 clock-names = "bus", "bus_a"; 522 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 523 <&rpmcc RPM_SMD_BIMC_A_CLK>; 524 }; 525 526 tsens: thermal-sensor@4a9000 { 527 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 528 reg = <0x004a9000 0x1000>, /* TM */ 529 <0x004a8000 0x1000>; /* SROT */ 530 531 // no hw_id 3 532 nvmem-cells = <&tsens_mode>, 533 <&tsens_base1>, <&tsens_base2>, 534 <&tsens_s0_p1>, <&tsens_s0_p2>, 535 <&tsens_s1_p1>, <&tsens_s1_p2>, 536 <&tsens_s2_p1>, <&tsens_s2_p2>, 537 <&tsens_s4_p1>, <&tsens_s4_p2>, 538 <&tsens_s5_p1>, <&tsens_s5_p2>; 539 nvmem-cell-names = "mode", 540 "base1", "base2", 541 "s0_p1", "s0_p2", 542 "s1_p1", "s1_p2", 543 "s2_p1", "s2_p2", 544 "s4_p1", "s4_p2", 545 "s5_p1", "s5_p2"; 546 #qcom,sensors = <5>; 547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "uplow"; 549 #thermal-sensor-cells = <1>; 550 }; 551 552 pcnoc: interconnect@500000 { 553 compatible = "qcom,msm8916-pcnoc"; 554 reg = <0x00500000 0x11000>; 555 #interconnect-cells = <1>; 556 clock-names = "bus", "bus_a"; 557 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 558 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 559 }; 560 561 snoc: interconnect@580000 { 562 compatible = "qcom,msm8916-snoc"; 563 reg = <0x00580000 0x14000>; 564 #interconnect-cells = <1>; 565 clock-names = "bus", "bus_a"; 566 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 567 <&rpmcc RPM_SMD_SNOC_A_CLK>; 568 }; 569 570 stm: stm@802000 { 571 compatible = "arm,coresight-stm", "arm,primecell"; 572 reg = <0x00802000 0x1000>, 573 <0x09280000 0x180000>; 574 reg-names = "stm-base", "stm-stimulus-base"; 575 576 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 577 clock-names = "apb_pclk", "atclk"; 578 579 status = "disabled"; 580 581 out-ports { 582 port { 583 stm_out: endpoint { 584 remote-endpoint = <&funnel0_in7>; 585 }; 586 }; 587 }; 588 }; 589 590 /* System CTIs */ 591 /* CTI 0 - TMC connections */ 592 cti0: cti@810000 { 593 compatible = "arm,coresight-cti", "arm,primecell"; 594 reg = <0x00810000 0x1000>; 595 596 clocks = <&rpmcc RPM_QDSS_CLK>; 597 clock-names = "apb_pclk"; 598 599 status = "disabled"; 600 }; 601 602 /* CTI 1 - TPIU connections */ 603 cti1: cti@811000 { 604 compatible = "arm,coresight-cti", "arm,primecell"; 605 reg = <0x00811000 0x1000>; 606 607 clocks = <&rpmcc RPM_QDSS_CLK>; 608 clock-names = "apb_pclk"; 609 610 status = "disabled"; 611 }; 612 613 /* CTIs 2-11 - no information - not instantiated */ 614 615 tpiu: tpiu@820000 { 616 compatible = "arm,coresight-tpiu", "arm,primecell"; 617 reg = <0x00820000 0x1000>; 618 619 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 620 clock-names = "apb_pclk", "atclk"; 621 622 status = "disabled"; 623 624 in-ports { 625 port { 626 tpiu_in: endpoint { 627 remote-endpoint = <&replicator_out1>; 628 }; 629 }; 630 }; 631 }; 632 633 funnel0: funnel@821000 { 634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 635 reg = <0x00821000 0x1000>; 636 637 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 638 clock-names = "apb_pclk", "atclk"; 639 640 status = "disabled"; 641 642 in-ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 /* 647 * Not described input ports: 648 * 0 - connected to Resource and Power Manger CPU ETM 649 * 1 - not-connected 650 * 2 - connected to Modem CPU ETM 651 * 3 - not-connected 652 * 5 - not-connected 653 * 6 - connected trought funnel to Wireless CPU ETM 654 * 7 - connected to STM component 655 */ 656 657 port@4 { 658 reg = <4>; 659 funnel0_in4: endpoint { 660 remote-endpoint = <&funnel1_out>; 661 }; 662 }; 663 664 port@7 { 665 reg = <7>; 666 funnel0_in7: endpoint { 667 remote-endpoint = <&stm_out>; 668 }; 669 }; 670 }; 671 672 out-ports { 673 port { 674 funnel0_out: endpoint { 675 remote-endpoint = <&etf_in>; 676 }; 677 }; 678 }; 679 }; 680 681 replicator: replicator@824000 { 682 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 683 reg = <0x00824000 0x1000>; 684 685 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 686 clock-names = "apb_pclk", "atclk"; 687 688 status = "disabled"; 689 690 out-ports { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 port@0 { 695 reg = <0>; 696 replicator_out0: endpoint { 697 remote-endpoint = <&etr_in>; 698 }; 699 }; 700 port@1 { 701 reg = <1>; 702 replicator_out1: endpoint { 703 remote-endpoint = <&tpiu_in>; 704 }; 705 }; 706 }; 707 708 in-ports { 709 port { 710 replicator_in: endpoint { 711 remote-endpoint = <&etf_out>; 712 }; 713 }; 714 }; 715 }; 716 717 etf: etf@825000 { 718 compatible = "arm,coresight-tmc", "arm,primecell"; 719 reg = <0x00825000 0x1000>; 720 721 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 722 clock-names = "apb_pclk", "atclk"; 723 724 status = "disabled"; 725 726 in-ports { 727 port { 728 etf_in: endpoint { 729 remote-endpoint = <&funnel0_out>; 730 }; 731 }; 732 }; 733 734 out-ports { 735 port { 736 etf_out: endpoint { 737 remote-endpoint = <&replicator_in>; 738 }; 739 }; 740 }; 741 }; 742 743 etr: etr@826000 { 744 compatible = "arm,coresight-tmc", "arm,primecell"; 745 reg = <0x00826000 0x1000>; 746 747 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 748 clock-names = "apb_pclk", "atclk"; 749 750 status = "disabled"; 751 752 in-ports { 753 port { 754 etr_in: endpoint { 755 remote-endpoint = <&replicator_out0>; 756 }; 757 }; 758 }; 759 }; 760 761 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 762 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 763 reg = <0x00841000 0x1000>; 764 765 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 766 clock-names = "apb_pclk", "atclk"; 767 768 status = "disabled"; 769 770 in-ports { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 port@0 { 775 reg = <0>; 776 funnel1_in0: endpoint { 777 remote-endpoint = <&etm0_out>; 778 }; 779 }; 780 port@1 { 781 reg = <1>; 782 funnel1_in1: endpoint { 783 remote-endpoint = <&etm1_out>; 784 }; 785 }; 786 port@2 { 787 reg = <2>; 788 funnel1_in2: endpoint { 789 remote-endpoint = <&etm2_out>; 790 }; 791 }; 792 port@3 { 793 reg = <3>; 794 funnel1_in3: endpoint { 795 remote-endpoint = <&etm3_out>; 796 }; 797 }; 798 }; 799 800 out-ports { 801 port { 802 funnel1_out: endpoint { 803 remote-endpoint = <&funnel0_in4>; 804 }; 805 }; 806 }; 807 }; 808 809 debug0: debug@850000 { 810 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 811 reg = <0x00850000 0x1000>; 812 clocks = <&rpmcc RPM_QDSS_CLK>; 813 clock-names = "apb_pclk"; 814 cpu = <&CPU0>; 815 status = "disabled"; 816 }; 817 818 debug1: debug@852000 { 819 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 820 reg = <0x00852000 0x1000>; 821 clocks = <&rpmcc RPM_QDSS_CLK>; 822 clock-names = "apb_pclk"; 823 cpu = <&CPU1>; 824 status = "disabled"; 825 }; 826 827 debug2: debug@854000 { 828 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 829 reg = <0x00854000 0x1000>; 830 clocks = <&rpmcc RPM_QDSS_CLK>; 831 clock-names = "apb_pclk"; 832 cpu = <&CPU2>; 833 status = "disabled"; 834 }; 835 836 debug3: debug@856000 { 837 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 838 reg = <0x00856000 0x1000>; 839 clocks = <&rpmcc RPM_QDSS_CLK>; 840 clock-names = "apb_pclk"; 841 cpu = <&CPU3>; 842 status = "disabled"; 843 }; 844 845 /* Core CTIs; CTIs 12-15 */ 846 /* CTI - CPU-0 */ 847 cti12: cti@858000 { 848 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 849 "arm,primecell"; 850 reg = <0x00858000 0x1000>; 851 852 clocks = <&rpmcc RPM_QDSS_CLK>; 853 clock-names = "apb_pclk"; 854 855 cpu = <&CPU0>; 856 arm,cs-dev-assoc = <&etm0>; 857 858 status = "disabled"; 859 }; 860 861 /* CTI - CPU-1 */ 862 cti13: cti@859000 { 863 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 864 "arm,primecell"; 865 reg = <0x00859000 0x1000>; 866 867 clocks = <&rpmcc RPM_QDSS_CLK>; 868 clock-names = "apb_pclk"; 869 870 cpu = <&CPU1>; 871 arm,cs-dev-assoc = <&etm1>; 872 873 status = "disabled"; 874 }; 875 876 /* CTI - CPU-2 */ 877 cti14: cti@85a000 { 878 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 879 "arm,primecell"; 880 reg = <0x0085a000 0x1000>; 881 882 clocks = <&rpmcc RPM_QDSS_CLK>; 883 clock-names = "apb_pclk"; 884 885 cpu = <&CPU2>; 886 arm,cs-dev-assoc = <&etm2>; 887 888 status = "disabled"; 889 }; 890 891 /* CTI - CPU-3 */ 892 cti15: cti@85b000 { 893 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 894 "arm,primecell"; 895 reg = <0x0085b000 0x1000>; 896 897 clocks = <&rpmcc RPM_QDSS_CLK>; 898 clock-names = "apb_pclk"; 899 900 cpu = <&CPU3>; 901 arm,cs-dev-assoc = <&etm3>; 902 903 status = "disabled"; 904 }; 905 906 etm0: etm@85c000 { 907 compatible = "arm,coresight-etm4x", "arm,primecell"; 908 reg = <0x0085c000 0x1000>; 909 910 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 911 clock-names = "apb_pclk", "atclk"; 912 arm,coresight-loses-context-with-cpu; 913 914 cpu = <&CPU0>; 915 916 status = "disabled"; 917 918 out-ports { 919 port { 920 etm0_out: endpoint { 921 remote-endpoint = <&funnel1_in0>; 922 }; 923 }; 924 }; 925 }; 926 927 etm1: etm@85d000 { 928 compatible = "arm,coresight-etm4x", "arm,primecell"; 929 reg = <0x0085d000 0x1000>; 930 931 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 932 clock-names = "apb_pclk", "atclk"; 933 arm,coresight-loses-context-with-cpu; 934 935 cpu = <&CPU1>; 936 937 status = "disabled"; 938 939 out-ports { 940 port { 941 etm1_out: endpoint { 942 remote-endpoint = <&funnel1_in1>; 943 }; 944 }; 945 }; 946 }; 947 948 etm2: etm@85e000 { 949 compatible = "arm,coresight-etm4x", "arm,primecell"; 950 reg = <0x0085e000 0x1000>; 951 952 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 953 clock-names = "apb_pclk", "atclk"; 954 arm,coresight-loses-context-with-cpu; 955 956 cpu = <&CPU2>; 957 958 status = "disabled"; 959 960 out-ports { 961 port { 962 etm2_out: endpoint { 963 remote-endpoint = <&funnel1_in2>; 964 }; 965 }; 966 }; 967 }; 968 969 etm3: etm@85f000 { 970 compatible = "arm,coresight-etm4x", "arm,primecell"; 971 reg = <0x0085f000 0x1000>; 972 973 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 974 clock-names = "apb_pclk", "atclk"; 975 arm,coresight-loses-context-with-cpu; 976 977 cpu = <&CPU3>; 978 979 status = "disabled"; 980 981 out-ports { 982 port { 983 etm3_out: endpoint { 984 remote-endpoint = <&funnel1_in3>; 985 }; 986 }; 987 }; 988 }; 989 990 tlmm: pinctrl@1000000 { 991 compatible = "qcom,msm8916-pinctrl"; 992 reg = <0x01000000 0x300000>; 993 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 994 gpio-controller; 995 gpio-ranges = <&tlmm 0 0 122>; 996 #gpio-cells = <2>; 997 interrupt-controller; 998 #interrupt-cells = <2>; 999 1000 blsp_i2c1_default: blsp-i2c1-default-state { 1001 pins = "gpio2", "gpio3"; 1002 function = "blsp_i2c1"; 1003 drive-strength = <2>; 1004 bias-disable; 1005 }; 1006 1007 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 1008 pins = "gpio2", "gpio3"; 1009 function = "gpio"; 1010 drive-strength = <2>; 1011 bias-disable; 1012 }; 1013 1014 blsp_i2c2_default: blsp-i2c2-default-state { 1015 pins = "gpio6", "gpio7"; 1016 function = "blsp_i2c2"; 1017 drive-strength = <2>; 1018 bias-disable; 1019 }; 1020 1021 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 1022 pins = "gpio6", "gpio7"; 1023 function = "gpio"; 1024 drive-strength = <2>; 1025 bias-disable; 1026 }; 1027 1028 blsp_i2c3_default: blsp-i2c3-default-state { 1029 pins = "gpio10", "gpio11"; 1030 function = "blsp_i2c3"; 1031 drive-strength = <2>; 1032 bias-disable; 1033 }; 1034 1035 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 1036 pins = "gpio10", "gpio11"; 1037 function = "gpio"; 1038 drive-strength = <2>; 1039 bias-disable; 1040 }; 1041 1042 blsp_i2c4_default: blsp-i2c4-default-state { 1043 pins = "gpio14", "gpio15"; 1044 function = "blsp_i2c4"; 1045 drive-strength = <2>; 1046 bias-disable; 1047 }; 1048 1049 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 1050 pins = "gpio14", "gpio15"; 1051 function = "gpio"; 1052 drive-strength = <2>; 1053 bias-disable; 1054 }; 1055 1056 blsp_i2c5_default: blsp-i2c5-default-state { 1057 pins = "gpio18", "gpio19"; 1058 function = "blsp_i2c5"; 1059 drive-strength = <2>; 1060 bias-disable; 1061 }; 1062 1063 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 1064 pins = "gpio18", "gpio19"; 1065 function = "gpio"; 1066 drive-strength = <2>; 1067 bias-disable; 1068 }; 1069 1070 blsp_i2c6_default: blsp-i2c6-default-state { 1071 pins = "gpio22", "gpio23"; 1072 function = "blsp_i2c6"; 1073 drive-strength = <2>; 1074 bias-disable; 1075 }; 1076 1077 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 1078 pins = "gpio22", "gpio23"; 1079 function = "gpio"; 1080 drive-strength = <2>; 1081 bias-disable; 1082 }; 1083 1084 blsp_spi1_default: blsp-spi1-default-state { 1085 spi-pins { 1086 pins = "gpio0", "gpio1", "gpio3"; 1087 function = "blsp_spi1"; 1088 drive-strength = <12>; 1089 bias-disable; 1090 }; 1091 cs-pins { 1092 pins = "gpio2"; 1093 function = "gpio"; 1094 drive-strength = <16>; 1095 bias-disable; 1096 output-high; 1097 }; 1098 }; 1099 1100 blsp_spi1_sleep: blsp-spi1-sleep-state { 1101 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1102 function = "gpio"; 1103 drive-strength = <2>; 1104 bias-pull-down; 1105 }; 1106 1107 blsp_spi2_default: blsp-spi2-default-state { 1108 spi-pins { 1109 pins = "gpio4", "gpio5", "gpio7"; 1110 function = "blsp_spi2"; 1111 drive-strength = <12>; 1112 bias-disable; 1113 }; 1114 cs-pins { 1115 pins = "gpio6"; 1116 function = "gpio"; 1117 drive-strength = <16>; 1118 bias-disable; 1119 output-high; 1120 }; 1121 }; 1122 1123 blsp_spi2_sleep: blsp-spi2-sleep-state { 1124 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1125 function = "gpio"; 1126 drive-strength = <2>; 1127 bias-pull-down; 1128 }; 1129 1130 blsp_spi3_default: blsp-spi3-default-state { 1131 spi-pins { 1132 pins = "gpio8", "gpio9", "gpio11"; 1133 function = "blsp_spi3"; 1134 drive-strength = <12>; 1135 bias-disable; 1136 }; 1137 cs-pins { 1138 pins = "gpio10"; 1139 function = "gpio"; 1140 drive-strength = <16>; 1141 bias-disable; 1142 output-high; 1143 }; 1144 }; 1145 1146 blsp_spi3_sleep: blsp-spi3-sleep-state { 1147 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1148 function = "gpio"; 1149 drive-strength = <2>; 1150 bias-pull-down; 1151 }; 1152 1153 blsp_spi4_default: blsp-spi4-default-state { 1154 spi-pins { 1155 pins = "gpio12", "gpio13", "gpio15"; 1156 function = "blsp_spi4"; 1157 drive-strength = <12>; 1158 bias-disable; 1159 }; 1160 cs-pins { 1161 pins = "gpio14"; 1162 function = "gpio"; 1163 drive-strength = <16>; 1164 bias-disable; 1165 output-high; 1166 }; 1167 }; 1168 1169 blsp_spi4_sleep: blsp-spi4-sleep-state { 1170 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 1171 function = "gpio"; 1172 drive-strength = <2>; 1173 bias-pull-down; 1174 }; 1175 1176 blsp_spi5_default: blsp-spi5-default-state { 1177 spi-pins { 1178 pins = "gpio16", "gpio17", "gpio19"; 1179 function = "blsp_spi5"; 1180 drive-strength = <12>; 1181 bias-disable; 1182 }; 1183 cs-pins { 1184 pins = "gpio18"; 1185 function = "gpio"; 1186 drive-strength = <16>; 1187 bias-disable; 1188 output-high; 1189 }; 1190 }; 1191 1192 blsp_spi5_sleep: blsp-spi5-sleep-state { 1193 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1194 function = "gpio"; 1195 drive-strength = <2>; 1196 bias-pull-down; 1197 }; 1198 1199 blsp_spi6_default: blsp-spi6-default-state { 1200 spi-pins { 1201 pins = "gpio20", "gpio21", "gpio23"; 1202 function = "blsp_spi6"; 1203 drive-strength = <12>; 1204 bias-disable; 1205 }; 1206 cs-pins { 1207 pins = "gpio22"; 1208 function = "gpio"; 1209 drive-strength = <16>; 1210 bias-disable; 1211 output-high; 1212 }; 1213 }; 1214 1215 blsp_spi6_sleep: blsp-spi6-sleep-state { 1216 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 1217 function = "gpio"; 1218 drive-strength = <2>; 1219 bias-pull-down; 1220 }; 1221 1222 blsp_uart1_default: blsp-uart1-default-state { 1223 /* TX, RX, CTS_N, RTS_N */ 1224 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1225 function = "blsp_uart1"; 1226 drive-strength = <16>; 1227 bias-disable; 1228 }; 1229 1230 blsp_uart1_sleep: blsp-uart1-sleep-state { 1231 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1232 function = "gpio"; 1233 drive-strength = <2>; 1234 bias-pull-down; 1235 }; 1236 1237 blsp_uart2_default: blsp-uart2-default-state { 1238 pins = "gpio4", "gpio5"; 1239 function = "blsp_uart2"; 1240 drive-strength = <16>; 1241 bias-disable; 1242 }; 1243 1244 blsp_uart2_sleep: blsp-uart2-sleep-state { 1245 pins = "gpio4", "gpio5"; 1246 function = "gpio"; 1247 drive-strength = <2>; 1248 bias-pull-down; 1249 }; 1250 1251 camera_front_default: camera-front-default-state { 1252 pwdn-pins { 1253 pins = "gpio33"; 1254 function = "gpio"; 1255 drive-strength = <16>; 1256 bias-disable; 1257 }; 1258 rst-pins { 1259 pins = "gpio28"; 1260 function = "gpio"; 1261 drive-strength = <16>; 1262 bias-disable; 1263 }; 1264 mclk1-pins { 1265 pins = "gpio27"; 1266 function = "cam_mclk1"; 1267 drive-strength = <16>; 1268 bias-disable; 1269 }; 1270 }; 1271 1272 camera_rear_default: camera-rear-default-state { 1273 pwdn-pins { 1274 pins = "gpio34"; 1275 function = "gpio"; 1276 drive-strength = <16>; 1277 bias-disable; 1278 }; 1279 rst-pins { 1280 pins = "gpio35"; 1281 function = "gpio"; 1282 drive-strength = <16>; 1283 bias-disable; 1284 }; 1285 mclk0-pins { 1286 pins = "gpio26"; 1287 function = "cam_mclk0"; 1288 drive-strength = <16>; 1289 bias-disable; 1290 }; 1291 }; 1292 1293 cci0_default: cci0-default-state { 1294 pins = "gpio29", "gpio30"; 1295 function = "cci_i2c"; 1296 drive-strength = <16>; 1297 bias-disable; 1298 }; 1299 1300 cdc_dmic_default: cdc-dmic-default-state { 1301 clk-pins { 1302 pins = "gpio0"; 1303 function = "dmic0_clk"; 1304 drive-strength = <8>; 1305 }; 1306 data-pins { 1307 pins = "gpio1"; 1308 function = "dmic0_data"; 1309 drive-strength = <8>; 1310 }; 1311 }; 1312 1313 cdc_dmic_sleep: cdc-dmic-sleep-state { 1314 clk-pins { 1315 pins = "gpio0"; 1316 function = "dmic0_clk"; 1317 drive-strength = <2>; 1318 bias-disable; 1319 }; 1320 data-pins { 1321 pins = "gpio1"; 1322 function = "dmic0_data"; 1323 drive-strength = <2>; 1324 bias-disable; 1325 }; 1326 }; 1327 1328 cdc_pdm_default: cdc-pdm-default-state { 1329 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1330 "gpio67", "gpio68"; 1331 function = "cdc_pdm0"; 1332 drive-strength = <8>; 1333 bias-disable; 1334 }; 1335 1336 cdc_pdm_sleep: cdc-pdm-sleep-state { 1337 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1338 "gpio67", "gpio68"; 1339 function = "cdc_pdm0"; 1340 drive-strength = <2>; 1341 bias-pull-down; 1342 }; 1343 1344 pri_mi2s_default: mi2s-pri-default-state { 1345 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1346 function = "pri_mi2s"; 1347 drive-strength = <8>; 1348 bias-disable; 1349 }; 1350 1351 pri_mi2s_sleep: mi2s-pri-sleep-state { 1352 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1353 function = "pri_mi2s"; 1354 drive-strength = <2>; 1355 bias-disable; 1356 }; 1357 1358 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1359 pins = "gpio116"; 1360 function = "pri_mi2s"; 1361 drive-strength = <8>; 1362 bias-disable; 1363 }; 1364 1365 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1366 pins = "gpio116"; 1367 function = "pri_mi2s"; 1368 drive-strength = <2>; 1369 bias-disable; 1370 }; 1371 1372 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1373 pins = "gpio110"; 1374 function = "pri_mi2s_ws"; 1375 drive-strength = <8>; 1376 bias-disable; 1377 }; 1378 1379 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1380 pins = "gpio110"; 1381 function = "pri_mi2s_ws"; 1382 drive-strength = <2>; 1383 bias-disable; 1384 }; 1385 1386 sec_mi2s_default: mi2s-sec-default-state { 1387 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1388 function = "sec_mi2s"; 1389 drive-strength = <8>; 1390 bias-disable; 1391 }; 1392 1393 sec_mi2s_sleep: mi2s-sec-sleep-state { 1394 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1395 function = "sec_mi2s"; 1396 drive-strength = <2>; 1397 bias-disable; 1398 }; 1399 1400 sdc1_default: sdc1-default-state { 1401 clk-pins { 1402 pins = "sdc1_clk"; 1403 bias-disable; 1404 drive-strength = <16>; 1405 }; 1406 cmd-pins { 1407 pins = "sdc1_cmd"; 1408 bias-pull-up; 1409 drive-strength = <10>; 1410 }; 1411 data-pins { 1412 pins = "sdc1_data"; 1413 bias-pull-up; 1414 drive-strength = <10>; 1415 }; 1416 }; 1417 1418 sdc1_sleep: sdc1-sleep-state { 1419 clk-pins { 1420 pins = "sdc1_clk"; 1421 bias-disable; 1422 drive-strength = <2>; 1423 }; 1424 cmd-pins { 1425 pins = "sdc1_cmd"; 1426 bias-pull-up; 1427 drive-strength = <2>; 1428 }; 1429 data-pins { 1430 pins = "sdc1_data"; 1431 bias-pull-up; 1432 drive-strength = <2>; 1433 }; 1434 }; 1435 1436 sdc2_default: sdc2-default-state { 1437 clk-pins { 1438 pins = "sdc2_clk"; 1439 bias-disable; 1440 drive-strength = <16>; 1441 }; 1442 cmd-pins { 1443 pins = "sdc2_cmd"; 1444 bias-pull-up; 1445 drive-strength = <10>; 1446 }; 1447 data-pins { 1448 pins = "sdc2_data"; 1449 bias-pull-up; 1450 drive-strength = <10>; 1451 }; 1452 }; 1453 1454 sdc2_sleep: sdc2-sleep-state { 1455 clk-pins { 1456 pins = "sdc2_clk"; 1457 bias-disable; 1458 drive-strength = <2>; 1459 }; 1460 cmd-pins { 1461 pins = "sdc2_cmd"; 1462 bias-pull-up; 1463 drive-strength = <2>; 1464 }; 1465 data-pins { 1466 pins = "sdc2_data"; 1467 bias-pull-up; 1468 drive-strength = <2>; 1469 }; 1470 }; 1471 1472 wcss_wlan_default: wcss-wlan-default-state { 1473 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1474 function = "wcss_wlan"; 1475 drive-strength = <6>; 1476 bias-pull-up; 1477 }; 1478 }; 1479 1480 gcc: clock-controller@1800000 { 1481 compatible = "qcom,gcc-msm8916"; 1482 #clock-cells = <1>; 1483 #reset-cells = <1>; 1484 #power-domain-cells = <1>; 1485 reg = <0x01800000 0x80000>; 1486 clocks = <&xo_board>, 1487 <&sleep_clk>, 1488 <&mdss_dsi0_phy 1>, 1489 <&mdss_dsi0_phy 0>, 1490 <0>, 1491 <0>, 1492 <0>; 1493 clock-names = "xo", 1494 "sleep_clk", 1495 "dsi0pll", 1496 "dsi0pllbyte", 1497 "ext_mclk", 1498 "ext_pri_i2s", 1499 "ext_sec_i2s"; 1500 }; 1501 1502 tcsr_mutex: hwlock@1905000 { 1503 compatible = "qcom,tcsr-mutex"; 1504 reg = <0x01905000 0x20000>; 1505 #hwlock-cells = <1>; 1506 }; 1507 1508 tcsr: syscon@1937000 { 1509 compatible = "qcom,tcsr-msm8916", "syscon"; 1510 reg = <0x01937000 0x30000>; 1511 }; 1512 1513 mdss: display-subsystem@1a00000 { 1514 status = "disabled"; 1515 compatible = "qcom,mdss"; 1516 reg = <0x01a00000 0x1000>, 1517 <0x01ac8000 0x3000>; 1518 reg-names = "mdss_phys", "vbif_phys"; 1519 1520 power-domains = <&gcc MDSS_GDSC>; 1521 1522 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1523 <&gcc GCC_MDSS_AXI_CLK>, 1524 <&gcc GCC_MDSS_VSYNC_CLK>; 1525 clock-names = "iface", 1526 "bus", 1527 "vsync"; 1528 1529 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1530 1531 interrupt-controller; 1532 #interrupt-cells = <1>; 1533 1534 #address-cells = <1>; 1535 #size-cells = <1>; 1536 ranges; 1537 1538 mdss_mdp: display-controller@1a01000 { 1539 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1540 reg = <0x01a01000 0x89000>; 1541 reg-names = "mdp_phys"; 1542 1543 interrupt-parent = <&mdss>; 1544 interrupts = <0>; 1545 1546 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1547 <&gcc GCC_MDSS_AXI_CLK>, 1548 <&gcc GCC_MDSS_MDP_CLK>, 1549 <&gcc GCC_MDSS_VSYNC_CLK>; 1550 clock-names = "iface", 1551 "bus", 1552 "core", 1553 "vsync"; 1554 1555 iommus = <&apps_iommu 4>; 1556 1557 ports { 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 1561 port@0 { 1562 reg = <0>; 1563 mdss_mdp_intf1_out: endpoint { 1564 remote-endpoint = <&mdss_dsi0_in>; 1565 }; 1566 }; 1567 }; 1568 }; 1569 1570 mdss_dsi0: dsi@1a98000 { 1571 compatible = "qcom,msm8916-dsi-ctrl", 1572 "qcom,mdss-dsi-ctrl"; 1573 reg = <0x01a98000 0x25c>; 1574 reg-names = "dsi_ctrl"; 1575 1576 interrupt-parent = <&mdss>; 1577 interrupts = <4>; 1578 1579 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1580 <&gcc PCLK0_CLK_SRC>; 1581 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1582 <&mdss_dsi0_phy 1>; 1583 1584 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1585 <&gcc GCC_MDSS_AHB_CLK>, 1586 <&gcc GCC_MDSS_AXI_CLK>, 1587 <&gcc GCC_MDSS_BYTE0_CLK>, 1588 <&gcc GCC_MDSS_PCLK0_CLK>, 1589 <&gcc GCC_MDSS_ESC0_CLK>; 1590 clock-names = "mdp_core", 1591 "iface", 1592 "bus", 1593 "byte", 1594 "pixel", 1595 "core"; 1596 phys = <&mdss_dsi0_phy>; 1597 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 ports { 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 port@0 { 1606 reg = <0>; 1607 mdss_dsi0_in: endpoint { 1608 remote-endpoint = <&mdss_mdp_intf1_out>; 1609 }; 1610 }; 1611 1612 port@1 { 1613 reg = <1>; 1614 mdss_dsi0_out: endpoint { 1615 }; 1616 }; 1617 }; 1618 }; 1619 1620 mdss_dsi0_phy: phy@1a98300 { 1621 compatible = "qcom,dsi-phy-28nm-lp"; 1622 reg = <0x01a98300 0xd4>, 1623 <0x01a98500 0x280>, 1624 <0x01a98780 0x30>; 1625 reg-names = "dsi_pll", 1626 "dsi_phy", 1627 "dsi_phy_regulator"; 1628 1629 #clock-cells = <1>; 1630 #phy-cells = <0>; 1631 1632 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1633 <&xo_board>; 1634 clock-names = "iface", "ref"; 1635 }; 1636 }; 1637 1638 camss: camss@1b0ac00 { 1639 compatible = "qcom,msm8916-camss"; 1640 reg = <0x01b0ac00 0x200>, 1641 <0x01b00030 0x4>, 1642 <0x01b0b000 0x200>, 1643 <0x01b00038 0x4>, 1644 <0x01b08000 0x100>, 1645 <0x01b08400 0x100>, 1646 <0x01b0a000 0x500>, 1647 <0x01b00020 0x10>, 1648 <0x01b10000 0x1000>; 1649 reg-names = "csiphy0", 1650 "csiphy0_clk_mux", 1651 "csiphy1", 1652 "csiphy1_clk_mux", 1653 "csid0", 1654 "csid1", 1655 "ispif", 1656 "csi_clk_mux", 1657 "vfe0"; 1658 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1659 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1660 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1661 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1662 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1663 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1664 interrupt-names = "csiphy0", 1665 "csiphy1", 1666 "csid0", 1667 "csid1", 1668 "ispif", 1669 "vfe0"; 1670 power-domains = <&gcc VFE_GDSC>; 1671 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1672 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1673 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1674 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1675 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1676 <&gcc GCC_CAMSS_CSI0_CLK>, 1677 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1678 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1679 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1680 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1681 <&gcc GCC_CAMSS_CSI1_CLK>, 1682 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1683 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1684 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1685 <&gcc GCC_CAMSS_AHB_CLK>, 1686 <&gcc GCC_CAMSS_VFE0_CLK>, 1687 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1688 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1689 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1690 clock-names = "top_ahb", 1691 "ispif_ahb", 1692 "csiphy0_timer", 1693 "csiphy1_timer", 1694 "csi0_ahb", 1695 "csi0", 1696 "csi0_phy", 1697 "csi0_pix", 1698 "csi0_rdi", 1699 "csi1_ahb", 1700 "csi1", 1701 "csi1_phy", 1702 "csi1_pix", 1703 "csi1_rdi", 1704 "ahb", 1705 "vfe0", 1706 "csi_vfe0", 1707 "vfe_ahb", 1708 "vfe_axi"; 1709 iommus = <&apps_iommu 3>; 1710 status = "disabled"; 1711 ports { 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 }; 1715 }; 1716 1717 cci: cci@1b0c000 { 1718 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 reg = <0x01b0c000 0x1000>; 1722 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1723 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1724 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1725 <&gcc GCC_CAMSS_CCI_CLK>, 1726 <&gcc GCC_CAMSS_AHB_CLK>; 1727 clock-names = "camss_top_ahb", "cci_ahb", 1728 "cci", "camss_ahb"; 1729 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1730 <&gcc GCC_CAMSS_CCI_CLK>; 1731 assigned-clock-rates = <80000000>, <19200000>; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&cci0_default>; 1734 status = "disabled"; 1735 1736 cci_i2c0: i2c-bus@0 { 1737 reg = <0>; 1738 clock-frequency = <400000>; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 }; 1742 }; 1743 1744 gpu@1c00000 { 1745 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1746 reg = <0x01c00000 0x20000>; 1747 reg-names = "kgsl_3d0_reg_memory"; 1748 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1749 interrupt-names = "kgsl_3d0_irq"; 1750 clock-names = 1751 "core", 1752 "iface", 1753 "mem", 1754 "mem_iface", 1755 "alt_mem_iface", 1756 "gfx3d"; 1757 clocks = 1758 <&gcc GCC_OXILI_GFX3D_CLK>, 1759 <&gcc GCC_OXILI_AHB_CLK>, 1760 <&gcc GCC_OXILI_GMEM_CLK>, 1761 <&gcc GCC_BIMC_GFX_CLK>, 1762 <&gcc GCC_BIMC_GPU_CLK>, 1763 <&gcc GFX3D_CLK_SRC>; 1764 power-domains = <&gcc OXILI_GDSC>; 1765 operating-points-v2 = <&gpu_opp_table>; 1766 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1767 1768 gpu_opp_table: opp-table { 1769 compatible = "operating-points-v2"; 1770 1771 opp-400000000 { 1772 opp-hz = /bits/ 64 <400000000>; 1773 }; 1774 opp-19200000 { 1775 opp-hz = /bits/ 64 <19200000>; 1776 }; 1777 }; 1778 }; 1779 1780 venus: video-codec@1d00000 { 1781 compatible = "qcom,msm8916-venus"; 1782 reg = <0x01d00000 0xff000>; 1783 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1784 power-domains = <&gcc VENUS_GDSC>; 1785 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1786 <&gcc GCC_VENUS0_AHB_CLK>, 1787 <&gcc GCC_VENUS0_AXI_CLK>; 1788 clock-names = "core", "iface", "bus"; 1789 iommus = <&apps_iommu 5>; 1790 memory-region = <&venus_mem>; 1791 status = "okay"; 1792 1793 video-decoder { 1794 compatible = "venus-decoder"; 1795 }; 1796 1797 video-encoder { 1798 compatible = "venus-encoder"; 1799 }; 1800 }; 1801 1802 apps_iommu: iommu@1ef0000 { 1803 #address-cells = <1>; 1804 #size-cells = <1>; 1805 #iommu-cells = <1>; 1806 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1807 ranges = <0 0x01e20000 0x40000>; 1808 reg = <0x01ef0000 0x3000>; 1809 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1810 <&gcc GCC_APSS_TCU_CLK>; 1811 clock-names = "iface", "bus"; 1812 qcom,iommu-secure-id = <17>; 1813 1814 /* VFE */ 1815 iommu-ctx@3000 { 1816 compatible = "qcom,msm-iommu-v1-sec"; 1817 reg = <0x3000 0x1000>; 1818 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1819 }; 1820 1821 /* MDP_0 */ 1822 iommu-ctx@4000 { 1823 compatible = "qcom,msm-iommu-v1-ns"; 1824 reg = <0x4000 0x1000>; 1825 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1826 }; 1827 1828 /* VENUS_NS */ 1829 iommu-ctx@5000 { 1830 compatible = "qcom,msm-iommu-v1-sec"; 1831 reg = <0x5000 0x1000>; 1832 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1833 }; 1834 }; 1835 1836 gpu_iommu: iommu@1f08000 { 1837 #address-cells = <1>; 1838 #size-cells = <1>; 1839 #iommu-cells = <1>; 1840 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1841 ranges = <0 0x01f08000 0x10000>; 1842 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1843 <&gcc GCC_GFX_TCU_CLK>; 1844 clock-names = "iface", "bus"; 1845 qcom,iommu-secure-id = <18>; 1846 1847 /* GFX3D_USER */ 1848 iommu-ctx@1000 { 1849 compatible = "qcom,msm-iommu-v1-ns"; 1850 reg = <0x1000 0x1000>; 1851 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1852 }; 1853 1854 /* GFX3D_PRIV */ 1855 iommu-ctx@2000 { 1856 compatible = "qcom,msm-iommu-v1-ns"; 1857 reg = <0x2000 0x1000>; 1858 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1859 }; 1860 }; 1861 1862 spmi_bus: spmi@200f000 { 1863 compatible = "qcom,spmi-pmic-arb"; 1864 reg = <0x0200f000 0x001000>, 1865 <0x02400000 0x400000>, 1866 <0x02c00000 0x400000>, 1867 <0x03800000 0x200000>, 1868 <0x0200a000 0x002100>; 1869 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1870 interrupt-names = "periph_irq"; 1871 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1872 qcom,ee = <0>; 1873 qcom,channel = <0>; 1874 #address-cells = <2>; 1875 #size-cells = <0>; 1876 interrupt-controller; 1877 #interrupt-cells = <4>; 1878 }; 1879 1880 bam_dmux_dma: dma-controller@4044000 { 1881 compatible = "qcom,bam-v1.7.0"; 1882 reg = <0x04044000 0x19000>; 1883 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1884 #dma-cells = <1>; 1885 qcom,ee = <0>; 1886 1887 num-channels = <6>; 1888 qcom,num-ees = <1>; 1889 qcom,powered-remotely; 1890 1891 status = "disabled"; 1892 }; 1893 1894 mpss: remoteproc@4080000 { 1895 compatible = "qcom,msm8916-mss-pil"; 1896 reg = <0x04080000 0x100>, 1897 <0x04020000 0x040>; 1898 1899 reg-names = "qdsp6", "rmb"; 1900 1901 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1902 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1903 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1904 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1905 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1906 interrupt-names = "wdog", "fatal", "ready", 1907 "handover", "stop-ack"; 1908 1909 power-domains = <&rpmpd MSM8916_VDDCX>, 1910 <&rpmpd MSM8916_VDDMX>; 1911 power-domain-names = "cx", "mx"; 1912 1913 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1914 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1915 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1916 <&xo_board>; 1917 clock-names = "iface", "bus", "mem", "xo"; 1918 1919 qcom,smem-states = <&hexagon_smp2p_out 0>; 1920 qcom,smem-state-names = "stop"; 1921 1922 resets = <&scm 0>; 1923 reset-names = "mss_restart"; 1924 1925 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1926 1927 status = "disabled"; 1928 1929 mba { 1930 memory-region = <&mba_mem>; 1931 }; 1932 1933 mpss { 1934 memory-region = <&mpss_mem>; 1935 }; 1936 1937 bam_dmux: bam-dmux { 1938 compatible = "qcom,bam-dmux"; 1939 1940 interrupt-parent = <&hexagon_smsm>; 1941 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1942 interrupt-names = "pc", "pc-ack"; 1943 1944 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1945 qcom,smem-state-names = "pc", "pc-ack"; 1946 1947 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1948 dma-names = "tx", "rx"; 1949 1950 status = "disabled"; 1951 }; 1952 1953 smd-edge { 1954 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1955 1956 qcom,smd-edge = <0>; 1957 qcom,ipc = <&apcs 8 12>; 1958 qcom,remote-pid = <1>; 1959 1960 label = "hexagon"; 1961 1962 fastrpc { 1963 compatible = "qcom,fastrpc"; 1964 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1965 label = "adsp"; 1966 qcom,non-secure-domain; 1967 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 1971 cb@1 { 1972 compatible = "qcom,fastrpc-compute-cb"; 1973 reg = <1>; 1974 }; 1975 }; 1976 }; 1977 }; 1978 1979 sound: sound@7702000 { 1980 status = "disabled"; 1981 compatible = "qcom,apq8016-sbc-sndcard"; 1982 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1983 reg-names = "mic-iomux", "spkr-iomux"; 1984 }; 1985 1986 lpass: audio-controller@7708000 { 1987 status = "disabled"; 1988 compatible = "qcom,apq8016-lpass-cpu"; 1989 1990 /* 1991 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1992 * is actually only used by Tertiary MI2S while 1993 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1994 */ 1995 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1996 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1997 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1998 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1999 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 2000 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 2001 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 2002 2003 clock-names = "ahbix-clk", 2004 "mi2s-bit-clk0", 2005 "mi2s-bit-clk1", 2006 "mi2s-bit-clk2", 2007 "mi2s-bit-clk3", 2008 "pcnoc-mport-clk", 2009 "pcnoc-sway-clk"; 2010 #sound-dai-cells = <1>; 2011 2012 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2013 interrupt-names = "lpass-irq-lpaif"; 2014 reg = <0x07708000 0x10000>; 2015 reg-names = "lpass-lpaif"; 2016 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 }; 2020 2021 lpass_codec: audio-codec@771c000 { 2022 compatible = "qcom,msm8916-wcd-digital-codec"; 2023 reg = <0x0771c000 0x400>; 2024 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2025 <&gcc GCC_CODEC_DIGCODEC_CLK>; 2026 clock-names = "ahbix-clk", "mclk"; 2027 #sound-dai-cells = <1>; 2028 status = "disabled"; 2029 }; 2030 2031 sdhc_1: mmc@7824900 { 2032 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2033 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 2034 reg-names = "hc", "core"; 2035 2036 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "hc_irq", "pwr_irq"; 2039 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2040 <&gcc GCC_SDCC1_APPS_CLK>, 2041 <&xo_board>; 2042 clock-names = "iface", "core", "xo"; 2043 pinctrl-0 = <&sdc1_default>; 2044 pinctrl-1 = <&sdc1_sleep>; 2045 pinctrl-names = "default", "sleep"; 2046 mmc-ddr-1_8v; 2047 bus-width = <8>; 2048 non-removable; 2049 status = "disabled"; 2050 }; 2051 2052 sdhc_2: mmc@7864900 { 2053 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2054 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 2055 reg-names = "hc", "core"; 2056 2057 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2059 interrupt-names = "hc_irq", "pwr_irq"; 2060 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2061 <&gcc GCC_SDCC2_APPS_CLK>, 2062 <&xo_board>; 2063 clock-names = "iface", "core", "xo"; 2064 pinctrl-0 = <&sdc2_default>; 2065 pinctrl-1 = <&sdc2_sleep>; 2066 pinctrl-names = "default", "sleep"; 2067 bus-width = <4>; 2068 status = "disabled"; 2069 }; 2070 2071 blsp_dma: dma-controller@7884000 { 2072 compatible = "qcom,bam-v1.7.0"; 2073 reg = <0x07884000 0x23000>; 2074 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2075 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2076 clock-names = "bam_clk"; 2077 #dma-cells = <1>; 2078 qcom,ee = <0>; 2079 }; 2080 2081 blsp_uart1: serial@78af000 { 2082 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2083 reg = <0x078af000 0x200>; 2084 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2085 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2086 clock-names = "core", "iface"; 2087 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 2088 dma-names = "tx", "rx"; 2089 pinctrl-names = "default", "sleep"; 2090 pinctrl-0 = <&blsp_uart1_default>; 2091 pinctrl-1 = <&blsp_uart1_sleep>; 2092 status = "disabled"; 2093 }; 2094 2095 blsp_uart2: serial@78b0000 { 2096 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2097 reg = <0x078b0000 0x200>; 2098 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2099 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2100 clock-names = "core", "iface"; 2101 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 2102 dma-names = "tx", "rx"; 2103 pinctrl-names = "default", "sleep"; 2104 pinctrl-0 = <&blsp_uart2_default>; 2105 pinctrl-1 = <&blsp_uart2_sleep>; 2106 status = "disabled"; 2107 }; 2108 2109 blsp_i2c1: i2c@78b5000 { 2110 compatible = "qcom,i2c-qup-v2.2.1"; 2111 reg = <0x078b5000 0x500>; 2112 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2113 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2114 <&gcc GCC_BLSP1_AHB_CLK>; 2115 clock-names = "core", "iface"; 2116 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2117 dma-names = "tx", "rx"; 2118 pinctrl-names = "default", "sleep"; 2119 pinctrl-0 = <&blsp_i2c1_default>; 2120 pinctrl-1 = <&blsp_i2c1_sleep>; 2121 #address-cells = <1>; 2122 #size-cells = <0>; 2123 status = "disabled"; 2124 }; 2125 2126 blsp_spi1: spi@78b5000 { 2127 compatible = "qcom,spi-qup-v2.2.1"; 2128 reg = <0x078b5000 0x500>; 2129 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2130 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2131 <&gcc GCC_BLSP1_AHB_CLK>; 2132 clock-names = "core", "iface"; 2133 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2134 dma-names = "tx", "rx"; 2135 pinctrl-names = "default", "sleep"; 2136 pinctrl-0 = <&blsp_spi1_default>; 2137 pinctrl-1 = <&blsp_spi1_sleep>; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 status = "disabled"; 2141 }; 2142 2143 blsp_i2c2: i2c@78b6000 { 2144 compatible = "qcom,i2c-qup-v2.2.1"; 2145 reg = <0x078b6000 0x500>; 2146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2147 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2148 <&gcc GCC_BLSP1_AHB_CLK>; 2149 clock-names = "core", "iface"; 2150 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2151 dma-names = "tx", "rx"; 2152 pinctrl-names = "default", "sleep"; 2153 pinctrl-0 = <&blsp_i2c2_default>; 2154 pinctrl-1 = <&blsp_i2c2_sleep>; 2155 #address-cells = <1>; 2156 #size-cells = <0>; 2157 status = "disabled"; 2158 }; 2159 2160 blsp_spi2: spi@78b6000 { 2161 compatible = "qcom,spi-qup-v2.2.1"; 2162 reg = <0x078b6000 0x500>; 2163 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2164 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2165 <&gcc GCC_BLSP1_AHB_CLK>; 2166 clock-names = "core", "iface"; 2167 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2168 dma-names = "tx", "rx"; 2169 pinctrl-names = "default", "sleep"; 2170 pinctrl-0 = <&blsp_spi2_default>; 2171 pinctrl-1 = <&blsp_spi2_sleep>; 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 status = "disabled"; 2175 }; 2176 2177 blsp_i2c3: i2c@78b7000 { 2178 compatible = "qcom,i2c-qup-v2.2.1"; 2179 reg = <0x078b7000 0x500>; 2180 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2181 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2182 <&gcc GCC_BLSP1_AHB_CLK>; 2183 clock-names = "core", "iface"; 2184 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2185 dma-names = "tx", "rx"; 2186 pinctrl-names = "default", "sleep"; 2187 pinctrl-0 = <&blsp_i2c3_default>; 2188 pinctrl-1 = <&blsp_i2c3_sleep>; 2189 #address-cells = <1>; 2190 #size-cells = <0>; 2191 status = "disabled"; 2192 }; 2193 2194 blsp_spi3: spi@78b7000 { 2195 compatible = "qcom,spi-qup-v2.2.1"; 2196 reg = <0x078b7000 0x500>; 2197 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2199 <&gcc GCC_BLSP1_AHB_CLK>; 2200 clock-names = "core", "iface"; 2201 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2202 dma-names = "tx", "rx"; 2203 pinctrl-names = "default", "sleep"; 2204 pinctrl-0 = <&blsp_spi3_default>; 2205 pinctrl-1 = <&blsp_spi3_sleep>; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 status = "disabled"; 2209 }; 2210 2211 blsp_i2c4: i2c@78b8000 { 2212 compatible = "qcom,i2c-qup-v2.2.1"; 2213 reg = <0x078b8000 0x500>; 2214 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2215 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2216 <&gcc GCC_BLSP1_AHB_CLK>; 2217 clock-names = "core", "iface"; 2218 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2219 dma-names = "tx", "rx"; 2220 pinctrl-names = "default", "sleep"; 2221 pinctrl-0 = <&blsp_i2c4_default>; 2222 pinctrl-1 = <&blsp_i2c4_sleep>; 2223 #address-cells = <1>; 2224 #size-cells = <0>; 2225 status = "disabled"; 2226 }; 2227 2228 blsp_spi4: spi@78b8000 { 2229 compatible = "qcom,spi-qup-v2.2.1"; 2230 reg = <0x078b8000 0x500>; 2231 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2232 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2233 <&gcc GCC_BLSP1_AHB_CLK>; 2234 clock-names = "core", "iface"; 2235 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2236 dma-names = "tx", "rx"; 2237 pinctrl-names = "default", "sleep"; 2238 pinctrl-0 = <&blsp_spi4_default>; 2239 pinctrl-1 = <&blsp_spi4_sleep>; 2240 #address-cells = <1>; 2241 #size-cells = <0>; 2242 status = "disabled"; 2243 }; 2244 2245 blsp_i2c5: i2c@78b9000 { 2246 compatible = "qcom,i2c-qup-v2.2.1"; 2247 reg = <0x078b9000 0x500>; 2248 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2250 <&gcc GCC_BLSP1_AHB_CLK>; 2251 clock-names = "core", "iface"; 2252 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2253 dma-names = "tx", "rx"; 2254 pinctrl-names = "default", "sleep"; 2255 pinctrl-0 = <&blsp_i2c5_default>; 2256 pinctrl-1 = <&blsp_i2c5_sleep>; 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 status = "disabled"; 2260 }; 2261 2262 blsp_spi5: spi@78b9000 { 2263 compatible = "qcom,spi-qup-v2.2.1"; 2264 reg = <0x078b9000 0x500>; 2265 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2266 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2267 <&gcc GCC_BLSP1_AHB_CLK>; 2268 clock-names = "core", "iface"; 2269 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2270 dma-names = "tx", "rx"; 2271 pinctrl-names = "default", "sleep"; 2272 pinctrl-0 = <&blsp_spi5_default>; 2273 pinctrl-1 = <&blsp_spi5_sleep>; 2274 #address-cells = <1>; 2275 #size-cells = <0>; 2276 status = "disabled"; 2277 }; 2278 2279 blsp_i2c6: i2c@78ba000 { 2280 compatible = "qcom,i2c-qup-v2.2.1"; 2281 reg = <0x078ba000 0x500>; 2282 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2283 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2284 <&gcc GCC_BLSP1_AHB_CLK>; 2285 clock-names = "core", "iface"; 2286 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2287 dma-names = "tx", "rx"; 2288 pinctrl-names = "default", "sleep"; 2289 pinctrl-0 = <&blsp_i2c6_default>; 2290 pinctrl-1 = <&blsp_i2c6_sleep>; 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 status = "disabled"; 2294 }; 2295 2296 blsp_spi6: spi@78ba000 { 2297 compatible = "qcom,spi-qup-v2.2.1"; 2298 reg = <0x078ba000 0x500>; 2299 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2300 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2301 <&gcc GCC_BLSP1_AHB_CLK>; 2302 clock-names = "core", "iface"; 2303 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2304 dma-names = "tx", "rx"; 2305 pinctrl-names = "default", "sleep"; 2306 pinctrl-0 = <&blsp_spi6_default>; 2307 pinctrl-1 = <&blsp_spi6_sleep>; 2308 #address-cells = <1>; 2309 #size-cells = <0>; 2310 status = "disabled"; 2311 }; 2312 2313 usb: usb@78d9000 { 2314 compatible = "qcom,ci-hdrc"; 2315 reg = <0x078d9000 0x200>, 2316 <0x078d9200 0x200>; 2317 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2319 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2320 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2321 clock-names = "iface", "core"; 2322 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2323 assigned-clock-rates = <80000000>; 2324 resets = <&gcc GCC_USB_HS_BCR>; 2325 reset-names = "core"; 2326 phy_type = "ulpi"; 2327 dr_mode = "otg"; 2328 hnp-disable; 2329 srp-disable; 2330 adp-disable; 2331 ahb-burst-config = <0>; 2332 phy-names = "usb-phy"; 2333 phys = <&usb_hs_phy>; 2334 status = "disabled"; 2335 #reset-cells = <1>; 2336 2337 ulpi { 2338 usb_hs_phy: phy { 2339 compatible = "qcom,usb-hs-phy-msm8916", 2340 "qcom,usb-hs-phy"; 2341 #phy-cells = <0>; 2342 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2343 clock-names = "ref", "sleep"; 2344 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2345 reset-names = "phy", "por"; 2346 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2347 <0x1 0x6b>, 2348 <0x2 0x24>, 2349 <0x3 0x13>; 2350 }; 2351 }; 2352 }; 2353 2354 wcnss: remoteproc@a204000 { 2355 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2356 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2357 reg-names = "ccu", "dxe", "pmu"; 2358 2359 memory-region = <&wcnss_mem>; 2360 2361 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2362 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2363 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2364 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2365 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2366 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2367 2368 power-domains = <&rpmpd MSM8916_VDDCX>, 2369 <&rpmpd MSM8916_VDDMX>; 2370 power-domain-names = "cx", "mx"; 2371 2372 qcom,smem-states = <&wcnss_smp2p_out 0>; 2373 qcom,smem-state-names = "stop"; 2374 2375 pinctrl-names = "default"; 2376 pinctrl-0 = <&wcss_wlan_default>; 2377 2378 status = "disabled"; 2379 2380 wcnss_iris: iris { 2381 /* Separate chip, compatible is board-specific */ 2382 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2383 clock-names = "xo"; 2384 }; 2385 2386 smd-edge { 2387 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2388 2389 qcom,ipc = <&apcs 8 17>; 2390 qcom,smd-edge = <6>; 2391 qcom,remote-pid = <4>; 2392 2393 label = "pronto"; 2394 2395 wcnss_ctrl: wcnss { 2396 compatible = "qcom,wcnss"; 2397 qcom,smd-channels = "WCNSS_CTRL"; 2398 2399 qcom,mmio = <&wcnss>; 2400 2401 wcnss_bt: bluetooth { 2402 compatible = "qcom,wcnss-bt"; 2403 }; 2404 2405 wcnss_wifi: wifi { 2406 compatible = "qcom,wcnss-wlan"; 2407 2408 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2410 interrupt-names = "tx", "rx"; 2411 2412 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2413 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 2414 }; 2415 }; 2416 }; 2417 }; 2418 2419 intc: interrupt-controller@b000000 { 2420 compatible = "qcom,msm-qgic2"; 2421 interrupt-controller; 2422 #interrupt-cells = <3>; 2423 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2424 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2425 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2426 }; 2427 2428 apcs: mailbox@b011000 { 2429 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 2430 reg = <0x0b011000 0x1000>; 2431 #mbox-cells = <1>; 2432 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 2433 clock-names = "pll", "aux"; 2434 #clock-cells = <0>; 2435 }; 2436 2437 a53pll: clock@b016000 { 2438 compatible = "qcom,msm8916-a53pll"; 2439 reg = <0x0b016000 0x40>; 2440 #clock-cells = <0>; 2441 clocks = <&xo_board>; 2442 clock-names = "xo"; 2443 }; 2444 2445 timer@b020000 { 2446 #address-cells = <1>; 2447 #size-cells = <1>; 2448 ranges; 2449 compatible = "arm,armv7-timer-mem"; 2450 reg = <0x0b020000 0x1000>; 2451 clock-frequency = <19200000>; 2452 2453 frame@b021000 { 2454 frame-number = <0>; 2455 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2457 reg = <0x0b021000 0x1000>, 2458 <0x0b022000 0x1000>; 2459 }; 2460 2461 frame@b023000 { 2462 frame-number = <1>; 2463 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2464 reg = <0x0b023000 0x1000>; 2465 status = "disabled"; 2466 }; 2467 2468 frame@b024000 { 2469 frame-number = <2>; 2470 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2471 reg = <0x0b024000 0x1000>; 2472 status = "disabled"; 2473 }; 2474 2475 frame@b025000 { 2476 frame-number = <3>; 2477 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2478 reg = <0x0b025000 0x1000>; 2479 status = "disabled"; 2480 }; 2481 2482 frame@b026000 { 2483 frame-number = <4>; 2484 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2485 reg = <0x0b026000 0x1000>; 2486 status = "disabled"; 2487 }; 2488 2489 frame@b027000 { 2490 frame-number = <5>; 2491 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2492 reg = <0x0b027000 0x1000>; 2493 status = "disabled"; 2494 }; 2495 2496 frame@b028000 { 2497 frame-number = <6>; 2498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2499 reg = <0x0b028000 0x1000>; 2500 status = "disabled"; 2501 }; 2502 }; 2503 2504 cpu0_acc: power-manager@b088000 { 2505 compatible = "qcom,msm8916-acc"; 2506 reg = <0x0b088000 0x1000>; 2507 status = "reserved"; /* Controlled by PSCI firmware */ 2508 }; 2509 2510 cpu0_saw: power-manager@b089000 { 2511 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2512 reg = <0x0b089000 0x1000>; 2513 status = "reserved"; /* Controlled by PSCI firmware */ 2514 }; 2515 2516 cpu1_acc: power-manager@b098000 { 2517 compatible = "qcom,msm8916-acc"; 2518 reg = <0x0b098000 0x1000>; 2519 status = "reserved"; /* Controlled by PSCI firmware */ 2520 }; 2521 2522 cpu1_saw: power-manager@b099000 { 2523 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2524 reg = <0x0b099000 0x1000>; 2525 status = "reserved"; /* Controlled by PSCI firmware */ 2526 }; 2527 2528 cpu2_acc: power-manager@b0a8000 { 2529 compatible = "qcom,msm8916-acc"; 2530 reg = <0x0b0a8000 0x1000>; 2531 status = "reserved"; /* Controlled by PSCI firmware */ 2532 }; 2533 2534 cpu2_saw: power-manager@b0a9000 { 2535 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2536 reg = <0x0b0a9000 0x1000>; 2537 status = "reserved"; /* Controlled by PSCI firmware */ 2538 }; 2539 2540 cpu3_acc: power-manager@b0b8000 { 2541 compatible = "qcom,msm8916-acc"; 2542 reg = <0x0b0b8000 0x1000>; 2543 status = "reserved"; /* Controlled by PSCI firmware */ 2544 }; 2545 2546 cpu3_saw: power-manager@b0b9000 { 2547 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2548 reg = <0x0b0b9000 0x1000>; 2549 status = "reserved"; /* Controlled by PSCI firmware */ 2550 }; 2551 }; 2552 2553 thermal-zones { 2554 cpu0-1-thermal { 2555 polling-delay-passive = <250>; 2556 polling-delay = <1000>; 2557 2558 thermal-sensors = <&tsens 5>; 2559 2560 trips { 2561 cpu0_1_alert0: trip-point0 { 2562 temperature = <75000>; 2563 hysteresis = <2000>; 2564 type = "passive"; 2565 }; 2566 cpu0_1_crit: cpu-crit { 2567 temperature = <110000>; 2568 hysteresis = <2000>; 2569 type = "critical"; 2570 }; 2571 }; 2572 2573 cooling-maps { 2574 map0 { 2575 trip = <&cpu0_1_alert0>; 2576 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2577 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2578 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2579 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2580 }; 2581 }; 2582 }; 2583 2584 cpu2-3-thermal { 2585 polling-delay-passive = <250>; 2586 polling-delay = <1000>; 2587 2588 thermal-sensors = <&tsens 4>; 2589 2590 trips { 2591 cpu2_3_alert0: trip-point0 { 2592 temperature = <75000>; 2593 hysteresis = <2000>; 2594 type = "passive"; 2595 }; 2596 cpu2_3_crit: cpu-crit { 2597 temperature = <110000>; 2598 hysteresis = <2000>; 2599 type = "critical"; 2600 }; 2601 }; 2602 2603 cooling-maps { 2604 map0 { 2605 trip = <&cpu2_3_alert0>; 2606 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2607 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2608 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2609 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2610 }; 2611 }; 2612 }; 2613 2614 gpu-thermal { 2615 polling-delay-passive = <250>; 2616 polling-delay = <1000>; 2617 2618 thermal-sensors = <&tsens 2>; 2619 2620 trips { 2621 gpu_alert0: trip-point0 { 2622 temperature = <75000>; 2623 hysteresis = <2000>; 2624 type = "passive"; 2625 }; 2626 gpu_crit: gpu-crit { 2627 temperature = <95000>; 2628 hysteresis = <2000>; 2629 type = "critical"; 2630 }; 2631 }; 2632 }; 2633 2634 camera-thermal { 2635 polling-delay-passive = <250>; 2636 polling-delay = <1000>; 2637 2638 thermal-sensors = <&tsens 1>; 2639 2640 trips { 2641 cam_alert0: trip-point0 { 2642 temperature = <75000>; 2643 hysteresis = <2000>; 2644 type = "hot"; 2645 }; 2646 }; 2647 }; 2648 2649 modem-thermal { 2650 polling-delay-passive = <250>; 2651 polling-delay = <1000>; 2652 2653 thermal-sensors = <&tsens 0>; 2654 2655 trips { 2656 modem_alert0: trip-point0 { 2657 temperature = <85000>; 2658 hysteresis = <2000>; 2659 type = "hot"; 2660 }; 2661 }; 2662 }; 2663 }; 2664 2665 timer { 2666 compatible = "arm,armv8-timer"; 2667 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2668 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2669 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2670 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2671 }; 2672}; 2673