xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8916.dtsi (revision 5d0e4d78)
1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/clock/qcom,gcc-msm8916.h>
16#include <dt-bindings/reset/qcom,gcc-msm8916.h>
17#include <dt-bindings/clock/qcom,rpmcc.h>
18
19/ {
20	model = "Qualcomm Technologies, Inc. MSM8916";
21	compatible = "qcom,msm8916";
22
23	interrupt-parent = <&intc>;
24
25	#address-cells = <2>;
26	#size-cells = <2>;
27
28	aliases {
29		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
30		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
31	};
32
33	chosen { };
34
35	memory {
36		device_type = "memory";
37		/* We expect the bootloader to fill in the reg */
38		reg = <0 0 0 0>;
39	};
40
41	reserved-memory {
42		#address-cells = <2>;
43		#size-cells = <2>;
44		ranges;
45
46		tz-apps@86000000 {
47			reg = <0x0 0x86000000 0x0 0x300000>;
48			no-map;
49		};
50
51		smem_mem: smem_region@86300000 {
52			reg = <0x0 0x86300000 0x0 0x100000>;
53			no-map;
54		};
55
56		hypervisor@86400000 {
57			reg = <0x0 0x86400000 0x0 0x100000>;
58			no-map;
59		};
60
61		tz@86500000 {
62			reg = <0x0 0x86500000 0x0 0x180000>;
63			no-map;
64		};
65
66		reserved@8668000 {
67			reg = <0x0 0x86680000 0x0 0x80000>;
68			no-map;
69		};
70
71		rmtfs@86700000 {
72			reg = <0x0 0x86700000 0x0 0xe0000>;
73			no-map;
74		};
75
76		rfsa@867e00000 {
77			reg = <0x0 0x867e0000 0x0 0x20000>;
78			no-map;
79		};
80
81		mpss_mem: mpss@86800000 {
82			reg = <0x0 0x86800000 0x0 0x2b00000>;
83			no-map;
84		};
85
86		wcnss_mem: wcnss@89300000 {
87			reg = <0x0 0x89300000 0x0 0x600000>;
88			no-map;
89		};
90
91		mba_mem: mba@8ea00000 {
92			no-map;
93			reg = <0 0x8ea00000 0 0x100000>;
94		};
95	};
96
97	cpus {
98		#address-cells = <1>;
99		#size-cells = <0>;
100
101		CPU0: cpu@0 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a53", "arm,armv8";
104			reg = <0x0>;
105			next-level-cache = <&L2_0>;
106			enable-method = "psci";
107			cpu-idle-states = <&CPU_SPC>;
108		};
109
110		CPU1: cpu@1 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a53", "arm,armv8";
113			reg = <0x1>;
114			next-level-cache = <&L2_0>;
115			enable-method = "psci";
116			cpu-idle-states = <&CPU_SPC>;
117		};
118
119		CPU2: cpu@2 {
120			device_type = "cpu";
121			compatible = "arm,cortex-a53", "arm,armv8";
122			reg = <0x2>;
123			next-level-cache = <&L2_0>;
124			enable-method = "psci";
125			cpu-idle-states = <&CPU_SPC>;
126		};
127
128		CPU3: cpu@3 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a53", "arm,armv8";
131			reg = <0x3>;
132			next-level-cache = <&L2_0>;
133			enable-method = "psci";
134			cpu-idle-states = <&CPU_SPC>;
135		};
136
137		L2_0: l2-cache {
138		      compatible = "cache";
139		      cache-level = <2>;
140		};
141
142		idle-states {
143			CPU_SPC: spc {
144				compatible = "arm,idle-state";
145				arm,psci-suspend-param = <0x40000002>;
146				entry-latency-us = <130>;
147				exit-latency-us = <150>;
148				min-residency-us = <2000>;
149				local-timer-stop;
150			};
151		};
152	};
153
154	psci {
155		compatible = "arm,psci-1.0";
156		method = "smc";
157	};
158
159	pmu {
160		compatible = "arm,cortex-a53-pmu";
161		interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
162	};
163
164	thermal-zones {
165		cpu-thermal0 {
166			polling-delay-passive = <250>;
167			polling-delay = <1000>;
168
169			thermal-sensors = <&tsens 4>;
170
171			trips {
172				cpu_alert0: trip0 {
173					temperature = <75000>;
174					hysteresis = <2000>;
175					type = "passive";
176				};
177				cpu_crit0: trip1 {
178					temperature = <110000>;
179					hysteresis = <2000>;
180					type = "critical";
181				};
182			};
183		};
184
185		cpu-thermal1 {
186			polling-delay-passive = <250>;
187			polling-delay = <1000>;
188
189			thermal-sensors = <&tsens 3>;
190
191			trips {
192				cpu_alert1: trip0 {
193					temperature = <75000>;
194					hysteresis = <2000>;
195					type = "passive";
196				};
197				cpu_crit1: trip1 {
198					temperature = <110000>;
199					hysteresis = <2000>;
200					type = "critical";
201				};
202			};
203		};
204
205	};
206
207	timer {
208		compatible = "arm,armv8-timer";
209		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
211			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
212			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
213	};
214
215	clocks {
216		xo_board: xo_board {
217			compatible = "fixed-clock";
218			#clock-cells = <0>;
219			clock-frequency = <19200000>;
220		};
221
222		sleep_clk: sleep_clk {
223			compatible = "fixed-clock";
224			#clock-cells = <0>;
225			clock-frequency = <32768>;
226		};
227	};
228
229	smem {
230		compatible = "qcom,smem";
231
232		memory-region = <&smem_mem>;
233		qcom,rpm-msg-ram = <&rpm_msg_ram>;
234
235		hwlocks = <&tcsr_mutex 3>;
236	};
237
238	firmware {
239		scm: scm {
240			compatible = "qcom,scm";
241			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
242			clock-names = "core", "bus", "iface";
243			#reset-cells = <1>;
244		};
245	};
246
247	soc: soc {
248		#address-cells = <1>;
249		#size-cells = <1>;
250		ranges = <0 0 0 0xffffffff>;
251		compatible = "simple-bus";
252
253		restart@4ab000 {
254			compatible = "qcom,pshold";
255			reg = <0x4ab000 0x4>;
256		};
257
258		msmgpio: pinctrl@1000000 {
259			compatible = "qcom,msm8916-pinctrl";
260			reg = <0x1000000 0x300000>;
261			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
262			gpio-controller;
263			#gpio-cells = <2>;
264			interrupt-controller;
265			#interrupt-cells = <2>;
266		};
267
268		gcc: clock-controller@1800000 {
269			compatible = "qcom,gcc-msm8916";
270			#clock-cells = <1>;
271			#reset-cells = <1>;
272			#power-domain-cells = <1>;
273			reg = <0x1800000 0x80000>;
274		};
275
276		tcsr_mutex_regs: syscon@1905000 {
277			compatible = "syscon";
278			reg = <0x1905000 0x20000>;
279		};
280
281		tcsr: syscon@1937000 {
282			compatible = "qcom,tcsr-msm8916", "syscon";
283			reg = <0x1937000 0x30000>;
284		};
285
286		tcsr_mutex: hwlock {
287			compatible = "qcom,tcsr-mutex";
288			syscon = <&tcsr_mutex_regs 0 0x1000>;
289			#hwlock-cells = <1>;
290		};
291
292		rpm_msg_ram: memory@60000 {
293			compatible = "qcom,rpm-msg-ram";
294			reg = <0x60000 0x8000>;
295		};
296
297		blsp1_uart1: serial@78af000 {
298			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
299			reg = <0x78af000 0x200>;
300			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
301			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
302			clock-names = "core", "iface";
303			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
304			dma-names = "rx", "tx";
305			status = "disabled";
306		};
307
308		apcs: syscon@b011000 {
309			compatible = "syscon";
310			reg = <0x0b011000 0x1000>;
311		};
312
313		blsp1_uart2: serial@78b0000 {
314			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
315			reg = <0x78b0000 0x200>;
316			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
317			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
318			clock-names = "core", "iface";
319			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
320			dma-names = "rx", "tx";
321			status = "disabled";
322		};
323
324		blsp_dma: dma@7884000 {
325			compatible = "qcom,bam-v1.7.0";
326			reg = <0x07884000 0x23000>;
327			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
328			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
329			clock-names = "bam_clk";
330			#dma-cells = <1>;
331			qcom,ee = <0>;
332			status = "disabled";
333		};
334
335		blsp_spi1: spi@78b5000 {
336			compatible = "qcom,spi-qup-v2.2.1";
337			reg = <0x078b5000 0x600>;
338			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
339			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
340				 <&gcc GCC_BLSP1_AHB_CLK>;
341			clock-names = "core", "iface";
342			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
343			dma-names = "rx", "tx";
344			pinctrl-names = "default", "sleep";
345			pinctrl-0 = <&spi1_default>;
346			pinctrl-1 = <&spi1_sleep>;
347			#address-cells = <1>;
348			#size-cells = <0>;
349			status = "disabled";
350		};
351
352		blsp_spi2: spi@78b6000 {
353			compatible = "qcom,spi-qup-v2.2.1";
354			reg = <0x078b6000 0x600>;
355			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
357				 <&gcc GCC_BLSP1_AHB_CLK>;
358			clock-names = "core", "iface";
359			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
360			dma-names = "rx", "tx";
361			pinctrl-names = "default", "sleep";
362			pinctrl-0 = <&spi2_default>;
363			pinctrl-1 = <&spi2_sleep>;
364			#address-cells = <1>;
365			#size-cells = <0>;
366			status = "disabled";
367		};
368
369		blsp_spi3: spi@78b7000 {
370			compatible = "qcom,spi-qup-v2.2.1";
371			reg = <0x078b7000 0x600>;
372			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
373			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
374				 <&gcc GCC_BLSP1_AHB_CLK>;
375			clock-names = "core", "iface";
376			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
377			dma-names = "rx", "tx";
378			pinctrl-names = "default", "sleep";
379			pinctrl-0 = <&spi3_default>;
380			pinctrl-1 = <&spi3_sleep>;
381			#address-cells = <1>;
382			#size-cells = <0>;
383			status = "disabled";
384		};
385
386		blsp_spi4: spi@78b8000 {
387			compatible = "qcom,spi-qup-v2.2.1";
388			reg = <0x078b8000 0x600>;
389			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
390			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
391				 <&gcc GCC_BLSP1_AHB_CLK>;
392			clock-names = "core", "iface";
393			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
394			dma-names = "rx", "tx";
395			pinctrl-names = "default", "sleep";
396			pinctrl-0 = <&spi4_default>;
397			pinctrl-1 = <&spi4_sleep>;
398			#address-cells = <1>;
399			#size-cells = <0>;
400			status = "disabled";
401		};
402
403		blsp_spi5: spi@78b9000 {
404			compatible = "qcom,spi-qup-v2.2.1";
405			reg = <0x078b9000 0x600>;
406			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
407			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
408				 <&gcc GCC_BLSP1_AHB_CLK>;
409			clock-names = "core", "iface";
410			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
411			dma-names = "rx", "tx";
412			pinctrl-names = "default", "sleep";
413			pinctrl-0 = <&spi5_default>;
414			pinctrl-1 = <&spi5_sleep>;
415			#address-cells = <1>;
416			#size-cells = <0>;
417			status = "disabled";
418		};
419
420		blsp_spi6: spi@78ba000 {
421			compatible = "qcom,spi-qup-v2.2.1";
422			reg = <0x078ba000 0x600>;
423			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
424			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
425				 <&gcc GCC_BLSP1_AHB_CLK>;
426			clock-names = "core", "iface";
427			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
428			dma-names = "rx", "tx";
429			pinctrl-names = "default", "sleep";
430			pinctrl-0 = <&spi6_default>;
431			pinctrl-1 = <&spi6_sleep>;
432			#address-cells = <1>;
433			#size-cells = <0>;
434			status = "disabled";
435		};
436
437		blsp_i2c2: i2c@78b6000 {
438			compatible = "qcom,i2c-qup-v2.2.1";
439			reg = <0x78b6000 0x1000>;
440			interrupts = <GIC_SPI 96 0>;
441			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
442				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
443			clock-names = "iface", "core";
444			pinctrl-names = "default", "sleep";
445			pinctrl-0 = <&i2c2_default>;
446			pinctrl-1 = <&i2c2_sleep>;
447			#address-cells = <1>;
448			#size-cells = <0>;
449			status = "disabled";
450		};
451
452		blsp_i2c4: i2c@78b8000 {
453			compatible = "qcom,i2c-qup-v2.2.1";
454			reg = <0x78b8000 0x1000>;
455			interrupts = <GIC_SPI 98 0>;
456			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
457				<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
458			clock-names = "iface", "core";
459			pinctrl-names = "default", "sleep";
460			pinctrl-0 = <&i2c4_default>;
461			pinctrl-1 = <&i2c4_sleep>;
462			#address-cells = <1>;
463			#size-cells = <0>;
464			status = "disabled";
465		};
466
467		blsp_i2c6: i2c@78ba000 {
468			compatible = "qcom,i2c-qup-v2.2.1";
469			reg = <0x78ba000 0x1000>;
470			interrupts = <GIC_SPI 100 0>;
471			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
472				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
473			clock-names = "iface", "core";
474			pinctrl-names = "default", "sleep";
475			pinctrl-0 = <&i2c6_default>;
476			pinctrl-1 = <&i2c6_sleep>;
477			#address-cells = <1>;
478			#size-cells = <0>;
479			status = "disabled";
480		};
481
482		lpass: lpass@07708000 {
483			status = "disabled";
484			compatible = "qcom,lpass-cpu-apq8016";
485			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
486				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
487				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
488				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
489				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
490				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
491				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
492
493			clock-names = "ahbix-clk",
494					"pcnoc-mport-clk",
495					"pcnoc-sway-clk",
496					"mi2s-bit-clk0",
497					"mi2s-bit-clk1",
498					"mi2s-bit-clk2",
499					"mi2s-bit-clk3";
500			#sound-dai-cells = <1>;
501
502			interrupts = <0 160 0>;
503			interrupt-names = "lpass-irq-lpaif";
504			reg = <0x07708000 0x10000>;
505			reg-names = "lpass-lpaif";
506		};
507
508                lpass_codec: codec{
509			compatible = "qcom,msm8916-wcd-digital-codec";
510			reg = <0x0771c000 0x400>;
511			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
512				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
513			clock-names = "ahbix-clk", "mclk";
514			#sound-dai-cells = <1>;
515                };
516
517		sdhc_1: sdhci@07824000 {
518			compatible = "qcom,sdhci-msm-v4";
519			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
520			reg-names = "hc_mem", "core_mem";
521
522			interrupts = <0 123 0>, <0 138 0>;
523			interrupt-names = "hc_irq", "pwr_irq";
524			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
525				 <&gcc GCC_SDCC1_AHB_CLK>,
526				 <&xo_board>;
527			clock-names = "core", "iface", "xo";
528			mmc-ddr-1_8v;
529			bus-width = <8>;
530			non-removable;
531			status = "disabled";
532		};
533
534		sdhc_2: sdhci@07864000 {
535			compatible = "qcom,sdhci-msm-v4";
536			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
537			reg-names = "hc_mem", "core_mem";
538
539			interrupts = <0 125 0>, <0 221 0>;
540			interrupt-names = "hc_irq", "pwr_irq";
541			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
542				 <&gcc GCC_SDCC2_AHB_CLK>,
543				 <&xo_board>;
544			clock-names = "core", "iface", "xo";
545			bus-width = <4>;
546			status = "disabled";
547		};
548
549		otg: usb@78d9000 {
550			compatible = "qcom,ci-hdrc";
551			reg = <0x78d9000 0x200>,
552			      <0x78d9200 0x200>;
553			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
554				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
555			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
556				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
557			clock-names = "iface", "core";
558			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
559			assigned-clock-rates = <80000000>;
560			resets = <&gcc GCC_USB_HS_BCR>;
561			reset-names = "core";
562			phy_type = "ulpi";
563			dr_mode = "otg";
564			ahb-burst-config = <0>;
565			phy-names = "usb-phy";
566			phys = <&usb_hs_phy>;
567			status = "disabled";
568			#reset-cells = <1>;
569
570			ulpi {
571				usb_hs_phy: phy {
572					compatible = "qcom,usb-hs-phy-msm8916",
573						     "qcom,usb-hs-phy";
574					#phy-cells = <0>;
575					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
576					clock-names = "ref", "sleep";
577					resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
578					reset-names = "phy", "por";
579					qcom,init-seq = /bits/ 8 <0x0 0x44
580						0x1 0x6b 0x2 0x24 0x3 0x13>;
581				};
582			};
583		};
584
585		intc: interrupt-controller@b000000 {
586			compatible = "qcom,msm-qgic2";
587			interrupt-controller;
588			#interrupt-cells = <3>;
589			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
590		};
591
592		timer@b020000 {
593			#address-cells = <1>;
594			#size-cells = <1>;
595			ranges;
596			compatible = "arm,armv7-timer-mem";
597			reg = <0xb020000 0x1000>;
598			clock-frequency = <19200000>;
599
600			frame@b021000 {
601				frame-number = <0>;
602				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
603					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
604				reg = <0xb021000 0x1000>,
605				      <0xb022000 0x1000>;
606			};
607
608			frame@b023000 {
609				frame-number = <1>;
610				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
611				reg = <0xb023000 0x1000>;
612				status = "disabled";
613			};
614
615			frame@b024000 {
616				frame-number = <2>;
617				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
618				reg = <0xb024000 0x1000>;
619				status = "disabled";
620			};
621
622			frame@b025000 {
623				frame-number = <3>;
624				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
625				reg = <0xb025000 0x1000>;
626				status = "disabled";
627			};
628
629			frame@b026000 {
630				frame-number = <4>;
631				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
632				reg = <0xb026000 0x1000>;
633				status = "disabled";
634			};
635
636			frame@b027000 {
637				frame-number = <5>;
638				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
639				reg = <0xb027000 0x1000>;
640				status = "disabled";
641			};
642
643			frame@b028000 {
644				frame-number = <6>;
645				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
646				reg = <0xb028000 0x1000>;
647				status = "disabled";
648			};
649		};
650
651		spmi_bus: spmi@200f000 {
652			compatible = "qcom,spmi-pmic-arb";
653			reg = <0x200f000 0x001000>,
654			      <0x2400000 0x400000>,
655			      <0x2c00000 0x400000>,
656			      <0x3800000 0x200000>,
657			      <0x200a000 0x002100>;
658			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
659			interrupt-names = "periph_irq";
660			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
661			qcom,ee = <0>;
662			qcom,channel = <0>;
663			#address-cells = <2>;
664			#size-cells = <0>;
665			interrupt-controller;
666			#interrupt-cells = <4>;
667		};
668
669		rng@22000 {
670			compatible = "qcom,prng";
671			reg = <0x00022000 0x200>;
672			clocks = <&gcc GCC_PRNG_AHB_CLK>;
673			clock-names = "core";
674		};
675
676		qfprom: qfprom@5c000 {
677			compatible = "qcom,qfprom";
678			reg = <0x5c000 0x1000>;
679			#address-cells = <1>;
680			#size-cells = <1>;
681			tsens_caldata: caldata@d0 {
682				reg = <0xd0 0x8>;
683			};
684			tsens_calsel: calsel@ec {
685				reg = <0xec 0x4>;
686			};
687		};
688
689		tsens: thermal-sensor@4a8000 {
690			compatible = "qcom,msm8916-tsens";
691			reg = <0x4a8000 0x2000>;
692			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
693			nvmem-cell-names = "calib", "calib_sel";
694			#thermal-sensor-cells = <1>;
695		};
696
697		mdss: mdss@1a00000 {
698			compatible = "qcom,mdss";
699			reg = <0x1a00000 0x1000>,
700			      <0x1ac8000 0x3000>;
701			reg-names = "mdss_phys", "vbif_phys";
702
703			power-domains = <&gcc MDSS_GDSC>;
704
705			clocks = <&gcc GCC_MDSS_AHB_CLK>,
706				 <&gcc GCC_MDSS_AXI_CLK>,
707				 <&gcc GCC_MDSS_VSYNC_CLK>;
708			clock-names = "iface_clk",
709				      "bus_clk",
710				      "vsync_clk";
711
712			interrupts = <0 72 0>;
713
714			interrupt-controller;
715			#interrupt-cells = <1>;
716
717			#address-cells = <1>;
718			#size-cells = <1>;
719			ranges;
720
721			mdp: mdp@1a01000 {
722				compatible = "qcom,mdp5";
723				reg = <0x1a01000 0x90000>;
724				reg-names = "mdp_phys";
725
726				interrupt-parent = <&mdss>;
727				interrupts = <0 0>;
728
729				clocks = <&gcc GCC_MDSS_AHB_CLK>,
730					 <&gcc GCC_MDSS_AXI_CLK>,
731					 <&gcc GCC_MDSS_MDP_CLK>,
732					 <&gcc GCC_MDSS_VSYNC_CLK>;
733				clock-names = "iface_clk",
734					      "bus_clk",
735					      "core_clk",
736					      "vsync_clk";
737
738				ports {
739					#address-cells = <1>;
740					#size-cells = <0>;
741
742					port@0 {
743						reg = <0>;
744						mdp5_intf1_out: endpoint {
745							remote-endpoint = <&dsi0_in>;
746						};
747					};
748				};
749			};
750
751			dsi0: dsi@1a98000 {
752				compatible = "qcom,mdss-dsi-ctrl";
753				reg = <0x1a98000 0x25c>;
754				reg-names = "dsi_ctrl";
755
756				interrupt-parent = <&mdss>;
757				interrupts = <4 0>;
758
759				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
760						  <&gcc PCLK0_CLK_SRC>;
761				assigned-clock-parents = <&dsi_phy0 0>,
762							 <&dsi_phy0 1>;
763
764				clocks = <&gcc GCC_MDSS_MDP_CLK>,
765					 <&gcc GCC_MDSS_AHB_CLK>,
766					 <&gcc GCC_MDSS_AXI_CLK>,
767					 <&gcc GCC_MDSS_BYTE0_CLK>,
768					 <&gcc GCC_MDSS_PCLK0_CLK>,
769					 <&gcc GCC_MDSS_ESC0_CLK>;
770				clock-names = "mdp_core_clk",
771					      "iface_clk",
772					      "bus_clk",
773					      "byte_clk",
774					      "pixel_clk",
775					      "core_clk";
776				phys = <&dsi_phy0>;
777				phy-names = "dsi-phy";
778
779				ports {
780					#address-cells = <1>;
781					#size-cells = <0>;
782
783					port@0 {
784						reg = <0>;
785						dsi0_in: endpoint {
786							remote-endpoint = <&mdp5_intf1_out>;
787						};
788					};
789
790					port@1 {
791						reg = <1>;
792						dsi0_out: endpoint {
793						};
794					};
795				};
796			};
797
798			dsi_phy0: dsi-phy@1a98300 {
799				compatible = "qcom,dsi-phy-28nm-lp";
800				reg = <0x1a98300 0xd4>,
801				      <0x1a98500 0x280>,
802				      <0x1a98780 0x30>;
803				reg-names = "dsi_pll",
804					    "dsi_phy",
805					    "dsi_phy_regulator";
806
807				#clock-cells = <1>;
808
809				clocks = <&gcc GCC_MDSS_AHB_CLK>;
810				clock-names = "iface_clk";
811			};
812		};
813
814
815		hexagon@4080000 {
816			compatible = "qcom,q6v5-pil";
817			reg = <0x04080000 0x100>,
818			      <0x04020000 0x040>;
819
820			reg-names = "qdsp6", "rmb";
821
822			interrupts-extended = <&intc 0 24 1>,
823					      <&hexagon_smp2p_in 0 0>,
824					      <&hexagon_smp2p_in 1 0>,
825					      <&hexagon_smp2p_in 2 0>,
826					      <&hexagon_smp2p_in 3 0>;
827			interrupt-names = "wdog", "fatal", "ready",
828					  "handover", "stop-ack";
829
830			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
831				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
832				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
833				 <&xo_board>;
834			clock-names = "iface", "bus", "mem", "xo";
835
836			qcom,smem-states = <&hexagon_smp2p_out 0>;
837			qcom,smem-state-names = "stop";
838
839			resets = <&scm 0>;
840			reset-names = "mss_restart";
841
842			cx-supply = <&pm8916_s1>;
843			mx-supply = <&pm8916_l3>;
844			pll-supply = <&pm8916_l7>;
845
846			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
847
848			status = "disabled";
849
850			mba {
851				memory-region = <&mba_mem>;
852			};
853
854			mpss {
855				memory-region = <&mpss_mem>;
856			};
857
858			smd-edge {
859				interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
860
861				qcom,smd-edge = <0>;
862				qcom,ipc = <&apcs 8 12>;
863				qcom,remote-pid = <1>;
864
865				label = "hexagon";
866			};
867		};
868
869		pronto: wcnss@a21b000 {
870			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
871			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
872			reg-names = "ccu", "dxe", "pmu";
873
874			memory-region = <&wcnss_mem>;
875
876			interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
877					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
878					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
879					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
880					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
881			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
882
883			vddmx-supply = <&pm8916_l3>;
884			vddpx-supply = <&pm8916_l7>;
885
886			qcom,state = <&wcnss_smp2p_out 0>;
887			qcom,state-names = "stop";
888
889			pinctrl-names = "default";
890			pinctrl-0 = <&wcnss_pin_a>;
891
892			status = "disabled";
893
894			iris {
895				compatible = "qcom,wcn3620";
896
897				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
898				clock-names = "xo";
899
900				vddxo-supply = <&pm8916_l7>;
901				vddrfa-supply = <&pm8916_s3>;
902				vddpa-supply = <&pm8916_l9>;
903				vdddig-supply = <&pm8916_l5>;
904			};
905
906			smd-edge {
907				interrupts = <0 142 1>;
908
909				qcom,ipc = <&apcs 8 17>;
910				qcom,smd-edge = <6>;
911				qcom,remote-pid = <4>;
912
913				label = "pronto";
914
915				wcnss {
916					compatible = "qcom,wcnss";
917					qcom,smd-channels = "WCNSS_CTRL";
918
919					qcom,mmio = <&pronto>;
920
921					bt {
922						compatible = "qcom,wcnss-bt";
923					};
924
925					wifi {
926						compatible = "qcom,wcnss-wlan";
927
928						interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
929							     <0 146 IRQ_TYPE_LEVEL_HIGH>;
930						interrupt-names = "tx", "rx";
931
932						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
933						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
934					};
935				};
936			};
937		};
938
939		tpiu@820000 {
940			compatible = "arm,coresight-tpiu", "arm,primecell";
941			reg = <0x820000 0x1000>;
942
943			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
944			clock-names = "apb_pclk", "atclk";
945
946			port {
947				tpiu_in: endpoint {
948					slave-mode;
949					remote-endpoint = <&replicator_out1>;
950				};
951			};
952		};
953
954		funnel@821000 {
955			compatible = "arm,coresight-funnel", "arm,primecell";
956			reg = <0x821000 0x1000>;
957
958			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
959			clock-names = "apb_pclk", "atclk";
960
961			ports {
962				#address-cells = <1>;
963				#size-cells = <0>;
964
965				/*
966				 * Not described input ports:
967				 * 0 - connected to Resource and Power Manger CPU ETM
968				 * 1 - not-connected
969				 * 2 - connected to Modem CPU ETM
970				 * 3 - not-connected
971				 * 5 - not-connected
972				 * 6 - connected trought funnel to Wireless CPU ETM
973				 * 7 - connected to STM component
974				 */
975
976				port@4 {
977					reg = <4>;
978					funnel0_in4: endpoint {
979						slave-mode;
980						remote-endpoint = <&funnel1_out>;
981					};
982				};
983				port@8 {
984					reg = <0>;
985					funnel0_out: endpoint {
986						remote-endpoint = <&etf_in>;
987					};
988				};
989			};
990		};
991
992		replicator@824000 {
993			compatible = "qcom,coresight-replicator1x", "arm,primecell";
994			reg = <0x824000 0x1000>;
995
996			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
997			clock-names = "apb_pclk", "atclk";
998
999			ports {
1000				#address-cells = <1>;
1001				#size-cells = <0>;
1002
1003				port@0 {
1004					reg = <0>;
1005					replicator_out0: endpoint {
1006						remote-endpoint = <&etr_in>;
1007					};
1008				};
1009				port@1 {
1010					reg = <1>;
1011					replicator_out1: endpoint {
1012						remote-endpoint = <&tpiu_in>;
1013					};
1014				};
1015				port@2 {
1016					reg = <0>;
1017					replicator_in: endpoint {
1018						slave-mode;
1019						remote-endpoint = <&etf_out>;
1020					};
1021				};
1022			};
1023		};
1024
1025		etf@825000 {
1026			compatible = "arm,coresight-tmc", "arm,primecell";
1027			reg = <0x825000 0x1000>;
1028
1029			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1030			clock-names = "apb_pclk", "atclk";
1031
1032			ports {
1033				#address-cells = <1>;
1034				#size-cells = <0>;
1035
1036				port@0 {
1037					reg = <0>;
1038					etf_out: endpoint {
1039						slave-mode;
1040						remote-endpoint = <&funnel0_out>;
1041					};
1042				};
1043				port@1 {
1044					reg = <0>;
1045					etf_in: endpoint {
1046						remote-endpoint = <&replicator_in>;
1047					};
1048				};
1049			};
1050		};
1051
1052		etr@826000 {
1053			compatible = "arm,coresight-tmc", "arm,primecell";
1054			reg = <0x826000 0x1000>;
1055
1056			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1057			clock-names = "apb_pclk", "atclk";
1058
1059			port {
1060				etr_in: endpoint {
1061					slave-mode;
1062					remote-endpoint = <&replicator_out0>;
1063				};
1064			};
1065		};
1066
1067		funnel@841000 {	/* APSS funnel only 4 inputs are used */
1068			compatible = "arm,coresight-funnel", "arm,primecell";
1069			reg = <0x841000 0x1000>;
1070
1071			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1072			clock-names = "apb_pclk", "atclk";
1073
1074			ports {
1075				#address-cells = <1>;
1076				#size-cells = <0>;
1077
1078				port@0 {
1079					reg = <0>;
1080					funnel1_in0: endpoint {
1081						slave-mode;
1082						remote-endpoint = <&etm0_out>;
1083					};
1084				};
1085				port@1 {
1086					reg = <1>;
1087					funnel1_in1: endpoint {
1088						slave-mode;
1089						remote-endpoint = <&etm1_out>;
1090					};
1091				};
1092				port@2 {
1093					reg = <2>;
1094					funnel1_in2: endpoint {
1095						slave-mode;
1096						remote-endpoint = <&etm2_out>;
1097					};
1098				};
1099				port@3 {
1100					reg = <3>;
1101					funnel1_in3: endpoint {
1102						slave-mode;
1103						remote-endpoint = <&etm3_out>;
1104					};
1105				};
1106				port@4 {
1107					reg = <0>;
1108					funnel1_out: endpoint {
1109						remote-endpoint = <&funnel0_in4>;
1110					};
1111				};
1112			};
1113		};
1114
1115		debug@850000 {
1116			compatible = "arm,coresight-cpu-debug","arm,primecell";
1117			reg = <0x850000 0x1000>;
1118			clocks = <&rpmcc RPM_QDSS_CLK>;
1119			clock-names = "apb_pclk";
1120			cpu = <&CPU0>;
1121		};
1122
1123		debug@852000 {
1124			compatible = "arm,coresight-cpu-debug","arm,primecell";
1125			reg = <0x852000 0x1000>;
1126			clocks = <&rpmcc RPM_QDSS_CLK>;
1127			clock-names = "apb_pclk";
1128			cpu = <&CPU1>;
1129		};
1130
1131		debug@854000 {
1132			compatible = "arm,coresight-cpu-debug","arm,primecell";
1133			reg = <0x854000 0x1000>;
1134			clocks = <&rpmcc RPM_QDSS_CLK>;
1135			clock-names = "apb_pclk";
1136			cpu = <&CPU2>;
1137		};
1138
1139		debug@856000 {
1140			compatible = "arm,coresight-cpu-debug","arm,primecell";
1141			reg = <0x856000 0x1000>;
1142			clocks = <&rpmcc RPM_QDSS_CLK>;
1143			clock-names = "apb_pclk";
1144			cpu = <&CPU3>;
1145		};
1146
1147		etm@85c000 {
1148			compatible = "arm,coresight-etm4x", "arm,primecell";
1149			reg = <0x85c000 0x1000>;
1150
1151			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1152			clock-names = "apb_pclk", "atclk";
1153
1154			cpu = <&CPU0>;
1155
1156			port {
1157				etm0_out: endpoint {
1158				remote-endpoint = <&funnel1_in0>;
1159				};
1160			};
1161		};
1162
1163		etm@85d000 {
1164			compatible = "arm,coresight-etm4x", "arm,primecell";
1165			reg = <0x85d000 0x1000>;
1166
1167			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1168			clock-names = "apb_pclk", "atclk";
1169
1170			cpu = <&CPU1>;
1171
1172			port {
1173				etm1_out: endpoint {
1174					remote-endpoint = <&funnel1_in1>;
1175				};
1176			};
1177		};
1178
1179		etm@85e000 {
1180			compatible = "arm,coresight-etm4x", "arm,primecell";
1181			reg = <0x85e000 0x1000>;
1182
1183			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1184			clock-names = "apb_pclk", "atclk";
1185
1186			cpu = <&CPU2>;
1187
1188			port {
1189				etm2_out: endpoint {
1190					remote-endpoint = <&funnel1_in2>;
1191				};
1192			};
1193		};
1194
1195		etm@85f000 {
1196			compatible = "arm,coresight-etm4x", "arm,primecell";
1197			reg = <0x85f000 0x1000>;
1198
1199			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1200			clock-names = "apb_pclk", "atclk";
1201
1202			cpu = <&CPU3>;
1203
1204			port {
1205				etm3_out: endpoint {
1206					remote-endpoint = <&funnel1_in3>;
1207				};
1208			};
1209		};
1210	};
1211
1212	smd {
1213		compatible = "qcom,smd";
1214
1215		rpm {
1216			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1217			qcom,ipc = <&apcs 8 0>;
1218			qcom,smd-edge = <15>;
1219
1220			rpm_requests {
1221				compatible = "qcom,rpm-msm8916";
1222				qcom,smd-channels = "rpm_requests";
1223
1224				rpmcc: qcom,rpmcc {
1225					compatible = "qcom,rpmcc-msm8916";
1226					#clock-cells = <1>;
1227				};
1228
1229				smd_rpm_regulators: pm8916-regulators {
1230					compatible = "qcom,rpm-pm8916-regulators";
1231
1232					pm8916_s1: s1 {};
1233					pm8916_s3: s3 {};
1234					pm8916_s4: s4 {};
1235
1236					pm8916_l1: l1 {};
1237					pm8916_l2: l2 {};
1238					pm8916_l3: l3 {};
1239					pm8916_l4: l4 {};
1240					pm8916_l5: l5 {};
1241					pm8916_l6: l6 {};
1242					pm8916_l7: l7 {};
1243					pm8916_l8: l8 {};
1244					pm8916_l9: l9 {};
1245					pm8916_l10: l10 {};
1246					pm8916_l11: l11 {};
1247					pm8916_l12: l12 {};
1248					pm8916_l13: l13 {};
1249					pm8916_l14: l14 {};
1250					pm8916_l15: l15 {};
1251					pm8916_l16: l16 {};
1252					pm8916_l17: l17 {};
1253					pm8916_l18: l18 {};
1254				};
1255			};
1256		};
1257	};
1258
1259	hexagon-smp2p {
1260		compatible = "qcom,smp2p";
1261		qcom,smem = <435>, <428>;
1262
1263		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1264
1265		qcom,ipc = <&apcs 8 14>;
1266
1267		qcom,local-pid = <0>;
1268		qcom,remote-pid = <1>;
1269
1270		hexagon_smp2p_out: master-kernel {
1271			qcom,entry-name = "master-kernel";
1272
1273			#qcom,smem-state-cells = <1>;
1274		};
1275
1276		hexagon_smp2p_in: slave-kernel {
1277			qcom,entry-name = "slave-kernel";
1278
1279			interrupt-controller;
1280			#interrupt-cells = <2>;
1281		};
1282	};
1283
1284	wcnss-smp2p {
1285		compatible = "qcom,smp2p";
1286		qcom,smem = <451>, <431>;
1287
1288		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1289
1290		qcom,ipc = <&apcs 8 18>;
1291
1292		qcom,local-pid = <0>;
1293		qcom,remote-pid = <4>;
1294
1295		wcnss_smp2p_out: master-kernel {
1296			qcom,entry-name = "master-kernel";
1297
1298			#qcom,smem-state-cells = <1>;
1299		};
1300
1301		wcnss_smp2p_in: slave-kernel {
1302			qcom,entry-name = "slave-kernel";
1303
1304			interrupt-controller;
1305			#interrupt-cells = <2>;
1306		};
1307	};
1308
1309	smsm {
1310		compatible = "qcom,smsm";
1311
1312		#address-cells = <1>;
1313		#size-cells = <0>;
1314
1315		qcom,ipc-1 = <&apcs 0 13>;
1316		qcom,ipc-6 = <&apcs 0 19>;
1317
1318		apps_smsm: apps@0 {
1319			reg = <0>;
1320
1321			#qcom,smem-state-cells = <1>;
1322		};
1323
1324		hexagon_smsm: hexagon@1 {
1325			reg = <1>;
1326			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1327
1328			interrupt-controller;
1329			#interrupt-cells = <2>;
1330		};
1331
1332		wcnss_smsm: wcnss@6 {
1333			reg = <6>;
1334			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1335
1336			interrupt-controller;
1337			#interrupt-cells = <2>;
1338		};
1339	};
1340};
1341
1342#include "msm8916-pins.dtsi"
1343