1/* 2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-msm8916.h> 16#include <dt-bindings/reset/qcom,gcc-msm8916.h> 17#include <dt-bindings/clock/qcom,rpmcc.h> 18 19/ { 20 model = "Qualcomm Technologies, Inc. MSM8916"; 21 compatible = "qcom,msm8916"; 22 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 aliases { 29 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 30 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 31 }; 32 33 chosen { }; 34 35 memory { 36 device_type = "memory"; 37 /* We expect the bootloader to fill in the reg */ 38 reg = <0 0 0 0>; 39 }; 40 41 reserved-memory { 42 #address-cells = <2>; 43 #size-cells = <2>; 44 ranges; 45 46 tz-apps@86000000 { 47 reg = <0x0 0x86000000 0x0 0x300000>; 48 no-map; 49 }; 50 51 smem_mem: smem_region@86300000 { 52 reg = <0x0 0x86300000 0x0 0x100000>; 53 no-map; 54 }; 55 56 hypervisor@86400000 { 57 reg = <0x0 0x86400000 0x0 0x100000>; 58 no-map; 59 }; 60 61 tz@86500000 { 62 reg = <0x0 0x86500000 0x0 0x180000>; 63 no-map; 64 }; 65 66 reserved@8668000 { 67 reg = <0x0 0x86680000 0x0 0x80000>; 68 no-map; 69 }; 70 71 rmtfs@86700000 { 72 reg = <0x0 0x86700000 0x0 0xe0000>; 73 no-map; 74 }; 75 76 rfsa@867e00000 { 77 reg = <0x0 0x867e0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 mpss_mem: mpss@86800000 { 82 reg = <0x0 0x86800000 0x0 0x2b00000>; 83 no-map; 84 }; 85 86 wcnss_mem: wcnss@89300000 { 87 reg = <0x0 0x89300000 0x0 0x600000>; 88 no-map; 89 }; 90 91 mba_mem: mba@8ea00000 { 92 no-map; 93 reg = <0 0x8ea00000 0 0x100000>; 94 }; 95 }; 96 97 cpus { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 CPU0: cpu@0 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 reg = <0x0>; 105 next-level-cache = <&L2_0>; 106 enable-method = "psci"; 107 cpu-idle-states = <&CPU_SPC>; 108 }; 109 110 CPU1: cpu@1 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a53", "arm,armv8"; 113 reg = <0x1>; 114 next-level-cache = <&L2_0>; 115 enable-method = "psci"; 116 cpu-idle-states = <&CPU_SPC>; 117 }; 118 119 CPU2: cpu@2 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 reg = <0x2>; 123 next-level-cache = <&L2_0>; 124 enable-method = "psci"; 125 cpu-idle-states = <&CPU_SPC>; 126 }; 127 128 CPU3: cpu@3 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53", "arm,armv8"; 131 reg = <0x3>; 132 next-level-cache = <&L2_0>; 133 enable-method = "psci"; 134 cpu-idle-states = <&CPU_SPC>; 135 }; 136 137 L2_0: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 }; 141 142 idle-states { 143 CPU_SPC: spc { 144 compatible = "arm,idle-state"; 145 arm,psci-suspend-param = <0x40000002>; 146 entry-latency-us = <130>; 147 exit-latency-us = <150>; 148 min-residency-us = <2000>; 149 local-timer-stop; 150 }; 151 }; 152 }; 153 154 psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 pmu { 160 compatible = "arm,armv8-pmuv3"; 161 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; 162 }; 163 164 thermal-zones { 165 cpu-thermal0 { 166 polling-delay-passive = <250>; 167 polling-delay = <1000>; 168 169 thermal-sensors = <&tsens 4>; 170 171 trips { 172 cpu_alert0: trip0 { 173 temperature = <75000>; 174 hysteresis = <2000>; 175 type = "passive"; 176 }; 177 cpu_crit0: trip1 { 178 temperature = <110000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 cpu-thermal1 { 186 polling-delay-passive = <250>; 187 polling-delay = <1000>; 188 189 thermal-sensors = <&tsens 3>; 190 191 trips { 192 cpu_alert1: trip0 { 193 temperature = <75000>; 194 hysteresis = <2000>; 195 type = "passive"; 196 }; 197 cpu_crit1: trip1 { 198 temperature = <110000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 }; 204 205 }; 206 207 timer { 208 compatible = "arm,armv8-timer"; 209 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 210 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 211 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 212 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 213 }; 214 215 clocks { 216 xo_board: xo_board { 217 compatible = "fixed-clock"; 218 #clock-cells = <0>; 219 clock-frequency = <19200000>; 220 }; 221 222 sleep_clk: sleep_clk { 223 compatible = "fixed-clock"; 224 #clock-cells = <0>; 225 clock-frequency = <32768>; 226 }; 227 }; 228 229 smem { 230 compatible = "qcom,smem"; 231 232 memory-region = <&smem_mem>; 233 qcom,rpm-msg-ram = <&rpm_msg_ram>; 234 235 hwlocks = <&tcsr_mutex 3>; 236 }; 237 238 firmware { 239 scm: scm { 240 compatible = "qcom,scm"; 241 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 242 clock-names = "core", "bus", "iface"; 243 #reset-cells = <1>; 244 }; 245 }; 246 247 soc: soc { 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0 0 0 0xffffffff>; 251 compatible = "simple-bus"; 252 253 restart@4ab000 { 254 compatible = "qcom,pshold"; 255 reg = <0x4ab000 0x4>; 256 }; 257 258 msmgpio: pinctrl@1000000 { 259 compatible = "qcom,msm8916-pinctrl"; 260 reg = <0x1000000 0x300000>; 261 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 }; 267 268 gcc: clock-controller@1800000 { 269 compatible = "qcom,gcc-msm8916"; 270 #clock-cells = <1>; 271 #reset-cells = <1>; 272 #power-domain-cells = <1>; 273 reg = <0x1800000 0x80000>; 274 }; 275 276 tcsr_mutex_regs: syscon@1905000 { 277 compatible = "syscon"; 278 reg = <0x1905000 0x20000>; 279 }; 280 281 tcsr: syscon@1937000 { 282 compatible = "qcom,tcsr-msm8916", "syscon"; 283 reg = <0x1937000 0x30000>; 284 }; 285 286 tcsr_mutex: hwlock { 287 compatible = "qcom,tcsr-mutex"; 288 syscon = <&tcsr_mutex_regs 0 0x1000>; 289 #hwlock-cells = <1>; 290 }; 291 292 rpm_msg_ram: memory@60000 { 293 compatible = "qcom,rpm-msg-ram"; 294 reg = <0x60000 0x8000>; 295 }; 296 297 blsp1_uart1: serial@78af000 { 298 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 299 reg = <0x78af000 0x200>; 300 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 302 clock-names = "core", "iface"; 303 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 304 dma-names = "rx", "tx"; 305 status = "disabled"; 306 }; 307 308 apcs: syscon@b011000 { 309 compatible = "syscon"; 310 reg = <0x0b011000 0x1000>; 311 }; 312 313 blsp1_uart2: serial@78b0000 { 314 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 315 reg = <0x78b0000 0x200>; 316 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 318 clock-names = "core", "iface"; 319 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 324 blsp_dma: dma@7884000 { 325 compatible = "qcom,bam-v1.7.0"; 326 reg = <0x07884000 0x23000>; 327 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 329 clock-names = "bam_clk"; 330 #dma-cells = <1>; 331 qcom,ee = <0>; 332 status = "disabled"; 333 }; 334 335 blsp_spi1: spi@78b5000 { 336 compatible = "qcom,spi-qup-v2.2.1"; 337 reg = <0x078b5000 0x600>; 338 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 340 <&gcc GCC_BLSP1_AHB_CLK>; 341 clock-names = "core", "iface"; 342 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 343 dma-names = "rx", "tx"; 344 pinctrl-names = "default", "sleep"; 345 pinctrl-0 = <&spi1_default>; 346 pinctrl-1 = <&spi1_sleep>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 status = "disabled"; 350 }; 351 352 blsp_spi2: spi@78b6000 { 353 compatible = "qcom,spi-qup-v2.2.1"; 354 reg = <0x078b6000 0x600>; 355 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 357 <&gcc GCC_BLSP1_AHB_CLK>; 358 clock-names = "core", "iface"; 359 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 360 dma-names = "rx", "tx"; 361 pinctrl-names = "default", "sleep"; 362 pinctrl-0 = <&spi2_default>; 363 pinctrl-1 = <&spi2_sleep>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 status = "disabled"; 367 }; 368 369 blsp_spi3: spi@78b7000 { 370 compatible = "qcom,spi-qup-v2.2.1"; 371 reg = <0x078b7000 0x600>; 372 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 374 <&gcc GCC_BLSP1_AHB_CLK>; 375 clock-names = "core", "iface"; 376 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 377 dma-names = "rx", "tx"; 378 pinctrl-names = "default", "sleep"; 379 pinctrl-0 = <&spi3_default>; 380 pinctrl-1 = <&spi3_sleep>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 status = "disabled"; 384 }; 385 386 blsp_spi4: spi@78b8000 { 387 compatible = "qcom,spi-qup-v2.2.1"; 388 reg = <0x078b8000 0x600>; 389 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 391 <&gcc GCC_BLSP1_AHB_CLK>; 392 clock-names = "core", "iface"; 393 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 394 dma-names = "rx", "tx"; 395 pinctrl-names = "default", "sleep"; 396 pinctrl-0 = <&spi4_default>; 397 pinctrl-1 = <&spi4_sleep>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 status = "disabled"; 401 }; 402 403 blsp_spi5: spi@78b9000 { 404 compatible = "qcom,spi-qup-v2.2.1"; 405 reg = <0x078b9000 0x600>; 406 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 408 <&gcc GCC_BLSP1_AHB_CLK>; 409 clock-names = "core", "iface"; 410 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 411 dma-names = "rx", "tx"; 412 pinctrl-names = "default", "sleep"; 413 pinctrl-0 = <&spi5_default>; 414 pinctrl-1 = <&spi5_sleep>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 blsp_spi6: spi@78ba000 { 421 compatible = "qcom,spi-qup-v2.2.1"; 422 reg = <0x078ba000 0x600>; 423 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 425 <&gcc GCC_BLSP1_AHB_CLK>; 426 clock-names = "core", "iface"; 427 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 428 dma-names = "rx", "tx"; 429 pinctrl-names = "default", "sleep"; 430 pinctrl-0 = <&spi6_default>; 431 pinctrl-1 = <&spi6_sleep>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 }; 436 437 blsp_i2c2: i2c@78b6000 { 438 compatible = "qcom,i2c-qup-v2.2.1"; 439 reg = <0x78b6000 0x1000>; 440 interrupts = <GIC_SPI 96 0>; 441 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 442 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 443 clock-names = "iface", "core"; 444 pinctrl-names = "default", "sleep"; 445 pinctrl-0 = <&i2c2_default>; 446 pinctrl-1 = <&i2c2_sleep>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 blsp_i2c4: i2c@78b8000 { 453 compatible = "qcom,i2c-qup-v2.2.1"; 454 reg = <0x78b8000 0x1000>; 455 interrupts = <GIC_SPI 98 0>; 456 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 457 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 458 clock-names = "iface", "core"; 459 pinctrl-names = "default", "sleep"; 460 pinctrl-0 = <&i2c4_default>; 461 pinctrl-1 = <&i2c4_sleep>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 blsp_i2c6: i2c@78ba000 { 468 compatible = "qcom,i2c-qup-v2.2.1"; 469 reg = <0x78ba000 0x1000>; 470 interrupts = <GIC_SPI 100 0>; 471 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 472 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 473 clock-names = "iface", "core"; 474 pinctrl-names = "default", "sleep"; 475 pinctrl-0 = <&i2c6_default>; 476 pinctrl-1 = <&i2c6_sleep>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 lpass: lpass@07708000 { 483 status = "disabled"; 484 compatible = "qcom,lpass-cpu-apq8016"; 485 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 486 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 487 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 488 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 489 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 490 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 491 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 492 493 clock-names = "ahbix-clk", 494 "pcnoc-mport-clk", 495 "pcnoc-sway-clk", 496 "mi2s-bit-clk0", 497 "mi2s-bit-clk1", 498 "mi2s-bit-clk2", 499 "mi2s-bit-clk3"; 500 #sound-dai-cells = <1>; 501 502 interrupts = <0 160 0>; 503 interrupt-names = "lpass-irq-lpaif"; 504 reg = <0x07708000 0x10000>; 505 reg-names = "lpass-lpaif"; 506 }; 507 508 lpass_codec: codec{ 509 compatible = "qcom,msm8916-wcd-digital-codec"; 510 reg = <0x0771c000 0x400>; 511 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 512 <&gcc GCC_CODEC_DIGCODEC_CLK>; 513 clock-names = "ahbix-clk", "mclk"; 514 #sound-dai-cells = <1>; 515 }; 516 517 sdhc_1: sdhci@07824000 { 518 compatible = "qcom,sdhci-msm-v4"; 519 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 520 reg-names = "hc_mem", "core_mem"; 521 522 interrupts = <0 123 0>, <0 138 0>; 523 interrupt-names = "hc_irq", "pwr_irq"; 524 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 525 <&gcc GCC_SDCC1_AHB_CLK>, 526 <&xo_board>; 527 clock-names = "core", "iface", "xo"; 528 mmc-ddr-1_8v; 529 bus-width = <8>; 530 non-removable; 531 status = "disabled"; 532 }; 533 534 sdhc_2: sdhci@07864000 { 535 compatible = "qcom,sdhci-msm-v4"; 536 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 537 reg-names = "hc_mem", "core_mem"; 538 539 interrupts = <0 125 0>, <0 221 0>; 540 interrupt-names = "hc_irq", "pwr_irq"; 541 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 542 <&gcc GCC_SDCC2_AHB_CLK>, 543 <&xo_board>; 544 clock-names = "core", "iface", "xo"; 545 bus-width = <4>; 546 status = "disabled"; 547 }; 548 549 usb_dev: usb@78d9000 { 550 compatible = "qcom,ci-hdrc"; 551 reg = <0x78d9000 0x400>; 552 dr_mode = "peripheral"; 553 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 554 usb-phy = <&usb_otg>; 555 status = "disabled"; 556 }; 557 558 usb_host: ehci@78d9000 { 559 compatible = "qcom,ehci-host"; 560 reg = <0x78d9000 0x400>; 561 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 562 usb-phy = <&usb_otg>; 563 status = "disabled"; 564 }; 565 566 usb_otg: phy@78d9000 { 567 compatible = "qcom,usb-otg-snps"; 568 reg = <0x78d9000 0x400>; 569 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 571 572 qcom,vdd-levels = <500000 1000000 1320000>; 573 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>; 574 dr_mode = "peripheral"; 575 qcom,otg-control = <2>; // PMIC 576 qcom,manual-pullup; 577 578 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 579 <&gcc GCC_USB_HS_SYSTEM_CLK>, 580 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 581 clock-names = "iface", "core", "sleep"; 582 583 resets = <&gcc GCC_USB2A_PHY_BCR>, 584 <&gcc GCC_USB_HS_BCR>; 585 reset-names = "phy", "link"; 586 status = "disabled"; 587 }; 588 589 intc: interrupt-controller@b000000 { 590 compatible = "qcom,msm-qgic2"; 591 interrupt-controller; 592 #interrupt-cells = <3>; 593 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 594 }; 595 596 timer@b020000 { 597 #address-cells = <1>; 598 #size-cells = <1>; 599 ranges; 600 compatible = "arm,armv7-timer-mem"; 601 reg = <0xb020000 0x1000>; 602 clock-frequency = <19200000>; 603 604 frame@b021000 { 605 frame-number = <0>; 606 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 608 reg = <0xb021000 0x1000>, 609 <0xb022000 0x1000>; 610 }; 611 612 frame@b023000 { 613 frame-number = <1>; 614 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 615 reg = <0xb023000 0x1000>; 616 status = "disabled"; 617 }; 618 619 frame@b024000 { 620 frame-number = <2>; 621 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 622 reg = <0xb024000 0x1000>; 623 status = "disabled"; 624 }; 625 626 frame@b025000 { 627 frame-number = <3>; 628 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 629 reg = <0xb025000 0x1000>; 630 status = "disabled"; 631 }; 632 633 frame@b026000 { 634 frame-number = <4>; 635 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 636 reg = <0xb026000 0x1000>; 637 status = "disabled"; 638 }; 639 640 frame@b027000 { 641 frame-number = <5>; 642 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 643 reg = <0xb027000 0x1000>; 644 status = "disabled"; 645 }; 646 647 frame@b028000 { 648 frame-number = <6>; 649 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 650 reg = <0xb028000 0x1000>; 651 status = "disabled"; 652 }; 653 }; 654 655 spmi_bus: spmi@200f000 { 656 compatible = "qcom,spmi-pmic-arb"; 657 reg = <0x200f000 0x001000>, 658 <0x2400000 0x400000>, 659 <0x2c00000 0x400000>, 660 <0x3800000 0x200000>, 661 <0x200a000 0x002100>; 662 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 663 interrupt-names = "periph_irq"; 664 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 665 qcom,ee = <0>; 666 qcom,channel = <0>; 667 #address-cells = <2>; 668 #size-cells = <0>; 669 interrupt-controller; 670 #interrupt-cells = <4>; 671 }; 672 673 rng@22000 { 674 compatible = "qcom,prng"; 675 reg = <0x00022000 0x200>; 676 clocks = <&gcc GCC_PRNG_AHB_CLK>; 677 clock-names = "core"; 678 }; 679 680 qfprom: qfprom@5c000 { 681 compatible = "qcom,qfprom"; 682 reg = <0x5c000 0x1000>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 tsens_caldata: caldata@d0 { 686 reg = <0xd0 0x8>; 687 }; 688 tsens_calsel: calsel@ec { 689 reg = <0xec 0x4>; 690 }; 691 }; 692 693 tsens: thermal-sensor@4a8000 { 694 compatible = "qcom,msm8916-tsens"; 695 reg = <0x4a8000 0x2000>; 696 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 697 nvmem-cell-names = "calib", "calib_sel"; 698 #thermal-sensor-cells = <1>; 699 }; 700 701 mdss: mdss@1a00000 { 702 compatible = "qcom,mdss"; 703 reg = <0x1a00000 0x1000>, 704 <0x1ac8000 0x3000>; 705 reg-names = "mdss_phys", "vbif_phys"; 706 707 power-domains = <&gcc MDSS_GDSC>; 708 709 clocks = <&gcc GCC_MDSS_AHB_CLK>, 710 <&gcc GCC_MDSS_AXI_CLK>, 711 <&gcc GCC_MDSS_VSYNC_CLK>; 712 clock-names = "iface_clk", 713 "bus_clk", 714 "vsync_clk"; 715 716 interrupts = <0 72 0>; 717 718 interrupt-controller; 719 #interrupt-cells = <1>; 720 721 #address-cells = <1>; 722 #size-cells = <1>; 723 ranges; 724 725 mdp: mdp@1a01000 { 726 compatible = "qcom,mdp5"; 727 reg = <0x1a01000 0x90000>; 728 reg-names = "mdp_phys"; 729 730 interrupt-parent = <&mdss>; 731 interrupts = <0 0>; 732 733 clocks = <&gcc GCC_MDSS_AHB_CLK>, 734 <&gcc GCC_MDSS_AXI_CLK>, 735 <&gcc GCC_MDSS_MDP_CLK>, 736 <&gcc GCC_MDSS_VSYNC_CLK>; 737 clock-names = "iface_clk", 738 "bus_clk", 739 "core_clk", 740 "vsync_clk"; 741 742 ports { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 746 port@0 { 747 reg = <0>; 748 mdp5_intf1_out: endpoint { 749 remote-endpoint = <&dsi0_in>; 750 }; 751 }; 752 }; 753 }; 754 755 dsi0: dsi@1a98000 { 756 compatible = "qcom,mdss-dsi-ctrl"; 757 reg = <0x1a98000 0x25c>; 758 reg-names = "dsi_ctrl"; 759 760 interrupt-parent = <&mdss>; 761 interrupts = <4 0>; 762 763 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 764 <&gcc PCLK0_CLK_SRC>; 765 assigned-clock-parents = <&dsi_phy0 0>, 766 <&dsi_phy0 1>; 767 768 clocks = <&gcc GCC_MDSS_MDP_CLK>, 769 <&gcc GCC_MDSS_AHB_CLK>, 770 <&gcc GCC_MDSS_AXI_CLK>, 771 <&gcc GCC_MDSS_BYTE0_CLK>, 772 <&gcc GCC_MDSS_PCLK0_CLK>, 773 <&gcc GCC_MDSS_ESC0_CLK>; 774 clock-names = "mdp_core_clk", 775 "iface_clk", 776 "bus_clk", 777 "byte_clk", 778 "pixel_clk", 779 "core_clk"; 780 phys = <&dsi_phy0>; 781 phy-names = "dsi-phy"; 782 783 ports { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 port@0 { 788 reg = <0>; 789 dsi0_in: endpoint { 790 remote-endpoint = <&mdp5_intf1_out>; 791 }; 792 }; 793 794 port@1 { 795 reg = <1>; 796 dsi0_out: endpoint { 797 }; 798 }; 799 }; 800 }; 801 802 dsi_phy0: dsi-phy@1a98300 { 803 compatible = "qcom,dsi-phy-28nm-lp"; 804 reg = <0x1a98300 0xd4>, 805 <0x1a98500 0x280>, 806 <0x1a98780 0x30>; 807 reg-names = "dsi_pll", 808 "dsi_phy", 809 "dsi_phy_regulator"; 810 811 #clock-cells = <1>; 812 813 clocks = <&gcc GCC_MDSS_AHB_CLK>; 814 clock-names = "iface_clk"; 815 }; 816 }; 817 818 819 hexagon@4080000 { 820 compatible = "qcom,q6v5-pil"; 821 reg = <0x04080000 0x100>, 822 <0x04020000 0x040>; 823 824 reg-names = "qdsp6", "rmb"; 825 826 interrupts-extended = <&intc 0 24 1>, 827 <&hexagon_smp2p_in 0 0>, 828 <&hexagon_smp2p_in 1 0>, 829 <&hexagon_smp2p_in 2 0>, 830 <&hexagon_smp2p_in 3 0>; 831 interrupt-names = "wdog", "fatal", "ready", 832 "handover", "stop-ack"; 833 834 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 835 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 836 <&gcc GCC_BOOT_ROM_AHB_CLK>; 837 clock-names = "iface", "bus", "mem"; 838 839 qcom,smem-states = <&hexagon_smp2p_out 0>; 840 qcom,smem-state-names = "stop"; 841 842 resets = <&scm 0>; 843 reset-names = "mss_restart"; 844 845 mx-supply = <&pm8916_l3>; 846 pll-supply = <&pm8916_l7>; 847 848 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 849 850 status = "disabled"; 851 852 mba { 853 memory-region = <&mba_mem>; 854 }; 855 856 mpss { 857 memory-region = <&mpss_mem>; 858 }; 859 }; 860 861 pronto: wcnss@a21b000 { 862 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 863 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 864 reg-names = "ccu", "dxe", "pmu"; 865 866 memory-region = <&wcnss_mem>; 867 868 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, 869 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 870 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 871 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 872 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 873 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 874 875 vddmx-supply = <&pm8916_l3>; 876 vddpx-supply = <&pm8916_l7>; 877 878 qcom,state = <&wcnss_smp2p_out 0>; 879 qcom,state-names = "stop"; 880 881 pinctrl-names = "default"; 882 pinctrl-0 = <&wcnss_pin_a>; 883 884 status = "disabled"; 885 886 iris { 887 compatible = "qcom,wcn3620"; 888 889 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 890 clock-names = "xo"; 891 892 vddxo-supply = <&pm8916_l7>; 893 vddrfa-supply = <&pm8916_s3>; 894 vddpa-supply = <&pm8916_l9>; 895 vdddig-supply = <&pm8916_l5>; 896 }; 897 898 smd-edge { 899 interrupts = <0 142 1>; 900 901 qcom,ipc = <&apcs 8 17>; 902 qcom,smd-edge = <6>; 903 qcom,remote-pid = <4>; 904 905 label = "pronto"; 906 907 wcnss { 908 compatible = "qcom,wcnss"; 909 qcom,smd-channels = "WCNSS_CTRL"; 910 911 qcom,mmio = <&pronto>; 912 913 bt { 914 compatible = "qcom,wcnss-bt"; 915 }; 916 917 wifi { 918 compatible = "qcom,wcnss-wlan"; 919 920 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, 921 <0 146 IRQ_TYPE_LEVEL_HIGH>; 922 interrupt-names = "tx", "rx"; 923 924 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 925 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 926 }; 927 }; 928 }; 929 }; 930 931 tpiu@820000 { 932 compatible = "arm,coresight-tpiu", "arm,primecell"; 933 reg = <0x820000 0x1000>; 934 935 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 936 clock-names = "apb_pclk", "atclk"; 937 938 port { 939 tpiu_in: endpoint { 940 slave-mode; 941 remote-endpoint = <&replicator_out1>; 942 }; 943 }; 944 }; 945 946 funnel@821000 { 947 compatible = "arm,coresight-funnel", "arm,primecell"; 948 reg = <0x821000 0x1000>; 949 950 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 951 clock-names = "apb_pclk", "atclk"; 952 953 ports { 954 #address-cells = <1>; 955 #size-cells = <0>; 956 957 /* 958 * Not described input ports: 959 * 0 - connected to Resource and Power Manger CPU ETM 960 * 1 - not-connected 961 * 2 - connected to Modem CPU ETM 962 * 3 - not-connected 963 * 5 - not-connected 964 * 6 - connected trought funnel to Wireless CPU ETM 965 * 7 - connected to STM component 966 */ 967 968 port@4 { 969 reg = <4>; 970 funnel0_in4: endpoint { 971 slave-mode; 972 remote-endpoint = <&funnel1_out>; 973 }; 974 }; 975 port@8 { 976 reg = <0>; 977 funnel0_out: endpoint { 978 remote-endpoint = <&etf_in>; 979 }; 980 }; 981 }; 982 }; 983 984 replicator@824000 { 985 compatible = "qcom,coresight-replicator1x", "arm,primecell"; 986 reg = <0x824000 0x1000>; 987 988 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 989 clock-names = "apb_pclk", "atclk"; 990 991 ports { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 port@0 { 996 reg = <0>; 997 replicator_out0: endpoint { 998 remote-endpoint = <&etr_in>; 999 }; 1000 }; 1001 port@1 { 1002 reg = <1>; 1003 replicator_out1: endpoint { 1004 remote-endpoint = <&tpiu_in>; 1005 }; 1006 }; 1007 port@2 { 1008 reg = <0>; 1009 replicator_in: endpoint { 1010 slave-mode; 1011 remote-endpoint = <&etf_out>; 1012 }; 1013 }; 1014 }; 1015 }; 1016 1017 etf@825000 { 1018 compatible = "arm,coresight-tmc", "arm,primecell"; 1019 reg = <0x825000 0x1000>; 1020 1021 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1022 clock-names = "apb_pclk", "atclk"; 1023 1024 ports { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 1028 port@0 { 1029 reg = <0>; 1030 etf_out: endpoint { 1031 slave-mode; 1032 remote-endpoint = <&funnel0_out>; 1033 }; 1034 }; 1035 port@1 { 1036 reg = <0>; 1037 etf_in: endpoint { 1038 remote-endpoint = <&replicator_in>; 1039 }; 1040 }; 1041 }; 1042 }; 1043 1044 etr@826000 { 1045 compatible = "arm,coresight-tmc", "arm,primecell"; 1046 reg = <0x826000 0x1000>; 1047 1048 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1049 clock-names = "apb_pclk", "atclk"; 1050 1051 port { 1052 etr_in: endpoint { 1053 slave-mode; 1054 remote-endpoint = <&replicator_out0>; 1055 }; 1056 }; 1057 }; 1058 1059 funnel@841000 { /* APSS funnel only 4 inputs are used */ 1060 compatible = "arm,coresight-funnel", "arm,primecell"; 1061 reg = <0x841000 0x1000>; 1062 1063 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1064 clock-names = "apb_pclk", "atclk"; 1065 1066 ports { 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 1070 port@0 { 1071 reg = <0>; 1072 funnel1_in0: endpoint { 1073 slave-mode; 1074 remote-endpoint = <&etm0_out>; 1075 }; 1076 }; 1077 port@1 { 1078 reg = <1>; 1079 funnel1_in1: endpoint { 1080 slave-mode; 1081 remote-endpoint = <&etm1_out>; 1082 }; 1083 }; 1084 port@2 { 1085 reg = <2>; 1086 funnel1_in2: endpoint { 1087 slave-mode; 1088 remote-endpoint = <&etm2_out>; 1089 }; 1090 }; 1091 port@3 { 1092 reg = <3>; 1093 funnel1_in3: endpoint { 1094 slave-mode; 1095 remote-endpoint = <&etm3_out>; 1096 }; 1097 }; 1098 port@4 { 1099 reg = <0>; 1100 funnel1_out: endpoint { 1101 remote-endpoint = <&funnel0_in4>; 1102 }; 1103 }; 1104 }; 1105 }; 1106 1107 etm@85c000 { 1108 compatible = "arm,coresight-etm4x", "arm,primecell"; 1109 reg = <0x85c000 0x1000>; 1110 1111 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1112 clock-names = "apb_pclk", "atclk"; 1113 1114 cpu = <&CPU0>; 1115 1116 port { 1117 etm0_out: endpoint { 1118 remote-endpoint = <&funnel1_in0>; 1119 }; 1120 }; 1121 }; 1122 1123 etm@85d000 { 1124 compatible = "arm,coresight-etm4x", "arm,primecell"; 1125 reg = <0x85d000 0x1000>; 1126 1127 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1128 clock-names = "apb_pclk", "atclk"; 1129 1130 cpu = <&CPU1>; 1131 1132 port { 1133 etm1_out: endpoint { 1134 remote-endpoint = <&funnel1_in1>; 1135 }; 1136 }; 1137 }; 1138 1139 etm@85e000 { 1140 compatible = "arm,coresight-etm4x", "arm,primecell"; 1141 reg = <0x85e000 0x1000>; 1142 1143 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1144 clock-names = "apb_pclk", "atclk"; 1145 1146 cpu = <&CPU2>; 1147 1148 port { 1149 etm2_out: endpoint { 1150 remote-endpoint = <&funnel1_in2>; 1151 }; 1152 }; 1153 }; 1154 1155 etm@85f000 { 1156 compatible = "arm,coresight-etm4x", "arm,primecell"; 1157 reg = <0x85f000 0x1000>; 1158 1159 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1160 clock-names = "apb_pclk", "atclk"; 1161 1162 cpu = <&CPU3>; 1163 1164 port { 1165 etm3_out: endpoint { 1166 remote-endpoint = <&funnel1_in3>; 1167 }; 1168 }; 1169 }; 1170 }; 1171 1172 smd { 1173 compatible = "qcom,smd"; 1174 1175 rpm { 1176 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1177 qcom,ipc = <&apcs 8 0>; 1178 qcom,smd-edge = <15>; 1179 1180 rpm_requests { 1181 compatible = "qcom,rpm-msm8916"; 1182 qcom,smd-channels = "rpm_requests"; 1183 1184 rpmcc: qcom,rpmcc { 1185 compatible = "qcom,rpmcc-msm8916"; 1186 #clock-cells = <1>; 1187 }; 1188 1189 smd_rpm_regulators: pm8916-regulators { 1190 compatible = "qcom,rpm-pm8916-regulators"; 1191 1192 pm8916_s1: s1 {}; 1193 pm8916_s3: s3 {}; 1194 pm8916_s4: s4 {}; 1195 1196 pm8916_l1: l1 {}; 1197 pm8916_l2: l2 {}; 1198 pm8916_l3: l3 {}; 1199 pm8916_l4: l4 {}; 1200 pm8916_l5: l5 {}; 1201 pm8916_l6: l6 {}; 1202 pm8916_l7: l7 {}; 1203 pm8916_l8: l8 {}; 1204 pm8916_l9: l9 {}; 1205 pm8916_l10: l10 {}; 1206 pm8916_l11: l11 {}; 1207 pm8916_l12: l12 {}; 1208 pm8916_l13: l13 {}; 1209 pm8916_l14: l14 {}; 1210 pm8916_l15: l15 {}; 1211 pm8916_l16: l16 {}; 1212 pm8916_l17: l17 {}; 1213 pm8916_l18: l18 {}; 1214 }; 1215 }; 1216 }; 1217 1218 hexagon { 1219 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1220 1221 qcom,smd-edge = <0>; 1222 qcom,ipc = <&apcs 8 12>; 1223 qcom,remote-pid = <1>; 1224 }; 1225 }; 1226 1227 hexagon-smp2p { 1228 compatible = "qcom,smp2p"; 1229 qcom,smem = <435>, <428>; 1230 1231 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 1232 1233 qcom,ipc = <&apcs 8 14>; 1234 1235 qcom,local-pid = <0>; 1236 qcom,remote-pid = <1>; 1237 1238 hexagon_smp2p_out: master-kernel { 1239 qcom,entry-name = "master-kernel"; 1240 1241 #qcom,smem-state-cells = <1>; 1242 }; 1243 1244 hexagon_smp2p_in: slave-kernel { 1245 qcom,entry-name = "slave-kernel"; 1246 1247 interrupt-controller; 1248 #interrupt-cells = <2>; 1249 }; 1250 }; 1251 1252 wcnss-smp2p { 1253 compatible = "qcom,smp2p"; 1254 qcom,smem = <451>, <431>; 1255 1256 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 1257 1258 qcom,ipc = <&apcs 8 18>; 1259 1260 qcom,local-pid = <0>; 1261 qcom,remote-pid = <4>; 1262 1263 wcnss_smp2p_out: master-kernel { 1264 qcom,entry-name = "master-kernel"; 1265 1266 #qcom,smem-state-cells = <1>; 1267 }; 1268 1269 wcnss_smp2p_in: slave-kernel { 1270 qcom,entry-name = "slave-kernel"; 1271 1272 interrupt-controller; 1273 #interrupt-cells = <2>; 1274 }; 1275 }; 1276 1277 smsm { 1278 compatible = "qcom,smsm"; 1279 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 1283 qcom,ipc-1 = <&apcs 0 13>; 1284 qcom,ipc-6 = <&apcs 0 19>; 1285 1286 apps_smsm: apps@0 { 1287 reg = <0>; 1288 1289 #qcom,smem-state-cells = <1>; 1290 }; 1291 1292 hexagon_smsm: hexagon@1 { 1293 reg = <1>; 1294 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 1295 1296 interrupt-controller; 1297 #interrupt-cells = <2>; 1298 }; 1299 1300 wcnss_smsm: wcnss@6 { 1301 reg = <6>; 1302 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 1303 1304 interrupt-controller; 1305 #interrupt-cells = <2>; 1306 }; 1307 }; 1308}; 1309 1310#include "msm8916-pins.dtsi" 1311