1/* 2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-msm8916.h> 16#include <dt-bindings/reset/qcom,gcc-msm8916.h> 17 18/ { 19 model = "Qualcomm Technologies, Inc. MSM8916"; 20 compatible = "qcom,msm8916"; 21 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 aliases { }; 28 29 chosen { }; 30 31 memory { 32 device_type = "memory"; 33 /* We expect the bootloader to fill in the reg */ 34 reg = <0 0 0 0>; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 reg = <0x0>; 45 }; 46 47 CPU1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53", "arm,armv8"; 50 reg = <0x1>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53", "arm,armv8"; 56 reg = <0x2>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <0x3>; 63 }; 64 }; 65 66 timer { 67 compatible = "arm,armv8-timer"; 68 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 }; 73 74 soc: soc { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges = <0 0 0 0xffffffff>; 78 compatible = "simple-bus"; 79 80 pinctrl@1000000 { 81 compatible = "qcom,msm8916-pinctrl"; 82 reg = <0x1000000 0x300000>; 83 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 84 gpio-controller; 85 #gpio-cells = <2>; 86 interrupt-controller; 87 #interrupt-cells = <2>; 88 89 blsp1_uart2_default: blsp1_uart2_default { 90 pinmux { 91 function = "blsp_uart2"; 92 pins = "gpio4", "gpio5"; 93 }; 94 pinconf { 95 pins = "gpio4", "gpio5"; 96 drive-strength = <16>; 97 bias-disable; 98 }; 99 }; 100 101 blsp1_uart2_sleep: blsp1_uart2_sleep { 102 pinmux { 103 function = "blsp_uart2"; 104 pins = "gpio4", "gpio5"; 105 }; 106 pinconf { 107 pins = "gpio4", "gpio5"; 108 drive-strength = <2>; 109 bias-pull-down; 110 }; 111 }; 112 }; 113 114 gcc: qcom,gcc@1800000 { 115 compatible = "qcom,gcc-msm8916"; 116 #clock-cells = <1>; 117 #reset-cells = <1>; 118 reg = <0x1800000 0x80000>; 119 }; 120 121 blsp1_uart2: serial@78b0000 { 122 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 123 reg = <0x78b0000 0x200>; 124 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 126 clock-names = "core", "iface"; 127 status = "disabled"; 128 }; 129 130 intc: interrupt-controller@b000000 { 131 compatible = "qcom,msm-qgic2"; 132 interrupt-controller; 133 #interrupt-cells = <3>; 134 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 135 }; 136 137 timer@b020000 { 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges; 141 compatible = "arm,armv7-timer-mem"; 142 reg = <0xb020000 0x1000>; 143 clock-frequency = <19200000>; 144 145 frame@b021000 { 146 frame-number = <0>; 147 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 149 reg = <0xb021000 0x1000>, 150 <0xb022000 0x1000>; 151 }; 152 153 frame@b023000 { 154 frame-number = <1>; 155 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 156 reg = <0xb023000 0x1000>; 157 status = "disabled"; 158 }; 159 160 frame@b024000 { 161 frame-number = <2>; 162 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 163 reg = <0xb024000 0x1000>; 164 status = "disabled"; 165 }; 166 167 frame@b025000 { 168 frame-number = <3>; 169 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 170 reg = <0xb025000 0x1000>; 171 status = "disabled"; 172 }; 173 174 frame@b026000 { 175 frame-number = <4>; 176 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 177 reg = <0xb026000 0x1000>; 178 status = "disabled"; 179 }; 180 181 frame@b027000 { 182 frame-number = <5>; 183 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 184 reg = <0xb027000 0x1000>; 185 status = "disabled"; 186 }; 187 188 frame@b028000 { 189 frame-number = <6>; 190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 191 reg = <0xb028000 0x1000>; 192 status = "disabled"; 193 }; 194 }; 195 }; 196}; 197