1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 23 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 24 }; 25 26 chosen { }; 27 28 memory@80000000 { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0x80000000 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 tz-apps@86000000 { 40 reg = <0x0 0x86000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 smem@86300000 { 45 compatible = "qcom,smem"; 46 reg = <0x0 0x86300000 0x0 0x100000>; 47 no-map; 48 49 hwlocks = <&tcsr_mutex 3>; 50 qcom,rpm-msg-ram = <&rpm_msg_ram>; 51 }; 52 53 hypervisor@86400000 { 54 reg = <0x0 0x86400000 0x0 0x100000>; 55 no-map; 56 }; 57 58 tz@86500000 { 59 reg = <0x0 0x86500000 0x0 0x180000>; 60 no-map; 61 }; 62 63 reserved@86680000 { 64 reg = <0x0 0x86680000 0x0 0x80000>; 65 no-map; 66 }; 67 68 rmtfs@86700000 { 69 compatible = "qcom,rmtfs-mem"; 70 reg = <0x0 0x86700000 0x0 0xe0000>; 71 no-map; 72 73 qcom,client-id = <1>; 74 }; 75 76 rfsa@867e0000 { 77 reg = <0x0 0x867e0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 mpss_mem: mpss@86800000 { 82 reg = <0x0 0x86800000 0x0 0x2b00000>; 83 no-map; 84 }; 85 86 wcnss_mem: wcnss@89300000 { 87 reg = <0x0 0x89300000 0x0 0x600000>; 88 no-map; 89 }; 90 91 venus_mem: venus@89900000 { 92 reg = <0x0 0x89900000 0x0 0x600000>; 93 no-map; 94 }; 95 96 mba_mem: mba@8ea00000 { 97 no-map; 98 reg = <0 0x8ea00000 0 0x100000>; 99 }; 100 }; 101 102 clocks { 103 xo_board: xo-board { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <19200000>; 107 }; 108 109 sleep_clk: sleep-clk { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <32768>; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 CPU0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x0>; 124 next-level-cache = <&L2_0>; 125 enable-method = "psci"; 126 clocks = <&apcs>; 127 operating-points-v2 = <&cpu_opp_table>; 128 #cooling-cells = <2>; 129 power-domains = <&CPU_PD0>; 130 power-domain-names = "psci"; 131 qcom,acc = <&cpu0_acc>; 132 qcom,saw = <&cpu0_saw>; 133 }; 134 135 CPU1: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x1>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 clocks = <&apcs>; 142 operating-points-v2 = <&cpu_opp_table>; 143 #cooling-cells = <2>; 144 power-domains = <&CPU_PD1>; 145 power-domain-names = "psci"; 146 qcom,acc = <&cpu1_acc>; 147 qcom,saw = <&cpu1_saw>; 148 }; 149 150 CPU2: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x2>; 154 next-level-cache = <&L2_0>; 155 enable-method = "psci"; 156 clocks = <&apcs>; 157 operating-points-v2 = <&cpu_opp_table>; 158 #cooling-cells = <2>; 159 power-domains = <&CPU_PD2>; 160 power-domain-names = "psci"; 161 qcom,acc = <&cpu2_acc>; 162 qcom,saw = <&cpu2_saw>; 163 }; 164 165 CPU3: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x3>; 169 next-level-cache = <&L2_0>; 170 enable-method = "psci"; 171 clocks = <&apcs>; 172 operating-points-v2 = <&cpu_opp_table>; 173 #cooling-cells = <2>; 174 power-domains = <&CPU_PD3>; 175 power-domain-names = "psci"; 176 qcom,acc = <&cpu3_acc>; 177 qcom,saw = <&cpu3_saw>; 178 }; 179 180 L2_0: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 }; 184 185 idle-states { 186 entry-method = "psci"; 187 188 CPU_SLEEP_0: cpu-sleep-0 { 189 compatible = "arm,idle-state"; 190 idle-state-name = "standalone-power-collapse"; 191 arm,psci-suspend-param = <0x40000002>; 192 entry-latency-us = <130>; 193 exit-latency-us = <150>; 194 min-residency-us = <2000>; 195 local-timer-stop; 196 }; 197 }; 198 199 domain-idle-states { 200 201 CLUSTER_RET: cluster-retention { 202 compatible = "domain-idle-state"; 203 arm,psci-suspend-param = <0x41000012>; 204 entry-latency-us = <500>; 205 exit-latency-us = <500>; 206 min-residency-us = <2000>; 207 }; 208 209 CLUSTER_PWRDN: cluster-gdhs { 210 compatible = "domain-idle-state"; 211 arm,psci-suspend-param = <0x41000032>; 212 entry-latency-us = <2000>; 213 exit-latency-us = <2000>; 214 min-residency-us = <6000>; 215 }; 216 }; 217 }; 218 219 cpu_opp_table: cpu-opp-table { 220 compatible = "operating-points-v2"; 221 opp-shared; 222 223 opp-200000000 { 224 opp-hz = /bits/ 64 <200000000>; 225 }; 226 opp-400000000 { 227 opp-hz = /bits/ 64 <400000000>; 228 }; 229 opp-800000000 { 230 opp-hz = /bits/ 64 <800000000>; 231 }; 232 opp-998400000 { 233 opp-hz = /bits/ 64 <998400000>; 234 }; 235 }; 236 237 firmware { 238 scm: scm { 239 compatible = "qcom,scm-msm8916", "qcom,scm"; 240 clocks = <&gcc GCC_CRYPTO_CLK>, 241 <&gcc GCC_CRYPTO_AXI_CLK>, 242 <&gcc GCC_CRYPTO_AHB_CLK>; 243 clock-names = "core", "bus", "iface"; 244 #reset-cells = <1>; 245 246 qcom,dload-mode = <&tcsr 0x6100>; 247 }; 248 }; 249 250 pmu { 251 compatible = "arm,cortex-a53-pmu"; 252 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 253 }; 254 255 psci { 256 compatible = "arm,psci-1.0"; 257 method = "smc"; 258 259 CPU_PD0: power-domain-cpu0 { 260 #power-domain-cells = <0>; 261 power-domains = <&CLUSTER_PD>; 262 domain-idle-states = <&CPU_SLEEP_0>; 263 }; 264 265 CPU_PD1: power-domain-cpu1 { 266 #power-domain-cells = <0>; 267 power-domains = <&CLUSTER_PD>; 268 domain-idle-states = <&CPU_SLEEP_0>; 269 }; 270 271 CPU_PD2: power-domain-cpu2 { 272 #power-domain-cells = <0>; 273 power-domains = <&CLUSTER_PD>; 274 domain-idle-states = <&CPU_SLEEP_0>; 275 }; 276 277 CPU_PD3: power-domain-cpu3 { 278 #power-domain-cells = <0>; 279 power-domains = <&CLUSTER_PD>; 280 domain-idle-states = <&CPU_SLEEP_0>; 281 }; 282 283 CLUSTER_PD: power-domain-cluster { 284 #power-domain-cells = <0>; 285 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 286 }; 287 }; 288 289 smd { 290 compatible = "qcom,smd"; 291 292 rpm { 293 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 294 qcom,ipc = <&apcs 8 0>; 295 qcom,smd-edge = <15>; 296 297 rpm_requests: rpm-requests { 298 compatible = "qcom,rpm-msm8916"; 299 qcom,smd-channels = "rpm_requests"; 300 301 rpmcc: clock-controller { 302 compatible = "qcom,rpmcc-msm8916"; 303 #clock-cells = <1>; 304 }; 305 306 rpmpd: power-controller { 307 compatible = "qcom,msm8916-rpmpd"; 308 #power-domain-cells = <1>; 309 operating-points-v2 = <&rpmpd_opp_table>; 310 311 rpmpd_opp_table: opp-table { 312 compatible = "operating-points-v2"; 313 314 rpmpd_opp_ret: opp1 { 315 opp-level = <1>; 316 }; 317 rpmpd_opp_svs_krait: opp2 { 318 opp-level = <2>; 319 }; 320 rpmpd_opp_svs_soc: opp3 { 321 opp-level = <3>; 322 }; 323 rpmpd_opp_nom: opp4 { 324 opp-level = <4>; 325 }; 326 rpmpd_opp_turbo: opp5 { 327 opp-level = <5>; 328 }; 329 rpmpd_opp_super_turbo: opp6 { 330 opp-level = <6>; 331 }; 332 }; 333 }; 334 }; 335 }; 336 }; 337 338 smp2p-hexagon { 339 compatible = "qcom,smp2p"; 340 qcom,smem = <435>, <428>; 341 342 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 343 344 qcom,ipc = <&apcs 8 14>; 345 346 qcom,local-pid = <0>; 347 qcom,remote-pid = <1>; 348 349 hexagon_smp2p_out: master-kernel { 350 qcom,entry-name = "master-kernel"; 351 352 #qcom,smem-state-cells = <1>; 353 }; 354 355 hexagon_smp2p_in: slave-kernel { 356 qcom,entry-name = "slave-kernel"; 357 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 }; 361 }; 362 363 smp2p-wcnss { 364 compatible = "qcom,smp2p"; 365 qcom,smem = <451>, <431>; 366 367 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 368 369 qcom,ipc = <&apcs 8 18>; 370 371 qcom,local-pid = <0>; 372 qcom,remote-pid = <4>; 373 374 wcnss_smp2p_out: master-kernel { 375 qcom,entry-name = "master-kernel"; 376 377 #qcom,smem-state-cells = <1>; 378 }; 379 380 wcnss_smp2p_in: slave-kernel { 381 qcom,entry-name = "slave-kernel"; 382 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smsm { 389 compatible = "qcom,smsm"; 390 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 qcom,ipc-1 = <&apcs 8 13>; 395 qcom,ipc-3 = <&apcs 8 19>; 396 397 apps_smsm: apps@0 { 398 reg = <0>; 399 400 #qcom,smem-state-cells = <1>; 401 }; 402 403 hexagon_smsm: hexagon@1 { 404 reg = <1>; 405 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 406 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 wcnss_smsm: wcnss@6 { 412 reg = <6>; 413 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 soc: soc@0 { 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges = <0 0 0 0xffffffff>; 424 compatible = "simple-bus"; 425 426 rng@22000 { 427 compatible = "qcom,prng"; 428 reg = <0x00022000 0x200>; 429 clocks = <&gcc GCC_PRNG_AHB_CLK>; 430 clock-names = "core"; 431 }; 432 433 restart@4ab000 { 434 compatible = "qcom,pshold"; 435 reg = <0x004ab000 0x4>; 436 }; 437 438 qfprom: qfprom@5c000 { 439 compatible = "qcom,qfprom"; 440 reg = <0x0005c000 0x1000>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 tsens_caldata: caldata@d0 { 444 reg = <0xd0 0x8>; 445 }; 446 tsens_calsel: calsel@ec { 447 reg = <0xec 0x4>; 448 }; 449 }; 450 451 rpm_msg_ram: sram@60000 { 452 compatible = "qcom,rpm-msg-ram"; 453 reg = <0x00060000 0x8000>; 454 }; 455 456 bimc: interconnect@400000 { 457 compatible = "qcom,msm8916-bimc"; 458 reg = <0x00400000 0x62000>; 459 #interconnect-cells = <1>; 460 clock-names = "bus", "bus_a"; 461 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 462 <&rpmcc RPM_SMD_BIMC_A_CLK>; 463 }; 464 465 tsens: thermal-sensor@4a9000 { 466 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 467 reg = <0x004a9000 0x1000>, /* TM */ 468 <0x004a8000 0x1000>; /* SROT */ 469 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 470 nvmem-cell-names = "calib", "calib_sel"; 471 #qcom,sensors = <5>; 472 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 473 interrupt-names = "uplow"; 474 #thermal-sensor-cells = <1>; 475 }; 476 477 pcnoc: interconnect@500000 { 478 compatible = "qcom,msm8916-pcnoc"; 479 reg = <0x00500000 0x11000>; 480 #interconnect-cells = <1>; 481 clock-names = "bus", "bus_a"; 482 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 483 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 484 }; 485 486 snoc: interconnect@580000 { 487 compatible = "qcom,msm8916-snoc"; 488 reg = <0x00580000 0x14000>; 489 #interconnect-cells = <1>; 490 clock-names = "bus", "bus_a"; 491 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 492 <&rpmcc RPM_SMD_SNOC_A_CLK>; 493 }; 494 495 stm: stm@802000 { 496 compatible = "arm,coresight-stm", "arm,primecell"; 497 reg = <0x00802000 0x1000>, 498 <0x09280000 0x180000>; 499 reg-names = "stm-base", "stm-stimulus-base"; 500 501 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 502 clock-names = "apb_pclk", "atclk"; 503 504 status = "disabled"; 505 506 out-ports { 507 port { 508 stm_out: endpoint { 509 remote-endpoint = <&funnel0_in7>; 510 }; 511 }; 512 }; 513 }; 514 515 /* System CTIs */ 516 /* CTI 0 - TMC connections */ 517 cti0: cti@810000 { 518 compatible = "arm,coresight-cti", "arm,primecell"; 519 reg = <0x00810000 0x1000>; 520 521 clocks = <&rpmcc RPM_QDSS_CLK>; 522 clock-names = "apb_pclk"; 523 524 status = "disabled"; 525 }; 526 527 /* CTI 1 - TPIU connections */ 528 cti1: cti@811000 { 529 compatible = "arm,coresight-cti", "arm,primecell"; 530 reg = <0x00811000 0x1000>; 531 532 clocks = <&rpmcc RPM_QDSS_CLK>; 533 clock-names = "apb_pclk"; 534 535 status = "disabled"; 536 }; 537 538 /* CTIs 2-11 - no information - not instantiated */ 539 540 tpiu: tpiu@820000 { 541 compatible = "arm,coresight-tpiu", "arm,primecell"; 542 reg = <0x00820000 0x1000>; 543 544 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 545 clock-names = "apb_pclk", "atclk"; 546 547 status = "disabled"; 548 549 in-ports { 550 port { 551 tpiu_in: endpoint { 552 remote-endpoint = <&replicator_out1>; 553 }; 554 }; 555 }; 556 }; 557 558 funnel0: funnel@821000 { 559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 560 reg = <0x00821000 0x1000>; 561 562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 563 clock-names = "apb_pclk", "atclk"; 564 565 status = "disabled"; 566 567 in-ports { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 /* 572 * Not described input ports: 573 * 0 - connected to Resource and Power Manger CPU ETM 574 * 1 - not-connected 575 * 2 - connected to Modem CPU ETM 576 * 3 - not-connected 577 * 5 - not-connected 578 * 6 - connected trought funnel to Wireless CPU ETM 579 * 7 - connected to STM component 580 */ 581 582 port@4 { 583 reg = <4>; 584 funnel0_in4: endpoint { 585 remote-endpoint = <&funnel1_out>; 586 }; 587 }; 588 589 port@7 { 590 reg = <7>; 591 funnel0_in7: endpoint { 592 remote-endpoint = <&stm_out>; 593 }; 594 }; 595 }; 596 597 out-ports { 598 port { 599 funnel0_out: endpoint { 600 remote-endpoint = <&etf_in>; 601 }; 602 }; 603 }; 604 }; 605 606 replicator: replicator@824000 { 607 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 608 reg = <0x00824000 0x1000>; 609 610 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 611 clock-names = "apb_pclk", "atclk"; 612 613 status = "disabled"; 614 615 out-ports { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 619 port@0 { 620 reg = <0>; 621 replicator_out0: endpoint { 622 remote-endpoint = <&etr_in>; 623 }; 624 }; 625 port@1 { 626 reg = <1>; 627 replicator_out1: endpoint { 628 remote-endpoint = <&tpiu_in>; 629 }; 630 }; 631 }; 632 633 in-ports { 634 port { 635 replicator_in: endpoint { 636 remote-endpoint = <&etf_out>; 637 }; 638 }; 639 }; 640 }; 641 642 etf: etf@825000 { 643 compatible = "arm,coresight-tmc", "arm,primecell"; 644 reg = <0x00825000 0x1000>; 645 646 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 647 clock-names = "apb_pclk", "atclk"; 648 649 status = "disabled"; 650 651 in-ports { 652 port { 653 etf_in: endpoint { 654 remote-endpoint = <&funnel0_out>; 655 }; 656 }; 657 }; 658 659 out-ports { 660 port { 661 etf_out: endpoint { 662 remote-endpoint = <&replicator_in>; 663 }; 664 }; 665 }; 666 }; 667 668 etr: etr@826000 { 669 compatible = "arm,coresight-tmc", "arm,primecell"; 670 reg = <0x00826000 0x1000>; 671 672 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 673 clock-names = "apb_pclk", "atclk"; 674 675 status = "disabled"; 676 677 in-ports { 678 port { 679 etr_in: endpoint { 680 remote-endpoint = <&replicator_out0>; 681 }; 682 }; 683 }; 684 }; 685 686 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 687 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 688 reg = <0x00841000 0x1000>; 689 690 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 691 clock-names = "apb_pclk", "atclk"; 692 693 status = "disabled"; 694 695 in-ports { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 port@0 { 700 reg = <0>; 701 funnel1_in0: endpoint { 702 remote-endpoint = <&etm0_out>; 703 }; 704 }; 705 port@1 { 706 reg = <1>; 707 funnel1_in1: endpoint { 708 remote-endpoint = <&etm1_out>; 709 }; 710 }; 711 port@2 { 712 reg = <2>; 713 funnel1_in2: endpoint { 714 remote-endpoint = <&etm2_out>; 715 }; 716 }; 717 port@3 { 718 reg = <3>; 719 funnel1_in3: endpoint { 720 remote-endpoint = <&etm3_out>; 721 }; 722 }; 723 }; 724 725 out-ports { 726 port { 727 funnel1_out: endpoint { 728 remote-endpoint = <&funnel0_in4>; 729 }; 730 }; 731 }; 732 }; 733 734 debug0: debug@850000 { 735 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 736 reg = <0x00850000 0x1000>; 737 clocks = <&rpmcc RPM_QDSS_CLK>; 738 clock-names = "apb_pclk"; 739 cpu = <&CPU0>; 740 status = "disabled"; 741 }; 742 743 debug1: debug@852000 { 744 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 745 reg = <0x00852000 0x1000>; 746 clocks = <&rpmcc RPM_QDSS_CLK>; 747 clock-names = "apb_pclk"; 748 cpu = <&CPU1>; 749 status = "disabled"; 750 }; 751 752 debug2: debug@854000 { 753 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 754 reg = <0x00854000 0x1000>; 755 clocks = <&rpmcc RPM_QDSS_CLK>; 756 clock-names = "apb_pclk"; 757 cpu = <&CPU2>; 758 status = "disabled"; 759 }; 760 761 debug3: debug@856000 { 762 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 763 reg = <0x00856000 0x1000>; 764 clocks = <&rpmcc RPM_QDSS_CLK>; 765 clock-names = "apb_pclk"; 766 cpu = <&CPU3>; 767 status = "disabled"; 768 }; 769 770 /* Core CTIs; CTIs 12-15 */ 771 /* CTI - CPU-0 */ 772 cti12: cti@858000 { 773 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 774 "arm,primecell"; 775 reg = <0x00858000 0x1000>; 776 777 clocks = <&rpmcc RPM_QDSS_CLK>; 778 clock-names = "apb_pclk"; 779 780 cpu = <&CPU0>; 781 arm,cs-dev-assoc = <&etm0>; 782 783 status = "disabled"; 784 }; 785 786 /* CTI - CPU-1 */ 787 cti13: cti@859000 { 788 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 789 "arm,primecell"; 790 reg = <0x00859000 0x1000>; 791 792 clocks = <&rpmcc RPM_QDSS_CLK>; 793 clock-names = "apb_pclk"; 794 795 cpu = <&CPU1>; 796 arm,cs-dev-assoc = <&etm1>; 797 798 status = "disabled"; 799 }; 800 801 /* CTI - CPU-2 */ 802 cti14: cti@85a000 { 803 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 804 "arm,primecell"; 805 reg = <0x0085a000 0x1000>; 806 807 clocks = <&rpmcc RPM_QDSS_CLK>; 808 clock-names = "apb_pclk"; 809 810 cpu = <&CPU2>; 811 arm,cs-dev-assoc = <&etm2>; 812 813 status = "disabled"; 814 }; 815 816 /* CTI - CPU-3 */ 817 cti15: cti@85b000 { 818 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 819 "arm,primecell"; 820 reg = <0x0085b000 0x1000>; 821 822 clocks = <&rpmcc RPM_QDSS_CLK>; 823 clock-names = "apb_pclk"; 824 825 cpu = <&CPU3>; 826 arm,cs-dev-assoc = <&etm3>; 827 828 status = "disabled"; 829 }; 830 831 etm0: etm@85c000 { 832 compatible = "arm,coresight-etm4x", "arm,primecell"; 833 reg = <0x0085c000 0x1000>; 834 835 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 836 clock-names = "apb_pclk", "atclk"; 837 arm,coresight-loses-context-with-cpu; 838 839 cpu = <&CPU0>; 840 841 status = "disabled"; 842 843 out-ports { 844 port { 845 etm0_out: endpoint { 846 remote-endpoint = <&funnel1_in0>; 847 }; 848 }; 849 }; 850 }; 851 852 etm1: etm@85d000 { 853 compatible = "arm,coresight-etm4x", "arm,primecell"; 854 reg = <0x0085d000 0x1000>; 855 856 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 857 clock-names = "apb_pclk", "atclk"; 858 arm,coresight-loses-context-with-cpu; 859 860 cpu = <&CPU1>; 861 862 status = "disabled"; 863 864 out-ports { 865 port { 866 etm1_out: endpoint { 867 remote-endpoint = <&funnel1_in1>; 868 }; 869 }; 870 }; 871 }; 872 873 etm2: etm@85e000 { 874 compatible = "arm,coresight-etm4x", "arm,primecell"; 875 reg = <0x0085e000 0x1000>; 876 877 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 878 clock-names = "apb_pclk", "atclk"; 879 arm,coresight-loses-context-with-cpu; 880 881 cpu = <&CPU2>; 882 883 status = "disabled"; 884 885 out-ports { 886 port { 887 etm2_out: endpoint { 888 remote-endpoint = <&funnel1_in2>; 889 }; 890 }; 891 }; 892 }; 893 894 etm3: etm@85f000 { 895 compatible = "arm,coresight-etm4x", "arm,primecell"; 896 reg = <0x0085f000 0x1000>; 897 898 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 899 clock-names = "apb_pclk", "atclk"; 900 arm,coresight-loses-context-with-cpu; 901 902 cpu = <&CPU3>; 903 904 status = "disabled"; 905 906 out-ports { 907 port { 908 etm3_out: endpoint { 909 remote-endpoint = <&funnel1_in3>; 910 }; 911 }; 912 }; 913 }; 914 915 msmgpio: pinctrl@1000000 { 916 compatible = "qcom,msm8916-pinctrl"; 917 reg = <0x01000000 0x300000>; 918 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 919 gpio-controller; 920 gpio-ranges = <&msmgpio 0 0 122>; 921 #gpio-cells = <2>; 922 interrupt-controller; 923 #interrupt-cells = <2>; 924 }; 925 926 gcc: clock-controller@1800000 { 927 compatible = "qcom,gcc-msm8916"; 928 #clock-cells = <1>; 929 #reset-cells = <1>; 930 #power-domain-cells = <1>; 931 reg = <0x01800000 0x80000>; 932 }; 933 934 tcsr_mutex: hwlock@1905000 { 935 compatible = "qcom,tcsr-mutex"; 936 reg = <0x01905000 0x20000>; 937 #hwlock-cells = <1>; 938 }; 939 940 tcsr: syscon@1937000 { 941 compatible = "qcom,tcsr-msm8916", "syscon"; 942 reg = <0x01937000 0x30000>; 943 }; 944 945 mdss: mdss@1a00000 { 946 status = "disabled"; 947 compatible = "qcom,mdss"; 948 reg = <0x01a00000 0x1000>, 949 <0x01ac8000 0x3000>; 950 reg-names = "mdss_phys", "vbif_phys"; 951 952 power-domains = <&gcc MDSS_GDSC>; 953 954 clocks = <&gcc GCC_MDSS_AHB_CLK>, 955 <&gcc GCC_MDSS_AXI_CLK>, 956 <&gcc GCC_MDSS_VSYNC_CLK>; 957 clock-names = "iface", 958 "bus", 959 "vsync"; 960 961 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 962 963 interrupt-controller; 964 #interrupt-cells = <1>; 965 966 #address-cells = <1>; 967 #size-cells = <1>; 968 ranges; 969 970 mdp: mdp@1a01000 { 971 compatible = "qcom,mdp5"; 972 reg = <0x01a01000 0x89000>; 973 reg-names = "mdp_phys"; 974 975 interrupt-parent = <&mdss>; 976 interrupts = <0>; 977 978 clocks = <&gcc GCC_MDSS_AHB_CLK>, 979 <&gcc GCC_MDSS_AXI_CLK>, 980 <&gcc GCC_MDSS_MDP_CLK>, 981 <&gcc GCC_MDSS_VSYNC_CLK>; 982 clock-names = "iface", 983 "bus", 984 "core", 985 "vsync"; 986 987 iommus = <&apps_iommu 4>; 988 989 ports { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 port@0 { 994 reg = <0>; 995 mdp5_intf1_out: endpoint { 996 remote-endpoint = <&dsi0_in>; 997 }; 998 }; 999 }; 1000 }; 1001 1002 dsi0: dsi@1a98000 { 1003 compatible = "qcom,mdss-dsi-ctrl"; 1004 reg = <0x01a98000 0x25c>; 1005 reg-names = "dsi_ctrl"; 1006 1007 interrupt-parent = <&mdss>; 1008 interrupts = <4>; 1009 1010 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1011 <&gcc PCLK0_CLK_SRC>; 1012 assigned-clock-parents = <&dsi_phy0 0>, 1013 <&dsi_phy0 1>; 1014 1015 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1016 <&gcc GCC_MDSS_AHB_CLK>, 1017 <&gcc GCC_MDSS_AXI_CLK>, 1018 <&gcc GCC_MDSS_BYTE0_CLK>, 1019 <&gcc GCC_MDSS_PCLK0_CLK>, 1020 <&gcc GCC_MDSS_ESC0_CLK>; 1021 clock-names = "mdp_core", 1022 "iface", 1023 "bus", 1024 "byte", 1025 "pixel", 1026 "core"; 1027 phys = <&dsi_phy0>; 1028 phy-names = "dsi-phy"; 1029 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 port@0 { 1038 reg = <0>; 1039 dsi0_in: endpoint { 1040 remote-endpoint = <&mdp5_intf1_out>; 1041 }; 1042 }; 1043 1044 port@1 { 1045 reg = <1>; 1046 dsi0_out: endpoint { 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 dsi_phy0: dsi-phy@1a98300 { 1053 compatible = "qcom,dsi-phy-28nm-lp"; 1054 reg = <0x01a98300 0xd4>, 1055 <0x01a98500 0x280>, 1056 <0x01a98780 0x30>; 1057 reg-names = "dsi_pll", 1058 "dsi_phy", 1059 "dsi_phy_regulator"; 1060 1061 #clock-cells = <1>; 1062 #phy-cells = <0>; 1063 1064 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1065 <&xo_board>; 1066 clock-names = "iface", "ref"; 1067 }; 1068 }; 1069 1070 camss: camss@1b00000 { 1071 compatible = "qcom,msm8916-camss"; 1072 reg = <0x01b0ac00 0x200>, 1073 <0x01b00030 0x4>, 1074 <0x01b0b000 0x200>, 1075 <0x01b00038 0x4>, 1076 <0x01b08000 0x100>, 1077 <0x01b08400 0x100>, 1078 <0x01b0a000 0x500>, 1079 <0x01b00020 0x10>, 1080 <0x01b10000 0x1000>; 1081 reg-names = "csiphy0", 1082 "csiphy0_clk_mux", 1083 "csiphy1", 1084 "csiphy1_clk_mux", 1085 "csid0", 1086 "csid1", 1087 "ispif", 1088 "csi_clk_mux", 1089 "vfe0"; 1090 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1091 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1092 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1093 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1094 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1095 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1096 interrupt-names = "csiphy0", 1097 "csiphy1", 1098 "csid0", 1099 "csid1", 1100 "ispif", 1101 "vfe0"; 1102 power-domains = <&gcc VFE_GDSC>; 1103 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1104 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1105 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1106 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1107 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1108 <&gcc GCC_CAMSS_CSI0_CLK>, 1109 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1110 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1111 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1112 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1113 <&gcc GCC_CAMSS_CSI1_CLK>, 1114 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1115 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1116 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1117 <&gcc GCC_CAMSS_AHB_CLK>, 1118 <&gcc GCC_CAMSS_VFE0_CLK>, 1119 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1120 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1121 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1122 clock-names = "top_ahb", 1123 "ispif_ahb", 1124 "csiphy0_timer", 1125 "csiphy1_timer", 1126 "csi0_ahb", 1127 "csi0", 1128 "csi0_phy", 1129 "csi0_pix", 1130 "csi0_rdi", 1131 "csi1_ahb", 1132 "csi1", 1133 "csi1_phy", 1134 "csi1_pix", 1135 "csi1_rdi", 1136 "ahb", 1137 "vfe0", 1138 "csi_vfe0", 1139 "vfe_ahb", 1140 "vfe_axi"; 1141 iommus = <&apps_iommu 3>; 1142 status = "disabled"; 1143 ports { 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 }; 1147 }; 1148 1149 cci: cci@1b0c000 { 1150 compatible = "qcom,msm8916-cci"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 reg = <0x01b0c000 0x1000>; 1154 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1155 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1156 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1157 <&gcc GCC_CAMSS_CCI_CLK>, 1158 <&gcc GCC_CAMSS_AHB_CLK>; 1159 clock-names = "camss_top_ahb", "cci_ahb", 1160 "cci", "camss_ahb"; 1161 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1162 <&gcc GCC_CAMSS_CCI_CLK>; 1163 assigned-clock-rates = <80000000>, <19200000>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&cci0_default>; 1166 status = "disabled"; 1167 1168 cci_i2c0: i2c-bus@0 { 1169 reg = <0>; 1170 clock-frequency = <400000>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 }; 1174 }; 1175 1176 gpu@1c00000 { 1177 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1178 reg = <0x01c00000 0x20000>; 1179 reg-names = "kgsl_3d0_reg_memory"; 1180 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1181 interrupt-names = "kgsl_3d0_irq"; 1182 clock-names = 1183 "core", 1184 "iface", 1185 "mem", 1186 "mem_iface", 1187 "alt_mem_iface", 1188 "gfx3d"; 1189 clocks = 1190 <&gcc GCC_OXILI_GFX3D_CLK>, 1191 <&gcc GCC_OXILI_AHB_CLK>, 1192 <&gcc GCC_OXILI_GMEM_CLK>, 1193 <&gcc GCC_BIMC_GFX_CLK>, 1194 <&gcc GCC_BIMC_GPU_CLK>, 1195 <&gcc GFX3D_CLK_SRC>; 1196 power-domains = <&gcc OXILI_GDSC>; 1197 operating-points-v2 = <&gpu_opp_table>; 1198 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1199 1200 gpu_opp_table: opp-table { 1201 compatible = "operating-points-v2"; 1202 1203 opp-400000000 { 1204 opp-hz = /bits/ 64 <400000000>; 1205 }; 1206 opp-19200000 { 1207 opp-hz = /bits/ 64 <19200000>; 1208 }; 1209 }; 1210 }; 1211 1212 venus: video-codec@1d00000 { 1213 compatible = "qcom,msm8916-venus"; 1214 reg = <0x01d00000 0xff000>; 1215 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1216 power-domains = <&gcc VENUS_GDSC>; 1217 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1218 <&gcc GCC_VENUS0_AHB_CLK>, 1219 <&gcc GCC_VENUS0_AXI_CLK>; 1220 clock-names = "core", "iface", "bus"; 1221 iommus = <&apps_iommu 5>; 1222 memory-region = <&venus_mem>; 1223 status = "okay"; 1224 1225 video-decoder { 1226 compatible = "venus-decoder"; 1227 }; 1228 1229 video-encoder { 1230 compatible = "venus-encoder"; 1231 }; 1232 }; 1233 1234 apps_iommu: iommu@1ef0000 { 1235 #address-cells = <1>; 1236 #size-cells = <1>; 1237 #iommu-cells = <1>; 1238 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1239 ranges = <0 0x01e20000 0x40000>; 1240 reg = <0x01ef0000 0x3000>; 1241 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1242 <&gcc GCC_APSS_TCU_CLK>; 1243 clock-names = "iface", "bus"; 1244 qcom,iommu-secure-id = <17>; 1245 1246 // vfe: 1247 iommu-ctx@3000 { 1248 compatible = "qcom,msm-iommu-v1-sec"; 1249 reg = <0x3000 0x1000>; 1250 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1251 }; 1252 1253 // mdp_0: 1254 iommu-ctx@4000 { 1255 compatible = "qcom,msm-iommu-v1-ns"; 1256 reg = <0x4000 0x1000>; 1257 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1258 }; 1259 1260 // venus_ns: 1261 iommu-ctx@5000 { 1262 compatible = "qcom,msm-iommu-v1-sec"; 1263 reg = <0x5000 0x1000>; 1264 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1265 }; 1266 }; 1267 1268 gpu_iommu: iommu@1f08000 { 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 #iommu-cells = <1>; 1272 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1273 ranges = <0 0x01f08000 0x10000>; 1274 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1275 <&gcc GCC_GFX_TCU_CLK>; 1276 clock-names = "iface", "bus"; 1277 qcom,iommu-secure-id = <18>; 1278 1279 // gfx3d_user: 1280 iommu-ctx@1000 { 1281 compatible = "qcom,msm-iommu-v1-ns"; 1282 reg = <0x1000 0x1000>; 1283 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1284 }; 1285 1286 // gfx3d_priv: 1287 iommu-ctx@2000 { 1288 compatible = "qcom,msm-iommu-v1-ns"; 1289 reg = <0x2000 0x1000>; 1290 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1291 }; 1292 }; 1293 1294 spmi_bus: spmi@200f000 { 1295 compatible = "qcom,spmi-pmic-arb"; 1296 reg = <0x0200f000 0x001000>, 1297 <0x02400000 0x400000>, 1298 <0x02c00000 0x400000>, 1299 <0x03800000 0x200000>, 1300 <0x0200a000 0x002100>; 1301 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1302 interrupt-names = "periph_irq"; 1303 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1304 qcom,ee = <0>; 1305 qcom,channel = <0>; 1306 #address-cells = <2>; 1307 #size-cells = <0>; 1308 interrupt-controller; 1309 #interrupt-cells = <4>; 1310 }; 1311 1312 mpss: remoteproc@4080000 { 1313 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; 1314 reg = <0x04080000 0x100>, 1315 <0x04020000 0x040>; 1316 1317 reg-names = "qdsp6", "rmb"; 1318 1319 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1320 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1321 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1322 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1323 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1324 interrupt-names = "wdog", "fatal", "ready", 1325 "handover", "stop-ack"; 1326 1327 power-domains = <&rpmpd MSM8916_VDDCX>, 1328 <&rpmpd MSM8916_VDDMX>; 1329 power-domain-names = "cx", "mx"; 1330 1331 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1332 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1333 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1334 <&xo_board>; 1335 clock-names = "iface", "bus", "mem", "xo"; 1336 1337 qcom,smem-states = <&hexagon_smp2p_out 0>; 1338 qcom,smem-state-names = "stop"; 1339 1340 resets = <&scm 0>; 1341 reset-names = "mss_restart"; 1342 1343 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1344 1345 status = "disabled"; 1346 1347 mba { 1348 memory-region = <&mba_mem>; 1349 }; 1350 1351 mpss { 1352 memory-region = <&mpss_mem>; 1353 }; 1354 1355 smd-edge { 1356 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1357 1358 qcom,smd-edge = <0>; 1359 qcom,ipc = <&apcs 8 12>; 1360 qcom,remote-pid = <1>; 1361 1362 label = "hexagon"; 1363 1364 fastrpc { 1365 compatible = "qcom,fastrpc"; 1366 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1367 label = "adsp"; 1368 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 1372 cb@1 { 1373 compatible = "qcom,fastrpc-compute-cb"; 1374 reg = <1>; 1375 }; 1376 }; 1377 }; 1378 }; 1379 1380 sound: sound@7702000 { 1381 status = "disabled"; 1382 compatible = "qcom,apq8016-sbc-sndcard"; 1383 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1384 reg-names = "mic-iomux", "spkr-iomux"; 1385 }; 1386 1387 lpass: audio-controller@7708000 { 1388 status = "disabled"; 1389 compatible = "qcom,lpass-cpu-apq8016"; 1390 1391 /* 1392 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1393 * is actually only used by Tertiary MI2S while 1394 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1395 */ 1396 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1397 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1398 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 1399 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1400 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1401 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1402 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 1403 1404 clock-names = "ahbix-clk", 1405 "pcnoc-mport-clk", 1406 "pcnoc-sway-clk", 1407 "mi2s-bit-clk0", 1408 "mi2s-bit-clk1", 1409 "mi2s-bit-clk2", 1410 "mi2s-bit-clk3"; 1411 #sound-dai-cells = <1>; 1412 1413 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1414 interrupt-names = "lpass-irq-lpaif"; 1415 reg = <0x07708000 0x10000>; 1416 reg-names = "lpass-lpaif"; 1417 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 }; 1421 1422 lpass_codec: audio-codec@771c000 { 1423 compatible = "qcom,msm8916-wcd-digital-codec"; 1424 reg = <0x0771c000 0x400>; 1425 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1426 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1427 clock-names = "ahbix-clk", "mclk"; 1428 #sound-dai-cells = <1>; 1429 }; 1430 1431 sdhc_1: sdhci@7824000 { 1432 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1433 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1434 reg-names = "hc_mem", "core_mem"; 1435 1436 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1438 interrupt-names = "hc_irq", "pwr_irq"; 1439 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1440 <&gcc GCC_SDCC1_AHB_CLK>, 1441 <&xo_board>; 1442 clock-names = "core", "iface", "xo"; 1443 mmc-ddr-1_8v; 1444 bus-width = <8>; 1445 non-removable; 1446 status = "disabled"; 1447 }; 1448 1449 sdhc_2: sdhci@7864000 { 1450 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1451 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1452 reg-names = "hc_mem", "core_mem"; 1453 1454 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1456 interrupt-names = "hc_irq", "pwr_irq"; 1457 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1458 <&gcc GCC_SDCC2_AHB_CLK>, 1459 <&xo_board>; 1460 clock-names = "core", "iface", "xo"; 1461 bus-width = <4>; 1462 status = "disabled"; 1463 }; 1464 1465 blsp_dma: dma-controller@7884000 { 1466 compatible = "qcom,bam-v1.7.0"; 1467 reg = <0x07884000 0x23000>; 1468 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1470 clock-names = "bam_clk"; 1471 #dma-cells = <1>; 1472 qcom,ee = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 blsp1_uart1: serial@78af000 { 1477 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1478 reg = <0x078af000 0x200>; 1479 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1481 clock-names = "core", "iface"; 1482 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 1483 dma-names = "rx", "tx"; 1484 pinctrl-names = "default", "sleep"; 1485 pinctrl-0 = <&blsp1_uart1_default>; 1486 pinctrl-1 = <&blsp1_uart1_sleep>; 1487 status = "disabled"; 1488 }; 1489 1490 blsp1_uart2: serial@78b0000 { 1491 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1492 reg = <0x078b0000 0x200>; 1493 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1495 clock-names = "core", "iface"; 1496 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 1497 dma-names = "rx", "tx"; 1498 pinctrl-names = "default", "sleep"; 1499 pinctrl-0 = <&blsp1_uart2_default>; 1500 pinctrl-1 = <&blsp1_uart2_sleep>; 1501 status = "disabled"; 1502 }; 1503 1504 blsp_i2c1: i2c@78b5000 { 1505 compatible = "qcom,i2c-qup-v2.2.1"; 1506 reg = <0x078b5000 0x500>; 1507 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1508 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1509 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 1510 clock-names = "iface", "core"; 1511 pinctrl-names = "default", "sleep"; 1512 pinctrl-0 = <&i2c1_default>; 1513 pinctrl-1 = <&i2c1_sleep>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 status = "disabled"; 1517 }; 1518 1519 blsp_spi1: spi@78b5000 { 1520 compatible = "qcom,spi-qup-v2.2.1"; 1521 reg = <0x078b5000 0x500>; 1522 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1523 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1524 <&gcc GCC_BLSP1_AHB_CLK>; 1525 clock-names = "core", "iface"; 1526 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 1527 dma-names = "rx", "tx"; 1528 pinctrl-names = "default", "sleep"; 1529 pinctrl-0 = <&spi1_default>; 1530 pinctrl-1 = <&spi1_sleep>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 blsp_i2c2: i2c@78b6000 { 1537 compatible = "qcom,i2c-qup-v2.2.1"; 1538 reg = <0x078b6000 0x500>; 1539 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1541 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 1542 clock-names = "iface", "core"; 1543 pinctrl-names = "default", "sleep"; 1544 pinctrl-0 = <&i2c2_default>; 1545 pinctrl-1 = <&i2c2_sleep>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 1551 blsp_spi2: spi@78b6000 { 1552 compatible = "qcom,spi-qup-v2.2.1"; 1553 reg = <0x078b6000 0x500>; 1554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1556 <&gcc GCC_BLSP1_AHB_CLK>; 1557 clock-names = "core", "iface"; 1558 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 1559 dma-names = "rx", "tx"; 1560 pinctrl-names = "default", "sleep"; 1561 pinctrl-0 = <&spi2_default>; 1562 pinctrl-1 = <&spi2_sleep>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 blsp_i2c3: i2c@78b7000 { 1569 compatible = "qcom,i2c-qup-v2.2.1"; 1570 reg = <0x078b7000 0x500>; 1571 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1572 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1573 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1574 clock-names = "iface", "core"; 1575 pinctrl-names = "default", "sleep"; 1576 pinctrl-0 = <&i2c3_default>; 1577 pinctrl-1 = <&i2c3_sleep>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 blsp_spi3: spi@78b7000 { 1584 compatible = "qcom,spi-qup-v2.2.1"; 1585 reg = <0x078b7000 0x500>; 1586 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1588 <&gcc GCC_BLSP1_AHB_CLK>; 1589 clock-names = "core", "iface"; 1590 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 1591 dma-names = "rx", "tx"; 1592 pinctrl-names = "default", "sleep"; 1593 pinctrl-0 = <&spi3_default>; 1594 pinctrl-1 = <&spi3_sleep>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 blsp_i2c4: i2c@78b8000 { 1601 compatible = "qcom,i2c-qup-v2.2.1"; 1602 reg = <0x078b8000 0x500>; 1603 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1604 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1605 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 1606 clock-names = "iface", "core"; 1607 pinctrl-names = "default", "sleep"; 1608 pinctrl-0 = <&i2c4_default>; 1609 pinctrl-1 = <&i2c4_sleep>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 1615 blsp_spi4: spi@78b8000 { 1616 compatible = "qcom,spi-qup-v2.2.1"; 1617 reg = <0x078b8000 0x500>; 1618 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1620 <&gcc GCC_BLSP1_AHB_CLK>; 1621 clock-names = "core", "iface"; 1622 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 1623 dma-names = "rx", "tx"; 1624 pinctrl-names = "default", "sleep"; 1625 pinctrl-0 = <&spi4_default>; 1626 pinctrl-1 = <&spi4_sleep>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 blsp_i2c5: i2c@78b9000 { 1633 compatible = "qcom,i2c-qup-v2.2.1"; 1634 reg = <0x078b9000 0x500>; 1635 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1637 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 1638 clock-names = "iface", "core"; 1639 pinctrl-names = "default", "sleep"; 1640 pinctrl-0 = <&i2c5_default>; 1641 pinctrl-1 = <&i2c5_sleep>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 blsp_spi5: spi@78b9000 { 1648 compatible = "qcom,spi-qup-v2.2.1"; 1649 reg = <0x078b9000 0x500>; 1650 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1651 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1652 <&gcc GCC_BLSP1_AHB_CLK>; 1653 clock-names = "core", "iface"; 1654 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 1655 dma-names = "rx", "tx"; 1656 pinctrl-names = "default", "sleep"; 1657 pinctrl-0 = <&spi5_default>; 1658 pinctrl-1 = <&spi5_sleep>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 blsp_i2c6: i2c@78ba000 { 1665 compatible = "qcom,i2c-qup-v2.2.1"; 1666 reg = <0x078ba000 0x500>; 1667 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1669 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 1670 clock-names = "iface", "core"; 1671 pinctrl-names = "default", "sleep"; 1672 pinctrl-0 = <&i2c6_default>; 1673 pinctrl-1 = <&i2c6_sleep>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 blsp_spi6: spi@78ba000 { 1680 compatible = "qcom,spi-qup-v2.2.1"; 1681 reg = <0x078ba000 0x500>; 1682 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1684 <&gcc GCC_BLSP1_AHB_CLK>; 1685 clock-names = "core", "iface"; 1686 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 1687 dma-names = "rx", "tx"; 1688 pinctrl-names = "default", "sleep"; 1689 pinctrl-0 = <&spi6_default>; 1690 pinctrl-1 = <&spi6_sleep>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 usb: usb@78d9000 { 1697 compatible = "qcom,ci-hdrc"; 1698 reg = <0x078d9000 0x200>, 1699 <0x078d9200 0x200>; 1700 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1703 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1704 clock-names = "iface", "core"; 1705 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1706 assigned-clock-rates = <80000000>; 1707 resets = <&gcc GCC_USB_HS_BCR>; 1708 reset-names = "core"; 1709 phy_type = "ulpi"; 1710 dr_mode = "otg"; 1711 hnp-disable; 1712 srp-disable; 1713 adp-disable; 1714 ahb-burst-config = <0>; 1715 phy-names = "usb-phy"; 1716 phys = <&usb_hs_phy>; 1717 status = "disabled"; 1718 #reset-cells = <1>; 1719 1720 ulpi { 1721 usb_hs_phy: phy { 1722 compatible = "qcom,usb-hs-phy-msm8916", 1723 "qcom,usb-hs-phy"; 1724 #phy-cells = <0>; 1725 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1726 clock-names = "ref", "sleep"; 1727 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1728 reset-names = "phy", "por"; 1729 qcom,init-seq = /bits/ 8 <0x0 0x44 1730 0x1 0x6b 0x2 0x24 0x3 0x13>; 1731 }; 1732 }; 1733 }; 1734 1735 pronto: remoteproc@a21b000 { 1736 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1737 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1738 reg-names = "ccu", "dxe", "pmu"; 1739 1740 memory-region = <&wcnss_mem>; 1741 1742 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1743 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1744 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1745 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1746 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1747 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1748 1749 power-domains = <&rpmpd MSM8916_VDDCX>, 1750 <&rpmpd MSM8916_VDDMX>; 1751 power-domain-names = "cx", "mx"; 1752 1753 qcom,state = <&wcnss_smp2p_out 0>; 1754 qcom,state-names = "stop"; 1755 1756 pinctrl-names = "default"; 1757 pinctrl-0 = <&wcnss_pin_a>; 1758 1759 status = "disabled"; 1760 1761 iris { 1762 compatible = "qcom,wcn3620"; 1763 1764 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1765 clock-names = "xo"; 1766 }; 1767 1768 smd-edge { 1769 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1770 1771 qcom,ipc = <&apcs 8 17>; 1772 qcom,smd-edge = <6>; 1773 qcom,remote-pid = <4>; 1774 1775 label = "pronto"; 1776 1777 wcnss_ctrl: wcnss { 1778 compatible = "qcom,wcnss"; 1779 qcom,smd-channels = "WCNSS_CTRL"; 1780 1781 qcom,mmio = <&pronto>; 1782 1783 bt { 1784 compatible = "qcom,wcnss-bt"; 1785 }; 1786 1787 wifi { 1788 compatible = "qcom,wcnss-wlan"; 1789 1790 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1792 interrupt-names = "tx", "rx"; 1793 1794 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1795 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1796 }; 1797 }; 1798 }; 1799 }; 1800 1801 intc: interrupt-controller@b000000 { 1802 compatible = "qcom,msm-qgic2"; 1803 interrupt-controller; 1804 #interrupt-cells = <3>; 1805 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 1806 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 1807 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1808 }; 1809 1810 apcs: mailbox@b011000 { 1811 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 1812 reg = <0x0b011000 0x1000>; 1813 #mbox-cells = <1>; 1814 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 1815 clock-names = "pll", "aux"; 1816 #clock-cells = <0>; 1817 }; 1818 1819 a53pll: clock@b016000 { 1820 compatible = "qcom,msm8916-a53pll"; 1821 reg = <0x0b016000 0x40>; 1822 #clock-cells = <0>; 1823 }; 1824 1825 timer@b020000 { 1826 #address-cells = <1>; 1827 #size-cells = <1>; 1828 ranges; 1829 compatible = "arm,armv7-timer-mem"; 1830 reg = <0x0b020000 0x1000>; 1831 clock-frequency = <19200000>; 1832 1833 frame@b021000 { 1834 frame-number = <0>; 1835 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1837 reg = <0x0b021000 0x1000>, 1838 <0x0b022000 0x1000>; 1839 }; 1840 1841 frame@b023000 { 1842 frame-number = <1>; 1843 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1844 reg = <0x0b023000 0x1000>; 1845 status = "disabled"; 1846 }; 1847 1848 frame@b024000 { 1849 frame-number = <2>; 1850 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1851 reg = <0x0b024000 0x1000>; 1852 status = "disabled"; 1853 }; 1854 1855 frame@b025000 { 1856 frame-number = <3>; 1857 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1858 reg = <0x0b025000 0x1000>; 1859 status = "disabled"; 1860 }; 1861 1862 frame@b026000 { 1863 frame-number = <4>; 1864 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1865 reg = <0x0b026000 0x1000>; 1866 status = "disabled"; 1867 }; 1868 1869 frame@b027000 { 1870 frame-number = <5>; 1871 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1872 reg = <0x0b027000 0x1000>; 1873 status = "disabled"; 1874 }; 1875 1876 frame@b028000 { 1877 frame-number = <6>; 1878 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1879 reg = <0x0b028000 0x1000>; 1880 status = "disabled"; 1881 }; 1882 }; 1883 1884 cpu0_acc: power-manager@b088000 { 1885 compatible = "qcom,msm8916-acc"; 1886 reg = <0x0b088000 0x1000>; 1887 status = "reserved"; /* Controlled by PSCI firmware */ 1888 }; 1889 1890 cpu0_saw: power-manager@b089000 { 1891 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1892 reg = <0x0b089000 0x1000>; 1893 status = "reserved"; /* Controlled by PSCI firmware */ 1894 }; 1895 1896 cpu1_acc: power-manager@b098000 { 1897 compatible = "qcom,msm8916-acc"; 1898 reg = <0x0b098000 0x1000>; 1899 status = "reserved"; /* Controlled by PSCI firmware */ 1900 }; 1901 1902 cpu1_saw: power-manager@b099000 { 1903 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1904 reg = <0x0b099000 0x1000>; 1905 status = "reserved"; /* Controlled by PSCI firmware */ 1906 }; 1907 1908 cpu2_acc: power-manager@b0a8000 { 1909 compatible = "qcom,msm8916-acc"; 1910 reg = <0x0b0a8000 0x1000>; 1911 status = "reserved"; /* Controlled by PSCI firmware */ 1912 }; 1913 1914 cpu2_saw: power-manager@b0a9000 { 1915 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1916 reg = <0x0b0a9000 0x1000>; 1917 status = "reserved"; /* Controlled by PSCI firmware */ 1918 }; 1919 1920 cpu3_acc: power-manager@b0b8000 { 1921 compatible = "qcom,msm8916-acc"; 1922 reg = <0x0b0b8000 0x1000>; 1923 status = "reserved"; /* Controlled by PSCI firmware */ 1924 }; 1925 1926 cpu3_saw: power-manager@b0b9000 { 1927 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 1928 reg = <0x0b0b9000 0x1000>; 1929 status = "reserved"; /* Controlled by PSCI firmware */ 1930 }; 1931 }; 1932 1933 thermal-zones { 1934 cpu0-1-thermal { 1935 polling-delay-passive = <250>; 1936 polling-delay = <1000>; 1937 1938 thermal-sensors = <&tsens 5>; 1939 1940 trips { 1941 cpu0_1_alert0: trip-point0 { 1942 temperature = <75000>; 1943 hysteresis = <2000>; 1944 type = "passive"; 1945 }; 1946 cpu0_1_crit: cpu_crit { 1947 temperature = <110000>; 1948 hysteresis = <2000>; 1949 type = "critical"; 1950 }; 1951 }; 1952 1953 cooling-maps { 1954 map0 { 1955 trip = <&cpu0_1_alert0>; 1956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1957 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1958 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1959 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1960 }; 1961 }; 1962 }; 1963 1964 cpu2-3-thermal { 1965 polling-delay-passive = <250>; 1966 polling-delay = <1000>; 1967 1968 thermal-sensors = <&tsens 4>; 1969 1970 trips { 1971 cpu2_3_alert0: trip-point0 { 1972 temperature = <75000>; 1973 hysteresis = <2000>; 1974 type = "passive"; 1975 }; 1976 cpu2_3_crit: cpu_crit { 1977 temperature = <110000>; 1978 hysteresis = <2000>; 1979 type = "critical"; 1980 }; 1981 }; 1982 1983 cooling-maps { 1984 map0 { 1985 trip = <&cpu2_3_alert0>; 1986 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1987 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1988 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1989 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1990 }; 1991 }; 1992 }; 1993 1994 gpu-thermal { 1995 polling-delay-passive = <250>; 1996 polling-delay = <1000>; 1997 1998 thermal-sensors = <&tsens 2>; 1999 2000 trips { 2001 gpu_alert0: trip-point0 { 2002 temperature = <75000>; 2003 hysteresis = <2000>; 2004 type = "passive"; 2005 }; 2006 gpu_crit: gpu_crit { 2007 temperature = <95000>; 2008 hysteresis = <2000>; 2009 type = "critical"; 2010 }; 2011 }; 2012 }; 2013 2014 camera-thermal { 2015 polling-delay-passive = <250>; 2016 polling-delay = <1000>; 2017 2018 thermal-sensors = <&tsens 1>; 2019 2020 trips { 2021 cam_alert0: trip-point0 { 2022 temperature = <75000>; 2023 hysteresis = <2000>; 2024 type = "hot"; 2025 }; 2026 }; 2027 }; 2028 2029 modem-thermal { 2030 polling-delay-passive = <250>; 2031 polling-delay = <1000>; 2032 2033 thermal-sensors = <&tsens 0>; 2034 2035 trips { 2036 modem_alert0: trip-point0 { 2037 temperature = <85000>; 2038 hysteresis = <2000>; 2039 type = "hot"; 2040 }; 2041 }; 2042 }; 2043 2044 }; 2045 2046 timer { 2047 compatible = "arm,armv8-timer"; 2048 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2049 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2050 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2051 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2052 }; 2053}; 2054 2055#include "msm8916-pins.dtsi" 2056