1/* 2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-msm8916.h> 16#include <dt-bindings/reset/qcom,gcc-msm8916.h> 17 18/ { 19 model = "Qualcomm Technologies, Inc. MSM8916"; 20 compatible = "qcom,msm8916"; 21 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 aliases { 28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 30 }; 31 32 chosen { }; 33 34 memory { 35 device_type = "memory"; 36 /* We expect the bootloader to fill in the reg */ 37 reg = <0 0 0 0>; 38 }; 39 40 reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 tz-apps@86000000 { 46 reg = <0x0 0x86000000 0x0 0x300000>; 47 no-map; 48 }; 49 50 smem_mem: smem_region@86300000 { 51 reg = <0x0 0x86300000 0x0 0x100000>; 52 no-map; 53 }; 54 55 hypervisor@86400000 { 56 reg = <0x0 0x86400000 0x0 0x100000>; 57 no-map; 58 }; 59 60 tz@86500000 { 61 reg = <0x0 0x86500000 0x0 0x180000>; 62 no-map; 63 }; 64 65 reserved@8668000 { 66 reg = <0x0 0x86680000 0x0 0x80000>; 67 no-map; 68 }; 69 70 rmtfs@86700000 { 71 reg = <0x0 0x86700000 0x0 0xe0000>; 72 no-map; 73 }; 74 75 rfsa@867e00000 { 76 reg = <0x0 0x867e0000 0x0 0x20000>; 77 no-map; 78 }; 79 80 mpss@86800000 { 81 reg = <0x0 0x86800000 0x0 0x2b00000>; 82 no-map; 83 }; 84 85 wcnss@89300000 { 86 reg = <0x0 0x89300000 0x0 0x600000>; 87 no-map; 88 }; 89 }; 90 91 cpus { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 CPU0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 reg = <0x0>; 99 next-level-cache = <&L2_0>; 100 enable-method = "psci"; 101 cpu-idle-states = <&CPU_SPC>; 102 }; 103 104 CPU1: cpu@1 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53", "arm,armv8"; 107 reg = <0x1>; 108 next-level-cache = <&L2_0>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SPC>; 111 }; 112 113 CPU2: cpu@2 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a53", "arm,armv8"; 116 reg = <0x2>; 117 next-level-cache = <&L2_0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&CPU_SPC>; 120 }; 121 122 CPU3: cpu@3 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x3>; 126 next-level-cache = <&L2_0>; 127 enable-method = "psci"; 128 cpu-idle-states = <&CPU_SPC>; 129 }; 130 131 L2_0: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 }; 135 136 idle-states { 137 CPU_SPC: spc { 138 compatible = "arm,idle-state"; 139 arm,psci-suspend-param = <0x40000002>; 140 entry-latency-us = <130>; 141 exit-latency-us = <150>; 142 min-residency-us = <2000>; 143 local-timer-stop; 144 }; 145 }; 146 }; 147 148 psci { 149 compatible = "arm,psci-1.0"; 150 method = "smc"; 151 }; 152 153 pmu { 154 compatible = "arm,armv8-pmuv3"; 155 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; 156 }; 157 158 timer { 159 compatible = "arm,armv8-timer"; 160 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 162 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 164 }; 165 166 clocks { 167 xo_board: xo_board { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <19200000>; 171 }; 172 173 sleep_clk: sleep_clk { 174 compatible = "fixed-clock"; 175 #clock-cells = <0>; 176 clock-frequency = <32768>; 177 }; 178 }; 179 180 smem { 181 compatible = "qcom,smem"; 182 183 memory-region = <&smem_mem>; 184 qcom,rpm-msg-ram = <&rpm_msg_ram>; 185 186 hwlocks = <&tcsr_mutex 3>; 187 }; 188 189 firmware { 190 scm { 191 compatible = "qcom,scm"; 192 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 193 clock-names = "core", "bus", "iface"; 194 }; 195 }; 196 197 soc: soc { 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0 0 0 0xffffffff>; 201 compatible = "simple-bus"; 202 203 restart@4ab000 { 204 compatible = "qcom,pshold"; 205 reg = <0x4ab000 0x4>; 206 }; 207 208 msmgpio: pinctrl@1000000 { 209 compatible = "qcom,msm8916-pinctrl"; 210 reg = <0x1000000 0x300000>; 211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 }; 217 218 gcc: clock-controller@1800000 { 219 compatible = "qcom,gcc-msm8916"; 220 #clock-cells = <1>; 221 #reset-cells = <1>; 222 #power-domain-cells = <1>; 223 reg = <0x1800000 0x80000>; 224 }; 225 226 tcsr_mutex_regs: syscon@1905000 { 227 compatible = "syscon"; 228 reg = <0x1905000 0x20000>; 229 }; 230 231 tcsr_mutex: hwlock { 232 compatible = "qcom,tcsr-mutex"; 233 syscon = <&tcsr_mutex_regs 0 0x1000>; 234 #hwlock-cells = <1>; 235 }; 236 237 rpm_msg_ram: memory@60000 { 238 compatible = "qcom,rpm-msg-ram"; 239 reg = <0x60000 0x8000>; 240 }; 241 242 blsp1_uart1: serial@78af000 { 243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 244 reg = <0x78af000 0x200>; 245 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 247 clock-names = "core", "iface"; 248 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 249 dma-names = "rx", "tx"; 250 status = "disabled"; 251 }; 252 253 apcs: syscon@b011000 { 254 compatible = "syscon"; 255 reg = <0x0b011000 0x1000>; 256 }; 257 258 blsp1_uart2: serial@78b0000 { 259 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 260 reg = <0x78b0000 0x200>; 261 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 263 clock-names = "core", "iface"; 264 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 265 dma-names = "rx", "tx"; 266 status = "disabled"; 267 }; 268 269 blsp_dma: dma@7884000 { 270 compatible = "qcom,bam-v1.7.0"; 271 reg = <0x07884000 0x23000>; 272 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 274 clock-names = "bam_clk"; 275 #dma-cells = <1>; 276 qcom,ee = <0>; 277 status = "disabled"; 278 }; 279 280 blsp_spi1: spi@78b5000 { 281 compatible = "qcom,spi-qup-v2.2.1"; 282 reg = <0x078b5000 0x600>; 283 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 285 <&gcc GCC_BLSP1_AHB_CLK>; 286 clock-names = "core", "iface"; 287 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 288 dma-names = "rx", "tx"; 289 pinctrl-names = "default", "sleep"; 290 pinctrl-0 = <&spi1_default>; 291 pinctrl-1 = <&spi1_sleep>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 blsp_spi2: spi@78b6000 { 298 compatible = "qcom,spi-qup-v2.2.1"; 299 reg = <0x078b6000 0x600>; 300 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 302 <&gcc GCC_BLSP1_AHB_CLK>; 303 clock-names = "core", "iface"; 304 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 305 dma-names = "rx", "tx"; 306 pinctrl-names = "default", "sleep"; 307 pinctrl-0 = <&spi2_default>; 308 pinctrl-1 = <&spi2_sleep>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 blsp_spi3: spi@78b7000 { 315 compatible = "qcom,spi-qup-v2.2.1"; 316 reg = <0x078b7000 0x600>; 317 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 319 <&gcc GCC_BLSP1_AHB_CLK>; 320 clock-names = "core", "iface"; 321 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 322 dma-names = "rx", "tx"; 323 pinctrl-names = "default", "sleep"; 324 pinctrl-0 = <&spi3_default>; 325 pinctrl-1 = <&spi3_sleep>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 blsp_spi4: spi@78b8000 { 332 compatible = "qcom,spi-qup-v2.2.1"; 333 reg = <0x078b8000 0x600>; 334 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 336 <&gcc GCC_BLSP1_AHB_CLK>; 337 clock-names = "core", "iface"; 338 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 339 dma-names = "rx", "tx"; 340 pinctrl-names = "default", "sleep"; 341 pinctrl-0 = <&spi4_default>; 342 pinctrl-1 = <&spi4_sleep>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 status = "disabled"; 346 }; 347 348 blsp_spi5: spi@78b9000 { 349 compatible = "qcom,spi-qup-v2.2.1"; 350 reg = <0x078b9000 0x600>; 351 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 353 <&gcc GCC_BLSP1_AHB_CLK>; 354 clock-names = "core", "iface"; 355 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 356 dma-names = "rx", "tx"; 357 pinctrl-names = "default", "sleep"; 358 pinctrl-0 = <&spi5_default>; 359 pinctrl-1 = <&spi5_sleep>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 blsp_spi6: spi@78ba000 { 366 compatible = "qcom,spi-qup-v2.2.1"; 367 reg = <0x078ba000 0x600>; 368 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 370 <&gcc GCC_BLSP1_AHB_CLK>; 371 clock-names = "core", "iface"; 372 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 373 dma-names = "rx", "tx"; 374 pinctrl-names = "default", "sleep"; 375 pinctrl-0 = <&spi6_default>; 376 pinctrl-1 = <&spi6_sleep>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 status = "disabled"; 380 }; 381 382 blsp_i2c2: i2c@78b6000 { 383 compatible = "qcom,i2c-qup-v2.2.1"; 384 reg = <0x78b6000 0x1000>; 385 interrupts = <GIC_SPI 96 0>; 386 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 387 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 388 clock-names = "iface", "core"; 389 pinctrl-names = "default", "sleep"; 390 pinctrl-0 = <&i2c2_default>; 391 pinctrl-1 = <&i2c2_sleep>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 blsp_i2c4: i2c@78b8000 { 398 compatible = "qcom,i2c-qup-v2.2.1"; 399 reg = <0x78b8000 0x1000>; 400 interrupts = <GIC_SPI 98 0>; 401 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 402 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 403 clock-names = "iface", "core"; 404 pinctrl-names = "default", "sleep"; 405 pinctrl-0 = <&i2c4_default>; 406 pinctrl-1 = <&i2c4_sleep>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 }; 411 412 blsp_i2c6: i2c@78ba000 { 413 compatible = "qcom,i2c-qup-v2.2.1"; 414 reg = <0x78ba000 0x1000>; 415 interrupts = <GIC_SPI 100 0>; 416 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 417 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 418 clock-names = "iface", "core"; 419 pinctrl-names = "default", "sleep"; 420 pinctrl-0 = <&i2c6_default>; 421 pinctrl-1 = <&i2c6_sleep>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 lpass: lpass@07708000 { 428 status = "disabled"; 429 compatible = "qcom,lpass-cpu-apq8016"; 430 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 431 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 432 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 433 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 434 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 435 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 436 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 437 438 clock-names = "ahbix-clk", 439 "pcnoc-mport-clk", 440 "pcnoc-sway-clk", 441 "mi2s-bit-clk0", 442 "mi2s-bit-clk1", 443 "mi2s-bit-clk2", 444 "mi2s-bit-clk3"; 445 #sound-dai-cells = <1>; 446 447 interrupts = <0 160 0>; 448 interrupt-names = "lpass-irq-lpaif"; 449 reg = <0x07708000 0x10000>; 450 reg-names = "lpass-lpaif"; 451 }; 452 453 sdhc_1: sdhci@07824000 { 454 compatible = "qcom,sdhci-msm-v4"; 455 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 456 reg-names = "hc_mem", "core_mem"; 457 458 interrupts = <0 123 0>, <0 138 0>; 459 interrupt-names = "hc_irq", "pwr_irq"; 460 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 461 <&gcc GCC_SDCC1_AHB_CLK>; 462 clock-names = "core", "iface"; 463 bus-width = <8>; 464 non-removable; 465 status = "disabled"; 466 }; 467 468 sdhc_2: sdhci@07864000 { 469 compatible = "qcom,sdhci-msm-v4"; 470 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 471 reg-names = "hc_mem", "core_mem"; 472 473 interrupts = <0 125 0>, <0 221 0>; 474 interrupt-names = "hc_irq", "pwr_irq"; 475 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 476 <&gcc GCC_SDCC2_AHB_CLK>; 477 clock-names = "core", "iface"; 478 bus-width = <4>; 479 status = "disabled"; 480 }; 481 482 usb_dev: usb@78d9000 { 483 compatible = "qcom,ci-hdrc"; 484 reg = <0x78d9000 0x400>; 485 dr_mode = "peripheral"; 486 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>; 487 usb-phy = <&usb_otg>; 488 status = "disabled"; 489 }; 490 491 usb_host: ehci@78d9000 { 492 compatible = "qcom,ehci-host"; 493 reg = <0x78d9000 0x400>; 494 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>; 495 usb-phy = <&usb_otg>; 496 status = "disabled"; 497 }; 498 499 usb_otg: phy@78d9000 { 500 compatible = "qcom,usb-otg-snps"; 501 reg = <0x78d9000 0x400>; 502 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>, 503 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 504 505 qcom,vdd-levels = <500000 1000000 1320000>; 506 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>; 507 dr_mode = "peripheral"; 508 qcom,otg-control = <2>; // PMIC 509 qcom,manual-pullup; 510 511 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 512 <&gcc GCC_USB_HS_SYSTEM_CLK>, 513 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 514 clock-names = "iface", "core", "sleep"; 515 516 resets = <&gcc GCC_USB2A_PHY_BCR>, 517 <&gcc GCC_USB_HS_BCR>; 518 reset-names = "phy", "link"; 519 status = "disabled"; 520 }; 521 522 intc: interrupt-controller@b000000 { 523 compatible = "qcom,msm-qgic2"; 524 interrupt-controller; 525 #interrupt-cells = <3>; 526 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 527 }; 528 529 timer@b020000 { 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 compatible = "arm,armv7-timer-mem"; 534 reg = <0xb020000 0x1000>; 535 clock-frequency = <19200000>; 536 537 frame@b021000 { 538 frame-number = <0>; 539 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 541 reg = <0xb021000 0x1000>, 542 <0xb022000 0x1000>; 543 }; 544 545 frame@b023000 { 546 frame-number = <1>; 547 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 548 reg = <0xb023000 0x1000>; 549 status = "disabled"; 550 }; 551 552 frame@b024000 { 553 frame-number = <2>; 554 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 555 reg = <0xb024000 0x1000>; 556 status = "disabled"; 557 }; 558 559 frame@b025000 { 560 frame-number = <3>; 561 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 562 reg = <0xb025000 0x1000>; 563 status = "disabled"; 564 }; 565 566 frame@b026000 { 567 frame-number = <4>; 568 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 569 reg = <0xb026000 0x1000>; 570 status = "disabled"; 571 }; 572 573 frame@b027000 { 574 frame-number = <5>; 575 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 576 reg = <0xb027000 0x1000>; 577 status = "disabled"; 578 }; 579 580 frame@b028000 { 581 frame-number = <6>; 582 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 583 reg = <0xb028000 0x1000>; 584 status = "disabled"; 585 }; 586 }; 587 588 spmi_bus: spmi@200f000 { 589 compatible = "qcom,spmi-pmic-arb"; 590 reg = <0x200f000 0x001000>, 591 <0x2400000 0x400000>, 592 <0x2c00000 0x400000>, 593 <0x3800000 0x200000>, 594 <0x200a000 0x002100>; 595 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 596 interrupt-names = "periph_irq"; 597 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; 598 qcom,ee = <0>; 599 qcom,channel = <0>; 600 #address-cells = <2>; 601 #size-cells = <0>; 602 interrupt-controller; 603 #interrupt-cells = <4>; 604 }; 605 606 rng@22000 { 607 compatible = "qcom,prng"; 608 reg = <0x00022000 0x200>; 609 clocks = <&gcc GCC_PRNG_AHB_CLK>; 610 clock-names = "core"; 611 }; 612 }; 613 614 smd { 615 compatible = "qcom,smd"; 616 617 rpm { 618 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 619 qcom,ipc = <&apcs 8 0>; 620 qcom,smd-edge = <15>; 621 622 rpm_requests { 623 compatible = "qcom,rpm-msm8916"; 624 qcom,smd-channels = "rpm_requests"; 625 626 rpmcc: qcom,rpmcc { 627 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 628 #clock-cells = <1>; 629 }; 630 631 smd_rpm_regulators: pm8916-regulators { 632 compatible = "qcom,rpm-pm8916-regulators"; 633 634 pm8916_s1: s1 {}; 635 pm8916_s3: s3 {}; 636 pm8916_s4: s4 {}; 637 638 pm8916_l1: l1 {}; 639 pm8916_l2: l2 {}; 640 pm8916_l3: l3 {}; 641 pm8916_l4: l4 {}; 642 pm8916_l5: l5 {}; 643 pm8916_l6: l6 {}; 644 pm8916_l7: l7 {}; 645 pm8916_l8: l8 {}; 646 pm8916_l9: l9 {}; 647 pm8916_l10: l10 {}; 648 pm8916_l11: l11 {}; 649 pm8916_l12: l12 {}; 650 pm8916_l13: l13 {}; 651 pm8916_l14: l14 {}; 652 pm8916_l15: l15 {}; 653 pm8916_l16: l16 {}; 654 pm8916_l17: l17 {}; 655 pm8916_l18: l18 {}; 656 }; 657 }; 658 }; 659 }; 660}; 661 662#include "msm8916-pins.dtsi" 663