1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/reset/qcom,gcc-msm8916.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 20 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 21 }; 22 23 chosen { }; 24 25 memory { 26 device_type = "memory"; 27 /* We expect the bootloader to fill in the reg */ 28 reg = <0 0 0 0>; 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 tz-apps@86000000 { 37 reg = <0x0 0x86000000 0x0 0x300000>; 38 no-map; 39 }; 40 41 smem_mem: smem_region@86300000 { 42 reg = <0x0 0x86300000 0x0 0x100000>; 43 no-map; 44 }; 45 46 hypervisor@86400000 { 47 reg = <0x0 0x86400000 0x0 0x100000>; 48 no-map; 49 }; 50 51 tz@86500000 { 52 reg = <0x0 0x86500000 0x0 0x180000>; 53 no-map; 54 }; 55 56 reserved@8668000 { 57 reg = <0x0 0x86680000 0x0 0x80000>; 58 no-map; 59 }; 60 61 rmtfs@86700000 { 62 compatible = "qcom,rmtfs-mem"; 63 reg = <0x0 0x86700000 0x0 0xe0000>; 64 no-map; 65 66 qcom,client-id = <1>; 67 }; 68 69 rfsa@867e00000 { 70 reg = <0x0 0x867e0000 0x0 0x20000>; 71 no-map; 72 }; 73 74 mpss_mem: mpss@86800000 { 75 reg = <0x0 0x86800000 0x0 0x2b00000>; 76 no-map; 77 }; 78 79 wcnss_mem: wcnss@89300000 { 80 reg = <0x0 0x89300000 0x0 0x600000>; 81 no-map; 82 }; 83 84 venus_mem: venus@89900000 { 85 reg = <0x0 0x89900000 0x0 0x600000>; 86 no-map; 87 }; 88 89 mba_mem: mba@8ea00000 { 90 no-map; 91 reg = <0 0x8ea00000 0 0x100000>; 92 }; 93 }; 94 95 cpus { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 CPU0: cpu@0 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0>; 103 next-level-cache = <&L2_0>; 104 enable-method = "psci"; 105 clocks = <&apcs>; 106 operating-points-v2 = <&cpu_opp_table>; 107 #cooling-cells = <2>; 108 power-domains = <&CPU_PD0>; 109 power-domain-names = "psci"; 110 }; 111 112 CPU1: cpu@1 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a53"; 115 reg = <0x1>; 116 next-level-cache = <&L2_0>; 117 enable-method = "psci"; 118 clocks = <&apcs>; 119 operating-points-v2 = <&cpu_opp_table>; 120 #cooling-cells = <2>; 121 power-domains = <&CPU_PD1>; 122 power-domain-names = "psci"; 123 }; 124 125 CPU2: cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x2>; 129 next-level-cache = <&L2_0>; 130 enable-method = "psci"; 131 clocks = <&apcs>; 132 operating-points-v2 = <&cpu_opp_table>; 133 #cooling-cells = <2>; 134 power-domains = <&CPU_PD2>; 135 power-domain-names = "psci"; 136 }; 137 138 CPU3: cpu@3 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a53"; 141 reg = <0x3>; 142 next-level-cache = <&L2_0>; 143 enable-method = "psci"; 144 clocks = <&apcs>; 145 operating-points-v2 = <&cpu_opp_table>; 146 #cooling-cells = <2>; 147 power-domains = <&CPU_PD3>; 148 power-domain-names = "psci"; 149 }; 150 151 L2_0: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 }; 155 156 idle-states { 157 entry-method = "psci"; 158 159 CPU_SLEEP_0: cpu-sleep-0 { 160 compatible = "arm,idle-state"; 161 idle-state-name = "standalone-power-collapse"; 162 arm,psci-suspend-param = <0x40000002>; 163 entry-latency-us = <130>; 164 exit-latency-us = <150>; 165 min-residency-us = <2000>; 166 local-timer-stop; 167 }; 168 169 CLUSTER_RET: cluster-retention { 170 compatible = "domain-idle-state"; 171 arm,psci-suspend-param = <0x41000012>; 172 entry-latency-us = <500>; 173 exit-latency-us = <500>; 174 min-residency-us = <2000>; 175 }; 176 177 CLUSTER_PWRDN: cluster-gdhs { 178 compatible = "domain-idle-state"; 179 arm,psci-suspend-param = <0x41000032>; 180 entry-latency-us = <2000>; 181 exit-latency-us = <2000>; 182 min-residency-us = <6000>; 183 }; 184 }; 185 }; 186 187 psci { 188 compatible = "arm,psci-1.0"; 189 method = "smc"; 190 191 CPU_PD0: cpu-pd0 { 192 #power-domain-cells = <0>; 193 power-domains = <&CLUSTER_PD>; 194 domain-idle-states = <&CPU_SLEEP_0>; 195 }; 196 197 CPU_PD1: cpu-pd1 { 198 #power-domain-cells = <0>; 199 power-domains = <&CLUSTER_PD>; 200 domain-idle-states = <&CPU_SLEEP_0>; 201 }; 202 203 CPU_PD2: cpu-pd2 { 204 #power-domain-cells = <0>; 205 power-domains = <&CLUSTER_PD>; 206 domain-idle-states = <&CPU_SLEEP_0>; 207 }; 208 209 CPU_PD3: cpu-pd3 { 210 #power-domain-cells = <0>; 211 power-domains = <&CLUSTER_PD>; 212 domain-idle-states = <&CPU_SLEEP_0>; 213 }; 214 215 CLUSTER_PD: cluster-pd { 216 #power-domain-cells = <0>; 217 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 218 }; 219 }; 220 221 pmu { 222 compatible = "arm,cortex-a53-pmu"; 223 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 224 }; 225 226 thermal-zones { 227 cpu0_1-thermal { 228 polling-delay-passive = <250>; 229 polling-delay = <1000>; 230 231 thermal-sensors = <&tsens 5>; 232 233 trips { 234 cpu0_1_alert0: trip-point@0 { 235 temperature = <75000>; 236 hysteresis = <2000>; 237 type = "passive"; 238 }; 239 cpu0_1_crit: cpu_crit { 240 temperature = <110000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu0_1_alert0>; 249 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 250 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 253 }; 254 }; 255 }; 256 257 cpu2_3-thermal { 258 polling-delay-passive = <250>; 259 polling-delay = <1000>; 260 261 thermal-sensors = <&tsens 4>; 262 263 trips { 264 cpu2_3_alert0: trip-point@0 { 265 temperature = <75000>; 266 hysteresis = <2000>; 267 type = "passive"; 268 }; 269 cpu2_3_crit: cpu_crit { 270 temperature = <110000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&cpu2_3_alert0>; 279 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 280 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 283 }; 284 }; 285 }; 286 287 gpu-thermal { 288 polling-delay-passive = <250>; 289 polling-delay = <1000>; 290 291 thermal-sensors = <&tsens 2>; 292 293 trips { 294 gpu_alert0: trip-point@0 { 295 temperature = <75000>; 296 hysteresis = <2000>; 297 type = "passive"; 298 }; 299 gpu_crit: gpu_crit { 300 temperature = <95000>; 301 hysteresis = <2000>; 302 type = "critical"; 303 }; 304 }; 305 }; 306 307 camera-thermal { 308 polling-delay-passive = <250>; 309 polling-delay = <1000>; 310 311 thermal-sensors = <&tsens 1>; 312 313 trips { 314 cam_alert0: trip-point@0 { 315 temperature = <75000>; 316 hysteresis = <2000>; 317 type = "hot"; 318 }; 319 }; 320 }; 321 322 modem-thermal { 323 polling-delay-passive = <250>; 324 polling-delay = <1000>; 325 326 thermal-sensors = <&tsens 0>; 327 328 trips { 329 modem_alert0: trip-point@0 { 330 temperature = <85000>; 331 hysteresis = <2000>; 332 type = "hot"; 333 }; 334 }; 335 }; 336 337 }; 338 339 cpu_opp_table: cpu_opp_table { 340 compatible = "operating-points-v2"; 341 opp-shared; 342 343 opp-200000000 { 344 opp-hz = /bits/ 64 <200000000>; 345 }; 346 opp-400000000 { 347 opp-hz = /bits/ 64 <400000000>; 348 }; 349 opp-800000000 { 350 opp-hz = /bits/ 64 <800000000>; 351 }; 352 opp-998400000 { 353 opp-hz = /bits/ 64 <998400000>; 354 }; 355 }; 356 357 gpu_opp_table: opp_table { 358 compatible = "operating-points-v2"; 359 360 opp-400000000 { 361 opp-hz = /bits/ 64 <400000000>; 362 }; 363 opp-19200000 { 364 opp-hz = /bits/ 64 <19200000>; 365 }; 366 }; 367 368 timer { 369 compatible = "arm,armv8-timer"; 370 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 371 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 372 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 373 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 374 }; 375 376 clocks { 377 xo_board: xo_board { 378 compatible = "fixed-clock"; 379 #clock-cells = <0>; 380 clock-frequency = <19200000>; 381 }; 382 383 sleep_clk: sleep_clk { 384 compatible = "fixed-clock"; 385 #clock-cells = <0>; 386 clock-frequency = <32768>; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 393 memory-region = <&smem_mem>; 394 qcom,rpm-msg-ram = <&rpm_msg_ram>; 395 396 hwlocks = <&tcsr_mutex 3>; 397 }; 398 399 firmware { 400 scm: scm { 401 compatible = "qcom,scm"; 402 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 403 clock-names = "core", "bus", "iface"; 404 #reset-cells = <1>; 405 406 qcom,dload-mode = <&tcsr 0x6100>; 407 }; 408 }; 409 410 soc: soc { 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0 0 0 0xffffffff>; 414 compatible = "simple-bus"; 415 416 restart@4ab000 { 417 compatible = "qcom,pshold"; 418 reg = <0x4ab000 0x4>; 419 }; 420 421 msmgpio: pinctrl@1000000 { 422 compatible = "qcom,msm8916-pinctrl"; 423 reg = <0x1000000 0x300000>; 424 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 425 gpio-controller; 426 gpio-ranges = <&msmgpio 0 0 122>; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 }; 431 432 gcc: clock-controller@1800000 { 433 compatible = "qcom,gcc-msm8916"; 434 #clock-cells = <1>; 435 #reset-cells = <1>; 436 #power-domain-cells = <1>; 437 reg = <0x1800000 0x80000>; 438 }; 439 440 tcsr_mutex_regs: syscon@1905000 { 441 compatible = "syscon"; 442 reg = <0x1905000 0x20000>; 443 }; 444 445 tcsr: syscon@1937000 { 446 compatible = "qcom,tcsr-msm8916", "syscon"; 447 reg = <0x1937000 0x30000>; 448 }; 449 450 tcsr_mutex: hwlock { 451 compatible = "qcom,tcsr-mutex"; 452 syscon = <&tcsr_mutex_regs 0 0x1000>; 453 #hwlock-cells = <1>; 454 }; 455 456 rpm_msg_ram: memory@60000 { 457 compatible = "qcom,rpm-msg-ram"; 458 reg = <0x60000 0x8000>; 459 }; 460 461 blsp1_uart1: serial@78af000 { 462 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 463 reg = <0x78af000 0x200>; 464 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 466 clock-names = "core", "iface"; 467 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 468 dma-names = "rx", "tx"; 469 status = "disabled"; 470 }; 471 472 a53pll: clock@b016000 { 473 compatible = "qcom,msm8916-a53pll"; 474 reg = <0xb016000 0x40>; 475 #clock-cells = <0>; 476 }; 477 478 apcs: mailbox@b011000 { 479 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 480 reg = <0xb011000 0x1000>; 481 #mbox-cells = <1>; 482 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 483 clock-names = "pll", "aux"; 484 #clock-cells = <0>; 485 }; 486 487 blsp1_uart2: serial@78b0000 { 488 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 489 reg = <0x78b0000 0x200>; 490 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 492 clock-names = "core", "iface"; 493 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 494 dma-names = "rx", "tx"; 495 status = "disabled"; 496 }; 497 498 blsp_dma: dma@7884000 { 499 compatible = "qcom,bam-v1.7.0"; 500 reg = <0x07884000 0x23000>; 501 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 503 clock-names = "bam_clk"; 504 #dma-cells = <1>; 505 qcom,ee = <0>; 506 status = "disabled"; 507 }; 508 509 blsp_spi1: spi@78b5000 { 510 compatible = "qcom,spi-qup-v2.2.1"; 511 reg = <0x078b5000 0x500>; 512 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 514 <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "core", "iface"; 516 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 517 dma-names = "rx", "tx"; 518 pinctrl-names = "default", "sleep"; 519 pinctrl-0 = <&spi1_default>; 520 pinctrl-1 = <&spi1_sleep>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 blsp_spi2: spi@78b6000 { 527 compatible = "qcom,spi-qup-v2.2.1"; 528 reg = <0x078b6000 0x500>; 529 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 531 <&gcc GCC_BLSP1_AHB_CLK>; 532 clock-names = "core", "iface"; 533 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 534 dma-names = "rx", "tx"; 535 pinctrl-names = "default", "sleep"; 536 pinctrl-0 = <&spi2_default>; 537 pinctrl-1 = <&spi2_sleep>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 blsp_spi3: spi@78b7000 { 544 compatible = "qcom,spi-qup-v2.2.1"; 545 reg = <0x078b7000 0x500>; 546 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 548 <&gcc GCC_BLSP1_AHB_CLK>; 549 clock-names = "core", "iface"; 550 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 551 dma-names = "rx", "tx"; 552 pinctrl-names = "default", "sleep"; 553 pinctrl-0 = <&spi3_default>; 554 pinctrl-1 = <&spi3_sleep>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 blsp_spi4: spi@78b8000 { 561 compatible = "qcom,spi-qup-v2.2.1"; 562 reg = <0x078b8000 0x500>; 563 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 565 <&gcc GCC_BLSP1_AHB_CLK>; 566 clock-names = "core", "iface"; 567 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 568 dma-names = "rx", "tx"; 569 pinctrl-names = "default", "sleep"; 570 pinctrl-0 = <&spi4_default>; 571 pinctrl-1 = <&spi4_sleep>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 blsp_spi5: spi@78b9000 { 578 compatible = "qcom,spi-qup-v2.2.1"; 579 reg = <0x078b9000 0x500>; 580 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 582 <&gcc GCC_BLSP1_AHB_CLK>; 583 clock-names = "core", "iface"; 584 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 585 dma-names = "rx", "tx"; 586 pinctrl-names = "default", "sleep"; 587 pinctrl-0 = <&spi5_default>; 588 pinctrl-1 = <&spi5_sleep>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 blsp_spi6: spi@78ba000 { 595 compatible = "qcom,spi-qup-v2.2.1"; 596 reg = <0x078ba000 0x500>; 597 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 599 <&gcc GCC_BLSP1_AHB_CLK>; 600 clock-names = "core", "iface"; 601 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 602 dma-names = "rx", "tx"; 603 pinctrl-names = "default", "sleep"; 604 pinctrl-0 = <&spi6_default>; 605 pinctrl-1 = <&spi6_sleep>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 blsp_i2c2: i2c@78b6000 { 612 compatible = "qcom,i2c-qup-v2.2.1"; 613 reg = <0x078b6000 0x500>; 614 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 616 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 617 clock-names = "iface", "core"; 618 pinctrl-names = "default", "sleep"; 619 pinctrl-0 = <&i2c2_default>; 620 pinctrl-1 = <&i2c2_sleep>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 blsp_i2c4: i2c@78b8000 { 627 compatible = "qcom,i2c-qup-v2.2.1"; 628 reg = <0x078b8000 0x500>; 629 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 631 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 632 clock-names = "iface", "core"; 633 pinctrl-names = "default", "sleep"; 634 pinctrl-0 = <&i2c4_default>; 635 pinctrl-1 = <&i2c4_sleep>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 blsp_i2c6: i2c@78ba000 { 642 compatible = "qcom,i2c-qup-v2.2.1"; 643 reg = <0x078ba000 0x500>; 644 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 646 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 647 clock-names = "iface", "core"; 648 pinctrl-names = "default", "sleep"; 649 pinctrl-0 = <&i2c6_default>; 650 pinctrl-1 = <&i2c6_sleep>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 status = "disabled"; 654 }; 655 656 lpass: lpass@7708000 { 657 status = "disabled"; 658 compatible = "qcom,lpass-cpu-apq8016"; 659 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 660 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 661 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 662 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 663 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 664 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 665 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 666 667 clock-names = "ahbix-clk", 668 "pcnoc-mport-clk", 669 "pcnoc-sway-clk", 670 "mi2s-bit-clk0", 671 "mi2s-bit-clk1", 672 "mi2s-bit-clk2", 673 "mi2s-bit-clk3"; 674 #sound-dai-cells = <1>; 675 676 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; 677 interrupt-names = "lpass-irq-lpaif"; 678 reg = <0x07708000 0x10000>; 679 reg-names = "lpass-lpaif"; 680 }; 681 682 lpass_codec: codec{ 683 compatible = "qcom,msm8916-wcd-digital-codec"; 684 reg = <0x0771c000 0x400>; 685 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 686 <&gcc GCC_CODEC_DIGCODEC_CLK>; 687 clock-names = "ahbix-clk", "mclk"; 688 #sound-dai-cells = <1>; 689 }; 690 691 sdhc_1: sdhci@7824000 { 692 compatible = "qcom,sdhci-msm-v4"; 693 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 694 reg-names = "hc_mem", "core_mem"; 695 696 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; 697 interrupt-names = "hc_irq", "pwr_irq"; 698 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 699 <&gcc GCC_SDCC1_AHB_CLK>, 700 <&xo_board>; 701 clock-names = "core", "iface", "xo"; 702 mmc-ddr-1_8v; 703 bus-width = <8>; 704 non-removable; 705 status = "disabled"; 706 }; 707 708 sdhc_2: sdhci@7864000 { 709 compatible = "qcom,sdhci-msm-v4"; 710 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 711 reg-names = "hc_mem", "core_mem"; 712 713 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "hc_irq", "pwr_irq"; 715 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 716 <&gcc GCC_SDCC2_AHB_CLK>, 717 <&xo_board>; 718 clock-names = "core", "iface", "xo"; 719 bus-width = <4>; 720 status = "disabled"; 721 }; 722 723 otg: usb@78d9000 { 724 compatible = "qcom,ci-hdrc"; 725 reg = <0x78d9000 0x200>, 726 <0x78d9200 0x200>; 727 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 730 <&gcc GCC_USB_HS_SYSTEM_CLK>; 731 clock-names = "iface", "core"; 732 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 733 assigned-clock-rates = <80000000>; 734 resets = <&gcc GCC_USB_HS_BCR>; 735 reset-names = "core"; 736 phy_type = "ulpi"; 737 dr_mode = "otg"; 738 ahb-burst-config = <0>; 739 phy-names = "usb-phy"; 740 phys = <&usb_hs_phy>; 741 status = "disabled"; 742 #reset-cells = <1>; 743 744 ulpi { 745 usb_hs_phy: phy { 746 compatible = "qcom,usb-hs-phy-msm8916", 747 "qcom,usb-hs-phy"; 748 #phy-cells = <0>; 749 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 750 clock-names = "ref", "sleep"; 751 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 752 reset-names = "phy", "por"; 753 qcom,init-seq = /bits/ 8 <0x0 0x44 754 0x1 0x6b 0x2 0x24 0x3 0x13>; 755 }; 756 }; 757 }; 758 759 intc: interrupt-controller@b000000 { 760 compatible = "qcom,msm-qgic2"; 761 interrupt-controller; 762 #interrupt-cells = <3>; 763 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 764 }; 765 766 timer@b020000 { 767 #address-cells = <1>; 768 #size-cells = <1>; 769 ranges; 770 compatible = "arm,armv7-timer-mem"; 771 reg = <0xb020000 0x1000>; 772 clock-frequency = <19200000>; 773 774 frame@b021000 { 775 frame-number = <0>; 776 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0xb021000 0x1000>, 779 <0xb022000 0x1000>; 780 }; 781 782 frame@b023000 { 783 frame-number = <1>; 784 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 785 reg = <0xb023000 0x1000>; 786 status = "disabled"; 787 }; 788 789 frame@b024000 { 790 frame-number = <2>; 791 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 792 reg = <0xb024000 0x1000>; 793 status = "disabled"; 794 }; 795 796 frame@b025000 { 797 frame-number = <3>; 798 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 799 reg = <0xb025000 0x1000>; 800 status = "disabled"; 801 }; 802 803 frame@b026000 { 804 frame-number = <4>; 805 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 806 reg = <0xb026000 0x1000>; 807 status = "disabled"; 808 }; 809 810 frame@b027000 { 811 frame-number = <5>; 812 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 813 reg = <0xb027000 0x1000>; 814 status = "disabled"; 815 }; 816 817 frame@b028000 { 818 frame-number = <6>; 819 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 820 reg = <0xb028000 0x1000>; 821 status = "disabled"; 822 }; 823 }; 824 825 spmi_bus: spmi@200f000 { 826 compatible = "qcom,spmi-pmic-arb"; 827 reg = <0x200f000 0x001000>, 828 <0x2400000 0x400000>, 829 <0x2c00000 0x400000>, 830 <0x3800000 0x200000>, 831 <0x200a000 0x002100>; 832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 833 interrupt-names = "periph_irq"; 834 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 835 qcom,ee = <0>; 836 qcom,channel = <0>; 837 #address-cells = <2>; 838 #size-cells = <0>; 839 interrupt-controller; 840 #interrupt-cells = <4>; 841 }; 842 843 rng@22000 { 844 compatible = "qcom,prng"; 845 reg = <0x00022000 0x200>; 846 clocks = <&gcc GCC_PRNG_AHB_CLK>; 847 clock-names = "core"; 848 }; 849 850 qfprom: qfprom@5c000 { 851 compatible = "qcom,qfprom"; 852 reg = <0x5c000 0x1000>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 tsens_caldata: caldata@d0 { 856 reg = <0xd0 0x8>; 857 }; 858 tsens_calsel: calsel@ec { 859 reg = <0xec 0x4>; 860 }; 861 }; 862 863 tsens: thermal-sensor@4a9000 { 864 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 865 reg = <0x4a9000 0x1000>, /* TM */ 866 <0x4a8000 0x1000>; /* SROT */ 867 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 868 nvmem-cell-names = "calib", "calib_sel"; 869 #qcom,sensors = <5>; 870 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "uplow"; 872 #thermal-sensor-cells = <1>; 873 }; 874 875 apps_iommu: iommu@1ef0000 { 876 #address-cells = <1>; 877 #size-cells = <1>; 878 #iommu-cells = <1>; 879 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 880 ranges = <0 0x1e20000 0x40000>; 881 reg = <0x1ef0000 0x3000>; 882 clocks = <&gcc GCC_SMMU_CFG_CLK>, 883 <&gcc GCC_APSS_TCU_CLK>; 884 clock-names = "iface", "bus"; 885 qcom,iommu-secure-id = <17>; 886 887 // vfe: 888 iommu-ctx@3000 { 889 compatible = "qcom,msm-iommu-v1-sec"; 890 reg = <0x3000 0x1000>; 891 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 892 }; 893 894 // mdp_0: 895 iommu-ctx@4000 { 896 compatible = "qcom,msm-iommu-v1-ns"; 897 reg = <0x4000 0x1000>; 898 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 899 }; 900 901 // venus_ns: 902 iommu-ctx@5000 { 903 compatible = "qcom,msm-iommu-v1-sec"; 904 reg = <0x5000 0x1000>; 905 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 906 }; 907 }; 908 909 gpu_iommu: iommu@1f08000 { 910 #address-cells = <1>; 911 #size-cells = <1>; 912 #iommu-cells = <1>; 913 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 914 ranges = <0 0x1f08000 0x10000>; 915 clocks = <&gcc GCC_SMMU_CFG_CLK>, 916 <&gcc GCC_GFX_TCU_CLK>; 917 clock-names = "iface", "bus"; 918 qcom,iommu-secure-id = <18>; 919 920 // gfx3d_user: 921 iommu-ctx@1000 { 922 compatible = "qcom,msm-iommu-v1-ns"; 923 reg = <0x1000 0x1000>; 924 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 925 }; 926 927 // gfx3d_priv: 928 iommu-ctx@2000 { 929 compatible = "qcom,msm-iommu-v1-ns"; 930 reg = <0x2000 0x1000>; 931 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 932 }; 933 }; 934 935 gpu@1c00000 { 936 compatible = "qcom,adreno-306.0", "qcom,adreno"; 937 reg = <0x01c00000 0x20000>; 938 reg-names = "kgsl_3d0_reg_memory"; 939 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "kgsl_3d0_irq"; 941 clock-names = 942 "core", 943 "iface", 944 "mem", 945 "mem_iface", 946 "alt_mem_iface", 947 "gfx3d"; 948 clocks = 949 <&gcc GCC_OXILI_GFX3D_CLK>, 950 <&gcc GCC_OXILI_AHB_CLK>, 951 <&gcc GCC_OXILI_GMEM_CLK>, 952 <&gcc GCC_BIMC_GFX_CLK>, 953 <&gcc GCC_BIMC_GPU_CLK>, 954 <&gcc GFX3D_CLK_SRC>; 955 power-domains = <&gcc OXILI_GDSC>; 956 operating-points-v2 = <&gpu_opp_table>; 957 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 958 }; 959 960 mdss: mdss@1a00000 { 961 compatible = "qcom,mdss"; 962 reg = <0x1a00000 0x1000>, 963 <0x1ac8000 0x3000>; 964 reg-names = "mdss_phys", "vbif_phys"; 965 966 power-domains = <&gcc MDSS_GDSC>; 967 968 clocks = <&gcc GCC_MDSS_AHB_CLK>, 969 <&gcc GCC_MDSS_AXI_CLK>, 970 <&gcc GCC_MDSS_VSYNC_CLK>; 971 clock-names = "iface", 972 "bus", 973 "vsync"; 974 975 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 976 977 interrupt-controller; 978 #interrupt-cells = <1>; 979 980 #address-cells = <1>; 981 #size-cells = <1>; 982 ranges; 983 984 mdp: mdp@1a01000 { 985 compatible = "qcom,mdp5"; 986 reg = <0x1a01000 0x89000>; 987 reg-names = "mdp_phys"; 988 989 interrupt-parent = <&mdss>; 990 interrupts = <0 0>; 991 992 clocks = <&gcc GCC_MDSS_AHB_CLK>, 993 <&gcc GCC_MDSS_AXI_CLK>, 994 <&gcc GCC_MDSS_MDP_CLK>, 995 <&gcc GCC_MDSS_VSYNC_CLK>; 996 clock-names = "iface", 997 "bus", 998 "core", 999 "vsync"; 1000 1001 iommus = <&apps_iommu 4>; 1002 1003 ports { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 1007 port@0 { 1008 reg = <0>; 1009 mdp5_intf1_out: endpoint { 1010 remote-endpoint = <&dsi0_in>; 1011 }; 1012 }; 1013 }; 1014 }; 1015 1016 dsi0: dsi@1a98000 { 1017 compatible = "qcom,mdss-dsi-ctrl"; 1018 reg = <0x1a98000 0x25c>; 1019 reg-names = "dsi_ctrl"; 1020 1021 interrupt-parent = <&mdss>; 1022 interrupts = <4 0>; 1023 1024 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1025 <&gcc PCLK0_CLK_SRC>; 1026 assigned-clock-parents = <&dsi_phy0 0>, 1027 <&dsi_phy0 1>; 1028 1029 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1030 <&gcc GCC_MDSS_AHB_CLK>, 1031 <&gcc GCC_MDSS_AXI_CLK>, 1032 <&gcc GCC_MDSS_BYTE0_CLK>, 1033 <&gcc GCC_MDSS_PCLK0_CLK>, 1034 <&gcc GCC_MDSS_ESC0_CLK>; 1035 clock-names = "mdp_core", 1036 "iface", 1037 "bus", 1038 "byte", 1039 "pixel", 1040 "core"; 1041 phys = <&dsi_phy0>; 1042 phy-names = "dsi-phy"; 1043 1044 ports { 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 1048 port@0 { 1049 reg = <0>; 1050 dsi0_in: endpoint { 1051 remote-endpoint = <&mdp5_intf1_out>; 1052 }; 1053 }; 1054 1055 port@1 { 1056 reg = <1>; 1057 dsi0_out: endpoint { 1058 }; 1059 }; 1060 }; 1061 }; 1062 1063 dsi_phy0: dsi-phy@1a98300 { 1064 compatible = "qcom,dsi-phy-28nm-lp"; 1065 reg = <0x1a98300 0xd4>, 1066 <0x1a98500 0x280>, 1067 <0x1a98780 0x30>; 1068 reg-names = "dsi_pll", 1069 "dsi_phy", 1070 "dsi_phy_regulator"; 1071 1072 #clock-cells = <1>; 1073 #phy-cells = <0>; 1074 1075 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1076 <&xo_board>; 1077 clock-names = "iface", "ref"; 1078 }; 1079 }; 1080 1081 1082 hexagon@4080000 { 1083 compatible = "qcom,q6v5-pil"; 1084 reg = <0x04080000 0x100>, 1085 <0x04020000 0x040>; 1086 1087 reg-names = "qdsp6", "rmb"; 1088 1089 interrupts-extended = <&intc 0 24 1>, 1090 <&hexagon_smp2p_in 0 0>, 1091 <&hexagon_smp2p_in 1 0>, 1092 <&hexagon_smp2p_in 2 0>, 1093 <&hexagon_smp2p_in 3 0>; 1094 interrupt-names = "wdog", "fatal", "ready", 1095 "handover", "stop-ack"; 1096 1097 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1098 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1099 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1100 <&xo_board>; 1101 clock-names = "iface", "bus", "mem", "xo"; 1102 1103 qcom,smem-states = <&hexagon_smp2p_out 0>; 1104 qcom,smem-state-names = "stop"; 1105 1106 resets = <&scm 0>; 1107 reset-names = "mss_restart"; 1108 1109 cx-supply = <&pm8916_s1>; 1110 mx-supply = <&pm8916_l3>; 1111 pll-supply = <&pm8916_l7>; 1112 1113 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1114 1115 status = "disabled"; 1116 1117 mba { 1118 memory-region = <&mba_mem>; 1119 }; 1120 1121 mpss { 1122 memory-region = <&mpss_mem>; 1123 }; 1124 1125 smd-edge { 1126 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1127 1128 qcom,smd-edge = <0>; 1129 qcom,ipc = <&apcs 8 12>; 1130 qcom,remote-pid = <1>; 1131 1132 label = "hexagon"; 1133 1134 fastrpc { 1135 compatible = "qcom,fastrpc"; 1136 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1137 label = "adsp"; 1138 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 cb@1{ 1143 compatible = "qcom,fastrpc-compute-cb"; 1144 reg = <1>; 1145 }; 1146 }; 1147 }; 1148 }; 1149 1150 pronto: wcnss@a21b000 { 1151 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1152 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1153 reg-names = "ccu", "dxe", "pmu"; 1154 1155 memory-region = <&wcnss_mem>; 1156 1157 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, 1158 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1159 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1160 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1161 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1162 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1163 1164 vddmx-supply = <&pm8916_l3>; 1165 vddpx-supply = <&pm8916_l7>; 1166 1167 qcom,state = <&wcnss_smp2p_out 0>; 1168 qcom,state-names = "stop"; 1169 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&wcnss_pin_a>; 1172 1173 status = "disabled"; 1174 1175 iris { 1176 compatible = "qcom,wcn3620"; 1177 1178 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1179 clock-names = "xo"; 1180 1181 vddxo-supply = <&pm8916_l7>; 1182 vddrfa-supply = <&pm8916_s3>; 1183 vddpa-supply = <&pm8916_l9>; 1184 vdddig-supply = <&pm8916_l5>; 1185 }; 1186 1187 smd-edge { 1188 interrupts = <0 142 1>; 1189 1190 qcom,ipc = <&apcs 8 17>; 1191 qcom,smd-edge = <6>; 1192 qcom,remote-pid = <4>; 1193 1194 label = "pronto"; 1195 1196 wcnss { 1197 compatible = "qcom,wcnss"; 1198 qcom,smd-channels = "WCNSS_CTRL"; 1199 1200 qcom,mmio = <&pronto>; 1201 1202 bt { 1203 compatible = "qcom,wcnss-bt"; 1204 }; 1205 1206 wifi { 1207 compatible = "qcom,wcnss-wlan"; 1208 1209 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, 1210 <0 146 IRQ_TYPE_LEVEL_HIGH>; 1211 interrupt-names = "tx", "rx"; 1212 1213 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1214 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1215 }; 1216 }; 1217 }; 1218 }; 1219 1220 tpiu@820000 { 1221 compatible = "arm,coresight-tpiu", "arm,primecell"; 1222 reg = <0x820000 0x1000>; 1223 1224 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1225 clock-names = "apb_pclk", "atclk"; 1226 1227 in-ports { 1228 port { 1229 tpiu_in: endpoint { 1230 remote-endpoint = <&replicator_out1>; 1231 }; 1232 }; 1233 }; 1234 }; 1235 1236 funnel@821000 { 1237 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1238 reg = <0x821000 0x1000>; 1239 1240 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1241 clock-names = "apb_pclk", "atclk"; 1242 1243 in-ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 /* 1248 * Not described input ports: 1249 * 0 - connected to Resource and Power Manger CPU ETM 1250 * 1 - not-connected 1251 * 2 - connected to Modem CPU ETM 1252 * 3 - not-connected 1253 * 5 - not-connected 1254 * 6 - connected trought funnel to Wireless CPU ETM 1255 * 7 - connected to STM component 1256 */ 1257 1258 port@4 { 1259 reg = <4>; 1260 funnel0_in4: endpoint { 1261 remote-endpoint = <&funnel1_out>; 1262 }; 1263 }; 1264 }; 1265 1266 out-ports { 1267 port { 1268 funnel0_out: endpoint { 1269 remote-endpoint = <&etf_in>; 1270 }; 1271 }; 1272 }; 1273 }; 1274 1275 replicator@824000 { 1276 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1277 reg = <0x824000 0x1000>; 1278 1279 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1280 clock-names = "apb_pclk", "atclk"; 1281 1282 out-ports { 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 1286 port@0 { 1287 reg = <0>; 1288 replicator_out0: endpoint { 1289 remote-endpoint = <&etr_in>; 1290 }; 1291 }; 1292 port@1 { 1293 reg = <1>; 1294 replicator_out1: endpoint { 1295 remote-endpoint = <&tpiu_in>; 1296 }; 1297 }; 1298 }; 1299 1300 in-ports { 1301 port { 1302 replicator_in: endpoint { 1303 remote-endpoint = <&etf_out>; 1304 }; 1305 }; 1306 }; 1307 }; 1308 1309 etf@825000 { 1310 compatible = "arm,coresight-tmc", "arm,primecell"; 1311 reg = <0x825000 0x1000>; 1312 1313 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1314 clock-names = "apb_pclk", "atclk"; 1315 1316 in-ports { 1317 port { 1318 etf_in: endpoint { 1319 remote-endpoint = <&funnel0_out>; 1320 }; 1321 }; 1322 }; 1323 1324 out-ports { 1325 port { 1326 etf_out: endpoint { 1327 remote-endpoint = <&replicator_in>; 1328 }; 1329 }; 1330 }; 1331 }; 1332 1333 etr@826000 { 1334 compatible = "arm,coresight-tmc", "arm,primecell"; 1335 reg = <0x826000 0x1000>; 1336 1337 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1338 clock-names = "apb_pclk", "atclk"; 1339 1340 in-ports { 1341 port { 1342 etr_in: endpoint { 1343 remote-endpoint = <&replicator_out0>; 1344 }; 1345 }; 1346 }; 1347 }; 1348 1349 funnel@841000 { /* APSS funnel only 4 inputs are used */ 1350 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1351 reg = <0x841000 0x1000>; 1352 1353 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1354 clock-names = "apb_pclk", "atclk"; 1355 1356 in-ports { 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 1360 port@0 { 1361 reg = <0>; 1362 funnel1_in0: endpoint { 1363 remote-endpoint = <&etm0_out>; 1364 }; 1365 }; 1366 port@1 { 1367 reg = <1>; 1368 funnel1_in1: endpoint { 1369 remote-endpoint = <&etm1_out>; 1370 }; 1371 }; 1372 port@2 { 1373 reg = <2>; 1374 funnel1_in2: endpoint { 1375 remote-endpoint = <&etm2_out>; 1376 }; 1377 }; 1378 port@3 { 1379 reg = <3>; 1380 funnel1_in3: endpoint { 1381 remote-endpoint = <&etm3_out>; 1382 }; 1383 }; 1384 }; 1385 1386 out-ports { 1387 port { 1388 funnel1_out: endpoint { 1389 remote-endpoint = <&funnel0_in4>; 1390 }; 1391 }; 1392 }; 1393 }; 1394 1395 debug@850000 { 1396 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1397 reg = <0x850000 0x1000>; 1398 clocks = <&rpmcc RPM_QDSS_CLK>; 1399 clock-names = "apb_pclk"; 1400 cpu = <&CPU0>; 1401 }; 1402 1403 debug@852000 { 1404 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1405 reg = <0x852000 0x1000>; 1406 clocks = <&rpmcc RPM_QDSS_CLK>; 1407 clock-names = "apb_pclk"; 1408 cpu = <&CPU1>; 1409 }; 1410 1411 debug@854000 { 1412 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1413 reg = <0x854000 0x1000>; 1414 clocks = <&rpmcc RPM_QDSS_CLK>; 1415 clock-names = "apb_pclk"; 1416 cpu = <&CPU2>; 1417 }; 1418 1419 debug@856000 { 1420 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1421 reg = <0x856000 0x1000>; 1422 clocks = <&rpmcc RPM_QDSS_CLK>; 1423 clock-names = "apb_pclk"; 1424 cpu = <&CPU3>; 1425 }; 1426 1427 etm@85c000 { 1428 compatible = "arm,coresight-etm4x", "arm,primecell"; 1429 reg = <0x85c000 0x1000>; 1430 1431 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1432 clock-names = "apb_pclk", "atclk"; 1433 arm,coresight-loses-context-with-cpu; 1434 1435 cpu = <&CPU0>; 1436 1437 out-ports { 1438 port { 1439 etm0_out: endpoint { 1440 remote-endpoint = <&funnel1_in0>; 1441 }; 1442 }; 1443 }; 1444 }; 1445 1446 etm@85d000 { 1447 compatible = "arm,coresight-etm4x", "arm,primecell"; 1448 reg = <0x85d000 0x1000>; 1449 1450 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1451 clock-names = "apb_pclk", "atclk"; 1452 arm,coresight-loses-context-with-cpu; 1453 1454 cpu = <&CPU1>; 1455 1456 out-ports { 1457 port { 1458 etm1_out: endpoint { 1459 remote-endpoint = <&funnel1_in1>; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 etm@85e000 { 1466 compatible = "arm,coresight-etm4x", "arm,primecell"; 1467 reg = <0x85e000 0x1000>; 1468 1469 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1470 clock-names = "apb_pclk", "atclk"; 1471 arm,coresight-loses-context-with-cpu; 1472 1473 cpu = <&CPU2>; 1474 1475 out-ports { 1476 port { 1477 etm2_out: endpoint { 1478 remote-endpoint = <&funnel1_in2>; 1479 }; 1480 }; 1481 }; 1482 }; 1483 1484 etm@85f000 { 1485 compatible = "arm,coresight-etm4x", "arm,primecell"; 1486 reg = <0x85f000 0x1000>; 1487 1488 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1489 clock-names = "apb_pclk", "atclk"; 1490 arm,coresight-loses-context-with-cpu; 1491 1492 cpu = <&CPU3>; 1493 1494 out-ports { 1495 port { 1496 etm3_out: endpoint { 1497 remote-endpoint = <&funnel1_in3>; 1498 }; 1499 }; 1500 }; 1501 }; 1502 1503 venus: video-codec@1d00000 { 1504 compatible = "qcom,msm8916-venus"; 1505 reg = <0x01d00000 0xff000>; 1506 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1507 power-domains = <&gcc VENUS_GDSC>; 1508 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1509 <&gcc GCC_VENUS0_AHB_CLK>, 1510 <&gcc GCC_VENUS0_AXI_CLK>; 1511 clock-names = "core", "iface", "bus"; 1512 iommus = <&apps_iommu 5>; 1513 memory-region = <&venus_mem>; 1514 status = "okay"; 1515 1516 video-decoder { 1517 compatible = "venus-decoder"; 1518 }; 1519 1520 video-encoder { 1521 compatible = "venus-encoder"; 1522 }; 1523 }; 1524 1525 camss: camss@1b00000 { 1526 compatible = "qcom,msm8916-camss"; 1527 reg = <0x1b0ac00 0x200>, 1528 <0x1b00030 0x4>, 1529 <0x1b0b000 0x200>, 1530 <0x1b00038 0x4>, 1531 <0x1b08000 0x100>, 1532 <0x1b08400 0x100>, 1533 <0x1b0a000 0x500>, 1534 <0x1b00020 0x10>, 1535 <0x1b10000 0x1000>; 1536 reg-names = "csiphy0", 1537 "csiphy0_clk_mux", 1538 "csiphy1", 1539 "csiphy1_clk_mux", 1540 "csid0", 1541 "csid1", 1542 "ispif", 1543 "csi_clk_mux", 1544 "vfe0"; 1545 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1546 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1547 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1548 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1549 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1550 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1551 interrupt-names = "csiphy0", 1552 "csiphy1", 1553 "csid0", 1554 "csid1", 1555 "ispif", 1556 "vfe0"; 1557 power-domains = <&gcc VFE_GDSC>; 1558 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1559 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1560 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1561 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1562 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1563 <&gcc GCC_CAMSS_CSI0_CLK>, 1564 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1565 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1566 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1567 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1568 <&gcc GCC_CAMSS_CSI1_CLK>, 1569 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1570 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1571 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1572 <&gcc GCC_CAMSS_AHB_CLK>, 1573 <&gcc GCC_CAMSS_VFE0_CLK>, 1574 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1575 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1576 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1577 clock-names = "top_ahb", 1578 "ispif_ahb", 1579 "csiphy0_timer", 1580 "csiphy1_timer", 1581 "csi0_ahb", 1582 "csi0", 1583 "csi0_phy", 1584 "csi0_pix", 1585 "csi0_rdi", 1586 "csi1_ahb", 1587 "csi1", 1588 "csi1_phy", 1589 "csi1_pix", 1590 "csi1_rdi", 1591 "ahb", 1592 "vfe0", 1593 "csi_vfe0", 1594 "vfe_ahb", 1595 "vfe_axi"; 1596 vdda-supply = <&pm8916_l2>; 1597 iommus = <&apps_iommu 3>; 1598 status = "disabled"; 1599 ports { 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 }; 1603 }; 1604 }; 1605 1606 smd { 1607 compatible = "qcom,smd"; 1608 1609 rpm { 1610 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1611 qcom,ipc = <&apcs 8 0>; 1612 qcom,smd-edge = <15>; 1613 1614 rpm_requests { 1615 compatible = "qcom,rpm-msm8916"; 1616 qcom,smd-channels = "rpm_requests"; 1617 1618 rpmcc: qcom,rpmcc { 1619 compatible = "qcom,rpmcc-msm8916"; 1620 #clock-cells = <1>; 1621 }; 1622 1623 smd_rpm_regulators: pm8916-regulators { 1624 compatible = "qcom,rpm-pm8916-regulators"; 1625 1626 pm8916_s1: s1 {}; 1627 pm8916_s3: s3 {}; 1628 pm8916_s4: s4 {}; 1629 1630 pm8916_l1: l1 {}; 1631 pm8916_l2: l2 {}; 1632 pm8916_l3: l3 {}; 1633 pm8916_l4: l4 {}; 1634 pm8916_l5: l5 {}; 1635 pm8916_l6: l6 {}; 1636 pm8916_l7: l7 {}; 1637 pm8916_l8: l8 {}; 1638 pm8916_l9: l9 {}; 1639 pm8916_l10: l10 {}; 1640 pm8916_l11: l11 {}; 1641 pm8916_l12: l12 {}; 1642 pm8916_l13: l13 {}; 1643 pm8916_l14: l14 {}; 1644 pm8916_l15: l15 {}; 1645 pm8916_l16: l16 {}; 1646 pm8916_l17: l17 {}; 1647 pm8916_l18: l18 {}; 1648 }; 1649 }; 1650 }; 1651 }; 1652 1653 hexagon-smp2p { 1654 compatible = "qcom,smp2p"; 1655 qcom,smem = <435>, <428>; 1656 1657 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 1658 1659 qcom,ipc = <&apcs 8 14>; 1660 1661 qcom,local-pid = <0>; 1662 qcom,remote-pid = <1>; 1663 1664 hexagon_smp2p_out: master-kernel { 1665 qcom,entry-name = "master-kernel"; 1666 1667 #qcom,smem-state-cells = <1>; 1668 }; 1669 1670 hexagon_smp2p_in: slave-kernel { 1671 qcom,entry-name = "slave-kernel"; 1672 1673 interrupt-controller; 1674 #interrupt-cells = <2>; 1675 }; 1676 }; 1677 1678 wcnss-smp2p { 1679 compatible = "qcom,smp2p"; 1680 qcom,smem = <451>, <431>; 1681 1682 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 1683 1684 qcom,ipc = <&apcs 8 18>; 1685 1686 qcom,local-pid = <0>; 1687 qcom,remote-pid = <4>; 1688 1689 wcnss_smp2p_out: master-kernel { 1690 qcom,entry-name = "master-kernel"; 1691 1692 #qcom,smem-state-cells = <1>; 1693 }; 1694 1695 wcnss_smp2p_in: slave-kernel { 1696 qcom,entry-name = "slave-kernel"; 1697 1698 interrupt-controller; 1699 #interrupt-cells = <2>; 1700 }; 1701 }; 1702 1703 smsm { 1704 compatible = "qcom,smsm"; 1705 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 1709 qcom,ipc-1 = <&apcs 8 13>; 1710 qcom,ipc-3 = <&apcs 8 19>; 1711 1712 apps_smsm: apps@0 { 1713 reg = <0>; 1714 1715 #qcom,smem-state-cells = <1>; 1716 }; 1717 1718 hexagon_smsm: hexagon@1 { 1719 reg = <1>; 1720 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 1721 1722 interrupt-controller; 1723 #interrupt-cells = <2>; 1724 }; 1725 1726 wcnss_smsm: wcnss@6 { 1727 reg = <6>; 1728 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 1729 1730 interrupt-controller; 1731 #interrupt-cells = <2>; 1732 }; 1733 }; 1734}; 1735 1736#include "msm8916-pins.dtsi" 1737