1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* We expect the bootloader to fill in the reg */ 26 reg = <0 0x80000000 0 0>; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 tz-apps@86000000 { 35 reg = <0x0 0x86000000 0x0 0x300000>; 36 no-map; 37 }; 38 39 smem@86300000 { 40 compatible = "qcom,smem"; 41 reg = <0x0 0x86300000 0x0 0x100000>; 42 no-map; 43 44 hwlocks = <&tcsr_mutex 3>; 45 qcom,rpm-msg-ram = <&rpm_msg_ram>; 46 }; 47 48 hypervisor@86400000 { 49 reg = <0x0 0x86400000 0x0 0x100000>; 50 no-map; 51 }; 52 53 tz@86500000 { 54 reg = <0x0 0x86500000 0x0 0x180000>; 55 no-map; 56 }; 57 58 reserved@86680000 { 59 reg = <0x0 0x86680000 0x0 0x80000>; 60 no-map; 61 }; 62 63 rmtfs@86700000 { 64 compatible = "qcom,rmtfs-mem"; 65 reg = <0x0 0x86700000 0x0 0xe0000>; 66 no-map; 67 68 qcom,client-id = <1>; 69 }; 70 71 rfsa@867e0000 { 72 reg = <0x0 0x867e0000 0x0 0x20000>; 73 no-map; 74 }; 75 76 mpss_mem: mpss@86800000 { 77 reg = <0x0 0x86800000 0x0 0x2b00000>; 78 no-map; 79 }; 80 81 wcnss_mem: wcnss@89300000 { 82 reg = <0x0 0x89300000 0x0 0x600000>; 83 no-map; 84 }; 85 86 venus_mem: venus@89900000 { 87 reg = <0x0 0x89900000 0x0 0x600000>; 88 no-map; 89 }; 90 91 mba_mem: mba@8ea00000 { 92 no-map; 93 reg = <0 0x8ea00000 0 0x100000>; 94 }; 95 }; 96 97 clocks { 98 xo_board: xo-board { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <19200000>; 102 }; 103 104 sleep_clk: sleep-clk { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 }; 109 }; 110 111 cpus { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 115 CPU0: cpu@0 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x0>; 119 next-level-cache = <&L2_0>; 120 enable-method = "psci"; 121 clocks = <&apcs>; 122 operating-points-v2 = <&cpu_opp_table>; 123 #cooling-cells = <2>; 124 power-domains = <&CPU_PD0>; 125 power-domain-names = "psci"; 126 qcom,acc = <&cpu0_acc>; 127 qcom,saw = <&cpu0_saw>; 128 }; 129 130 CPU1: cpu@1 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 reg = <0x1>; 134 next-level-cache = <&L2_0>; 135 enable-method = "psci"; 136 clocks = <&apcs>; 137 operating-points-v2 = <&cpu_opp_table>; 138 #cooling-cells = <2>; 139 power-domains = <&CPU_PD1>; 140 power-domain-names = "psci"; 141 qcom,acc = <&cpu1_acc>; 142 qcom,saw = <&cpu1_saw>; 143 }; 144 145 CPU2: cpu@2 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a53"; 148 reg = <0x2>; 149 next-level-cache = <&L2_0>; 150 enable-method = "psci"; 151 clocks = <&apcs>; 152 operating-points-v2 = <&cpu_opp_table>; 153 #cooling-cells = <2>; 154 power-domains = <&CPU_PD2>; 155 power-domain-names = "psci"; 156 qcom,acc = <&cpu2_acc>; 157 qcom,saw = <&cpu2_saw>; 158 }; 159 160 CPU3: cpu@3 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a53"; 163 reg = <0x3>; 164 next-level-cache = <&L2_0>; 165 enable-method = "psci"; 166 clocks = <&apcs>; 167 operating-points-v2 = <&cpu_opp_table>; 168 #cooling-cells = <2>; 169 power-domains = <&CPU_PD3>; 170 power-domain-names = "psci"; 171 qcom,acc = <&cpu3_acc>; 172 qcom,saw = <&cpu3_saw>; 173 }; 174 175 L2_0: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 }; 179 180 idle-states { 181 entry-method = "psci"; 182 183 CPU_SLEEP_0: cpu-sleep-0 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "standalone-power-collapse"; 186 arm,psci-suspend-param = <0x40000002>; 187 entry-latency-us = <130>; 188 exit-latency-us = <150>; 189 min-residency-us = <2000>; 190 local-timer-stop; 191 }; 192 }; 193 194 domain-idle-states { 195 196 CLUSTER_RET: cluster-retention { 197 compatible = "domain-idle-state"; 198 arm,psci-suspend-param = <0x41000012>; 199 entry-latency-us = <500>; 200 exit-latency-us = <500>; 201 min-residency-us = <2000>; 202 }; 203 204 CLUSTER_PWRDN: cluster-gdhs { 205 compatible = "domain-idle-state"; 206 arm,psci-suspend-param = <0x41000032>; 207 entry-latency-us = <2000>; 208 exit-latency-us = <2000>; 209 min-residency-us = <6000>; 210 }; 211 }; 212 }; 213 214 cpu_opp_table: opp-table-cpu { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-200000000 { 219 opp-hz = /bits/ 64 <200000000>; 220 }; 221 opp-400000000 { 222 opp-hz = /bits/ 64 <400000000>; 223 }; 224 opp-800000000 { 225 opp-hz = /bits/ 64 <800000000>; 226 }; 227 opp-998400000 { 228 opp-hz = /bits/ 64 <998400000>; 229 }; 230 }; 231 232 firmware { 233 scm: scm { 234 compatible = "qcom,scm-msm8916", "qcom,scm"; 235 clocks = <&gcc GCC_CRYPTO_CLK>, 236 <&gcc GCC_CRYPTO_AXI_CLK>, 237 <&gcc GCC_CRYPTO_AHB_CLK>; 238 clock-names = "core", "bus", "iface"; 239 #reset-cells = <1>; 240 241 qcom,dload-mode = <&tcsr 0x6100>; 242 }; 243 }; 244 245 pmu { 246 compatible = "arm,cortex-a53-pmu"; 247 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 248 }; 249 250 psci { 251 compatible = "arm,psci-1.0"; 252 method = "smc"; 253 254 CPU_PD0: power-domain-cpu0 { 255 #power-domain-cells = <0>; 256 power-domains = <&CLUSTER_PD>; 257 domain-idle-states = <&CPU_SLEEP_0>; 258 }; 259 260 CPU_PD1: power-domain-cpu1 { 261 #power-domain-cells = <0>; 262 power-domains = <&CLUSTER_PD>; 263 domain-idle-states = <&CPU_SLEEP_0>; 264 }; 265 266 CPU_PD2: power-domain-cpu2 { 267 #power-domain-cells = <0>; 268 power-domains = <&CLUSTER_PD>; 269 domain-idle-states = <&CPU_SLEEP_0>; 270 }; 271 272 CPU_PD3: power-domain-cpu3 { 273 #power-domain-cells = <0>; 274 power-domains = <&CLUSTER_PD>; 275 domain-idle-states = <&CPU_SLEEP_0>; 276 }; 277 278 CLUSTER_PD: power-domain-cluster { 279 #power-domain-cells = <0>; 280 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 281 }; 282 }; 283 284 smd { 285 compatible = "qcom,smd"; 286 287 rpm { 288 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 289 qcom,ipc = <&apcs 8 0>; 290 qcom,smd-edge = <15>; 291 292 rpm_requests: rpm-requests { 293 compatible = "qcom,rpm-msm8916"; 294 qcom,smd-channels = "rpm_requests"; 295 296 rpmcc: clock-controller { 297 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 298 #clock-cells = <1>; 299 clocks = <&xo_board>; 300 clock-names = "xo"; 301 }; 302 303 rpmpd: power-controller { 304 compatible = "qcom,msm8916-rpmpd"; 305 #power-domain-cells = <1>; 306 operating-points-v2 = <&rpmpd_opp_table>; 307 308 rpmpd_opp_table: opp-table { 309 compatible = "operating-points-v2"; 310 311 rpmpd_opp_ret: opp1 { 312 opp-level = <1>; 313 }; 314 rpmpd_opp_svs_krait: opp2 { 315 opp-level = <2>; 316 }; 317 rpmpd_opp_svs_soc: opp3 { 318 opp-level = <3>; 319 }; 320 rpmpd_opp_nom: opp4 { 321 opp-level = <4>; 322 }; 323 rpmpd_opp_turbo: opp5 { 324 opp-level = <5>; 325 }; 326 rpmpd_opp_super_turbo: opp6 { 327 opp-level = <6>; 328 }; 329 }; 330 }; 331 }; 332 }; 333 }; 334 335 smp2p-hexagon { 336 compatible = "qcom,smp2p"; 337 qcom,smem = <435>, <428>; 338 339 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 340 341 qcom,ipc = <&apcs 8 14>; 342 343 qcom,local-pid = <0>; 344 qcom,remote-pid = <1>; 345 346 hexagon_smp2p_out: master-kernel { 347 qcom,entry-name = "master-kernel"; 348 349 #qcom,smem-state-cells = <1>; 350 }; 351 352 hexagon_smp2p_in: slave-kernel { 353 qcom,entry-name = "slave-kernel"; 354 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 }; 358 }; 359 360 smp2p-wcnss { 361 compatible = "qcom,smp2p"; 362 qcom,smem = <451>, <431>; 363 364 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 365 366 qcom,ipc = <&apcs 8 18>; 367 368 qcom,local-pid = <0>; 369 qcom,remote-pid = <4>; 370 371 wcnss_smp2p_out: master-kernel { 372 qcom,entry-name = "master-kernel"; 373 374 #qcom,smem-state-cells = <1>; 375 }; 376 377 wcnss_smp2p_in: slave-kernel { 378 qcom,entry-name = "slave-kernel"; 379 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 }; 384 385 smsm { 386 compatible = "qcom,smsm"; 387 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 qcom,ipc-1 = <&apcs 8 13>; 392 qcom,ipc-3 = <&apcs 8 19>; 393 394 apps_smsm: apps@0 { 395 reg = <0>; 396 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 hexagon_smsm: hexagon@1 { 401 reg = <1>; 402 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 403 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 408 wcnss_smsm: wcnss@6 { 409 reg = <6>; 410 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 411 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 }; 416 417 soc: soc@0 { 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0 0 0 0xffffffff>; 421 compatible = "simple-bus"; 422 423 rng@22000 { 424 compatible = "qcom,prng"; 425 reg = <0x00022000 0x200>; 426 clocks = <&gcc GCC_PRNG_AHB_CLK>; 427 clock-names = "core"; 428 }; 429 430 restart@4ab000 { 431 compatible = "qcom,pshold"; 432 reg = <0x004ab000 0x4>; 433 }; 434 435 qfprom: qfprom@5c000 { 436 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 437 reg = <0x0005c000 0x1000>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 441 tsens_base1: base1@d0 { 442 reg = <0xd0 0x1>; 443 bits = <0 7>; 444 }; 445 446 tsens_s0_p1: s0-p1@d0 { 447 reg = <0xd0 0x2>; 448 bits = <7 5>; 449 }; 450 451 tsens_s0_p2: s0-p2@d1 { 452 reg = <0xd1 0x2>; 453 bits = <4 5>; 454 }; 455 456 tsens_s1_p1: s1-p1@d2 { 457 reg = <0xd2 0x1>; 458 bits = <1 5>; 459 }; 460 tsens_s1_p2: s1-p2@d2 { 461 reg = <0xd2 0x2>; 462 bits = <6 5>; 463 }; 464 tsens_s2_p1: s2-p1@d3 { 465 reg = <0xd3 0x1>; 466 bits = <3 5>; 467 }; 468 469 tsens_s2_p2: s2-p2@d4 { 470 reg = <0xd4 0x1>; 471 bits = <0 5>; 472 }; 473 474 // no tsens with hw_id 3 475 476 tsens_s4_p1: s4-p1@d4 { 477 reg = <0xd4 0x2>; 478 bits = <5 5>; 479 }; 480 481 tsens_s4_p2: s4-p2@d5 { 482 reg = <0xd5 0x1>; 483 bits = <2 5>; 484 }; 485 486 tsens_s5_p1: s5-p1@d5 { 487 reg = <0xd5 0x2>; 488 bits = <7 5>; 489 }; 490 491 tsens_s5_p2: s5-p2@d6 { 492 reg = <0xd6 0x2>; 493 bits = <4 5>; 494 }; 495 496 tsens_base2: base2@d7 { 497 reg = <0xd7 0x1>; 498 bits = <1 7>; 499 }; 500 501 tsens_mode: mode@ef { 502 reg = <0xef 0x1>; 503 bits = <5 3>; 504 }; 505 }; 506 507 rpm_msg_ram: sram@60000 { 508 compatible = "qcom,rpm-msg-ram"; 509 reg = <0x00060000 0x8000>; 510 }; 511 512 sram@290000 { 513 compatible = "qcom,msm8916-rpm-stats"; 514 reg = <0x00290000 0x10000>; 515 }; 516 517 bimc: interconnect@400000 { 518 compatible = "qcom,msm8916-bimc"; 519 reg = <0x00400000 0x62000>; 520 #interconnect-cells = <1>; 521 clock-names = "bus", "bus_a"; 522 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 523 <&rpmcc RPM_SMD_BIMC_A_CLK>; 524 }; 525 526 tsens: thermal-sensor@4a9000 { 527 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 528 reg = <0x004a9000 0x1000>, /* TM */ 529 <0x004a8000 0x1000>; /* SROT */ 530 531 // no hw_id 3 532 nvmem-cells = <&tsens_mode>, 533 <&tsens_base1>, <&tsens_base2>, 534 <&tsens_s0_p1>, <&tsens_s0_p2>, 535 <&tsens_s1_p1>, <&tsens_s1_p2>, 536 <&tsens_s2_p1>, <&tsens_s2_p2>, 537 <&tsens_s4_p1>, <&tsens_s4_p2>, 538 <&tsens_s5_p1>, <&tsens_s5_p2>; 539 nvmem-cell-names = "mode", 540 "base1", "base2", 541 "s0_p1", "s0_p2", 542 "s1_p1", "s1_p2", 543 "s2_p1", "s2_p2", 544 "s4_p1", "s4_p2", 545 "s5_p1", "s5_p2"; 546 #qcom,sensors = <5>; 547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "uplow"; 549 #thermal-sensor-cells = <1>; 550 }; 551 552 pcnoc: interconnect@500000 { 553 compatible = "qcom,msm8916-pcnoc"; 554 reg = <0x00500000 0x11000>; 555 #interconnect-cells = <1>; 556 clock-names = "bus", "bus_a"; 557 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 558 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 559 }; 560 561 snoc: interconnect@580000 { 562 compatible = "qcom,msm8916-snoc"; 563 reg = <0x00580000 0x14000>; 564 #interconnect-cells = <1>; 565 clock-names = "bus", "bus_a"; 566 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 567 <&rpmcc RPM_SMD_SNOC_A_CLK>; 568 }; 569 570 stm: stm@802000 { 571 compatible = "arm,coresight-stm", "arm,primecell"; 572 reg = <0x00802000 0x1000>, 573 <0x09280000 0x180000>; 574 reg-names = "stm-base", "stm-stimulus-base"; 575 576 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 577 clock-names = "apb_pclk", "atclk"; 578 579 status = "disabled"; 580 581 out-ports { 582 port { 583 stm_out: endpoint { 584 remote-endpoint = <&funnel0_in7>; 585 }; 586 }; 587 }; 588 }; 589 590 /* System CTIs */ 591 /* CTI 0 - TMC connections */ 592 cti0: cti@810000 { 593 compatible = "arm,coresight-cti", "arm,primecell"; 594 reg = <0x00810000 0x1000>; 595 596 clocks = <&rpmcc RPM_QDSS_CLK>; 597 clock-names = "apb_pclk"; 598 599 status = "disabled"; 600 }; 601 602 /* CTI 1 - TPIU connections */ 603 cti1: cti@811000 { 604 compatible = "arm,coresight-cti", "arm,primecell"; 605 reg = <0x00811000 0x1000>; 606 607 clocks = <&rpmcc RPM_QDSS_CLK>; 608 clock-names = "apb_pclk"; 609 610 status = "disabled"; 611 }; 612 613 /* CTIs 2-11 - no information - not instantiated */ 614 615 tpiu: tpiu@820000 { 616 compatible = "arm,coresight-tpiu", "arm,primecell"; 617 reg = <0x00820000 0x1000>; 618 619 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 620 clock-names = "apb_pclk", "atclk"; 621 622 status = "disabled"; 623 624 in-ports { 625 port { 626 tpiu_in: endpoint { 627 remote-endpoint = <&replicator_out1>; 628 }; 629 }; 630 }; 631 }; 632 633 funnel0: funnel@821000 { 634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 635 reg = <0x00821000 0x1000>; 636 637 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 638 clock-names = "apb_pclk", "atclk"; 639 640 status = "disabled"; 641 642 in-ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 /* 647 * Not described input ports: 648 * 0 - connected to Resource and Power Manger CPU ETM 649 * 1 - not-connected 650 * 2 - connected to Modem CPU ETM 651 * 3 - not-connected 652 * 5 - not-connected 653 * 6 - connected trought funnel to Wireless CPU ETM 654 * 7 - connected to STM component 655 */ 656 657 port@4 { 658 reg = <4>; 659 funnel0_in4: endpoint { 660 remote-endpoint = <&funnel1_out>; 661 }; 662 }; 663 664 port@7 { 665 reg = <7>; 666 funnel0_in7: endpoint { 667 remote-endpoint = <&stm_out>; 668 }; 669 }; 670 }; 671 672 out-ports { 673 port { 674 funnel0_out: endpoint { 675 remote-endpoint = <&etf_in>; 676 }; 677 }; 678 }; 679 }; 680 681 replicator: replicator@824000 { 682 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 683 reg = <0x00824000 0x1000>; 684 685 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 686 clock-names = "apb_pclk", "atclk"; 687 688 status = "disabled"; 689 690 out-ports { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 port@0 { 695 reg = <0>; 696 replicator_out0: endpoint { 697 remote-endpoint = <&etr_in>; 698 }; 699 }; 700 port@1 { 701 reg = <1>; 702 replicator_out1: endpoint { 703 remote-endpoint = <&tpiu_in>; 704 }; 705 }; 706 }; 707 708 in-ports { 709 port { 710 replicator_in: endpoint { 711 remote-endpoint = <&etf_out>; 712 }; 713 }; 714 }; 715 }; 716 717 etf: etf@825000 { 718 compatible = "arm,coresight-tmc", "arm,primecell"; 719 reg = <0x00825000 0x1000>; 720 721 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 722 clock-names = "apb_pclk", "atclk"; 723 724 status = "disabled"; 725 726 in-ports { 727 port { 728 etf_in: endpoint { 729 remote-endpoint = <&funnel0_out>; 730 }; 731 }; 732 }; 733 734 out-ports { 735 port { 736 etf_out: endpoint { 737 remote-endpoint = <&replicator_in>; 738 }; 739 }; 740 }; 741 }; 742 743 etr: etr@826000 { 744 compatible = "arm,coresight-tmc", "arm,primecell"; 745 reg = <0x00826000 0x1000>; 746 747 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 748 clock-names = "apb_pclk", "atclk"; 749 750 status = "disabled"; 751 752 in-ports { 753 port { 754 etr_in: endpoint { 755 remote-endpoint = <&replicator_out0>; 756 }; 757 }; 758 }; 759 }; 760 761 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 762 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 763 reg = <0x00841000 0x1000>; 764 765 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 766 clock-names = "apb_pclk", "atclk"; 767 768 status = "disabled"; 769 770 in-ports { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 port@0 { 775 reg = <0>; 776 funnel1_in0: endpoint { 777 remote-endpoint = <&etm0_out>; 778 }; 779 }; 780 port@1 { 781 reg = <1>; 782 funnel1_in1: endpoint { 783 remote-endpoint = <&etm1_out>; 784 }; 785 }; 786 port@2 { 787 reg = <2>; 788 funnel1_in2: endpoint { 789 remote-endpoint = <&etm2_out>; 790 }; 791 }; 792 port@3 { 793 reg = <3>; 794 funnel1_in3: endpoint { 795 remote-endpoint = <&etm3_out>; 796 }; 797 }; 798 }; 799 800 out-ports { 801 port { 802 funnel1_out: endpoint { 803 remote-endpoint = <&funnel0_in4>; 804 }; 805 }; 806 }; 807 }; 808 809 debug0: debug@850000 { 810 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 811 reg = <0x00850000 0x1000>; 812 clocks = <&rpmcc RPM_QDSS_CLK>; 813 clock-names = "apb_pclk"; 814 cpu = <&CPU0>; 815 status = "disabled"; 816 }; 817 818 debug1: debug@852000 { 819 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 820 reg = <0x00852000 0x1000>; 821 clocks = <&rpmcc RPM_QDSS_CLK>; 822 clock-names = "apb_pclk"; 823 cpu = <&CPU1>; 824 status = "disabled"; 825 }; 826 827 debug2: debug@854000 { 828 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 829 reg = <0x00854000 0x1000>; 830 clocks = <&rpmcc RPM_QDSS_CLK>; 831 clock-names = "apb_pclk"; 832 cpu = <&CPU2>; 833 status = "disabled"; 834 }; 835 836 debug3: debug@856000 { 837 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 838 reg = <0x00856000 0x1000>; 839 clocks = <&rpmcc RPM_QDSS_CLK>; 840 clock-names = "apb_pclk"; 841 cpu = <&CPU3>; 842 status = "disabled"; 843 }; 844 845 /* Core CTIs; CTIs 12-15 */ 846 /* CTI - CPU-0 */ 847 cti12: cti@858000 { 848 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 849 "arm,primecell"; 850 reg = <0x00858000 0x1000>; 851 852 clocks = <&rpmcc RPM_QDSS_CLK>; 853 clock-names = "apb_pclk"; 854 855 cpu = <&CPU0>; 856 arm,cs-dev-assoc = <&etm0>; 857 858 status = "disabled"; 859 }; 860 861 /* CTI - CPU-1 */ 862 cti13: cti@859000 { 863 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 864 "arm,primecell"; 865 reg = <0x00859000 0x1000>; 866 867 clocks = <&rpmcc RPM_QDSS_CLK>; 868 clock-names = "apb_pclk"; 869 870 cpu = <&CPU1>; 871 arm,cs-dev-assoc = <&etm1>; 872 873 status = "disabled"; 874 }; 875 876 /* CTI - CPU-2 */ 877 cti14: cti@85a000 { 878 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 879 "arm,primecell"; 880 reg = <0x0085a000 0x1000>; 881 882 clocks = <&rpmcc RPM_QDSS_CLK>; 883 clock-names = "apb_pclk"; 884 885 cpu = <&CPU2>; 886 arm,cs-dev-assoc = <&etm2>; 887 888 status = "disabled"; 889 }; 890 891 /* CTI - CPU-3 */ 892 cti15: cti@85b000 { 893 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 894 "arm,primecell"; 895 reg = <0x0085b000 0x1000>; 896 897 clocks = <&rpmcc RPM_QDSS_CLK>; 898 clock-names = "apb_pclk"; 899 900 cpu = <&CPU3>; 901 arm,cs-dev-assoc = <&etm3>; 902 903 status = "disabled"; 904 }; 905 906 etm0: etm@85c000 { 907 compatible = "arm,coresight-etm4x", "arm,primecell"; 908 reg = <0x0085c000 0x1000>; 909 910 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 911 clock-names = "apb_pclk", "atclk"; 912 arm,coresight-loses-context-with-cpu; 913 914 cpu = <&CPU0>; 915 916 status = "disabled"; 917 918 out-ports { 919 port { 920 etm0_out: endpoint { 921 remote-endpoint = <&funnel1_in0>; 922 }; 923 }; 924 }; 925 }; 926 927 etm1: etm@85d000 { 928 compatible = "arm,coresight-etm4x", "arm,primecell"; 929 reg = <0x0085d000 0x1000>; 930 931 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 932 clock-names = "apb_pclk", "atclk"; 933 arm,coresight-loses-context-with-cpu; 934 935 cpu = <&CPU1>; 936 937 status = "disabled"; 938 939 out-ports { 940 port { 941 etm1_out: endpoint { 942 remote-endpoint = <&funnel1_in1>; 943 }; 944 }; 945 }; 946 }; 947 948 etm2: etm@85e000 { 949 compatible = "arm,coresight-etm4x", "arm,primecell"; 950 reg = <0x0085e000 0x1000>; 951 952 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 953 clock-names = "apb_pclk", "atclk"; 954 arm,coresight-loses-context-with-cpu; 955 956 cpu = <&CPU2>; 957 958 status = "disabled"; 959 960 out-ports { 961 port { 962 etm2_out: endpoint { 963 remote-endpoint = <&funnel1_in2>; 964 }; 965 }; 966 }; 967 }; 968 969 etm3: etm@85f000 { 970 compatible = "arm,coresight-etm4x", "arm,primecell"; 971 reg = <0x0085f000 0x1000>; 972 973 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 974 clock-names = "apb_pclk", "atclk"; 975 arm,coresight-loses-context-with-cpu; 976 977 cpu = <&CPU3>; 978 979 status = "disabled"; 980 981 out-ports { 982 port { 983 etm3_out: endpoint { 984 remote-endpoint = <&funnel1_in3>; 985 }; 986 }; 987 }; 988 }; 989 990 tlmm: pinctrl@1000000 { 991 compatible = "qcom,msm8916-pinctrl"; 992 reg = <0x01000000 0x300000>; 993 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 994 gpio-controller; 995 gpio-ranges = <&tlmm 0 0 122>; 996 #gpio-cells = <2>; 997 interrupt-controller; 998 #interrupt-cells = <2>; 999 }; 1000 1001 gcc: clock-controller@1800000 { 1002 compatible = "qcom,gcc-msm8916"; 1003 #clock-cells = <1>; 1004 #reset-cells = <1>; 1005 #power-domain-cells = <1>; 1006 reg = <0x01800000 0x80000>; 1007 clocks = <&xo_board>, 1008 <&sleep_clk>, 1009 <&mdss_dsi0_phy 1>, 1010 <&mdss_dsi0_phy 0>, 1011 <0>, 1012 <0>, 1013 <0>; 1014 clock-names = "xo", 1015 "sleep_clk", 1016 "dsi0pll", 1017 "dsi0pllbyte", 1018 "ext_mclk", 1019 "ext_pri_i2s", 1020 "ext_sec_i2s"; 1021 }; 1022 1023 tcsr_mutex: hwlock@1905000 { 1024 compatible = "qcom,tcsr-mutex"; 1025 reg = <0x01905000 0x20000>; 1026 #hwlock-cells = <1>; 1027 }; 1028 1029 tcsr: syscon@1937000 { 1030 compatible = "qcom,tcsr-msm8916", "syscon"; 1031 reg = <0x01937000 0x30000>; 1032 }; 1033 1034 mdss: display-subsystem@1a00000 { 1035 status = "disabled"; 1036 compatible = "qcom,mdss"; 1037 reg = <0x01a00000 0x1000>, 1038 <0x01ac8000 0x3000>; 1039 reg-names = "mdss_phys", "vbif_phys"; 1040 1041 power-domains = <&gcc MDSS_GDSC>; 1042 1043 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1044 <&gcc GCC_MDSS_AXI_CLK>, 1045 <&gcc GCC_MDSS_VSYNC_CLK>; 1046 clock-names = "iface", 1047 "bus", 1048 "vsync"; 1049 1050 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1051 1052 interrupt-controller; 1053 #interrupt-cells = <1>; 1054 1055 #address-cells = <1>; 1056 #size-cells = <1>; 1057 ranges; 1058 1059 mdss_mdp: display-controller@1a01000 { 1060 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1061 reg = <0x01a01000 0x89000>; 1062 reg-names = "mdp_phys"; 1063 1064 interrupt-parent = <&mdss>; 1065 interrupts = <0>; 1066 1067 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1068 <&gcc GCC_MDSS_AXI_CLK>, 1069 <&gcc GCC_MDSS_MDP_CLK>, 1070 <&gcc GCC_MDSS_VSYNC_CLK>; 1071 clock-names = "iface", 1072 "bus", 1073 "core", 1074 "vsync"; 1075 1076 iommus = <&apps_iommu 4>; 1077 1078 ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 port@0 { 1083 reg = <0>; 1084 mdss_mdp_intf1_out: endpoint { 1085 remote-endpoint = <&mdss_dsi0_in>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 mdss_dsi0: dsi@1a98000 { 1092 compatible = "qcom,msm8916-dsi-ctrl", 1093 "qcom,mdss-dsi-ctrl"; 1094 reg = <0x01a98000 0x25c>; 1095 reg-names = "dsi_ctrl"; 1096 1097 interrupt-parent = <&mdss>; 1098 interrupts = <4>; 1099 1100 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1101 <&gcc PCLK0_CLK_SRC>; 1102 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1103 <&mdss_dsi0_phy 1>; 1104 1105 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1106 <&gcc GCC_MDSS_AHB_CLK>, 1107 <&gcc GCC_MDSS_AXI_CLK>, 1108 <&gcc GCC_MDSS_BYTE0_CLK>, 1109 <&gcc GCC_MDSS_PCLK0_CLK>, 1110 <&gcc GCC_MDSS_ESC0_CLK>; 1111 clock-names = "mdp_core", 1112 "iface", 1113 "bus", 1114 "byte", 1115 "pixel", 1116 "core"; 1117 phys = <&mdss_dsi0_phy>; 1118 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 1122 ports { 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 1126 port@0 { 1127 reg = <0>; 1128 mdss_dsi0_in: endpoint { 1129 remote-endpoint = <&mdss_mdp_intf1_out>; 1130 }; 1131 }; 1132 1133 port@1 { 1134 reg = <1>; 1135 mdss_dsi0_out: endpoint { 1136 }; 1137 }; 1138 }; 1139 }; 1140 1141 mdss_dsi0_phy: phy@1a98300 { 1142 compatible = "qcom,dsi-phy-28nm-lp"; 1143 reg = <0x01a98300 0xd4>, 1144 <0x01a98500 0x280>, 1145 <0x01a98780 0x30>; 1146 reg-names = "dsi_pll", 1147 "dsi_phy", 1148 "dsi_phy_regulator"; 1149 1150 #clock-cells = <1>; 1151 #phy-cells = <0>; 1152 1153 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1154 <&xo_board>; 1155 clock-names = "iface", "ref"; 1156 }; 1157 }; 1158 1159 camss: camss@1b0ac00 { 1160 compatible = "qcom,msm8916-camss"; 1161 reg = <0x01b0ac00 0x200>, 1162 <0x01b00030 0x4>, 1163 <0x01b0b000 0x200>, 1164 <0x01b00038 0x4>, 1165 <0x01b08000 0x100>, 1166 <0x01b08400 0x100>, 1167 <0x01b0a000 0x500>, 1168 <0x01b00020 0x10>, 1169 <0x01b10000 0x1000>; 1170 reg-names = "csiphy0", 1171 "csiphy0_clk_mux", 1172 "csiphy1", 1173 "csiphy1_clk_mux", 1174 "csid0", 1175 "csid1", 1176 "ispif", 1177 "csi_clk_mux", 1178 "vfe0"; 1179 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1180 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1181 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1182 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1183 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1184 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1185 interrupt-names = "csiphy0", 1186 "csiphy1", 1187 "csid0", 1188 "csid1", 1189 "ispif", 1190 "vfe0"; 1191 power-domains = <&gcc VFE_GDSC>; 1192 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1193 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1194 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1195 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1196 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1197 <&gcc GCC_CAMSS_CSI0_CLK>, 1198 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1199 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1200 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1201 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1202 <&gcc GCC_CAMSS_CSI1_CLK>, 1203 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1204 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1205 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1206 <&gcc GCC_CAMSS_AHB_CLK>, 1207 <&gcc GCC_CAMSS_VFE0_CLK>, 1208 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1209 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1210 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1211 clock-names = "top_ahb", 1212 "ispif_ahb", 1213 "csiphy0_timer", 1214 "csiphy1_timer", 1215 "csi0_ahb", 1216 "csi0", 1217 "csi0_phy", 1218 "csi0_pix", 1219 "csi0_rdi", 1220 "csi1_ahb", 1221 "csi1", 1222 "csi1_phy", 1223 "csi1_pix", 1224 "csi1_rdi", 1225 "ahb", 1226 "vfe0", 1227 "csi_vfe0", 1228 "vfe_ahb", 1229 "vfe_axi"; 1230 iommus = <&apps_iommu 3>; 1231 status = "disabled"; 1232 ports { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 }; 1236 }; 1237 1238 cci: cci@1b0c000 { 1239 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 reg = <0x01b0c000 0x1000>; 1243 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1244 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1245 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1246 <&gcc GCC_CAMSS_CCI_CLK>, 1247 <&gcc GCC_CAMSS_AHB_CLK>; 1248 clock-names = "camss_top_ahb", "cci_ahb", 1249 "cci", "camss_ahb"; 1250 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1251 <&gcc GCC_CAMSS_CCI_CLK>; 1252 assigned-clock-rates = <80000000>, <19200000>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&cci0_default>; 1255 status = "disabled"; 1256 1257 cci_i2c0: i2c-bus@0 { 1258 reg = <0>; 1259 clock-frequency = <400000>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 }; 1263 }; 1264 1265 gpu@1c00000 { 1266 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1267 reg = <0x01c00000 0x20000>; 1268 reg-names = "kgsl_3d0_reg_memory"; 1269 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "kgsl_3d0_irq"; 1271 clock-names = 1272 "core", 1273 "iface", 1274 "mem", 1275 "mem_iface", 1276 "alt_mem_iface", 1277 "gfx3d"; 1278 clocks = 1279 <&gcc GCC_OXILI_GFX3D_CLK>, 1280 <&gcc GCC_OXILI_AHB_CLK>, 1281 <&gcc GCC_OXILI_GMEM_CLK>, 1282 <&gcc GCC_BIMC_GFX_CLK>, 1283 <&gcc GCC_BIMC_GPU_CLK>, 1284 <&gcc GFX3D_CLK_SRC>; 1285 power-domains = <&gcc OXILI_GDSC>; 1286 operating-points-v2 = <&gpu_opp_table>; 1287 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1288 1289 gpu_opp_table: opp-table { 1290 compatible = "operating-points-v2"; 1291 1292 opp-400000000 { 1293 opp-hz = /bits/ 64 <400000000>; 1294 }; 1295 opp-19200000 { 1296 opp-hz = /bits/ 64 <19200000>; 1297 }; 1298 }; 1299 }; 1300 1301 venus: video-codec@1d00000 { 1302 compatible = "qcom,msm8916-venus"; 1303 reg = <0x01d00000 0xff000>; 1304 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&gcc VENUS_GDSC>; 1306 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1307 <&gcc GCC_VENUS0_AHB_CLK>, 1308 <&gcc GCC_VENUS0_AXI_CLK>; 1309 clock-names = "core", "iface", "bus"; 1310 iommus = <&apps_iommu 5>; 1311 memory-region = <&venus_mem>; 1312 status = "okay"; 1313 1314 video-decoder { 1315 compatible = "venus-decoder"; 1316 }; 1317 1318 video-encoder { 1319 compatible = "venus-encoder"; 1320 }; 1321 }; 1322 1323 apps_iommu: iommu@1ef0000 { 1324 #address-cells = <1>; 1325 #size-cells = <1>; 1326 #iommu-cells = <1>; 1327 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1328 ranges = <0 0x01e20000 0x40000>; 1329 reg = <0x01ef0000 0x3000>; 1330 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1331 <&gcc GCC_APSS_TCU_CLK>; 1332 clock-names = "iface", "bus"; 1333 qcom,iommu-secure-id = <17>; 1334 1335 /* VFE */ 1336 iommu-ctx@3000 { 1337 compatible = "qcom,msm-iommu-v1-sec"; 1338 reg = <0x3000 0x1000>; 1339 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1340 }; 1341 1342 /* MDP_0 */ 1343 iommu-ctx@4000 { 1344 compatible = "qcom,msm-iommu-v1-ns"; 1345 reg = <0x4000 0x1000>; 1346 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1347 }; 1348 1349 /* VENUS_NS */ 1350 iommu-ctx@5000 { 1351 compatible = "qcom,msm-iommu-v1-sec"; 1352 reg = <0x5000 0x1000>; 1353 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1354 }; 1355 }; 1356 1357 gpu_iommu: iommu@1f08000 { 1358 #address-cells = <1>; 1359 #size-cells = <1>; 1360 #iommu-cells = <1>; 1361 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1362 ranges = <0 0x01f08000 0x10000>; 1363 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1364 <&gcc GCC_GFX_TCU_CLK>; 1365 clock-names = "iface", "bus"; 1366 qcom,iommu-secure-id = <18>; 1367 1368 /* GFX3D_USER */ 1369 iommu-ctx@1000 { 1370 compatible = "qcom,msm-iommu-v1-ns"; 1371 reg = <0x1000 0x1000>; 1372 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1373 }; 1374 1375 /* GFX3D_PRIV */ 1376 iommu-ctx@2000 { 1377 compatible = "qcom,msm-iommu-v1-ns"; 1378 reg = <0x2000 0x1000>; 1379 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1380 }; 1381 }; 1382 1383 spmi_bus: spmi@200f000 { 1384 compatible = "qcom,spmi-pmic-arb"; 1385 reg = <0x0200f000 0x001000>, 1386 <0x02400000 0x400000>, 1387 <0x02c00000 0x400000>, 1388 <0x03800000 0x200000>, 1389 <0x0200a000 0x002100>; 1390 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1391 interrupt-names = "periph_irq"; 1392 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1393 qcom,ee = <0>; 1394 qcom,channel = <0>; 1395 #address-cells = <2>; 1396 #size-cells = <0>; 1397 interrupt-controller; 1398 #interrupt-cells = <4>; 1399 }; 1400 1401 bam_dmux_dma: dma-controller@4044000 { 1402 compatible = "qcom,bam-v1.7.0"; 1403 reg = <0x04044000 0x19000>; 1404 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1405 #dma-cells = <1>; 1406 qcom,ee = <0>; 1407 1408 num-channels = <6>; 1409 qcom,num-ees = <1>; 1410 qcom,powered-remotely; 1411 1412 status = "disabled"; 1413 }; 1414 1415 mpss: remoteproc@4080000 { 1416 compatible = "qcom,msm8916-mss-pil"; 1417 reg = <0x04080000 0x100>, 1418 <0x04020000 0x040>; 1419 1420 reg-names = "qdsp6", "rmb"; 1421 1422 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1423 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1424 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1425 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1426 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1427 interrupt-names = "wdog", "fatal", "ready", 1428 "handover", "stop-ack"; 1429 1430 power-domains = <&rpmpd MSM8916_VDDCX>, 1431 <&rpmpd MSM8916_VDDMX>; 1432 power-domain-names = "cx", "mx"; 1433 1434 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1435 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1436 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1437 <&xo_board>; 1438 clock-names = "iface", "bus", "mem", "xo"; 1439 1440 qcom,smem-states = <&hexagon_smp2p_out 0>; 1441 qcom,smem-state-names = "stop"; 1442 1443 resets = <&scm 0>; 1444 reset-names = "mss_restart"; 1445 1446 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1447 1448 status = "disabled"; 1449 1450 mba { 1451 memory-region = <&mba_mem>; 1452 }; 1453 1454 mpss { 1455 memory-region = <&mpss_mem>; 1456 }; 1457 1458 bam_dmux: bam-dmux { 1459 compatible = "qcom,bam-dmux"; 1460 1461 interrupt-parent = <&hexagon_smsm>; 1462 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1463 interrupt-names = "pc", "pc-ack"; 1464 1465 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1466 qcom,smem-state-names = "pc", "pc-ack"; 1467 1468 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1469 dma-names = "tx", "rx"; 1470 1471 status = "disabled"; 1472 }; 1473 1474 smd-edge { 1475 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1476 1477 qcom,smd-edge = <0>; 1478 qcom,ipc = <&apcs 8 12>; 1479 qcom,remote-pid = <1>; 1480 1481 label = "hexagon"; 1482 1483 fastrpc { 1484 compatible = "qcom,fastrpc"; 1485 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1486 label = "adsp"; 1487 qcom,non-secure-domain; 1488 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 1492 cb@1 { 1493 compatible = "qcom,fastrpc-compute-cb"; 1494 reg = <1>; 1495 }; 1496 }; 1497 }; 1498 }; 1499 1500 sound: sound@7702000 { 1501 status = "disabled"; 1502 compatible = "qcom,apq8016-sbc-sndcard"; 1503 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1504 reg-names = "mic-iomux", "spkr-iomux"; 1505 }; 1506 1507 lpass: audio-controller@7708000 { 1508 status = "disabled"; 1509 compatible = "qcom,apq8016-lpass-cpu"; 1510 1511 /* 1512 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1513 * is actually only used by Tertiary MI2S while 1514 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1515 */ 1516 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1517 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1518 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1519 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1520 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 1521 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1522 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 1523 1524 clock-names = "ahbix-clk", 1525 "mi2s-bit-clk0", 1526 "mi2s-bit-clk1", 1527 "mi2s-bit-clk2", 1528 "mi2s-bit-clk3", 1529 "pcnoc-mport-clk", 1530 "pcnoc-sway-clk"; 1531 #sound-dai-cells = <1>; 1532 1533 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1534 interrupt-names = "lpass-irq-lpaif"; 1535 reg = <0x07708000 0x10000>; 1536 reg-names = "lpass-lpaif"; 1537 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 }; 1541 1542 lpass_codec: audio-codec@771c000 { 1543 compatible = "qcom,msm8916-wcd-digital-codec"; 1544 reg = <0x0771c000 0x400>; 1545 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1546 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1547 clock-names = "ahbix-clk", "mclk"; 1548 #sound-dai-cells = <1>; 1549 status = "disabled"; 1550 }; 1551 1552 sdhc_1: mmc@7824900 { 1553 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1554 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1555 reg-names = "hc", "core"; 1556 1557 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1559 interrupt-names = "hc_irq", "pwr_irq"; 1560 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1561 <&gcc GCC_SDCC1_APPS_CLK>, 1562 <&xo_board>; 1563 clock-names = "iface", "core", "xo"; 1564 mmc-ddr-1_8v; 1565 bus-width = <8>; 1566 non-removable; 1567 status = "disabled"; 1568 }; 1569 1570 sdhc_2: mmc@7864900 { 1571 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1572 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1573 reg-names = "hc", "core"; 1574 1575 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1577 interrupt-names = "hc_irq", "pwr_irq"; 1578 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1579 <&gcc GCC_SDCC2_APPS_CLK>, 1580 <&xo_board>; 1581 clock-names = "iface", "core", "xo"; 1582 bus-width = <4>; 1583 status = "disabled"; 1584 }; 1585 1586 blsp_dma: dma-controller@7884000 { 1587 compatible = "qcom,bam-v1.7.0"; 1588 reg = <0x07884000 0x23000>; 1589 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1590 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1591 clock-names = "bam_clk"; 1592 #dma-cells = <1>; 1593 qcom,ee = <0>; 1594 }; 1595 1596 blsp_uart1: serial@78af000 { 1597 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1598 reg = <0x078af000 0x200>; 1599 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1601 clock-names = "core", "iface"; 1602 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1603 dma-names = "tx", "rx"; 1604 pinctrl-names = "default", "sleep"; 1605 pinctrl-0 = <&blsp_uart1_default>; 1606 pinctrl-1 = <&blsp_uart1_sleep>; 1607 status = "disabled"; 1608 }; 1609 1610 blsp_uart2: serial@78b0000 { 1611 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1612 reg = <0x078b0000 0x200>; 1613 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1615 clock-names = "core", "iface"; 1616 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1617 dma-names = "tx", "rx"; 1618 pinctrl-names = "default", "sleep"; 1619 pinctrl-0 = <&blsp_uart2_default>; 1620 pinctrl-1 = <&blsp_uart2_sleep>; 1621 status = "disabled"; 1622 }; 1623 1624 blsp_i2c1: i2c@78b5000 { 1625 compatible = "qcom,i2c-qup-v2.2.1"; 1626 reg = <0x078b5000 0x500>; 1627 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1628 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1629 <&gcc GCC_BLSP1_AHB_CLK>; 1630 clock-names = "core", "iface"; 1631 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1632 dma-names = "tx", "rx"; 1633 pinctrl-names = "default", "sleep"; 1634 pinctrl-0 = <&blsp_i2c1_default>; 1635 pinctrl-1 = <&blsp_i2c1_sleep>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 blsp_spi1: spi@78b5000 { 1642 compatible = "qcom,spi-qup-v2.2.1"; 1643 reg = <0x078b5000 0x500>; 1644 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1646 <&gcc GCC_BLSP1_AHB_CLK>; 1647 clock-names = "core", "iface"; 1648 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1649 dma-names = "tx", "rx"; 1650 pinctrl-names = "default", "sleep"; 1651 pinctrl-0 = <&blsp_spi1_default>; 1652 pinctrl-1 = <&blsp_spi1_sleep>; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 }; 1657 1658 blsp_i2c2: i2c@78b6000 { 1659 compatible = "qcom,i2c-qup-v2.2.1"; 1660 reg = <0x078b6000 0x500>; 1661 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1662 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1663 <&gcc GCC_BLSP1_AHB_CLK>; 1664 clock-names = "core", "iface"; 1665 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1666 dma-names = "tx", "rx"; 1667 pinctrl-names = "default", "sleep"; 1668 pinctrl-0 = <&blsp_i2c2_default>; 1669 pinctrl-1 = <&blsp_i2c2_sleep>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 blsp_spi2: spi@78b6000 { 1676 compatible = "qcom,spi-qup-v2.2.1"; 1677 reg = <0x078b6000 0x500>; 1678 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1679 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1680 <&gcc GCC_BLSP1_AHB_CLK>; 1681 clock-names = "core", "iface"; 1682 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1683 dma-names = "tx", "rx"; 1684 pinctrl-names = "default", "sleep"; 1685 pinctrl-0 = <&blsp_spi2_default>; 1686 pinctrl-1 = <&blsp_spi2_sleep>; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 blsp_i2c3: i2c@78b7000 { 1693 compatible = "qcom,i2c-qup-v2.2.1"; 1694 reg = <0x078b7000 0x500>; 1695 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1697 <&gcc GCC_BLSP1_AHB_CLK>; 1698 clock-names = "core", "iface"; 1699 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1700 dma-names = "tx", "rx"; 1701 pinctrl-names = "default", "sleep"; 1702 pinctrl-0 = <&blsp_i2c3_default>; 1703 pinctrl-1 = <&blsp_i2c3_sleep>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 blsp_spi3: spi@78b7000 { 1710 compatible = "qcom,spi-qup-v2.2.1"; 1711 reg = <0x078b7000 0x500>; 1712 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1714 <&gcc GCC_BLSP1_AHB_CLK>; 1715 clock-names = "core", "iface"; 1716 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1717 dma-names = "tx", "rx"; 1718 pinctrl-names = "default", "sleep"; 1719 pinctrl-0 = <&blsp_spi3_default>; 1720 pinctrl-1 = <&blsp_spi3_sleep>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 blsp_i2c4: i2c@78b8000 { 1727 compatible = "qcom,i2c-qup-v2.2.1"; 1728 reg = <0x078b8000 0x500>; 1729 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1731 <&gcc GCC_BLSP1_AHB_CLK>; 1732 clock-names = "core", "iface"; 1733 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1734 dma-names = "tx", "rx"; 1735 pinctrl-names = "default", "sleep"; 1736 pinctrl-0 = <&blsp_i2c4_default>; 1737 pinctrl-1 = <&blsp_i2c4_sleep>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 blsp_spi4: spi@78b8000 { 1744 compatible = "qcom,spi-qup-v2.2.1"; 1745 reg = <0x078b8000 0x500>; 1746 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1747 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1748 <&gcc GCC_BLSP1_AHB_CLK>; 1749 clock-names = "core", "iface"; 1750 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1751 dma-names = "tx", "rx"; 1752 pinctrl-names = "default", "sleep"; 1753 pinctrl-0 = <&blsp_spi4_default>; 1754 pinctrl-1 = <&blsp_spi4_sleep>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 status = "disabled"; 1758 }; 1759 1760 blsp_i2c5: i2c@78b9000 { 1761 compatible = "qcom,i2c-qup-v2.2.1"; 1762 reg = <0x078b9000 0x500>; 1763 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1764 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1765 <&gcc GCC_BLSP1_AHB_CLK>; 1766 clock-names = "core", "iface"; 1767 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1768 dma-names = "tx", "rx"; 1769 pinctrl-names = "default", "sleep"; 1770 pinctrl-0 = <&blsp_i2c5_default>; 1771 pinctrl-1 = <&blsp_i2c5_sleep>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 status = "disabled"; 1775 }; 1776 1777 blsp_spi5: spi@78b9000 { 1778 compatible = "qcom,spi-qup-v2.2.1"; 1779 reg = <0x078b9000 0x500>; 1780 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1781 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1782 <&gcc GCC_BLSP1_AHB_CLK>; 1783 clock-names = "core", "iface"; 1784 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1785 dma-names = "tx", "rx"; 1786 pinctrl-names = "default", "sleep"; 1787 pinctrl-0 = <&blsp_spi5_default>; 1788 pinctrl-1 = <&blsp_spi5_sleep>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 status = "disabled"; 1792 }; 1793 1794 blsp_i2c6: i2c@78ba000 { 1795 compatible = "qcom,i2c-qup-v2.2.1"; 1796 reg = <0x078ba000 0x500>; 1797 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1798 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1799 <&gcc GCC_BLSP1_AHB_CLK>; 1800 clock-names = "core", "iface"; 1801 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1802 dma-names = "tx", "rx"; 1803 pinctrl-names = "default", "sleep"; 1804 pinctrl-0 = <&blsp_i2c6_default>; 1805 pinctrl-1 = <&blsp_i2c6_sleep>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 status = "disabled"; 1809 }; 1810 1811 blsp_spi6: spi@78ba000 { 1812 compatible = "qcom,spi-qup-v2.2.1"; 1813 reg = <0x078ba000 0x500>; 1814 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1815 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1816 <&gcc GCC_BLSP1_AHB_CLK>; 1817 clock-names = "core", "iface"; 1818 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1819 dma-names = "tx", "rx"; 1820 pinctrl-names = "default", "sleep"; 1821 pinctrl-0 = <&blsp_spi6_default>; 1822 pinctrl-1 = <&blsp_spi6_sleep>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 status = "disabled"; 1826 }; 1827 1828 usb: usb@78d9000 { 1829 compatible = "qcom,ci-hdrc"; 1830 reg = <0x078d9000 0x200>, 1831 <0x078d9200 0x200>; 1832 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1835 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1836 clock-names = "iface", "core"; 1837 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1838 assigned-clock-rates = <80000000>; 1839 resets = <&gcc GCC_USB_HS_BCR>; 1840 reset-names = "core"; 1841 phy_type = "ulpi"; 1842 dr_mode = "otg"; 1843 hnp-disable; 1844 srp-disable; 1845 adp-disable; 1846 ahb-burst-config = <0>; 1847 phy-names = "usb-phy"; 1848 phys = <&usb_hs_phy>; 1849 status = "disabled"; 1850 #reset-cells = <1>; 1851 1852 ulpi { 1853 usb_hs_phy: phy { 1854 compatible = "qcom,usb-hs-phy-msm8916", 1855 "qcom,usb-hs-phy"; 1856 #phy-cells = <0>; 1857 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1858 clock-names = "ref", "sleep"; 1859 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1860 reset-names = "phy", "por"; 1861 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1862 <0x1 0x6b>, 1863 <0x2 0x24>, 1864 <0x3 0x13>; 1865 }; 1866 }; 1867 }; 1868 1869 wcnss: remoteproc@a204000 { 1870 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1871 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1872 reg-names = "ccu", "dxe", "pmu"; 1873 1874 memory-region = <&wcnss_mem>; 1875 1876 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1877 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1878 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1879 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1880 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1881 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1882 1883 power-domains = <&rpmpd MSM8916_VDDCX>, 1884 <&rpmpd MSM8916_VDDMX>; 1885 power-domain-names = "cx", "mx"; 1886 1887 qcom,smem-states = <&wcnss_smp2p_out 0>; 1888 qcom,smem-state-names = "stop"; 1889 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&wcnss_pin_a>; 1892 1893 status = "disabled"; 1894 1895 wcnss_iris: iris { 1896 /* Separate chip, compatible is board-specific */ 1897 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1898 clock-names = "xo"; 1899 }; 1900 1901 smd-edge { 1902 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1903 1904 qcom,ipc = <&apcs 8 17>; 1905 qcom,smd-edge = <6>; 1906 qcom,remote-pid = <4>; 1907 1908 label = "pronto"; 1909 1910 wcnss_ctrl: wcnss { 1911 compatible = "qcom,wcnss"; 1912 qcom,smd-channels = "WCNSS_CTRL"; 1913 1914 qcom,mmio = <&wcnss>; 1915 1916 wcnss_bt: bluetooth { 1917 compatible = "qcom,wcnss-bt"; 1918 }; 1919 1920 wcnss_wifi: wifi { 1921 compatible = "qcom,wcnss-wlan"; 1922 1923 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1925 interrupt-names = "tx", "rx"; 1926 1927 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1928 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1929 }; 1930 }; 1931 }; 1932 }; 1933 1934 intc: interrupt-controller@b000000 { 1935 compatible = "qcom,msm-qgic2"; 1936 interrupt-controller; 1937 #interrupt-cells = <3>; 1938 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 1939 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 1940 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1941 }; 1942 1943 apcs: mailbox@b011000 { 1944 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 1945 reg = <0x0b011000 0x1000>; 1946 #mbox-cells = <1>; 1947 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 1948 clock-names = "pll", "aux"; 1949 #clock-cells = <0>; 1950 }; 1951 1952 a53pll: clock@b016000 { 1953 compatible = "qcom,msm8916-a53pll"; 1954 reg = <0x0b016000 0x40>; 1955 #clock-cells = <0>; 1956 clocks = <&xo_board>; 1957 clock-names = "xo"; 1958 }; 1959 1960 timer@b020000 { 1961 #address-cells = <1>; 1962 #size-cells = <1>; 1963 ranges; 1964 compatible = "arm,armv7-timer-mem"; 1965 reg = <0x0b020000 0x1000>; 1966 clock-frequency = <19200000>; 1967 1968 frame@b021000 { 1969 frame-number = <0>; 1970 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1972 reg = <0x0b021000 0x1000>, 1973 <0x0b022000 0x1000>; 1974 }; 1975 1976 frame@b023000 { 1977 frame-number = <1>; 1978 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1979 reg = <0x0b023000 0x1000>; 1980 status = "disabled"; 1981 }; 1982 1983 frame@b024000 { 1984 frame-number = <2>; 1985 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1986 reg = <0x0b024000 0x1000>; 1987 status = "disabled"; 1988 }; 1989 1990 frame@b025000 { 1991 frame-number = <3>; 1992 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1993 reg = <0x0b025000 0x1000>; 1994 status = "disabled"; 1995 }; 1996 1997 frame@b026000 { 1998 frame-number = <4>; 1999 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2000 reg = <0x0b026000 0x1000>; 2001 status = "disabled"; 2002 }; 2003 2004 frame@b027000 { 2005 frame-number = <5>; 2006 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2007 reg = <0x0b027000 0x1000>; 2008 status = "disabled"; 2009 }; 2010 2011 frame@b028000 { 2012 frame-number = <6>; 2013 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2014 reg = <0x0b028000 0x1000>; 2015 status = "disabled"; 2016 }; 2017 }; 2018 2019 cpu0_acc: power-manager@b088000 { 2020 compatible = "qcom,msm8916-acc"; 2021 reg = <0x0b088000 0x1000>; 2022 status = "reserved"; /* Controlled by PSCI firmware */ 2023 }; 2024 2025 cpu0_saw: power-manager@b089000 { 2026 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2027 reg = <0x0b089000 0x1000>; 2028 status = "reserved"; /* Controlled by PSCI firmware */ 2029 }; 2030 2031 cpu1_acc: power-manager@b098000 { 2032 compatible = "qcom,msm8916-acc"; 2033 reg = <0x0b098000 0x1000>; 2034 status = "reserved"; /* Controlled by PSCI firmware */ 2035 }; 2036 2037 cpu1_saw: power-manager@b099000 { 2038 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2039 reg = <0x0b099000 0x1000>; 2040 status = "reserved"; /* Controlled by PSCI firmware */ 2041 }; 2042 2043 cpu2_acc: power-manager@b0a8000 { 2044 compatible = "qcom,msm8916-acc"; 2045 reg = <0x0b0a8000 0x1000>; 2046 status = "reserved"; /* Controlled by PSCI firmware */ 2047 }; 2048 2049 cpu2_saw: power-manager@b0a9000 { 2050 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2051 reg = <0x0b0a9000 0x1000>; 2052 status = "reserved"; /* Controlled by PSCI firmware */ 2053 }; 2054 2055 cpu3_acc: power-manager@b0b8000 { 2056 compatible = "qcom,msm8916-acc"; 2057 reg = <0x0b0b8000 0x1000>; 2058 status = "reserved"; /* Controlled by PSCI firmware */ 2059 }; 2060 2061 cpu3_saw: power-manager@b0b9000 { 2062 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2063 reg = <0x0b0b9000 0x1000>; 2064 status = "reserved"; /* Controlled by PSCI firmware */ 2065 }; 2066 }; 2067 2068 thermal-zones { 2069 cpu0-1-thermal { 2070 polling-delay-passive = <250>; 2071 polling-delay = <1000>; 2072 2073 thermal-sensors = <&tsens 5>; 2074 2075 trips { 2076 cpu0_1_alert0: trip-point0 { 2077 temperature = <75000>; 2078 hysteresis = <2000>; 2079 type = "passive"; 2080 }; 2081 cpu0_1_crit: cpu-crit { 2082 temperature = <110000>; 2083 hysteresis = <2000>; 2084 type = "critical"; 2085 }; 2086 }; 2087 2088 cooling-maps { 2089 map0 { 2090 trip = <&cpu0_1_alert0>; 2091 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2092 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2093 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2094 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2095 }; 2096 }; 2097 }; 2098 2099 cpu2-3-thermal { 2100 polling-delay-passive = <250>; 2101 polling-delay = <1000>; 2102 2103 thermal-sensors = <&tsens 4>; 2104 2105 trips { 2106 cpu2_3_alert0: trip-point0 { 2107 temperature = <75000>; 2108 hysteresis = <2000>; 2109 type = "passive"; 2110 }; 2111 cpu2_3_crit: cpu-crit { 2112 temperature = <110000>; 2113 hysteresis = <2000>; 2114 type = "critical"; 2115 }; 2116 }; 2117 2118 cooling-maps { 2119 map0 { 2120 trip = <&cpu2_3_alert0>; 2121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2122 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2123 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2124 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2125 }; 2126 }; 2127 }; 2128 2129 gpu-thermal { 2130 polling-delay-passive = <250>; 2131 polling-delay = <1000>; 2132 2133 thermal-sensors = <&tsens 2>; 2134 2135 trips { 2136 gpu_alert0: trip-point0 { 2137 temperature = <75000>; 2138 hysteresis = <2000>; 2139 type = "passive"; 2140 }; 2141 gpu_crit: gpu-crit { 2142 temperature = <95000>; 2143 hysteresis = <2000>; 2144 type = "critical"; 2145 }; 2146 }; 2147 }; 2148 2149 camera-thermal { 2150 polling-delay-passive = <250>; 2151 polling-delay = <1000>; 2152 2153 thermal-sensors = <&tsens 1>; 2154 2155 trips { 2156 cam_alert0: trip-point0 { 2157 temperature = <75000>; 2158 hysteresis = <2000>; 2159 type = "hot"; 2160 }; 2161 }; 2162 }; 2163 2164 modem-thermal { 2165 polling-delay-passive = <250>; 2166 polling-delay = <1000>; 2167 2168 thermal-sensors = <&tsens 0>; 2169 2170 trips { 2171 modem_alert0: trip-point0 { 2172 temperature = <85000>; 2173 hysteresis = <2000>; 2174 type = "hot"; 2175 }; 2176 }; 2177 }; 2178 }; 2179 2180 timer { 2181 compatible = "arm,armv8-timer"; 2182 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2183 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2184 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2185 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2186 }; 2187}; 2188 2189#include "msm8916-pins.dtsi" 2190