1*8a465494SDevi Priya// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*8a465494SDevi Priya/* 3*8a465494SDevi Priya * IPQ9574 RDP453 board device tree source 4*8a465494SDevi Priya * 5*8a465494SDevi Priya * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6*8a465494SDevi Priya * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 7*8a465494SDevi Priya */ 8*8a465494SDevi Priya 9*8a465494SDevi Priya/dts-v1/; 10*8a465494SDevi Priya 11*8a465494SDevi Priya#include "ipq9574.dtsi" 12*8a465494SDevi Priya 13*8a465494SDevi Priya/ { 14*8a465494SDevi Priya model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; 15*8a465494SDevi Priya compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; 16*8a465494SDevi Priya 17*8a465494SDevi Priya aliases { 18*8a465494SDevi Priya serial0 = &blsp1_uart2; 19*8a465494SDevi Priya }; 20*8a465494SDevi Priya 21*8a465494SDevi Priya chosen { 22*8a465494SDevi Priya stdout-path = "serial0:115200n8"; 23*8a465494SDevi Priya }; 24*8a465494SDevi Priya}; 25*8a465494SDevi Priya 26*8a465494SDevi Priya&blsp1_spi0 { 27*8a465494SDevi Priya pinctrl-0 = <&spi_0_pins>; 28*8a465494SDevi Priya pinctrl-names = "default"; 29*8a465494SDevi Priya status = "okay"; 30*8a465494SDevi Priya 31*8a465494SDevi Priya flash@0 { 32*8a465494SDevi Priya compatible = "micron,n25q128a11", "jedec,spi-nor"; 33*8a465494SDevi Priya reg = <0>; 34*8a465494SDevi Priya #address-cells = <1>; 35*8a465494SDevi Priya #size-cells = <1>; 36*8a465494SDevi Priya spi-max-frequency = <50000000>; 37*8a465494SDevi Priya }; 38*8a465494SDevi Priya}; 39*8a465494SDevi Priya 40*8a465494SDevi Priya&blsp1_uart2 { 41*8a465494SDevi Priya pinctrl-0 = <&uart2_pins>; 42*8a465494SDevi Priya pinctrl-names = "default"; 43*8a465494SDevi Priya status = "okay"; 44*8a465494SDevi Priya}; 45*8a465494SDevi Priya 46*8a465494SDevi Priya&rpm_requests { 47*8a465494SDevi Priya regulators { 48*8a465494SDevi Priya compatible = "qcom,rpm-mp5496-regulators"; 49*8a465494SDevi Priya 50*8a465494SDevi Priya ipq9574_s1: s1 { 51*8a465494SDevi Priya /* 52*8a465494SDevi Priya * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. 53*8a465494SDevi Priya * During regulator registration, kernel not knowing the initial voltage, 54*8a465494SDevi Priya * considers it as zero and brings up the regulators with minimum supported voltage. 55*8a465494SDevi Priya * Update the regulator-min-microvolt with SVS voltage of 725mV so that 56*8a465494SDevi Priya * the regulators are brought up with 725mV which is sufficient for all the 57*8a465494SDevi Priya * corner parts to operate at 800MHz 58*8a465494SDevi Priya */ 59*8a465494SDevi Priya regulator-min-microvolt = <725000>; 60*8a465494SDevi Priya regulator-max-microvolt = <1075000>; 61*8a465494SDevi Priya }; 62*8a465494SDevi Priya }; 63*8a465494SDevi Priya}; 64*8a465494SDevi Priya 65*8a465494SDevi Priya&sleep_clk { 66*8a465494SDevi Priya clock-frequency = <32000>; 67*8a465494SDevi Priya}; 68*8a465494SDevi Priya 69*8a465494SDevi Priya&tlmm { 70*8a465494SDevi Priya spi_0_pins: spi-0-state { 71*8a465494SDevi Priya pins = "gpio11", "gpio12", "gpio13", "gpio14"; 72*8a465494SDevi Priya function = "blsp0_spi"; 73*8a465494SDevi Priya drive-strength = <8>; 74*8a465494SDevi Priya bias-disable; 75*8a465494SDevi Priya }; 76*8a465494SDevi Priya}; 77*8a465494SDevi Priya 78*8a465494SDevi Priya&xo_board_clk { 79*8a465494SDevi Priya clock-frequency = <24000000>; 80*8a465494SDevi Priya}; 81