1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <0x1>; 33 #size-cells = <0x0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 }; 72 }; 73 74 pmu { 75 compatible = "arm,cortex-a53-pmu"; 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 77 }; 78 79 psci { 80 compatible = "arm,psci-1.0"; 81 method = "smc"; 82 }; 83 84 reserved-memory { 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges; 88 89 smem@4ab00000 { 90 compatible = "qcom,smem"; 91 reg = <0x0 0x4ab00000 0x0 0x00100000>; 92 no-map; 93 94 hwlocks = <&tcsr_mutex 0>; 95 }; 96 97 memory@4ac00000 { 98 no-map; 99 reg = <0x0 0x4ac00000 0x0 0x00400000>; 100 }; 101 }; 102 103 firmware { 104 scm { 105 compatible = "qcom,scm-ipq8074", "qcom,scm"; 106 }; 107 }; 108 109 soc: soc { 110 #address-cells = <0x1>; 111 #size-cells = <0x1>; 112 ranges = <0 0 0 0xffffffff>; 113 compatible = "simple-bus"; 114 115 ssphy_1: phy@58000 { 116 compatible = "qcom,ipq8074-qmp-usb3-phy"; 117 reg = <0x00058000 0x1c4>; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges; 121 122 clocks = <&gcc GCC_USB1_AUX_CLK>, 123 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 124 <&xo>; 125 clock-names = "aux", "cfg_ahb", "ref"; 126 127 resets = <&gcc GCC_USB1_PHY_BCR>, 128 <&gcc GCC_USB3PHY_1_PHY_BCR>; 129 reset-names = "phy","common"; 130 status = "disabled"; 131 132 usb1_ssphy: phy@58200 { 133 reg = <0x00058200 0x130>, /* Tx */ 134 <0x00058400 0x200>, /* Rx */ 135 <0x00058800 0x1f8>, /* PCS */ 136 <0x00058600 0x044>; /* PCS misc */ 137 #phy-cells = <0>; 138 #clock-cells = <0>; 139 clocks = <&gcc GCC_USB1_PIPE_CLK>; 140 clock-names = "pipe0"; 141 clock-output-names = "usb3phy_1_cc_pipe_clk"; 142 }; 143 }; 144 145 qusb_phy_1: phy@59000 { 146 compatible = "qcom,ipq8074-qusb2-phy"; 147 reg = <0x00059000 0x180>; 148 #phy-cells = <0>; 149 150 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 151 <&xo>; 152 clock-names = "cfg_ahb", "ref"; 153 154 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 155 status = "disabled"; 156 }; 157 158 ssphy_0: phy@78000 { 159 compatible = "qcom,ipq8074-qmp-usb3-phy"; 160 reg = <0x00078000 0x1c4>; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 165 clocks = <&gcc GCC_USB0_AUX_CLK>, 166 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 167 <&xo>; 168 clock-names = "aux", "cfg_ahb", "ref"; 169 170 resets = <&gcc GCC_USB0_PHY_BCR>, 171 <&gcc GCC_USB3PHY_0_PHY_BCR>; 172 reset-names = "phy","common"; 173 status = "disabled"; 174 175 usb0_ssphy: phy@78200 { 176 reg = <0x00078200 0x130>, /* Tx */ 177 <0x00078400 0x200>, /* Rx */ 178 <0x00078800 0x1f8>, /* PCS */ 179 <0x00078600 0x044>; /* PCS misc */ 180 #phy-cells = <0>; 181 #clock-cells = <0>; 182 clocks = <&gcc GCC_USB0_PIPE_CLK>; 183 clock-names = "pipe0"; 184 clock-output-names = "usb3phy_0_cc_pipe_clk"; 185 }; 186 }; 187 188 qusb_phy_0: phy@79000 { 189 compatible = "qcom,ipq8074-qusb2-phy"; 190 reg = <0x00079000 0x180>; 191 #phy-cells = <0>; 192 193 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 194 <&xo>; 195 clock-names = "cfg_ahb", "ref"; 196 197 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 198 status = "disabled"; 199 }; 200 201 pcie_qmp0: phy@84000 { 202 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 203 reg = <0x00084000 0x1bc>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges; 207 208 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 209 <&gcc GCC_PCIE0_AHB_CLK>; 210 clock-names = "aux", "cfg_ahb"; 211 resets = <&gcc GCC_PCIE0_PHY_BCR>, 212 <&gcc GCC_PCIE0PHY_PHY_BCR>; 213 reset-names = "phy", 214 "common"; 215 status = "disabled"; 216 217 pcie_phy0: phy@84200 { 218 reg = <0x84200 0x16c>, 219 <0x84400 0x200>, 220 <0x84800 0x1f0>, 221 <0x84c00 0xf4>; 222 #phy-cells = <0>; 223 #clock-cells = <0>; 224 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 225 clock-names = "pipe0"; 226 clock-output-names = "pcie20_phy0_pipe_clk"; 227 }; 228 }; 229 230 pcie_qmp1: phy@8e000 { 231 compatible = "qcom,ipq8074-qmp-pcie-phy"; 232 reg = <0x0008e000 0x1c4>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges; 236 237 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 238 <&gcc GCC_PCIE1_AHB_CLK>; 239 clock-names = "aux", "cfg_ahb"; 240 resets = <&gcc GCC_PCIE1_PHY_BCR>, 241 <&gcc GCC_PCIE1PHY_PHY_BCR>; 242 reset-names = "phy", 243 "common"; 244 status = "disabled"; 245 246 pcie_phy1: phy@8e200 { 247 reg = <0x8e200 0x130>, 248 <0x8e400 0x200>, 249 <0x8e800 0x1f8>; 250 #phy-cells = <0>; 251 #clock-cells = <0>; 252 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 253 clock-names = "pipe0"; 254 clock-output-names = "pcie20_phy1_pipe_clk"; 255 }; 256 }; 257 258 mdio: mdio@90000 { 259 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 260 reg = <0x00090000 0x64>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 clocks = <&gcc GCC_MDIO_AHB_CLK>; 265 clock-names = "gcc_mdio_ahb_clk"; 266 267 status = "disabled"; 268 }; 269 270 qfprom: efuse@a4000 { 271 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 272 reg = <0x000a4000 0x2000>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 }; 276 277 prng: rng@e3000 { 278 compatible = "qcom,prng-ee"; 279 reg = <0x000e3000 0x1000>; 280 clocks = <&gcc GCC_PRNG_AHB_CLK>; 281 clock-names = "core"; 282 status = "disabled"; 283 }; 284 285 tsens: thermal-sensor@4a9000 { 286 compatible = "qcom,ipq8074-tsens"; 287 reg = <0x4a9000 0x1000>, /* TM */ 288 <0x4a8000 0x1000>; /* SROT */ 289 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "combined"; 291 #qcom,sensors = <16>; 292 #thermal-sensor-cells = <1>; 293 }; 294 295 cryptobam: dma-controller@704000 { 296 compatible = "qcom,bam-v1.7.0"; 297 reg = <0x00704000 0x20000>; 298 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 300 clock-names = "bam_clk"; 301 #dma-cells = <1>; 302 qcom,ee = <1>; 303 qcom,controlled-remotely; 304 status = "disabled"; 305 }; 306 307 crypto: crypto@73a000 { 308 compatible = "qcom,crypto-v5.1"; 309 reg = <0x0073a000 0x6000>; 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 311 <&gcc GCC_CRYPTO_AXI_CLK>, 312 <&gcc GCC_CRYPTO_CLK>; 313 clock-names = "iface", "bus", "core"; 314 dmas = <&cryptobam 2>, <&cryptobam 3>; 315 dma-names = "rx", "tx"; 316 status = "disabled"; 317 }; 318 319 tlmm: pinctrl@1000000 { 320 compatible = "qcom,ipq8074-pinctrl"; 321 reg = <0x01000000 0x300000>; 322 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 323 gpio-controller; 324 gpio-ranges = <&tlmm 0 0 70>; 325 #gpio-cells = <0x2>; 326 interrupt-controller; 327 #interrupt-cells = <0x2>; 328 329 serial_4_pins: serial4-state { 330 pins = "gpio23", "gpio24"; 331 function = "blsp4_uart1"; 332 drive-strength = <8>; 333 bias-disable; 334 }; 335 336 i2c_0_pins: i2c-0-state { 337 pins = "gpio42", "gpio43"; 338 function = "blsp1_i2c"; 339 drive-strength = <8>; 340 bias-disable; 341 }; 342 343 spi_0_pins: spi-0-state { 344 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 345 function = "blsp0_spi"; 346 drive-strength = <8>; 347 bias-disable; 348 }; 349 350 hsuart_pins: hsuart-state { 351 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 352 function = "blsp2_uart"; 353 drive-strength = <8>; 354 bias-disable; 355 }; 356 357 qpic_pins: qpic-state { 358 pins = "gpio1", "gpio3", "gpio4", 359 "gpio5", "gpio6", "gpio7", 360 "gpio8", "gpio10", "gpio11", 361 "gpio12", "gpio13", "gpio14", 362 "gpio15", "gpio16", "gpio17"; 363 function = "qpic"; 364 drive-strength = <8>; 365 bias-disable; 366 }; 367 }; 368 369 gcc: gcc@1800000 { 370 compatible = "qcom,gcc-ipq8074"; 371 reg = <0x01800000 0x80000>; 372 clocks = <&xo>, <&sleep_clk>; 373 clock-names = "xo", "sleep_clk"; 374 #clock-cells = <1>; 375 #power-domain-cells = <1>; 376 #reset-cells = <1>; 377 }; 378 379 tcsr_mutex: hwlock@1905000 { 380 compatible = "qcom,tcsr-mutex"; 381 reg = <0x01905000 0x20000>; 382 #hwlock-cells = <1>; 383 }; 384 385 spmi_bus: spmi@200f000 { 386 compatible = "qcom,spmi-pmic-arb"; 387 reg = <0x0200f000 0x001000>, 388 <0x02400000 0x800000>, 389 <0x02c00000 0x800000>, 390 <0x03800000 0x200000>, 391 <0x0200a000 0x000700>; 392 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 393 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-names = "periph_irq"; 395 qcom,ee = <0>; 396 qcom,channel = <0>; 397 #address-cells = <2>; 398 #size-cells = <0>; 399 interrupt-controller; 400 #interrupt-cells = <4>; 401 }; 402 403 sdhc_1: mmc@7824900 { 404 compatible = "qcom,sdhci-msm-v4"; 405 reg = <0x7824900 0x500>, <0x7824000 0x800>; 406 reg-names = "hc", "core"; 407 408 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "hc_irq", "pwr_irq"; 411 412 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 413 <&gcc GCC_SDCC1_APPS_CLK>, 414 <&xo>; 415 clock-names = "iface", "core", "xo"; 416 resets = <&gcc GCC_SDCC1_BCR>; 417 max-frequency = <384000000>; 418 mmc-ddr-1_8v; 419 mmc-hs200-1_8v; 420 mmc-hs400-1_8v; 421 bus-width = <8>; 422 423 status = "disabled"; 424 }; 425 426 blsp_dma: dma-controller@7884000 { 427 compatible = "qcom,bam-v1.7.0"; 428 reg = <0x07884000 0x2b000>; 429 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 431 clock-names = "bam_clk"; 432 #dma-cells = <1>; 433 qcom,ee = <0>; 434 }; 435 436 blsp1_uart1: serial@78af000 { 437 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 438 reg = <0x078af000 0x200>; 439 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 441 <&gcc GCC_BLSP1_AHB_CLK>; 442 clock-names = "core", "iface"; 443 status = "disabled"; 444 }; 445 446 blsp1_uart3: serial@78b1000 { 447 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 448 reg = <0x078b1000 0x200>; 449 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 451 <&gcc GCC_BLSP1_AHB_CLK>; 452 clock-names = "core", "iface"; 453 dmas = <&blsp_dma 4>, 454 <&blsp_dma 5>; 455 dma-names = "tx", "rx"; 456 pinctrl-0 = <&hsuart_pins>; 457 pinctrl-names = "default"; 458 status = "disabled"; 459 }; 460 461 blsp1_uart5: serial@78b3000 { 462 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 463 reg = <0x078b3000 0x200>; 464 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 466 <&gcc GCC_BLSP1_AHB_CLK>; 467 clock-names = "core", "iface"; 468 pinctrl-0 = <&serial_4_pins>; 469 pinctrl-names = "default"; 470 status = "disabled"; 471 }; 472 473 blsp1_spi1: spi@78b5000 { 474 compatible = "qcom,spi-qup-v2.2.1"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <0x078b5000 0x600>; 478 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 479 spi-max-frequency = <50000000>; 480 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 481 <&gcc GCC_BLSP1_AHB_CLK>; 482 clock-names = "core", "iface"; 483 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 484 dma-names = "tx", "rx"; 485 pinctrl-0 = <&spi_0_pins>; 486 pinctrl-names = "default"; 487 status = "disabled"; 488 }; 489 490 blsp1_i2c2: i2c@78b6000 { 491 compatible = "qcom,i2c-qup-v2.2.1"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0x078b6000 0x600>; 495 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 497 <&gcc GCC_BLSP1_AHB_CLK>; 498 clock-names = "core", "iface"; 499 clock-frequency = <400000>; 500 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 501 dma-names = "tx", "rx"; 502 pinctrl-0 = <&i2c_0_pins>; 503 pinctrl-names = "default"; 504 status = "disabled"; 505 }; 506 507 blsp1_i2c3: i2c@78b7000 { 508 compatible = "qcom,i2c-qup-v2.2.1"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0x078b7000 0x600>; 512 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 514 <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "core", "iface"; 516 clock-frequency = <100000>; 517 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 518 dma-names = "tx", "rx"; 519 status = "disabled"; 520 }; 521 522 blsp1_i2c5: i2c@78b9000 { 523 compatible = "qcom,i2c-qup-v2.2.1"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x78b9000 0x600>; 527 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 529 <&gcc GCC_BLSP1_AHB_CLK>; 530 clock-names = "core", "iface"; 531 clock-frequency = <400000>; 532 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c6: i2c@78ba000 { 538 compatible = "qcom,i2c-qup-v2.2.1"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x078ba000 0x600>; 542 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 clock-frequency = <100000>; 547 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 548 dma-names = "tx", "rx"; 549 status = "disabled"; 550 }; 551 552 qpic_bam: dma-controller@7984000 { 553 compatible = "qcom,bam-v1.7.0"; 554 reg = <0x07984000 0x1a000>; 555 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&gcc GCC_QPIC_AHB_CLK>; 557 clock-names = "bam_clk"; 558 #dma-cells = <1>; 559 qcom,ee = <0>; 560 status = "disabled"; 561 }; 562 563 qpic_nand: nand-controller@79b0000 { 564 compatible = "qcom,ipq8074-nand"; 565 reg = <0x079b0000 0x10000>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&gcc GCC_QPIC_CLK>, 569 <&gcc GCC_QPIC_AHB_CLK>; 570 clock-names = "core", "aon"; 571 572 dmas = <&qpic_bam 0>, 573 <&qpic_bam 1>, 574 <&qpic_bam 2>; 575 dma-names = "tx", "rx", "cmd"; 576 pinctrl-0 = <&qpic_pins>; 577 pinctrl-names = "default"; 578 status = "disabled"; 579 }; 580 581 usb_0: usb@8af8800 { 582 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 583 reg = <0x08af8800 0x400>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges; 587 588 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 589 <&gcc GCC_USB0_MASTER_CLK>, 590 <&gcc GCC_USB0_SLEEP_CLK>, 591 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 592 clock-names = "cfg_noc", 593 "core", 594 "sleep", 595 "mock_utmi"; 596 597 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 598 <&gcc GCC_USB0_MASTER_CLK>, 599 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 600 assigned-clock-rates = <133330000>, 601 <133330000>, 602 <19200000>; 603 604 power-domains = <&gcc USB0_GDSC>; 605 606 resets = <&gcc GCC_USB0_BCR>; 607 status = "disabled"; 608 609 dwc_0: usb@8a00000 { 610 compatible = "snps,dwc3"; 611 reg = <0x8a00000 0xcd00>; 612 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 613 phys = <&qusb_phy_0>, <&usb0_ssphy>; 614 phy-names = "usb2-phy", "usb3-phy"; 615 snps,is-utmi-l1-suspend; 616 snps,hird-threshold = /bits/ 8 <0x0>; 617 snps,dis_u2_susphy_quirk; 618 snps,dis_u3_susphy_quirk; 619 dr_mode = "host"; 620 }; 621 }; 622 623 usb_1: usb@8cf8800 { 624 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 625 reg = <0x08cf8800 0x400>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges; 629 630 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 631 <&gcc GCC_USB1_MASTER_CLK>, 632 <&gcc GCC_USB1_SLEEP_CLK>, 633 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 634 clock-names = "cfg_noc", 635 "core", 636 "sleep", 637 "mock_utmi"; 638 639 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 640 <&gcc GCC_USB1_MASTER_CLK>, 641 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 642 assigned-clock-rates = <133330000>, 643 <133330000>, 644 <19200000>; 645 646 power-domains = <&gcc USB1_GDSC>; 647 648 resets = <&gcc GCC_USB1_BCR>; 649 status = "disabled"; 650 651 dwc_1: usb@8c00000 { 652 compatible = "snps,dwc3"; 653 reg = <0x8c00000 0xcd00>; 654 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 655 phys = <&qusb_phy_1>, <&usb1_ssphy>; 656 phy-names = "usb2-phy", "usb3-phy"; 657 snps,is-utmi-l1-suspend; 658 snps,hird-threshold = /bits/ 8 <0x0>; 659 snps,dis_u2_susphy_quirk; 660 snps,dis_u3_susphy_quirk; 661 dr_mode = "host"; 662 }; 663 }; 664 665 intc: interrupt-controller@b000000 { 666 compatible = "qcom,msm-qgic2"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 interrupt-controller; 670 #interrupt-cells = <0x3>; 671 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 672 ranges = <0 0xb00a000 0xffd>; 673 674 v2m@0 { 675 compatible = "arm,gic-v2m-frame"; 676 msi-controller; 677 reg = <0x0 0xffd>; 678 }; 679 }; 680 681 watchdog: watchdog@b017000 { 682 compatible = "qcom,kpss-wdt"; 683 reg = <0xb017000 0x1000>; 684 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 685 clocks = <&sleep_clk>; 686 timeout-sec = <30>; 687 }; 688 689 apcs_glb: mailbox@b111000 { 690 compatible = "qcom,ipq8074-apcs-apps-global", 691 "qcom,ipq6018-apcs-apps-global"; 692 reg = <0x0b111000 0x1000>; 693 clocks = <&a53pll>, <&xo>; 694 clock-names = "pll", "xo"; 695 696 #clock-cells = <1>; 697 #mbox-cells = <1>; 698 }; 699 700 a53pll: clock@b116000 { 701 compatible = "qcom,ipq8074-a53pll"; 702 reg = <0x0b116000 0x40>; 703 #clock-cells = <0>; 704 clocks = <&xo>; 705 clock-names = "xo"; 706 }; 707 708 timer@b120000 { 709 #address-cells = <1>; 710 #size-cells = <1>; 711 ranges; 712 compatible = "arm,armv7-timer-mem"; 713 reg = <0x0b120000 0x1000>; 714 715 frame@b120000 { 716 frame-number = <0>; 717 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 719 reg = <0x0b121000 0x1000>, 720 <0x0b122000 0x1000>; 721 }; 722 723 frame@b123000 { 724 frame-number = <1>; 725 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 726 reg = <0x0b123000 0x1000>; 727 status = "disabled"; 728 }; 729 730 frame@b124000 { 731 frame-number = <2>; 732 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 733 reg = <0x0b124000 0x1000>; 734 status = "disabled"; 735 }; 736 737 frame@b125000 { 738 frame-number = <3>; 739 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 740 reg = <0x0b125000 0x1000>; 741 status = "disabled"; 742 }; 743 744 frame@b126000 { 745 frame-number = <4>; 746 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 747 reg = <0x0b126000 0x1000>; 748 status = "disabled"; 749 }; 750 751 frame@b127000 { 752 frame-number = <5>; 753 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 754 reg = <0x0b127000 0x1000>; 755 status = "disabled"; 756 }; 757 758 frame@b128000 { 759 frame-number = <6>; 760 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 761 reg = <0x0b128000 0x1000>; 762 status = "disabled"; 763 }; 764 }; 765 766 pcie1: pci@10000000 { 767 compatible = "qcom,pcie-ipq8074"; 768 reg = <0x10000000 0xf1d>, 769 <0x10000f20 0xa8>, 770 <0x00088000 0x2000>, 771 <0x10100000 0x1000>; 772 reg-names = "dbi", "elbi", "parf", "config"; 773 device_type = "pci"; 774 linux,pci-domain = <1>; 775 bus-range = <0x00 0xff>; 776 num-lanes = <1>; 777 max-link-speed = <2>; 778 #address-cells = <3>; 779 #size-cells = <2>; 780 781 phys = <&pcie_phy1>; 782 phy-names = "pciephy"; 783 784 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 785 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 786 787 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "msi"; 789 #interrupt-cells = <1>; 790 interrupt-map-mask = <0 0 0 0x7>; 791 interrupt-map = <0 0 0 1 &intc 0 142 792 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 793 <0 0 0 2 &intc 0 143 794 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 795 <0 0 0 3 &intc 0 144 796 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 797 <0 0 0 4 &intc 0 145 798 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 799 800 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 801 <&gcc GCC_PCIE1_AXI_M_CLK>, 802 <&gcc GCC_PCIE1_AXI_S_CLK>, 803 <&gcc GCC_PCIE1_AHB_CLK>, 804 <&gcc GCC_PCIE1_AUX_CLK>; 805 clock-names = "iface", 806 "axi_m", 807 "axi_s", 808 "ahb", 809 "aux"; 810 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 811 <&gcc GCC_PCIE1_SLEEP_ARES>, 812 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 813 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 814 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 815 <&gcc GCC_PCIE1_AHB_ARES>, 816 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 817 reset-names = "pipe", 818 "sleep", 819 "sticky", 820 "axi_m", 821 "axi_s", 822 "ahb", 823 "axi_m_sticky"; 824 status = "disabled"; 825 }; 826 827 pcie0: pci@20000000 { 828 compatible = "qcom,pcie-ipq8074-gen3"; 829 reg = <0x20000000 0xf1d>, 830 <0x20000f20 0xa8>, 831 <0x20001000 0x1000>, 832 <0x00080000 0x4000>, 833 <0x20100000 0x1000>; 834 reg-names = "dbi", "elbi", "atu", "parf", "config"; 835 device_type = "pci"; 836 linux,pci-domain = <0>; 837 bus-range = <0x00 0xff>; 838 num-lanes = <1>; 839 max-link-speed = <3>; 840 #address-cells = <3>; 841 #size-cells = <2>; 842 843 phys = <&pcie_phy0>; 844 phy-names = "pciephy"; 845 846 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 847 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 848 849 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "msi"; 851 #interrupt-cells = <1>; 852 interrupt-map-mask = <0 0 0 0x7>; 853 interrupt-map = <0 0 0 1 &intc 0 75 854 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 855 <0 0 0 2 &intc 0 78 856 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 857 <0 0 0 3 &intc 0 79 858 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 859 <0 0 0 4 &intc 0 83 860 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 861 862 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 863 <&gcc GCC_PCIE0_AXI_M_CLK>, 864 <&gcc GCC_PCIE0_AXI_S_CLK>, 865 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 866 <&gcc GCC_PCIE0_RCHNG_CLK>; 867 clock-names = "iface", 868 "axi_m", 869 "axi_s", 870 "axi_bridge", 871 "rchng"; 872 873 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 874 <&gcc GCC_PCIE0_SLEEP_ARES>, 875 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 876 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 877 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 878 <&gcc GCC_PCIE0_AHB_ARES>, 879 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 880 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 881 reset-names = "pipe", 882 "sleep", 883 "sticky", 884 "axi_m", 885 "axi_s", 886 "ahb", 887 "axi_m_sticky", 888 "axi_s_sticky"; 889 status = "disabled"; 890 }; 891 }; 892 893 timer { 894 compatible = "arm,armv8-timer"; 895 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 896 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 897 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 898 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 899 }; 900 901 thermal-zones { 902 nss-top-thermal { 903 polling-delay-passive = <250>; 904 polling-delay = <1000>; 905 906 thermal-sensors = <&tsens 4>; 907 }; 908 909 nss0-thermal { 910 polling-delay-passive = <250>; 911 polling-delay = <1000>; 912 913 thermal-sensors = <&tsens 5>; 914 }; 915 916 nss1-thermal { 917 polling-delay-passive = <250>; 918 polling-delay = <1000>; 919 920 thermal-sensors = <&tsens 6>; 921 }; 922 923 wcss-phya0-thermal { 924 polling-delay-passive = <250>; 925 polling-delay = <1000>; 926 927 thermal-sensors = <&tsens 7>; 928 }; 929 930 wcss-phya1-thermal { 931 polling-delay-passive = <250>; 932 polling-delay = <1000>; 933 934 thermal-sensors = <&tsens 8>; 935 }; 936 937 cpu0_thermal: cpu0-thermal { 938 polling-delay-passive = <250>; 939 polling-delay = <1000>; 940 941 thermal-sensors = <&tsens 9>; 942 }; 943 944 cpu1_thermal: cpu1-thermal { 945 polling-delay-passive = <250>; 946 polling-delay = <1000>; 947 948 thermal-sensors = <&tsens 10>; 949 }; 950 951 cpu2_thermal: cpu2-thermal { 952 polling-delay-passive = <250>; 953 polling-delay = <1000>; 954 955 thermal-sensors = <&tsens 11>; 956 }; 957 958 cpu3_thermal: cpu3-thermal { 959 polling-delay-passive = <250>; 960 polling-delay = <1000>; 961 962 thermal-sensors = <&tsens 12>; 963 }; 964 965 cluster_thermal: cluster-thermal { 966 polling-delay-passive = <250>; 967 polling-delay = <1000>; 968 969 thermal-sensors = <&tsens 13>; 970 }; 971 972 wcss-phyb0-thermal { 973 polling-delay-passive = <250>; 974 polling-delay = <1000>; 975 976 thermal-sensors = <&tsens 14>; 977 }; 978 979 wcss-phyb1-thermal { 980 polling-delay-passive = <250>; 981 polling-delay = <1000>; 982 983 thermal-sensors = <&tsens 15>; 984 }; 985 }; 986}; 987