1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <0x1>; 33 #size-cells = <0x0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <0x2>; 70 }; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 smem@4ab00000 { 89 compatible = "qcom,smem"; 90 reg = <0x0 0x4ab00000 0x0 0x00100000>; 91 no-map; 92 93 hwlocks = <&tcsr_mutex 0>; 94 }; 95 96 memory@4ac00000 { 97 no-map; 98 reg = <0x0 0x4ac00000 0x0 0x00400000>; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-ipq8074", "qcom,scm"; 105 }; 106 }; 107 108 soc: soc { 109 #address-cells = <0x1>; 110 #size-cells = <0x1>; 111 ranges = <0 0 0 0xffffffff>; 112 compatible = "simple-bus"; 113 114 ssphy_1: phy@58000 { 115 compatible = "qcom,ipq8074-qmp-usb3-phy"; 116 reg = <0x00058000 0x1c4>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 clocks = <&gcc GCC_USB1_AUX_CLK>, 122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 123 <&xo>; 124 clock-names = "aux", "cfg_ahb", "ref"; 125 126 resets = <&gcc GCC_USB1_PHY_BCR>, 127 <&gcc GCC_USB3PHY_1_PHY_BCR>; 128 reset-names = "phy","common"; 129 status = "disabled"; 130 131 usb1_ssphy: phy@58200 { 132 reg = <0x00058200 0x130>, /* Tx */ 133 <0x00058400 0x200>, /* Rx */ 134 <0x00058800 0x1f8>, /* PCS */ 135 <0x00058600 0x044>; /* PCS misc */ 136 #phy-cells = <0>; 137 #clock-cells = <0>; 138 clocks = <&gcc GCC_USB1_PIPE_CLK>; 139 clock-names = "pipe0"; 140 clock-output-names = "usb3phy_1_cc_pipe_clk"; 141 }; 142 }; 143 144 qusb_phy_1: phy@59000 { 145 compatible = "qcom,ipq8074-qusb2-phy"; 146 reg = <0x00059000 0x180>; 147 #phy-cells = <0>; 148 149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 150 <&xo>; 151 clock-names = "cfg_ahb", "ref"; 152 153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 154 status = "disabled"; 155 }; 156 157 ssphy_0: phy@78000 { 158 compatible = "qcom,ipq8074-qmp-usb3-phy"; 159 reg = <0x00078000 0x1c4>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges; 163 164 clocks = <&gcc GCC_USB0_AUX_CLK>, 165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 166 <&xo>; 167 clock-names = "aux", "cfg_ahb", "ref"; 168 169 resets = <&gcc GCC_USB0_PHY_BCR>, 170 <&gcc GCC_USB3PHY_0_PHY_BCR>; 171 reset-names = "phy","common"; 172 status = "disabled"; 173 174 usb0_ssphy: phy@78200 { 175 reg = <0x00078200 0x130>, /* Tx */ 176 <0x00078400 0x200>, /* Rx */ 177 <0x00078800 0x1f8>, /* PCS */ 178 <0x00078600 0x044>; /* PCS misc */ 179 #phy-cells = <0>; 180 #clock-cells = <0>; 181 clocks = <&gcc GCC_USB0_PIPE_CLK>; 182 clock-names = "pipe0"; 183 clock-output-names = "usb3phy_0_cc_pipe_clk"; 184 }; 185 }; 186 187 qusb_phy_0: phy@79000 { 188 compatible = "qcom,ipq8074-qusb2-phy"; 189 reg = <0x00079000 0x180>; 190 #phy-cells = <0>; 191 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 193 <&xo>; 194 clock-names = "cfg_ahb", "ref"; 195 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 197 status = "disabled"; 198 }; 199 200 pcie_qmp0: phy@84000 { 201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 202 reg = <0x00084000 0x1bc>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges; 206 207 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 208 <&gcc GCC_PCIE0_AHB_CLK>; 209 clock-names = "aux", "cfg_ahb"; 210 resets = <&gcc GCC_PCIE0_PHY_BCR>, 211 <&gcc GCC_PCIE0PHY_PHY_BCR>; 212 reset-names = "phy", 213 "common"; 214 status = "disabled"; 215 216 pcie_phy0: phy@84200 { 217 reg = <0x84200 0x16c>, 218 <0x84400 0x200>, 219 <0x84800 0x1f0>, 220 <0x84c00 0xf4>; 221 #phy-cells = <0>; 222 #clock-cells = <0>; 223 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 224 clock-names = "pipe0"; 225 clock-output-names = "pcie20_phy0_pipe_clk"; 226 }; 227 }; 228 229 pcie_qmp1: phy@8e000 { 230 compatible = "qcom,ipq8074-qmp-pcie-phy"; 231 reg = <0x0008e000 0x1c4>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 236 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 237 <&gcc GCC_PCIE1_AHB_CLK>; 238 clock-names = "aux", "cfg_ahb"; 239 resets = <&gcc GCC_PCIE1_PHY_BCR>, 240 <&gcc GCC_PCIE1PHY_PHY_BCR>; 241 reset-names = "phy", 242 "common"; 243 status = "disabled"; 244 245 pcie_phy1: phy@8e200 { 246 reg = <0x8e200 0x130>, 247 <0x8e400 0x200>, 248 <0x8e800 0x1f8>; 249 #phy-cells = <0>; 250 #clock-cells = <0>; 251 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 252 clock-names = "pipe0"; 253 clock-output-names = "pcie20_phy1_pipe_clk"; 254 }; 255 }; 256 257 mdio: mdio@90000 { 258 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 259 reg = <0x00090000 0x64>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 clocks = <&gcc GCC_MDIO_AHB_CLK>; 264 clock-names = "gcc_mdio_ahb_clk"; 265 266 status = "disabled"; 267 }; 268 269 qfprom: efuse@a4000 { 270 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 271 reg = <0x000a4000 0x2000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 }; 275 276 prng: rng@e3000 { 277 compatible = "qcom,prng-ee"; 278 reg = <0x000e3000 0x1000>; 279 clocks = <&gcc GCC_PRNG_AHB_CLK>; 280 clock-names = "core"; 281 status = "disabled"; 282 }; 283 284 tsens: thermal-sensor@4a9000 { 285 compatible = "qcom,ipq8074-tsens"; 286 reg = <0x4a9000 0x1000>, /* TM */ 287 <0x4a8000 0x1000>; /* SROT */ 288 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-names = "combined"; 290 #qcom,sensors = <16>; 291 #thermal-sensor-cells = <1>; 292 }; 293 294 cryptobam: dma-controller@704000 { 295 compatible = "qcom,bam-v1.7.0"; 296 reg = <0x00704000 0x20000>; 297 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 299 clock-names = "bam_clk"; 300 #dma-cells = <1>; 301 qcom,ee = <1>; 302 qcom,controlled-remotely; 303 status = "disabled"; 304 }; 305 306 crypto: crypto@73a000 { 307 compatible = "qcom,crypto-v5.1"; 308 reg = <0x0073a000 0x6000>; 309 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 310 <&gcc GCC_CRYPTO_AXI_CLK>, 311 <&gcc GCC_CRYPTO_CLK>; 312 clock-names = "iface", "bus", "core"; 313 dmas = <&cryptobam 2>, <&cryptobam 3>; 314 dma-names = "rx", "tx"; 315 status = "disabled"; 316 }; 317 318 tlmm: pinctrl@1000000 { 319 compatible = "qcom,ipq8074-pinctrl"; 320 reg = <0x01000000 0x300000>; 321 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 322 gpio-controller; 323 gpio-ranges = <&tlmm 0 0 70>; 324 #gpio-cells = <0x2>; 325 interrupt-controller; 326 #interrupt-cells = <0x2>; 327 328 serial_4_pins: serial4-state { 329 pins = "gpio23", "gpio24"; 330 function = "blsp4_uart1"; 331 drive-strength = <8>; 332 bias-disable; 333 }; 334 335 i2c_0_pins: i2c-0-state { 336 pins = "gpio42", "gpio43"; 337 function = "blsp1_i2c"; 338 drive-strength = <8>; 339 bias-disable; 340 }; 341 342 spi_0_pins: spi-0-state { 343 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 344 function = "blsp0_spi"; 345 drive-strength = <8>; 346 bias-disable; 347 }; 348 349 hsuart_pins: hsuart-state { 350 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 351 function = "blsp2_uart"; 352 drive-strength = <8>; 353 bias-disable; 354 }; 355 356 qpic_pins: qpic-state { 357 pins = "gpio1", "gpio3", "gpio4", 358 "gpio5", "gpio6", "gpio7", 359 "gpio8", "gpio10", "gpio11", 360 "gpio12", "gpio13", "gpio14", 361 "gpio15", "gpio16", "gpio17"; 362 function = "qpic"; 363 drive-strength = <8>; 364 bias-disable; 365 }; 366 }; 367 368 gcc: gcc@1800000 { 369 compatible = "qcom,gcc-ipq8074"; 370 reg = <0x01800000 0x80000>; 371 clocks = <&xo>, <&sleep_clk>; 372 clock-names = "xo", "sleep_clk"; 373 #clock-cells = <1>; 374 #power-domain-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 tcsr_mutex: hwlock@1905000 { 379 compatible = "qcom,tcsr-mutex"; 380 reg = <0x01905000 0x20000>; 381 #hwlock-cells = <1>; 382 }; 383 384 spmi_bus: spmi@200f000 { 385 compatible = "qcom,spmi-pmic-arb"; 386 reg = <0x0200f000 0x001000>, 387 <0x02400000 0x800000>, 388 <0x02c00000 0x800000>, 389 <0x03800000 0x200000>, 390 <0x0200a000 0x000700>; 391 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 392 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "periph_irq"; 394 qcom,ee = <0>; 395 qcom,channel = <0>; 396 #address-cells = <2>; 397 #size-cells = <0>; 398 interrupt-controller; 399 #interrupt-cells = <4>; 400 }; 401 402 sdhc_1: mmc@7824900 { 403 compatible = "qcom,sdhci-msm-v4"; 404 reg = <0x7824900 0x500>, <0x7824000 0x800>; 405 reg-names = "hc", "core"; 406 407 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "hc_irq", "pwr_irq"; 410 411 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 412 <&gcc GCC_SDCC1_APPS_CLK>, 413 <&xo>; 414 clock-names = "iface", "core", "xo"; 415 resets = <&gcc GCC_SDCC1_BCR>; 416 max-frequency = <384000000>; 417 mmc-ddr-1_8v; 418 mmc-hs200-1_8v; 419 mmc-hs400-1_8v; 420 bus-width = <8>; 421 422 status = "disabled"; 423 }; 424 425 blsp_dma: dma-controller@7884000 { 426 compatible = "qcom,bam-v1.7.0"; 427 reg = <0x07884000 0x2b000>; 428 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 430 clock-names = "bam_clk"; 431 #dma-cells = <1>; 432 qcom,ee = <0>; 433 }; 434 435 blsp1_uart1: serial@78af000 { 436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 437 reg = <0x078af000 0x200>; 438 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 440 <&gcc GCC_BLSP1_AHB_CLK>; 441 clock-names = "core", "iface"; 442 status = "disabled"; 443 }; 444 445 blsp1_uart3: serial@78b1000 { 446 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 447 reg = <0x078b1000 0x200>; 448 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 450 <&gcc GCC_BLSP1_AHB_CLK>; 451 clock-names = "core", "iface"; 452 dmas = <&blsp_dma 4>, 453 <&blsp_dma 5>; 454 dma-names = "tx", "rx"; 455 pinctrl-0 = <&hsuart_pins>; 456 pinctrl-names = "default"; 457 status = "disabled"; 458 }; 459 460 blsp1_uart5: serial@78b3000 { 461 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 462 reg = <0x078b3000 0x200>; 463 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 465 <&gcc GCC_BLSP1_AHB_CLK>; 466 clock-names = "core", "iface"; 467 pinctrl-0 = <&serial_4_pins>; 468 pinctrl-names = "default"; 469 status = "disabled"; 470 }; 471 472 blsp1_spi1: spi@78b5000 { 473 compatible = "qcom,spi-qup-v2.2.1"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <0x078b5000 0x600>; 477 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 478 spi-max-frequency = <50000000>; 479 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 480 <&gcc GCC_BLSP1_AHB_CLK>; 481 clock-names = "core", "iface"; 482 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 483 dma-names = "tx", "rx"; 484 pinctrl-0 = <&spi_0_pins>; 485 pinctrl-names = "default"; 486 status = "disabled"; 487 }; 488 489 blsp1_i2c2: i2c@78b6000 { 490 compatible = "qcom,i2c-qup-v2.2.1"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0x078b6000 0x600>; 494 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 496 <&gcc GCC_BLSP1_AHB_CLK>; 497 clock-names = "core", "iface"; 498 clock-frequency = <400000>; 499 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 500 dma-names = "tx", "rx"; 501 pinctrl-0 = <&i2c_0_pins>; 502 pinctrl-names = "default"; 503 status = "disabled"; 504 }; 505 506 blsp1_i2c3: i2c@78b7000 { 507 compatible = "qcom,i2c-qup-v2.2.1"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 reg = <0x078b7000 0x600>; 511 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 513 <&gcc GCC_BLSP1_AHB_CLK>; 514 clock-names = "core", "iface"; 515 clock-frequency = <100000>; 516 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 517 dma-names = "tx", "rx"; 518 status = "disabled"; 519 }; 520 521 blsp1_i2c5: i2c@78b9000 { 522 compatible = "qcom,i2c-qup-v2.2.1"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 reg = <0x78b9000 0x600>; 526 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 528 <&gcc GCC_BLSP1_AHB_CLK>; 529 clock-names = "core", "iface"; 530 clock-frequency = <400000>; 531 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 532 dma-names = "tx", "rx"; 533 status = "disabled"; 534 }; 535 536 blsp1_i2c6: i2c@78ba000 { 537 compatible = "qcom,i2c-qup-v2.2.1"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 reg = <0x078ba000 0x600>; 541 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 543 <&gcc GCC_BLSP1_AHB_CLK>; 544 clock-names = "core", "iface"; 545 clock-frequency = <100000>; 546 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 547 dma-names = "tx", "rx"; 548 status = "disabled"; 549 }; 550 551 qpic_bam: dma-controller@7984000 { 552 compatible = "qcom,bam-v1.7.0"; 553 reg = <0x07984000 0x1a000>; 554 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&gcc GCC_QPIC_AHB_CLK>; 556 clock-names = "bam_clk"; 557 #dma-cells = <1>; 558 qcom,ee = <0>; 559 status = "disabled"; 560 }; 561 562 qpic_nand: nand-controller@79b0000 { 563 compatible = "qcom,ipq8074-nand"; 564 reg = <0x079b0000 0x10000>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&gcc GCC_QPIC_CLK>, 568 <&gcc GCC_QPIC_AHB_CLK>; 569 clock-names = "core", "aon"; 570 571 dmas = <&qpic_bam 0>, 572 <&qpic_bam 1>, 573 <&qpic_bam 2>; 574 dma-names = "tx", "rx", "cmd"; 575 pinctrl-0 = <&qpic_pins>; 576 pinctrl-names = "default"; 577 status = "disabled"; 578 }; 579 580 usb_0: usb@8af8800 { 581 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 582 reg = <0x08af8800 0x400>; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges; 586 587 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 588 <&gcc GCC_USB0_MASTER_CLK>, 589 <&gcc GCC_USB0_SLEEP_CLK>, 590 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 591 clock-names = "cfg_noc", 592 "core", 593 "sleep", 594 "mock_utmi"; 595 596 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 597 <&gcc GCC_USB0_MASTER_CLK>, 598 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 599 assigned-clock-rates = <133330000>, 600 <133330000>, 601 <19200000>; 602 603 power-domains = <&gcc USB0_GDSC>; 604 605 resets = <&gcc GCC_USB0_BCR>; 606 status = "disabled"; 607 608 dwc_0: usb@8a00000 { 609 compatible = "snps,dwc3"; 610 reg = <0x8a00000 0xcd00>; 611 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 612 phys = <&qusb_phy_0>, <&usb0_ssphy>; 613 phy-names = "usb2-phy", "usb3-phy"; 614 snps,is-utmi-l1-suspend; 615 snps,hird-threshold = /bits/ 8 <0x0>; 616 snps,dis_u2_susphy_quirk; 617 snps,dis_u3_susphy_quirk; 618 dr_mode = "host"; 619 }; 620 }; 621 622 usb_1: usb@8cf8800 { 623 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 624 reg = <0x08cf8800 0x400>; 625 #address-cells = <1>; 626 #size-cells = <1>; 627 ranges; 628 629 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 630 <&gcc GCC_USB1_MASTER_CLK>, 631 <&gcc GCC_USB1_SLEEP_CLK>, 632 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 633 clock-names = "cfg_noc", 634 "core", 635 "sleep", 636 "mock_utmi"; 637 638 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 639 <&gcc GCC_USB1_MASTER_CLK>, 640 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 641 assigned-clock-rates = <133330000>, 642 <133330000>, 643 <19200000>; 644 645 power-domains = <&gcc USB1_GDSC>; 646 647 resets = <&gcc GCC_USB1_BCR>; 648 status = "disabled"; 649 650 dwc_1: usb@8c00000 { 651 compatible = "snps,dwc3"; 652 reg = <0x8c00000 0xcd00>; 653 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 654 phys = <&qusb_phy_1>, <&usb1_ssphy>; 655 phy-names = "usb2-phy", "usb3-phy"; 656 snps,is-utmi-l1-suspend; 657 snps,hird-threshold = /bits/ 8 <0x0>; 658 snps,dis_u2_susphy_quirk; 659 snps,dis_u3_susphy_quirk; 660 dr_mode = "host"; 661 }; 662 }; 663 664 intc: interrupt-controller@b000000 { 665 compatible = "qcom,msm-qgic2"; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 interrupt-controller; 669 #interrupt-cells = <0x3>; 670 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 671 ranges = <0 0xb00a000 0xffd>; 672 673 v2m@0 { 674 compatible = "arm,gic-v2m-frame"; 675 msi-controller; 676 reg = <0x0 0xffd>; 677 }; 678 }; 679 680 watchdog: watchdog@b017000 { 681 compatible = "qcom,kpss-wdt"; 682 reg = <0xb017000 0x1000>; 683 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 684 clocks = <&sleep_clk>; 685 timeout-sec = <30>; 686 }; 687 688 apcs_glb: mailbox@b111000 { 689 compatible = "qcom,ipq8074-apcs-apps-global", 690 "qcom,ipq6018-apcs-apps-global"; 691 reg = <0x0b111000 0x1000>; 692 clocks = <&a53pll>, <&xo>; 693 clock-names = "pll", "xo"; 694 695 #clock-cells = <1>; 696 #mbox-cells = <1>; 697 }; 698 699 a53pll: clock@b116000 { 700 compatible = "qcom,ipq8074-a53pll"; 701 reg = <0x0b116000 0x40>; 702 #clock-cells = <0>; 703 clocks = <&xo>; 704 clock-names = "xo"; 705 }; 706 707 timer@b120000 { 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges; 711 compatible = "arm,armv7-timer-mem"; 712 reg = <0x0b120000 0x1000>; 713 714 frame@b120000 { 715 frame-number = <0>; 716 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 718 reg = <0x0b121000 0x1000>, 719 <0x0b122000 0x1000>; 720 }; 721 722 frame@b123000 { 723 frame-number = <1>; 724 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 725 reg = <0x0b123000 0x1000>; 726 status = "disabled"; 727 }; 728 729 frame@b124000 { 730 frame-number = <2>; 731 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 732 reg = <0x0b124000 0x1000>; 733 status = "disabled"; 734 }; 735 736 frame@b125000 { 737 frame-number = <3>; 738 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 739 reg = <0x0b125000 0x1000>; 740 status = "disabled"; 741 }; 742 743 frame@b126000 { 744 frame-number = <4>; 745 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 746 reg = <0x0b126000 0x1000>; 747 status = "disabled"; 748 }; 749 750 frame@b127000 { 751 frame-number = <5>; 752 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 753 reg = <0x0b127000 0x1000>; 754 status = "disabled"; 755 }; 756 757 frame@b128000 { 758 frame-number = <6>; 759 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 760 reg = <0x0b128000 0x1000>; 761 status = "disabled"; 762 }; 763 }; 764 765 pcie1: pci@10000000 { 766 compatible = "qcom,pcie-ipq8074"; 767 reg = <0x10000000 0xf1d>, 768 <0x10000f20 0xa8>, 769 <0x00088000 0x2000>, 770 <0x10100000 0x1000>; 771 reg-names = "dbi", "elbi", "parf", "config"; 772 device_type = "pci"; 773 linux,pci-domain = <1>; 774 bus-range = <0x00 0xff>; 775 num-lanes = <1>; 776 max-link-speed = <2>; 777 #address-cells = <3>; 778 #size-cells = <2>; 779 780 phys = <&pcie_phy1>; 781 phy-names = "pciephy"; 782 783 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 784 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 785 786 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 787 interrupt-names = "msi"; 788 #interrupt-cells = <1>; 789 interrupt-map-mask = <0 0 0 0x7>; 790 interrupt-map = <0 0 0 1 &intc 0 142 791 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 792 <0 0 0 2 &intc 0 143 793 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 794 <0 0 0 3 &intc 0 144 795 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 796 <0 0 0 4 &intc 0 145 797 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 798 799 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 800 <&gcc GCC_PCIE1_AXI_M_CLK>, 801 <&gcc GCC_PCIE1_AXI_S_CLK>, 802 <&gcc GCC_PCIE1_AHB_CLK>, 803 <&gcc GCC_PCIE1_AUX_CLK>; 804 clock-names = "iface", 805 "axi_m", 806 "axi_s", 807 "ahb", 808 "aux"; 809 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 810 <&gcc GCC_PCIE1_SLEEP_ARES>, 811 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 812 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 813 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 814 <&gcc GCC_PCIE1_AHB_ARES>, 815 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 816 reset-names = "pipe", 817 "sleep", 818 "sticky", 819 "axi_m", 820 "axi_s", 821 "ahb", 822 "axi_m_sticky"; 823 status = "disabled"; 824 }; 825 826 pcie0: pci@20000000 { 827 compatible = "qcom,pcie-ipq8074-gen3"; 828 reg = <0x20000000 0xf1d>, 829 <0x20000f20 0xa8>, 830 <0x20001000 0x1000>, 831 <0x00080000 0x4000>, 832 <0x20100000 0x1000>; 833 reg-names = "dbi", "elbi", "atu", "parf", "config"; 834 device_type = "pci"; 835 linux,pci-domain = <0>; 836 bus-range = <0x00 0xff>; 837 num-lanes = <1>; 838 max-link-speed = <3>; 839 #address-cells = <3>; 840 #size-cells = <2>; 841 842 phys = <&pcie_phy0>; 843 phy-names = "pciephy"; 844 845 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 846 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 847 848 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "msi"; 850 #interrupt-cells = <1>; 851 interrupt-map-mask = <0 0 0 0x7>; 852 interrupt-map = <0 0 0 1 &intc 0 75 853 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 854 <0 0 0 2 &intc 0 78 855 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 856 <0 0 0 3 &intc 0 79 857 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 858 <0 0 0 4 &intc 0 83 859 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 860 861 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 862 <&gcc GCC_PCIE0_AXI_M_CLK>, 863 <&gcc GCC_PCIE0_AXI_S_CLK>, 864 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 865 <&gcc GCC_PCIE0_RCHNG_CLK>; 866 clock-names = "iface", 867 "axi_m", 868 "axi_s", 869 "axi_bridge", 870 "rchng"; 871 872 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 873 <&gcc GCC_PCIE0_SLEEP_ARES>, 874 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 875 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 876 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 877 <&gcc GCC_PCIE0_AHB_ARES>, 878 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 879 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 880 reset-names = "pipe", 881 "sleep", 882 "sticky", 883 "axi_m", 884 "axi_s", 885 "ahb", 886 "axi_m_sticky", 887 "axi_s_sticky"; 888 status = "disabled"; 889 }; 890 }; 891 892 timer { 893 compatible = "arm,armv8-timer"; 894 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 895 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 896 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 897 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 898 }; 899 900 thermal-zones { 901 nss-top-thermal { 902 polling-delay-passive = <250>; 903 polling-delay = <1000>; 904 905 thermal-sensors = <&tsens 4>; 906 }; 907 908 nss0-thermal { 909 polling-delay-passive = <250>; 910 polling-delay = <1000>; 911 912 thermal-sensors = <&tsens 5>; 913 }; 914 915 nss1-thermal { 916 polling-delay-passive = <250>; 917 polling-delay = <1000>; 918 919 thermal-sensors = <&tsens 6>; 920 }; 921 922 wcss-phya0-thermal { 923 polling-delay-passive = <250>; 924 polling-delay = <1000>; 925 926 thermal-sensors = <&tsens 7>; 927 }; 928 929 wcss-phya1-thermal { 930 polling-delay-passive = <250>; 931 polling-delay = <1000>; 932 933 thermal-sensors = <&tsens 8>; 934 }; 935 936 cpu0_thermal: cpu0-thermal { 937 polling-delay-passive = <250>; 938 polling-delay = <1000>; 939 940 thermal-sensors = <&tsens 9>; 941 }; 942 943 cpu1_thermal: cpu1-thermal { 944 polling-delay-passive = <250>; 945 polling-delay = <1000>; 946 947 thermal-sensors = <&tsens 10>; 948 }; 949 950 cpu2_thermal: cpu2-thermal { 951 polling-delay-passive = <250>; 952 polling-delay = <1000>; 953 954 thermal-sensors = <&tsens 11>; 955 }; 956 957 cpu3_thermal: cpu3-thermal { 958 polling-delay-passive = <250>; 959 polling-delay = <1000>; 960 961 thermal-sensors = <&tsens 12>; 962 }; 963 964 cluster_thermal: cluster-thermal { 965 polling-delay-passive = <250>; 966 polling-delay = <1000>; 967 968 thermal-sensors = <&tsens 13>; 969 }; 970 971 wcss-phyb0-thermal { 972 polling-delay-passive = <250>; 973 polling-delay = <1000>; 974 975 thermal-sensors = <&tsens 14>; 976 }; 977 978 wcss-phyb1-thermal { 979 polling-delay-passive = <250>; 980 polling-delay = <1000>; 981 982 thermal-sensors = <&tsens 15>; 983 }; 984 }; 985}; 986