1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <0x1>; 33 #size-cells = <0x0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <0x2>; 70 }; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 smem@4ab00000 { 89 compatible = "qcom,smem"; 90 reg = <0x0 0x4ab00000 0x0 0x00100000>; 91 no-map; 92 93 hwlocks = <&tcsr_mutex 0>; 94 }; 95 96 memory@4ac00000 { 97 no-map; 98 reg = <0x0 0x4ac00000 0x0 0x00400000>; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-ipq8074", "qcom,scm"; 105 }; 106 }; 107 108 soc: soc { 109 #address-cells = <0x1>; 110 #size-cells = <0x1>; 111 ranges = <0 0 0 0xffffffff>; 112 compatible = "simple-bus"; 113 114 ssphy_1: phy@58000 { 115 compatible = "qcom,ipq8074-qmp-usb3-phy"; 116 reg = <0x00058000 0x1c4>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 clocks = <&gcc GCC_USB1_AUX_CLK>, 122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 123 <&xo>; 124 clock-names = "aux", "cfg_ahb", "ref"; 125 126 resets = <&gcc GCC_USB1_PHY_BCR>, 127 <&gcc GCC_USB3PHY_1_PHY_BCR>; 128 reset-names = "phy","common"; 129 status = "disabled"; 130 131 usb1_ssphy: phy@58200 { 132 reg = <0x00058200 0x130>, /* Tx */ 133 <0x00058400 0x200>, /* Rx */ 134 <0x00058800 0x1f8>, /* PCS */ 135 <0x00058600 0x044>; /* PCS misc */ 136 #phy-cells = <0>; 137 #clock-cells = <0>; 138 clocks = <&gcc GCC_USB1_PIPE_CLK>; 139 clock-names = "pipe0"; 140 clock-output-names = "gcc_usb1_pipe_clk_src"; 141 }; 142 }; 143 144 qusb_phy_1: phy@59000 { 145 compatible = "qcom,ipq8074-qusb2-phy"; 146 reg = <0x00059000 0x180>; 147 #phy-cells = <0>; 148 149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 150 <&xo>; 151 clock-names = "cfg_ahb", "ref"; 152 153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 154 status = "disabled"; 155 }; 156 157 ssphy_0: phy@78000 { 158 compatible = "qcom,ipq8074-qmp-usb3-phy"; 159 reg = <0x00078000 0x1c4>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges; 163 164 clocks = <&gcc GCC_USB0_AUX_CLK>, 165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 166 <&xo>; 167 clock-names = "aux", "cfg_ahb", "ref"; 168 169 resets = <&gcc GCC_USB0_PHY_BCR>, 170 <&gcc GCC_USB3PHY_0_PHY_BCR>; 171 reset-names = "phy","common"; 172 status = "disabled"; 173 174 usb0_ssphy: phy@78200 { 175 reg = <0x00078200 0x130>, /* Tx */ 176 <0x00078400 0x200>, /* Rx */ 177 <0x00078800 0x1f8>, /* PCS */ 178 <0x00078600 0x044>; /* PCS misc */ 179 #phy-cells = <0>; 180 #clock-cells = <0>; 181 clocks = <&gcc GCC_USB0_PIPE_CLK>; 182 clock-names = "pipe0"; 183 clock-output-names = "gcc_usb0_pipe_clk_src"; 184 }; 185 }; 186 187 qusb_phy_0: phy@79000 { 188 compatible = "qcom,ipq8074-qusb2-phy"; 189 reg = <0x00079000 0x180>; 190 #phy-cells = <0>; 191 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 193 <&xo>; 194 clock-names = "cfg_ahb", "ref"; 195 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 197 status = "disabled"; 198 }; 199 200 pcie_qmp0: phy@86000 { 201 compatible = "qcom,ipq8074-qmp-pcie-phy"; 202 reg = <0x00086000 0x1c4>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges; 206 207 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 208 <&gcc GCC_PCIE0_AHB_CLK>; 209 clock-names = "aux", "cfg_ahb"; 210 resets = <&gcc GCC_PCIE0_PHY_BCR>, 211 <&gcc GCC_PCIE0PHY_PHY_BCR>; 212 reset-names = "phy", 213 "common"; 214 status = "disabled"; 215 216 pcie_phy0: phy@86200 { 217 reg = <0x86200 0x16c>, 218 <0x86400 0x200>, 219 <0x86800 0x4f4>; 220 #phy-cells = <0>; 221 #clock-cells = <0>; 222 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 223 clock-names = "pipe0"; 224 clock-output-names = "pcie_0_pipe_clk"; 225 }; 226 }; 227 228 pcie_qmp1: phy@8e000 { 229 compatible = "qcom,ipq8074-qmp-pcie-phy"; 230 reg = <0x0008e000 0x1c4>; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges; 234 235 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 236 <&gcc GCC_PCIE1_AHB_CLK>; 237 clock-names = "aux", "cfg_ahb"; 238 resets = <&gcc GCC_PCIE1_PHY_BCR>, 239 <&gcc GCC_PCIE1PHY_PHY_BCR>; 240 reset-names = "phy", 241 "common"; 242 status = "disabled"; 243 244 pcie_phy1: phy@8e200 { 245 reg = <0x8e200 0x16c>, 246 <0x8e400 0x200>, 247 <0x8e800 0x4f4>; 248 #phy-cells = <0>; 249 #clock-cells = <0>; 250 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 251 clock-names = "pipe0"; 252 clock-output-names = "pcie_1_pipe_clk"; 253 }; 254 }; 255 256 mdio: mdio@90000 { 257 compatible = "qcom,ipq4019-mdio"; 258 reg = <0x00090000 0x64>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 clocks = <&gcc GCC_MDIO_AHB_CLK>; 263 clock-names = "gcc_mdio_ahb_clk"; 264 265 status = "disabled"; 266 }; 267 268 prng: rng@e3000 { 269 compatible = "qcom,prng-ee"; 270 reg = <0x000e3000 0x1000>; 271 clocks = <&gcc GCC_PRNG_AHB_CLK>; 272 clock-names = "core"; 273 status = "disabled"; 274 }; 275 276 tsens: thermal-sensor@4a9000 { 277 compatible = "qcom,ipq8074-tsens"; 278 reg = <0x4a9000 0x1000>, /* TM */ 279 <0x4a8000 0x1000>; /* SROT */ 280 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-names = "combined"; 282 #qcom,sensors = <16>; 283 #thermal-sensor-cells = <1>; 284 }; 285 286 cryptobam: dma-controller@704000 { 287 compatible = "qcom,bam-v1.7.0"; 288 reg = <0x00704000 0x20000>; 289 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 291 clock-names = "bam_clk"; 292 #dma-cells = <1>; 293 qcom,ee = <1>; 294 qcom,controlled-remotely; 295 status = "disabled"; 296 }; 297 298 crypto: crypto@73a000 { 299 compatible = "qcom,crypto-v5.1"; 300 reg = <0x0073a000 0x6000>; 301 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 302 <&gcc GCC_CRYPTO_AXI_CLK>, 303 <&gcc GCC_CRYPTO_CLK>; 304 clock-names = "iface", "bus", "core"; 305 dmas = <&cryptobam 2>, <&cryptobam 3>; 306 dma-names = "rx", "tx"; 307 status = "disabled"; 308 }; 309 310 tlmm: pinctrl@1000000 { 311 compatible = "qcom,ipq8074-pinctrl"; 312 reg = <0x01000000 0x300000>; 313 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 314 gpio-controller; 315 gpio-ranges = <&tlmm 0 0 70>; 316 #gpio-cells = <0x2>; 317 interrupt-controller; 318 #interrupt-cells = <0x2>; 319 320 serial_4_pins: serial4-state { 321 pins = "gpio23", "gpio24"; 322 function = "blsp4_uart1"; 323 drive-strength = <8>; 324 bias-disable; 325 }; 326 327 i2c_0_pins: i2c-0-state { 328 pins = "gpio42", "gpio43"; 329 function = "blsp1_i2c"; 330 drive-strength = <8>; 331 bias-disable; 332 }; 333 334 spi_0_pins: spi-0-state { 335 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 336 function = "blsp0_spi"; 337 drive-strength = <8>; 338 bias-disable; 339 }; 340 341 hsuart_pins: hsuart-state { 342 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 343 function = "blsp2_uart"; 344 drive-strength = <8>; 345 bias-disable; 346 }; 347 348 qpic_pins: qpic-state { 349 pins = "gpio1", "gpio3", "gpio4", 350 "gpio5", "gpio6", "gpio7", 351 "gpio8", "gpio10", "gpio11", 352 "gpio12", "gpio13", "gpio14", 353 "gpio15", "gpio16", "gpio17"; 354 function = "qpic"; 355 drive-strength = <8>; 356 bias-disable; 357 }; 358 }; 359 360 gcc: gcc@1800000 { 361 compatible = "qcom,gcc-ipq8074"; 362 reg = <0x01800000 0x80000>; 363 clocks = <&xo>, <&sleep_clk>; 364 clock-names = "xo", "sleep_clk"; 365 #clock-cells = <1>; 366 #power-domain-cells = <1>; 367 #reset-cells = <1>; 368 }; 369 370 tcsr_mutex: hwlock@1905000 { 371 compatible = "qcom,tcsr-mutex"; 372 reg = <0x01905000 0x20000>; 373 #hwlock-cells = <1>; 374 }; 375 376 spmi_bus: spmi@200f000 { 377 compatible = "qcom,spmi-pmic-arb"; 378 reg = <0x0200f000 0x001000>, 379 <0x02400000 0x800000>, 380 <0x02c00000 0x800000>, 381 <0x03800000 0x200000>, 382 <0x0200a000 0x000700>; 383 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 384 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-names = "periph_irq"; 386 qcom,ee = <0>; 387 qcom,channel = <0>; 388 #address-cells = <2>; 389 #size-cells = <0>; 390 interrupt-controller; 391 #interrupt-cells = <4>; 392 cell-index = <0>; 393 }; 394 395 sdhc_1: mmc@7824900 { 396 compatible = "qcom,sdhci-msm-v4"; 397 reg = <0x7824900 0x500>, <0x7824000 0x800>; 398 reg-names = "hc", "core"; 399 400 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "hc_irq", "pwr_irq"; 403 404 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 405 <&gcc GCC_SDCC1_APPS_CLK>, 406 <&xo>; 407 clock-names = "iface", "core", "xo"; 408 resets = <&gcc GCC_SDCC1_BCR>; 409 max-frequency = <384000000>; 410 mmc-ddr-1_8v; 411 mmc-hs200-1_8v; 412 mmc-hs400-1_8v; 413 bus-width = <8>; 414 415 status = "disabled"; 416 }; 417 418 blsp_dma: dma-controller@7884000 { 419 compatible = "qcom,bam-v1.7.0"; 420 reg = <0x07884000 0x2b000>; 421 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 423 clock-names = "bam_clk"; 424 #dma-cells = <1>; 425 qcom,ee = <0>; 426 }; 427 428 blsp1_uart1: serial@78af000 { 429 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 430 reg = <0x078af000 0x200>; 431 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 433 <&gcc GCC_BLSP1_AHB_CLK>; 434 clock-names = "core", "iface"; 435 status = "disabled"; 436 }; 437 438 blsp1_uart3: serial@78b1000 { 439 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 440 reg = <0x078b1000 0x200>; 441 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 443 <&gcc GCC_BLSP1_AHB_CLK>; 444 clock-names = "core", "iface"; 445 dmas = <&blsp_dma 4>, 446 <&blsp_dma 5>; 447 dma-names = "tx", "rx"; 448 pinctrl-0 = <&hsuart_pins>; 449 pinctrl-names = "default"; 450 status = "disabled"; 451 }; 452 453 blsp1_uart5: serial@78b3000 { 454 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 455 reg = <0x078b3000 0x200>; 456 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 458 <&gcc GCC_BLSP1_AHB_CLK>; 459 clock-names = "core", "iface"; 460 pinctrl-0 = <&serial_4_pins>; 461 pinctrl-names = "default"; 462 status = "disabled"; 463 }; 464 465 blsp1_spi1: spi@78b5000 { 466 compatible = "qcom,spi-qup-v2.2.1"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0x078b5000 0x600>; 470 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 471 spi-max-frequency = <50000000>; 472 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 473 <&gcc GCC_BLSP1_AHB_CLK>; 474 clock-names = "core", "iface"; 475 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 476 dma-names = "tx", "rx"; 477 pinctrl-0 = <&spi_0_pins>; 478 pinctrl-names = "default"; 479 status = "disabled"; 480 }; 481 482 blsp1_i2c2: i2c@78b6000 { 483 compatible = "qcom,i2c-qup-v2.2.1"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <0x078b6000 0x600>; 487 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 489 <&gcc GCC_BLSP1_AHB_CLK>; 490 clock-names = "core", "iface"; 491 clock-frequency = <400000>; 492 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 493 dma-names = "tx", "rx"; 494 pinctrl-0 = <&i2c_0_pins>; 495 pinctrl-names = "default"; 496 status = "disabled"; 497 }; 498 499 blsp1_i2c3: i2c@78b7000 { 500 compatible = "qcom,i2c-qup-v2.2.1"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0x078b7000 0x600>; 504 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 506 <&gcc GCC_BLSP1_AHB_CLK>; 507 clock-names = "core", "iface"; 508 clock-frequency = <100000>; 509 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 510 dma-names = "tx", "rx"; 511 status = "disabled"; 512 }; 513 514 blsp1_i2c5: i2c@78b9000 { 515 compatible = "qcom,i2c-qup-v2.2.1"; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 reg = <0x78b9000 0x600>; 519 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 521 <&gcc GCC_BLSP1_AHB_CLK>; 522 clock-names = "core", "iface"; 523 clock-frequency = <400000>; 524 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 525 dma-names = "tx", "rx"; 526 status = "disabled"; 527 }; 528 529 blsp1_i2c6: i2c@78ba000 { 530 compatible = "qcom,i2c-qup-v2.2.1"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <0x078ba000 0x600>; 534 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 536 <&gcc GCC_BLSP1_AHB_CLK>; 537 clock-names = "core", "iface"; 538 clock-frequency = <100000>; 539 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 540 dma-names = "tx", "rx"; 541 status = "disabled"; 542 }; 543 544 qpic_bam: dma-controller@7984000 { 545 compatible = "qcom,bam-v1.7.0"; 546 reg = <0x07984000 0x1a000>; 547 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&gcc GCC_QPIC_AHB_CLK>; 549 clock-names = "bam_clk"; 550 #dma-cells = <1>; 551 qcom,ee = <0>; 552 status = "disabled"; 553 }; 554 555 qpic_nand: nand-controller@79b0000 { 556 compatible = "qcom,ipq8074-nand"; 557 reg = <0x079b0000 0x10000>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&gcc GCC_QPIC_CLK>, 561 <&gcc GCC_QPIC_AHB_CLK>; 562 clock-names = "core", "aon"; 563 564 dmas = <&qpic_bam 0>, 565 <&qpic_bam 1>, 566 <&qpic_bam 2>; 567 dma-names = "tx", "rx", "cmd"; 568 pinctrl-0 = <&qpic_pins>; 569 pinctrl-names = "default"; 570 status = "disabled"; 571 }; 572 573 usb_0: usb@8af8800 { 574 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 575 reg = <0x08af8800 0x400>; 576 #address-cells = <1>; 577 #size-cells = <1>; 578 ranges; 579 580 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 581 <&gcc GCC_USB0_MASTER_CLK>, 582 <&gcc GCC_USB0_SLEEP_CLK>, 583 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 584 clock-names = "cfg_noc", 585 "core", 586 "sleep", 587 "mock_utmi"; 588 589 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 590 <&gcc GCC_USB0_MASTER_CLK>, 591 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 592 assigned-clock-rates = <133330000>, 593 <133330000>, 594 <19200000>; 595 596 power-domains = <&gcc USB0_GDSC>; 597 598 resets = <&gcc GCC_USB0_BCR>; 599 status = "disabled"; 600 601 dwc_0: usb@8a00000 { 602 compatible = "snps,dwc3"; 603 reg = <0x8a00000 0xcd00>; 604 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 605 phys = <&qusb_phy_0>, <&usb0_ssphy>; 606 phy-names = "usb2-phy", "usb3-phy"; 607 snps,is-utmi-l1-suspend; 608 snps,hird-threshold = /bits/ 8 <0x0>; 609 snps,dis_u2_susphy_quirk; 610 snps,dis_u3_susphy_quirk; 611 dr_mode = "host"; 612 }; 613 }; 614 615 usb_1: usb@8cf8800 { 616 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 617 reg = <0x08cf8800 0x400>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges; 621 622 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 623 <&gcc GCC_USB1_MASTER_CLK>, 624 <&gcc GCC_USB1_SLEEP_CLK>, 625 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 626 clock-names = "cfg_noc", 627 "core", 628 "sleep", 629 "mock_utmi"; 630 631 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 632 <&gcc GCC_USB1_MASTER_CLK>, 633 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 634 assigned-clock-rates = <133330000>, 635 <133330000>, 636 <19200000>; 637 638 power-domains = <&gcc USB1_GDSC>; 639 640 resets = <&gcc GCC_USB1_BCR>; 641 status = "disabled"; 642 643 dwc_1: usb@8c00000 { 644 compatible = "snps,dwc3"; 645 reg = <0x8c00000 0xcd00>; 646 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 647 phys = <&qusb_phy_1>, <&usb1_ssphy>; 648 phy-names = "usb2-phy", "usb3-phy"; 649 snps,is-utmi-l1-suspend; 650 snps,hird-threshold = /bits/ 8 <0x0>; 651 snps,dis_u2_susphy_quirk; 652 snps,dis_u3_susphy_quirk; 653 dr_mode = "host"; 654 }; 655 }; 656 657 intc: interrupt-controller@b000000 { 658 compatible = "qcom,msm-qgic2"; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 interrupt-controller; 662 #interrupt-cells = <0x3>; 663 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 664 ranges = <0 0xb00a000 0xffd>; 665 666 v2m@0 { 667 compatible = "arm,gic-v2m-frame"; 668 msi-controller; 669 reg = <0x0 0xffd>; 670 }; 671 }; 672 673 watchdog: watchdog@b017000 { 674 compatible = "qcom,kpss-wdt"; 675 reg = <0xb017000 0x1000>; 676 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 677 clocks = <&sleep_clk>; 678 timeout-sec = <30>; 679 }; 680 681 apcs_glb: mailbox@b111000 { 682 compatible = "qcom,ipq8074-apcs-apps-global"; 683 reg = <0x0b111000 0x1000>; 684 clocks = <&a53pll>, <&xo>; 685 clock-names = "pll", "xo"; 686 687 #clock-cells = <1>; 688 #mbox-cells = <1>; 689 }; 690 691 a53pll: clock@b116000 { 692 compatible = "qcom,ipq8074-a53pll"; 693 reg = <0x0b116000 0x40>; 694 #clock-cells = <0>; 695 clocks = <&xo>; 696 clock-names = "xo"; 697 }; 698 699 timer@b120000 { 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges; 703 compatible = "arm,armv7-timer-mem"; 704 reg = <0x0b120000 0x1000>; 705 706 frame@b120000 { 707 frame-number = <0>; 708 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 710 reg = <0x0b121000 0x1000>, 711 <0x0b122000 0x1000>; 712 }; 713 714 frame@b123000 { 715 frame-number = <1>; 716 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 717 reg = <0x0b123000 0x1000>; 718 status = "disabled"; 719 }; 720 721 frame@b124000 { 722 frame-number = <2>; 723 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 724 reg = <0x0b124000 0x1000>; 725 status = "disabled"; 726 }; 727 728 frame@b125000 { 729 frame-number = <3>; 730 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 731 reg = <0x0b125000 0x1000>; 732 status = "disabled"; 733 }; 734 735 frame@b126000 { 736 frame-number = <4>; 737 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 738 reg = <0x0b126000 0x1000>; 739 status = "disabled"; 740 }; 741 742 frame@b127000 { 743 frame-number = <5>; 744 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 745 reg = <0x0b127000 0x1000>; 746 status = "disabled"; 747 }; 748 749 frame@b128000 { 750 frame-number = <6>; 751 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 752 reg = <0x0b128000 0x1000>; 753 status = "disabled"; 754 }; 755 }; 756 757 pcie1: pci@10000000 { 758 compatible = "qcom,pcie-ipq8074"; 759 reg = <0x10000000 0xf1d>, 760 <0x10000f20 0xa8>, 761 <0x00088000 0x2000>, 762 <0x10100000 0x1000>; 763 reg-names = "dbi", "elbi", "parf", "config"; 764 device_type = "pci"; 765 linux,pci-domain = <1>; 766 bus-range = <0x00 0xff>; 767 num-lanes = <1>; 768 #address-cells = <3>; 769 #size-cells = <2>; 770 771 phys = <&pcie_phy1>; 772 phy-names = "pciephy"; 773 774 ranges = <0x81000000 0 0x10200000 0x10200000 775 0 0x100000 /* downstream I/O */ 776 0x82000000 0 0x10300000 0x10300000 777 0 0xd00000>; /* non-prefetchable memory */ 778 779 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-names = "msi"; 781 #interrupt-cells = <1>; 782 interrupt-map-mask = <0 0 0 0x7>; 783 interrupt-map = <0 0 0 1 &intc 0 142 784 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 785 <0 0 0 2 &intc 0 143 786 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 787 <0 0 0 3 &intc 0 144 788 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 789 <0 0 0 4 &intc 0 145 790 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 791 792 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 793 <&gcc GCC_PCIE1_AXI_M_CLK>, 794 <&gcc GCC_PCIE1_AXI_S_CLK>, 795 <&gcc GCC_PCIE1_AHB_CLK>, 796 <&gcc GCC_PCIE1_AUX_CLK>; 797 clock-names = "iface", 798 "axi_m", 799 "axi_s", 800 "ahb", 801 "aux"; 802 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 803 <&gcc GCC_PCIE1_SLEEP_ARES>, 804 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 805 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 806 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 807 <&gcc GCC_PCIE1_AHB_ARES>, 808 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 809 reset-names = "pipe", 810 "sleep", 811 "sticky", 812 "axi_m", 813 "axi_s", 814 "ahb", 815 "axi_m_sticky"; 816 status = "disabled"; 817 }; 818 819 pcie0: pci@20000000 { 820 compatible = "qcom,pcie-ipq8074"; 821 reg = <0x20000000 0xf1d>, 822 <0x20000f20 0xa8>, 823 <0x00080000 0x2000>, 824 <0x20100000 0x1000>; 825 reg-names = "dbi", "elbi", "parf", "config"; 826 device_type = "pci"; 827 linux,pci-domain = <0>; 828 bus-range = <0x00 0xff>; 829 num-lanes = <1>; 830 #address-cells = <3>; 831 #size-cells = <2>; 832 833 phys = <&pcie_phy0>; 834 phy-names = "pciephy"; 835 836 ranges = <0x81000000 0 0x20200000 0x20200000 837 0 0x100000 /* downstream I/O */ 838 0x82000000 0 0x20300000 0x20300000 839 0 0xd00000>; /* non-prefetchable memory */ 840 841 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "msi"; 843 #interrupt-cells = <1>; 844 interrupt-map-mask = <0 0 0 0x7>; 845 interrupt-map = <0 0 0 1 &intc 0 75 846 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 847 <0 0 0 2 &intc 0 78 848 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 849 <0 0 0 3 &intc 0 79 850 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 851 <0 0 0 4 &intc 0 83 852 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 853 854 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 855 <&gcc GCC_PCIE0_AXI_M_CLK>, 856 <&gcc GCC_PCIE0_AXI_S_CLK>, 857 <&gcc GCC_PCIE0_AHB_CLK>, 858 <&gcc GCC_PCIE0_AUX_CLK>; 859 860 clock-names = "iface", 861 "axi_m", 862 "axi_s", 863 "ahb", 864 "aux"; 865 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 866 <&gcc GCC_PCIE0_SLEEP_ARES>, 867 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 868 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 869 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 870 <&gcc GCC_PCIE0_AHB_ARES>, 871 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 872 reset-names = "pipe", 873 "sleep", 874 "sticky", 875 "axi_m", 876 "axi_s", 877 "ahb", 878 "axi_m_sticky"; 879 status = "disabled"; 880 }; 881 }; 882 883 timer { 884 compatible = "arm,armv8-timer"; 885 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 886 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 887 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 888 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 889 }; 890 891 thermal-zones { 892 nss-top-thermal { 893 polling-delay-passive = <250>; 894 polling-delay = <1000>; 895 896 thermal-sensors = <&tsens 4>; 897 }; 898 899 nss0-thermal { 900 polling-delay-passive = <250>; 901 polling-delay = <1000>; 902 903 thermal-sensors = <&tsens 5>; 904 }; 905 906 nss1-thermal { 907 polling-delay-passive = <250>; 908 polling-delay = <1000>; 909 910 thermal-sensors = <&tsens 6>; 911 }; 912 913 wcss-phya0-thermal { 914 polling-delay-passive = <250>; 915 polling-delay = <1000>; 916 917 thermal-sensors = <&tsens 7>; 918 }; 919 920 wcss-phya1-thermal { 921 polling-delay-passive = <250>; 922 polling-delay = <1000>; 923 924 thermal-sensors = <&tsens 8>; 925 }; 926 927 cpu0_thermal: cpu0-thermal { 928 polling-delay-passive = <250>; 929 polling-delay = <1000>; 930 931 thermal-sensors = <&tsens 9>; 932 }; 933 934 cpu1_thermal: cpu1-thermal { 935 polling-delay-passive = <250>; 936 polling-delay = <1000>; 937 938 thermal-sensors = <&tsens 10>; 939 }; 940 941 cpu2_thermal: cpu2-thermal { 942 polling-delay-passive = <250>; 943 polling-delay = <1000>; 944 945 thermal-sensors = <&tsens 11>; 946 }; 947 948 cpu3_thermal: cpu3-thermal { 949 polling-delay-passive = <250>; 950 polling-delay = <1000>; 951 952 thermal-sensors = <&tsens 12>; 953 }; 954 955 cluster_thermal: cluster-thermal { 956 polling-delay-passive = <250>; 957 polling-delay = <1000>; 958 959 thermal-sensors = <&tsens 13>; 960 }; 961 962 wcss-phyb0-thermal { 963 polling-delay-passive = <250>; 964 polling-delay = <1000>; 965 966 thermal-sensors = <&tsens 14>; 967 }; 968 969 wcss-phyb1-thermal { 970 polling-delay-passive = <250>; 971 polling-delay = <1000>; 972 973 thermal-sensors = <&tsens 15>; 974 }; 975 }; 976}; 977