1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 soc: soc { 14 #address-cells = <0x1>; 15 #size-cells = <0x1>; 16 ranges = <0 0 0 0xffffffff>; 17 compatible = "simple-bus"; 18 19 tlmm: pinctrl@1000000 { 20 compatible = "qcom,ipq8074-pinctrl"; 21 reg = <0x1000000 0x300000>; 22 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 23 gpio-controller; 24 #gpio-cells = <0x2>; 25 interrupt-controller; 26 #interrupt-cells = <0x2>; 27 28 serial_4_pins: serial4-pinmux { 29 pins = "gpio23", "gpio24"; 30 function = "blsp4_uart1"; 31 drive-strength = <8>; 32 bias-disable; 33 }; 34 35 i2c_0_pins: i2c-0-pinmux { 36 pins = "gpio42", "gpio43"; 37 function = "blsp1_i2c"; 38 drive-strength = <8>; 39 bias-disable; 40 }; 41 42 spi_0_pins: spi-0-pins { 43 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 44 function = "blsp0_spi"; 45 drive-strength = <8>; 46 bias-disable; 47 }; 48 49 hsuart_pins: hsuart-pins { 50 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 51 function = "blsp2_uart"; 52 drive-strength = <8>; 53 bias-disable; 54 }; 55 56 qpic_pins: qpic-pins { 57 pins = "gpio1", "gpio3", "gpio4", 58 "gpio5", "gpio6", "gpio7", 59 "gpio8", "gpio10", "gpio11", 60 "gpio12", "gpio13", "gpio14", 61 "gpio15", "gpio16", "gpio17"; 62 function = "qpic"; 63 drive-strength = <8>; 64 bias-disable; 65 }; 66 }; 67 68 intc: interrupt-controller@b000000 { 69 compatible = "qcom,msm-qgic2"; 70 interrupt-controller; 71 #interrupt-cells = <0x3>; 72 reg = <0xb000000 0x1000>, <0xb002000 0x1000>; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 78 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 81 }; 82 83 timer@b120000 { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 compatible = "arm,armv7-timer-mem"; 88 reg = <0xb120000 0x1000>; 89 clock-frequency = <19200000>; 90 91 frame@b120000 { 92 frame-number = <0>; 93 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 95 reg = <0xb121000 0x1000>, 96 <0xb122000 0x1000>; 97 }; 98 99 frame@b123000 { 100 frame-number = <1>; 101 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 102 reg = <0xb123000 0x1000>; 103 status = "disabled"; 104 }; 105 106 frame@b124000 { 107 frame-number = <2>; 108 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 109 reg = <0xb124000 0x1000>; 110 status = "disabled"; 111 }; 112 113 frame@b125000 { 114 frame-number = <3>; 115 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 116 reg = <0xb125000 0x1000>; 117 status = "disabled"; 118 }; 119 120 frame@b126000 { 121 frame-number = <4>; 122 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 123 reg = <0xb126000 0x1000>; 124 status = "disabled"; 125 }; 126 127 frame@b127000 { 128 frame-number = <5>; 129 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 130 reg = <0xb127000 0x1000>; 131 status = "disabled"; 132 }; 133 134 frame@b128000 { 135 frame-number = <6>; 136 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 137 reg = <0xb128000 0x1000>; 138 status = "disabled"; 139 }; 140 }; 141 142 gcc: gcc@1800000 { 143 compatible = "qcom,gcc-ipq8074"; 144 reg = <0x1800000 0x80000>; 145 #clock-cells = <0x1>; 146 #reset-cells = <0x1>; 147 }; 148 149 blsp1_uart5: serial@78b3000 { 150 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 151 reg = <0x78b3000 0x200>; 152 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 154 <&gcc GCC_BLSP1_AHB_CLK>; 155 clock-names = "core", "iface"; 156 pinctrl-0 = <&serial_4_pins>; 157 pinctrl-names = "default"; 158 status = "disabled"; 159 }; 160 161 blsp_dma: dma@7884000 { 162 compatible = "qcom,bam-v1.7.0"; 163 reg = <0x7884000 0x2b000>; 164 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 166 clock-names = "bam_clk"; 167 #dma-cells = <1>; 168 qcom,ee = <0>; 169 }; 170 171 blsp1_uart1: serial@78af000 { 172 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 173 reg = <0x78af000 0x200>; 174 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 176 <&gcc GCC_BLSP1_AHB_CLK>; 177 clock-names = "core", "iface"; 178 status = "disabled"; 179 }; 180 181 blsp1_uart3: serial@78b1000 { 182 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 183 reg = <0x78b1000 0x200>; 184 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 186 <&gcc GCC_BLSP1_AHB_CLK>; 187 clock-names = "core", "iface"; 188 dmas = <&blsp_dma 4>, 189 <&blsp_dma 5>; 190 dma-names = "tx", "rx"; 191 pinctrl-0 = <&hsuart_pins>; 192 pinctrl-names = "default"; 193 status = "disabled"; 194 }; 195 196 blsp1_spi1: spi@78b5000 { 197 compatible = "qcom,spi-qup-v2.2.1"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 reg = <0x78b5000 0x600>; 201 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 202 spi-max-frequency = <50000000>; 203 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 204 <&gcc GCC_BLSP1_AHB_CLK>; 205 clock-names = "core", "iface"; 206 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 207 dma-names = "tx", "rx"; 208 pinctrl-0 = <&spi_0_pins>; 209 pinctrl-names = "default"; 210 status = "disabled"; 211 }; 212 213 blsp1_i2c2: i2c@78b6000 { 214 compatible = "qcom,i2c-qup-v2.2.1"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0x78b6000 0x600>; 218 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 220 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 221 clock-names = "iface", "core"; 222 clock-frequency = <400000>; 223 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 224 dma-names = "rx", "tx"; 225 pinctrl-0 = <&i2c_0_pins>; 226 pinctrl-names = "default"; 227 status = "disabled"; 228 }; 229 230 blsp1_i2c3: i2c@78b7000 { 231 compatible = "qcom,i2c-qup-v2.2.1"; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x78b7000 0x600>; 235 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 237 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 238 clock-names = "iface", "core"; 239 clock-frequency = <100000>; 240 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 241 dma-names = "rx", "tx"; 242 status = "disabled"; 243 }; 244 245 qpic_bam: dma@7984000 { 246 compatible = "qcom,bam-v1.7.0"; 247 reg = <0x7984000 0x1a000>; 248 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&gcc GCC_QPIC_AHB_CLK>; 250 clock-names = "bam_clk"; 251 #dma-cells = <1>; 252 qcom,ee = <0>; 253 status = "disabled"; 254 }; 255 256 qpic_nand: nand@79b0000 { 257 compatible = "qcom,ipq8074-nand"; 258 reg = <0x79b0000 0x10000>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 clocks = <&gcc GCC_QPIC_CLK>, 262 <&gcc GCC_QPIC_AHB_CLK>; 263 clock-names = "core", "aon"; 264 265 dmas = <&qpic_bam 0>, 266 <&qpic_bam 1>, 267 <&qpic_bam 2>; 268 dma-names = "tx", "rx", "cmd"; 269 pinctrl-0 = <&qpic_pins>; 270 pinctrl-names = "default"; 271 status = "disabled"; 272 }; 273 274 pcie_phy0: phy@86000 { 275 compatible = "qcom,ipq8074-qmp-pcie-phy"; 276 reg = <0x86000 0x1000>; 277 #phy-cells = <0>; 278 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 279 clock-names = "pipe_clk"; 280 clock-output-names = "pcie20_phy0_pipe_clk"; 281 282 resets = <&gcc GCC_PCIE0_PHY_BCR>, 283 <&gcc GCC_PCIE0PHY_PHY_BCR>; 284 reset-names = "phy", 285 "common"; 286 status = "disabled"; 287 }; 288 289 pcie0: pci@20000000 { 290 compatible = "qcom,pcie-ipq8074"; 291 reg = <0x20000000 0xf1d 292 0x20000f20 0xa8 293 0x80000 0x2000 294 0x20100000 0x1000>; 295 reg-names = "dbi", "elbi", "parf", "config"; 296 device_type = "pci"; 297 linux,pci-domain = <0>; 298 bus-range = <0x00 0xff>; 299 num-lanes = <1>; 300 #address-cells = <3>; 301 #size-cells = <2>; 302 303 phys = <&pcie_phy0>; 304 phy-names = "pciephy"; 305 306 ranges = <0x81000000 0 0x20200000 0x20200000 307 0 0x100000 /* downstream I/O */ 308 0x82000000 0 0x20300000 0x20300000 309 0 0xd00000>; /* non-prefetchable memory */ 310 311 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 312 interrupt-names = "msi"; 313 #interrupt-cells = <1>; 314 interrupt-map-mask = <0 0 0 0x7>; 315 interrupt-map = <0 0 0 1 &intc 0 75 316 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 317 <0 0 0 2 &intc 0 78 318 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 319 <0 0 0 3 &intc 0 79 320 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 321 <0 0 0 4 &intc 0 83 322 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 323 324 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 325 <&gcc GCC_PCIE0_AXI_M_CLK>, 326 <&gcc GCC_PCIE0_AXI_S_CLK>, 327 <&gcc GCC_PCIE0_AHB_CLK>, 328 <&gcc GCC_PCIE0_AUX_CLK>; 329 330 clock-names = "iface", 331 "axi_m", 332 "axi_s", 333 "ahb", 334 "aux"; 335 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 336 <&gcc GCC_PCIE0_SLEEP_ARES>, 337 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 338 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 339 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 340 <&gcc GCC_PCIE0_AHB_ARES>, 341 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 342 reset-names = "pipe", 343 "sleep", 344 "sticky", 345 "axi_m", 346 "axi_s", 347 "ahb", 348 "axi_m_sticky"; 349 status = "disabled"; 350 }; 351 352 pcie_phy1: phy@8e000 { 353 compatible = "qcom,ipq8074-qmp-pcie-phy"; 354 reg = <0x8e000 0x1000>; 355 #phy-cells = <0>; 356 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 357 clock-names = "pipe_clk"; 358 clock-output-names = "pcie20_phy1_pipe_clk"; 359 360 resets = <&gcc GCC_PCIE1_PHY_BCR>, 361 <&gcc GCC_PCIE1PHY_PHY_BCR>; 362 reset-names = "phy", 363 "common"; 364 status = "disabled"; 365 }; 366 367 pcie1: pci@10000000 { 368 compatible = "qcom,pcie-ipq8074"; 369 reg = <0x10000000 0xf1d 370 0x10000f20 0xa8 371 0x88000 0x2000 372 0x10100000 0x1000>; 373 reg-names = "dbi", "elbi", "parf", "config"; 374 device_type = "pci"; 375 linux,pci-domain = <1>; 376 bus-range = <0x00 0xff>; 377 num-lanes = <1>; 378 #address-cells = <3>; 379 #size-cells = <2>; 380 381 phys = <&pcie_phy1>; 382 phy-names = "pciephy"; 383 384 ranges = <0x81000000 0 0x10200000 0x10200000 385 0 0x100000 /* downstream I/O */ 386 0x82000000 0 0x10300000 0x10300000 387 0 0xd00000>; /* non-prefetchable memory */ 388 389 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "msi"; 391 #interrupt-cells = <1>; 392 interrupt-map-mask = <0 0 0 0x7>; 393 interrupt-map = <0 0 0 1 &intc 0 142 394 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 395 <0 0 0 2 &intc 0 143 396 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 397 <0 0 0 3 &intc 0 144 398 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 399 <0 0 0 4 &intc 0 145 400 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 401 402 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 403 <&gcc GCC_PCIE1_AXI_M_CLK>, 404 <&gcc GCC_PCIE1_AXI_S_CLK>, 405 <&gcc GCC_PCIE1_AHB_CLK>, 406 <&gcc GCC_PCIE1_AUX_CLK>; 407 clock-names = "iface", 408 "axi_m", 409 "axi_s", 410 "ahb", 411 "aux"; 412 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 413 <&gcc GCC_PCIE1_SLEEP_ARES>, 414 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 415 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 416 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 417 <&gcc GCC_PCIE1_AHB_ARES>, 418 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 419 reset-names = "pipe", 420 "sleep", 421 "sticky", 422 "axi_m", 423 "axi_s", 424 "ahb", 425 "axi_m_sticky"; 426 status = "disabled"; 427 }; 428 }; 429 430 cpus { 431 #address-cells = <0x1>; 432 #size-cells = <0x0>; 433 434 CPU0: cpu@0 { 435 device_type = "cpu"; 436 compatible = "arm,cortex-a53"; 437 reg = <0x0>; 438 next-level-cache = <&L2_0>; 439 enable-method = "psci"; 440 }; 441 442 CPU1: cpu@1 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a53"; 445 enable-method = "psci"; 446 reg = <0x1>; 447 next-level-cache = <&L2_0>; 448 }; 449 450 CPU2: cpu@2 { 451 device_type = "cpu"; 452 compatible = "arm,cortex-a53"; 453 enable-method = "psci"; 454 reg = <0x2>; 455 next-level-cache = <&L2_0>; 456 }; 457 458 CPU3: cpu@3 { 459 device_type = "cpu"; 460 compatible = "arm,cortex-a53"; 461 enable-method = "psci"; 462 reg = <0x3>; 463 next-level-cache = <&L2_0>; 464 }; 465 466 L2_0: l2-cache { 467 compatible = "cache"; 468 cache-level = <0x2>; 469 }; 470 }; 471 472 psci { 473 compatible = "arm,psci-1.0"; 474 method = "smc"; 475 }; 476 477 pmu { 478 compatible = "arm,armv8-pmuv3"; 479 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 480 }; 481 482 clocks { 483 sleep_clk: sleep_clk { 484 compatible = "fixed-clock"; 485 clock-frequency = <32000>; 486 #clock-cells = <0>; 487 }; 488 489 xo: xo { 490 compatible = "fixed-clock"; 491 clock-frequency = <19200000>; 492 #clock-cells = <0>; 493 }; 494 }; 495}; 496