1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32000>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 soc: soc { 80 #address-cells = <0x1>; 81 #size-cells = <0x1>; 82 ranges = <0 0 0 0xffffffff>; 83 compatible = "simple-bus"; 84 85 ssphy_1: phy@58000 { 86 compatible = "qcom,ipq8074-qmp-usb3-phy"; 87 reg = <0x00058000 0x1c4>; 88 #clock-cells = <1>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 93 clocks = <&gcc GCC_USB1_AUX_CLK>, 94 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 95 <&xo>; 96 clock-names = "aux", "cfg_ahb", "ref"; 97 98 resets = <&gcc GCC_USB1_PHY_BCR>, 99 <&gcc GCC_USB3PHY_1_PHY_BCR>; 100 reset-names = "phy","common"; 101 status = "disabled"; 102 103 usb1_ssphy: lane@58200 { 104 reg = <0x00058200 0x130>, /* Tx */ 105 <0x00058400 0x200>, /* Rx */ 106 <0x00058800 0x1f8>, /* PCS */ 107 <0x00058600 0x044>; /* PCS misc*/ 108 #phy-cells = <0>; 109 clocks = <&gcc GCC_USB1_PIPE_CLK>; 110 clock-names = "pipe0"; 111 clock-output-names = "gcc_usb1_pipe_clk_src"; 112 }; 113 }; 114 115 qusb_phy_1: phy@59000 { 116 compatible = "qcom,ipq8074-qusb2-phy"; 117 reg = <0x00059000 0x180>; 118 #phy-cells = <0>; 119 120 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 121 <&xo>; 122 clock-names = "cfg_ahb", "ref"; 123 124 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 125 status = "disabled"; 126 }; 127 128 ssphy_0: phy@78000 { 129 compatible = "qcom,ipq8074-qmp-usb3-phy"; 130 reg = <0x00078000 0x1c4>; 131 #clock-cells = <1>; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 136 clocks = <&gcc GCC_USB0_AUX_CLK>, 137 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 138 <&xo>; 139 clock-names = "aux", "cfg_ahb", "ref"; 140 141 resets = <&gcc GCC_USB0_PHY_BCR>, 142 <&gcc GCC_USB3PHY_0_PHY_BCR>; 143 reset-names = "phy","common"; 144 status = "disabled"; 145 146 usb0_ssphy: lane@78200 { 147 reg = <0x00078200 0x130>, /* Tx */ 148 <0x00078400 0x200>, /* Rx */ 149 <0x00078800 0x1f8>, /* PCS */ 150 <0x00078600 0x044>; /* PCS misc*/ 151 #phy-cells = <0>; 152 clocks = <&gcc GCC_USB0_PIPE_CLK>; 153 clock-names = "pipe0"; 154 clock-output-names = "gcc_usb0_pipe_clk_src"; 155 }; 156 }; 157 158 qusb_phy_0: phy@79000 { 159 compatible = "qcom,ipq8074-qusb2-phy"; 160 reg = <0x00079000 0x180>; 161 #phy-cells = <0>; 162 163 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 164 <&xo>; 165 clock-names = "cfg_ahb", "ref"; 166 167 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 168 status = "disabled"; 169 }; 170 171 pcie_phy0: phy@86000 { 172 compatible = "qcom,ipq8074-qmp-pcie-phy"; 173 reg = <0x00086000 0x1000>; 174 #phy-cells = <0>; 175 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 176 clock-names = "pipe_clk"; 177 clock-output-names = "pcie20_phy0_pipe_clk"; 178 179 resets = <&gcc GCC_PCIE0_PHY_BCR>, 180 <&gcc GCC_PCIE0PHY_PHY_BCR>; 181 reset-names = "phy", 182 "common"; 183 status = "disabled"; 184 }; 185 186 pcie_phy1: phy@8e000 { 187 compatible = "qcom,ipq8074-qmp-pcie-phy"; 188 reg = <0x0008e000 0x1000>; 189 #phy-cells = <0>; 190 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 191 clock-names = "pipe_clk"; 192 clock-output-names = "pcie20_phy1_pipe_clk"; 193 194 resets = <&gcc GCC_PCIE1_PHY_BCR>, 195 <&gcc GCC_PCIE1PHY_PHY_BCR>; 196 reset-names = "phy", 197 "common"; 198 status = "disabled"; 199 }; 200 201 tlmm: pinctrl@1000000 { 202 compatible = "qcom,ipq8074-pinctrl"; 203 reg = <0x01000000 0x300000>; 204 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 205 gpio-controller; 206 gpio-ranges = <&tlmm 0 0 70>; 207 #gpio-cells = <0x2>; 208 interrupt-controller; 209 #interrupt-cells = <0x2>; 210 211 serial_4_pins: serial4-pinmux { 212 pins = "gpio23", "gpio24"; 213 function = "blsp4_uart1"; 214 drive-strength = <8>; 215 bias-disable; 216 }; 217 218 i2c_0_pins: i2c-0-pinmux { 219 pins = "gpio42", "gpio43"; 220 function = "blsp1_i2c"; 221 drive-strength = <8>; 222 bias-disable; 223 }; 224 225 spi_0_pins: spi-0-pins { 226 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 227 function = "blsp0_spi"; 228 drive-strength = <8>; 229 bias-disable; 230 }; 231 232 hsuart_pins: hsuart-pins { 233 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 234 function = "blsp2_uart"; 235 drive-strength = <8>; 236 bias-disable; 237 }; 238 239 qpic_pins: qpic-pins { 240 pins = "gpio1", "gpio3", "gpio4", 241 "gpio5", "gpio6", "gpio7", 242 "gpio8", "gpio10", "gpio11", 243 "gpio12", "gpio13", "gpio14", 244 "gpio15", "gpio16", "gpio17"; 245 function = "qpic"; 246 drive-strength = <8>; 247 bias-disable; 248 }; 249 }; 250 251 gcc: gcc@1800000 { 252 compatible = "qcom,gcc-ipq8074"; 253 reg = <0x01800000 0x80000>; 254 #clock-cells = <0x1>; 255 #reset-cells = <0x1>; 256 }; 257 258 sdhc_1: sdhci@7824900 { 259 compatible = "qcom,sdhci-msm-v4"; 260 reg = <0x7824900 0x500>, <0x7824000 0x800>; 261 reg-names = "hc_mem", "core_mem"; 262 263 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "hc_irq", "pwr_irq"; 266 267 clocks = <&xo>, 268 <&gcc GCC_SDCC1_AHB_CLK>, 269 <&gcc GCC_SDCC1_APPS_CLK>; 270 clock-names = "xo", "iface", "core"; 271 max-frequency = <384000000>; 272 mmc-ddr-1_8v; 273 mmc-hs200-1_8v; 274 mmc-hs400-1_8v; 275 bus-width = <8>; 276 277 status = "disabled"; 278 }; 279 280 blsp_dma: dma-controller@7884000 { 281 compatible = "qcom,bam-v1.7.0"; 282 reg = <0x07884000 0x2b000>; 283 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 285 clock-names = "bam_clk"; 286 #dma-cells = <1>; 287 qcom,ee = <0>; 288 }; 289 290 blsp1_uart1: serial@78af000 { 291 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 292 reg = <0x078af000 0x200>; 293 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 295 <&gcc GCC_BLSP1_AHB_CLK>; 296 clock-names = "core", "iface"; 297 status = "disabled"; 298 }; 299 300 blsp1_uart3: serial@78b1000 { 301 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 302 reg = <0x078b1000 0x200>; 303 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 305 <&gcc GCC_BLSP1_AHB_CLK>; 306 clock-names = "core", "iface"; 307 dmas = <&blsp_dma 4>, 308 <&blsp_dma 5>; 309 dma-names = "tx", "rx"; 310 pinctrl-0 = <&hsuart_pins>; 311 pinctrl-names = "default"; 312 status = "disabled"; 313 }; 314 315 blsp1_uart5: serial@78b3000 { 316 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 317 reg = <0x078b3000 0x200>; 318 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 320 <&gcc GCC_BLSP1_AHB_CLK>; 321 clock-names = "core", "iface"; 322 pinctrl-0 = <&serial_4_pins>; 323 pinctrl-names = "default"; 324 status = "disabled"; 325 }; 326 327 blsp1_spi1: spi@78b5000 { 328 compatible = "qcom,spi-qup-v2.2.1"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0x078b5000 0x600>; 332 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 333 spi-max-frequency = <50000000>; 334 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 335 <&gcc GCC_BLSP1_AHB_CLK>; 336 clock-names = "core", "iface"; 337 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 338 dma-names = "tx", "rx"; 339 pinctrl-0 = <&spi_0_pins>; 340 pinctrl-names = "default"; 341 status = "disabled"; 342 }; 343 344 blsp1_i2c2: i2c@78b6000 { 345 compatible = "qcom,i2c-qup-v2.2.1"; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 reg = <0x078b6000 0x600>; 349 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 351 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 352 clock-names = "iface", "core"; 353 clock-frequency = <400000>; 354 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 355 dma-names = "rx", "tx"; 356 pinctrl-0 = <&i2c_0_pins>; 357 pinctrl-names = "default"; 358 status = "disabled"; 359 }; 360 361 blsp1_i2c3: i2c@78b7000 { 362 compatible = "qcom,i2c-qup-v2.2.1"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <0x078b7000 0x600>; 366 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 368 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 369 clock-names = "iface", "core"; 370 clock-frequency = <100000>; 371 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 372 dma-names = "rx", "tx"; 373 status = "disabled"; 374 }; 375 376 qpic_bam: dma-controller@7984000 { 377 compatible = "qcom,bam-v1.7.0"; 378 reg = <0x07984000 0x1a000>; 379 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&gcc GCC_QPIC_AHB_CLK>; 381 clock-names = "bam_clk"; 382 #dma-cells = <1>; 383 qcom,ee = <0>; 384 status = "disabled"; 385 }; 386 387 qpic_nand: nand@79b0000 { 388 compatible = "qcom,ipq8074-nand"; 389 reg = <0x079b0000 0x10000>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&gcc GCC_QPIC_CLK>, 393 <&gcc GCC_QPIC_AHB_CLK>; 394 clock-names = "core", "aon"; 395 396 dmas = <&qpic_bam 0>, 397 <&qpic_bam 1>, 398 <&qpic_bam 2>; 399 dma-names = "tx", "rx", "cmd"; 400 pinctrl-0 = <&qpic_pins>; 401 pinctrl-names = "default"; 402 status = "disabled"; 403 }; 404 405 usb_0: usb@8af8800 { 406 compatible = "qcom,dwc3"; 407 reg = <0x08af8800 0x400>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges; 411 412 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 413 <&gcc GCC_USB0_MASTER_CLK>, 414 <&gcc GCC_USB0_SLEEP_CLK>, 415 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 416 clock-names = "sys_noc_axi", 417 "master", 418 "sleep", 419 "mock_utmi"; 420 421 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 422 <&gcc GCC_USB0_MASTER_CLK>, 423 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 424 assigned-clock-rates = <133330000>, 425 <133330000>, 426 <19200000>; 427 428 resets = <&gcc GCC_USB0_BCR>; 429 status = "disabled"; 430 431 dwc_0: usb@8a00000 { 432 compatible = "snps,dwc3"; 433 reg = <0x8a00000 0xcd00>; 434 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 435 phys = <&qusb_phy_0>, <&usb0_ssphy>; 436 phy-names = "usb2-phy", "usb3-phy"; 437 tx-fifo-resize; 438 snps,is-utmi-l1-suspend; 439 snps,hird-threshold = /bits/ 8 <0x0>; 440 snps,dis_u2_susphy_quirk; 441 snps,dis_u3_susphy_quirk; 442 dr_mode = "host"; 443 }; 444 }; 445 446 usb_1: usb@8cf8800 { 447 compatible = "qcom,dwc3"; 448 reg = <0x08cf8800 0x400>; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 ranges; 452 453 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 454 <&gcc GCC_USB1_MASTER_CLK>, 455 <&gcc GCC_USB1_SLEEP_CLK>, 456 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 457 clock-names = "sys_noc_axi", 458 "master", 459 "sleep", 460 "mock_utmi"; 461 462 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 463 <&gcc GCC_USB1_MASTER_CLK>, 464 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 465 assigned-clock-rates = <133330000>, 466 <133330000>, 467 <19200000>; 468 469 resets = <&gcc GCC_USB1_BCR>; 470 status = "disabled"; 471 472 dwc_1: usb@8c00000 { 473 compatible = "snps,dwc3"; 474 reg = <0x8c00000 0xcd00>; 475 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 476 phys = <&qusb_phy_1>, <&usb1_ssphy>; 477 phy-names = "usb2-phy", "usb3-phy"; 478 tx-fifo-resize; 479 snps,is-utmi-l1-suspend; 480 snps,hird-threshold = /bits/ 8 <0x0>; 481 snps,dis_u2_susphy_quirk; 482 snps,dis_u3_susphy_quirk; 483 dr_mode = "host"; 484 }; 485 }; 486 487 intc: interrupt-controller@b000000 { 488 compatible = "qcom,msm-qgic2"; 489 interrupt-controller; 490 #interrupt-cells = <0x3>; 491 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 492 }; 493 494 timer { 495 compatible = "arm,armv8-timer"; 496 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 497 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 498 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 499 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 500 }; 501 502 watchdog: watchdog@b017000 { 503 compatible = "qcom,kpss-wdt"; 504 reg = <0xb017000 0x1000>; 505 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 506 clocks = <&sleep_clk>; 507 timeout-sec = <30>; 508 }; 509 510 timer@b120000 { 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges; 514 compatible = "arm,armv7-timer-mem"; 515 reg = <0x0b120000 0x1000>; 516 clock-frequency = <19200000>; 517 518 frame@b120000 { 519 frame-number = <0>; 520 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 522 reg = <0x0b121000 0x1000>, 523 <0x0b122000 0x1000>; 524 }; 525 526 frame@b123000 { 527 frame-number = <1>; 528 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 529 reg = <0x0b123000 0x1000>; 530 status = "disabled"; 531 }; 532 533 frame@b124000 { 534 frame-number = <2>; 535 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 536 reg = <0x0b124000 0x1000>; 537 status = "disabled"; 538 }; 539 540 frame@b125000 { 541 frame-number = <3>; 542 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 543 reg = <0x0b125000 0x1000>; 544 status = "disabled"; 545 }; 546 547 frame@b126000 { 548 frame-number = <4>; 549 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 550 reg = <0x0b126000 0x1000>; 551 status = "disabled"; 552 }; 553 554 frame@b127000 { 555 frame-number = <5>; 556 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 557 reg = <0x0b127000 0x1000>; 558 status = "disabled"; 559 }; 560 561 frame@b128000 { 562 frame-number = <6>; 563 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 564 reg = <0x0b128000 0x1000>; 565 status = "disabled"; 566 }; 567 }; 568 569 pcie1: pci@10000000 { 570 compatible = "qcom,pcie-ipq8074"; 571 reg = <0x10000000 0xf1d 572 0x10000f20 0xa8 573 0x00088000 0x2000 574 0x10100000 0x1000>; 575 reg-names = "dbi", "elbi", "parf", "config"; 576 device_type = "pci"; 577 linux,pci-domain = <1>; 578 bus-range = <0x00 0xff>; 579 num-lanes = <1>; 580 #address-cells = <3>; 581 #size-cells = <2>; 582 583 phys = <&pcie_phy1>; 584 phy-names = "pciephy"; 585 586 ranges = <0x81000000 0 0x10200000 0x10200000 587 0 0x100000 /* downstream I/O */ 588 0x82000000 0 0x10300000 0x10300000 589 0 0xd00000>; /* non-prefetchable memory */ 590 591 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "msi"; 593 #interrupt-cells = <1>; 594 interrupt-map-mask = <0 0 0 0x7>; 595 interrupt-map = <0 0 0 1 &intc 0 142 596 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 597 <0 0 0 2 &intc 0 143 598 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 599 <0 0 0 3 &intc 0 144 600 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 601 <0 0 0 4 &intc 0 145 602 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 603 604 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 605 <&gcc GCC_PCIE1_AXI_M_CLK>, 606 <&gcc GCC_PCIE1_AXI_S_CLK>, 607 <&gcc GCC_PCIE1_AHB_CLK>, 608 <&gcc GCC_PCIE1_AUX_CLK>; 609 clock-names = "iface", 610 "axi_m", 611 "axi_s", 612 "ahb", 613 "aux"; 614 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 615 <&gcc GCC_PCIE1_SLEEP_ARES>, 616 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 617 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 618 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 619 <&gcc GCC_PCIE1_AHB_ARES>, 620 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 621 reset-names = "pipe", 622 "sleep", 623 "sticky", 624 "axi_m", 625 "axi_s", 626 "ahb", 627 "axi_m_sticky"; 628 status = "disabled"; 629 }; 630 631 pcie0: pci@20000000 { 632 compatible = "qcom,pcie-ipq8074"; 633 reg = <0x20000000 0xf1d 634 0x20000f20 0xa8 635 0x00080000 0x2000 636 0x20100000 0x1000>; 637 reg-names = "dbi", "elbi", "parf", "config"; 638 device_type = "pci"; 639 linux,pci-domain = <0>; 640 bus-range = <0x00 0xff>; 641 num-lanes = <1>; 642 #address-cells = <3>; 643 #size-cells = <2>; 644 645 phys = <&pcie_phy0>; 646 phy-names = "pciephy"; 647 648 ranges = <0x81000000 0 0x20200000 0x20200000 649 0 0x100000 /* downstream I/O */ 650 0x82000000 0 0x20300000 0x20300000 651 0 0xd00000>; /* non-prefetchable memory */ 652 653 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "msi"; 655 #interrupt-cells = <1>; 656 interrupt-map-mask = <0 0 0 0x7>; 657 interrupt-map = <0 0 0 1 &intc 0 75 658 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 659 <0 0 0 2 &intc 0 78 660 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 661 <0 0 0 3 &intc 0 79 662 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 663 <0 0 0 4 &intc 0 83 664 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 665 666 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 667 <&gcc GCC_PCIE0_AXI_M_CLK>, 668 <&gcc GCC_PCIE0_AXI_S_CLK>, 669 <&gcc GCC_PCIE0_AHB_CLK>, 670 <&gcc GCC_PCIE0_AUX_CLK>; 671 672 clock-names = "iface", 673 "axi_m", 674 "axi_s", 675 "ahb", 676 "aux"; 677 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 678 <&gcc GCC_PCIE0_SLEEP_ARES>, 679 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 680 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 681 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 682 <&gcc GCC_PCIE0_AHB_ARES>, 683 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 684 reset-names = "pipe", 685 "sleep", 686 "sticky", 687 "axi_m", 688 "axi_s", 689 "ahb", 690 "axi_m_sticky"; 691 status = "disabled"; 692 }; 693 }; 694}; 695