1/* 2 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 16 17/ { 18 model = "Qualcomm Technologies, Inc. IPQ8074"; 19 compatible = "qcom,ipq8074"; 20 21 soc: soc { 22 #address-cells = <0x1>; 23 #size-cells = <0x1>; 24 ranges = <0 0 0 0xffffffff>; 25 compatible = "simple-bus"; 26 27 tlmm: pinctrl@1000000 { 28 compatible = "qcom,ipq8074-pinctrl"; 29 reg = <0x1000000 0x300000>; 30 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 31 gpio-controller; 32 #gpio-cells = <0x2>; 33 interrupt-controller; 34 #interrupt-cells = <0x2>; 35 36 serial_4_pins: serial4-pinmux { 37 pins = "gpio23", "gpio24"; 38 function = "blsp4_uart1"; 39 drive-strength = <8>; 40 bias-disable; 41 }; 42 43 i2c_0_pins: i2c-0-pinmux { 44 pins = "gpio42", "gpio43"; 45 function = "blsp1_i2c"; 46 drive-strength = <8>; 47 bias-disable; 48 }; 49 50 spi_0_pins: spi-0-pins { 51 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 52 function = "blsp0_spi"; 53 drive-strength = <8>; 54 bias-disable; 55 }; 56 57 hsuart_pins: hsuart-pins { 58 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 59 function = "blsp2_uart"; 60 drive-strength = <8>; 61 bias-disable; 62 }; 63 64 qpic_pins: qpic-pins { 65 pins = "gpio1", "gpio3", "gpio4", 66 "gpio5", "gpio6", "gpio7", 67 "gpio8", "gpio10", "gpio11", 68 "gpio12", "gpio13", "gpio14", 69 "gpio15", "gpio16", "gpio17"; 70 function = "qpic"; 71 drive-strength = <8>; 72 bias-disable; 73 }; 74 }; 75 76 intc: interrupt-controller@b000000 { 77 compatible = "qcom,msm-qgic2"; 78 interrupt-controller; 79 #interrupt-cells = <0x3>; 80 reg = <0xb000000 0x1000>, <0xb002000 0x1000>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 89 }; 90 91 timer@b120000 { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 compatible = "arm,armv7-timer-mem"; 96 reg = <0xb120000 0x1000>; 97 clock-frequency = <19200000>; 98 99 frame@b120000 { 100 frame-number = <0>; 101 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 103 reg = <0xb121000 0x1000>, 104 <0xb122000 0x1000>; 105 }; 106 107 frame@b123000 { 108 frame-number = <1>; 109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 110 reg = <0xb123000 0x1000>; 111 status = "disabled"; 112 }; 113 114 frame@b124000 { 115 frame-number = <2>; 116 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 117 reg = <0xb124000 0x1000>; 118 status = "disabled"; 119 }; 120 121 frame@b125000 { 122 frame-number = <3>; 123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 124 reg = <0xb125000 0x1000>; 125 status = "disabled"; 126 }; 127 128 frame@b126000 { 129 frame-number = <4>; 130 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 131 reg = <0xb126000 0x1000>; 132 status = "disabled"; 133 }; 134 135 frame@b127000 { 136 frame-number = <5>; 137 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 138 reg = <0xb127000 0x1000>; 139 status = "disabled"; 140 }; 141 142 frame@b128000 { 143 frame-number = <6>; 144 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 145 reg = <0xb128000 0x1000>; 146 status = "disabled"; 147 }; 148 }; 149 150 gcc: gcc@1800000 { 151 compatible = "qcom,gcc-ipq8074"; 152 reg = <0x1800000 0x80000>; 153 #clock-cells = <0x1>; 154 #reset-cells = <0x1>; 155 }; 156 157 blsp1_uart5: serial@78b3000 { 158 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 159 reg = <0x78b3000 0x200>; 160 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 162 <&gcc GCC_BLSP1_AHB_CLK>; 163 clock-names = "core", "iface"; 164 pinctrl-0 = <&serial_4_pins>; 165 pinctrl-names = "default"; 166 status = "disabled"; 167 }; 168 169 blsp_dma: dma@7884000 { 170 compatible = "qcom,bam-v1.7.0"; 171 reg = <0x7884000 0x2b000>; 172 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 174 clock-names = "bam_clk"; 175 #dma-cells = <1>; 176 qcom,ee = <0>; 177 }; 178 179 blsp1_uart1: serial@78af000 { 180 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 181 reg = <0x78af000 0x200>; 182 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 184 <&gcc GCC_BLSP1_AHB_CLK>; 185 clock-names = "core", "iface"; 186 status = "disabled"; 187 }; 188 189 blsp1_uart3: serial@78b1000 { 190 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 191 reg = <0x78b1000 0x200>; 192 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 194 <&gcc GCC_BLSP1_AHB_CLK>; 195 clock-names = "core", "iface"; 196 dmas = <&blsp_dma 4>, 197 <&blsp_dma 5>; 198 dma-names = "tx", "rx"; 199 pinctrl-0 = <&hsuart_pins>; 200 pinctrl-names = "default"; 201 status = "disabled"; 202 }; 203 204 blsp1_spi1: spi@78b5000 { 205 compatible = "qcom,spi-qup-v2.2.1"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 reg = <0x78b5000 0x600>; 209 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 210 spi-max-frequency = <50000000>; 211 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 212 <&gcc GCC_BLSP1_AHB_CLK>; 213 clock-names = "core", "iface"; 214 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 215 dma-names = "tx", "rx"; 216 pinctrl-0 = <&spi_0_pins>; 217 pinctrl-names = "default"; 218 status = "disabled"; 219 }; 220 221 blsp1_i2c2: i2c@78b6000 { 222 compatible = "qcom,i2c-qup-v2.2.1"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 reg = <0x78b6000 0x600>; 226 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 228 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 229 clock-names = "iface", "core"; 230 clock-frequency = <400000>; 231 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 232 dma-names = "rx", "tx"; 233 pinctrl-0 = <&i2c_0_pins>; 234 pinctrl-names = "default"; 235 status = "disabled"; 236 }; 237 238 blsp1_i2c3: i2c@78b7000 { 239 compatible = "qcom,i2c-qup-v2.2.1"; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 reg = <0x78b7000 0x600>; 243 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 245 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 246 clock-names = "iface", "core"; 247 clock-frequency = <100000>; 248 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 249 dma-names = "rx", "tx"; 250 status = "disabled"; 251 }; 252 253 qpic_bam: dma@7984000 { 254 compatible = "qcom,bam-v1.7.0"; 255 reg = <0x7984000 0x1a000>; 256 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&gcc GCC_QPIC_AHB_CLK>; 258 clock-names = "bam_clk"; 259 #dma-cells = <1>; 260 qcom,ee = <0>; 261 status = "disabled"; 262 }; 263 264 qpic_nand: nand@79b0000 { 265 compatible = "qcom,ipq8074-nand"; 266 reg = <0x79b0000 0x10000>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&gcc GCC_QPIC_CLK>, 270 <&gcc GCC_QPIC_AHB_CLK>; 271 clock-names = "core", "aon"; 272 273 dmas = <&qpic_bam 0>, 274 <&qpic_bam 1>, 275 <&qpic_bam 2>; 276 dma-names = "tx", "rx", "cmd"; 277 pinctrl-0 = <&qpic_pins>; 278 pinctrl-names = "default"; 279 status = "disabled"; 280 }; 281 282 pcie_phy0: phy@86000 { 283 compatible = "qcom,ipq8074-qmp-pcie-phy"; 284 reg = <0x86000 0x1000>; 285 #phy-cells = <0>; 286 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 287 clock-names = "pipe_clk"; 288 clock-output-names = "pcie20_phy0_pipe_clk"; 289 290 resets = <&gcc GCC_PCIE0_PHY_BCR>, 291 <&gcc GCC_PCIE0PHY_PHY_BCR>; 292 reset-names = "phy", 293 "common"; 294 status = "disabled"; 295 }; 296 297 pcie0: pci@20000000 { 298 compatible = "qcom,pcie-ipq8074"; 299 reg = <0x20000000 0xf1d 300 0x20000f20 0xa8 301 0x80000 0x2000 302 0x20100000 0x1000>; 303 reg-names = "dbi", "elbi", "parf", "config"; 304 device_type = "pci"; 305 linux,pci-domain = <0>; 306 bus-range = <0x00 0xff>; 307 num-lanes = <1>; 308 #address-cells = <3>; 309 #size-cells = <2>; 310 311 phys = <&pcie_phy0>; 312 phy-names = "pciephy"; 313 314 ranges = <0x81000000 0 0x20200000 0x20200000 315 0 0x100000 /* downstream I/O */ 316 0x82000000 0 0x20300000 0x20300000 317 0 0xd00000>; /* non-prefetchable memory */ 318 319 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-names = "msi"; 321 #interrupt-cells = <1>; 322 interrupt-map-mask = <0 0 0 0x7>; 323 interrupt-map = <0 0 0 1 &intc 0 75 324 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 325 <0 0 0 2 &intc 0 78 326 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 327 <0 0 0 3 &intc 0 79 328 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 329 <0 0 0 4 &intc 0 83 330 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 331 332 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 333 <&gcc GCC_PCIE0_AXI_M_CLK>, 334 <&gcc GCC_PCIE0_AXI_S_CLK>, 335 <&gcc GCC_PCIE0_AHB_CLK>, 336 <&gcc GCC_PCIE0_AUX_CLK>; 337 338 clock-names = "iface", 339 "axi_m", 340 "axi_s", 341 "ahb", 342 "aux"; 343 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 344 <&gcc GCC_PCIE0_SLEEP_ARES>, 345 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 346 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 347 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 348 <&gcc GCC_PCIE0_AHB_ARES>, 349 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 350 reset-names = "pipe", 351 "sleep", 352 "sticky", 353 "axi_m", 354 "axi_s", 355 "ahb", 356 "axi_m_sticky"; 357 status = "disabled"; 358 }; 359 360 pcie_phy1: phy@8e000 { 361 compatible = "qcom,ipq8074-qmp-pcie-phy"; 362 reg = <0x8e000 0x1000>; 363 #phy-cells = <0>; 364 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 365 clock-names = "pipe_clk"; 366 clock-output-names = "pcie20_phy1_pipe_clk"; 367 368 resets = <&gcc GCC_PCIE1_PHY_BCR>, 369 <&gcc GCC_PCIE1PHY_PHY_BCR>; 370 reset-names = "phy", 371 "common"; 372 status = "disabled"; 373 }; 374 375 pcie1: pci@10000000 { 376 compatible = "qcom,pcie-ipq8074"; 377 reg = <0x10000000 0xf1d 378 0x10000f20 0xa8 379 0x88000 0x2000 380 0x10100000 0x1000>; 381 reg-names = "dbi", "elbi", "parf", "config"; 382 device_type = "pci"; 383 linux,pci-domain = <1>; 384 bus-range = <0x00 0xff>; 385 num-lanes = <1>; 386 #address-cells = <3>; 387 #size-cells = <2>; 388 389 phys = <&pcie_phy1>; 390 phy-names = "pciephy"; 391 392 ranges = <0x81000000 0 0x10200000 0x10200000 393 0 0x100000 /* downstream I/O */ 394 0x82000000 0 0x10300000 0x10300000 395 0 0xd00000>; /* non-prefetchable memory */ 396 397 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "msi"; 399 #interrupt-cells = <1>; 400 interrupt-map-mask = <0 0 0 0x7>; 401 interrupt-map = <0 0 0 1 &intc 0 142 402 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 403 <0 0 0 2 &intc 0 143 404 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 405 <0 0 0 3 &intc 0 144 406 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 407 <0 0 0 4 &intc 0 145 408 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 409 410 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 411 <&gcc GCC_PCIE1_AXI_M_CLK>, 412 <&gcc GCC_PCIE1_AXI_S_CLK>, 413 <&gcc GCC_PCIE1_AHB_CLK>, 414 <&gcc GCC_PCIE1_AUX_CLK>; 415 clock-names = "iface", 416 "axi_m", 417 "axi_s", 418 "ahb", 419 "aux"; 420 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 421 <&gcc GCC_PCIE1_SLEEP_ARES>, 422 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 423 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 424 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 425 <&gcc GCC_PCIE1_AHB_ARES>, 426 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 427 reset-names = "pipe", 428 "sleep", 429 "sticky", 430 "axi_m", 431 "axi_s", 432 "ahb", 433 "axi_m_sticky"; 434 status = "disabled"; 435 }; 436 }; 437 438 cpus { 439 #address-cells = <0x1>; 440 #size-cells = <0x0>; 441 442 CPU0: cpu@0 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a53"; 445 reg = <0x0>; 446 next-level-cache = <&L2_0>; 447 enable-method = "psci"; 448 }; 449 450 CPU1: cpu@1 { 451 device_type = "cpu"; 452 compatible = "arm,cortex-a53"; 453 enable-method = "psci"; 454 reg = <0x1>; 455 next-level-cache = <&L2_0>; 456 }; 457 458 CPU2: cpu@2 { 459 device_type = "cpu"; 460 compatible = "arm,cortex-a53"; 461 enable-method = "psci"; 462 reg = <0x2>; 463 next-level-cache = <&L2_0>; 464 }; 465 466 CPU3: cpu@3 { 467 device_type = "cpu"; 468 compatible = "arm,cortex-a53"; 469 enable-method = "psci"; 470 reg = <0x3>; 471 next-level-cache = <&L2_0>; 472 }; 473 474 L2_0: l2-cache { 475 compatible = "cache"; 476 cache-level = <0x2>; 477 }; 478 }; 479 480 psci { 481 compatible = "arm,psci-1.0"; 482 method = "smc"; 483 }; 484 485 pmu { 486 compatible = "arm,armv8-pmuv3"; 487 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 488 }; 489 490 clocks { 491 sleep_clk: sleep_clk { 492 compatible = "fixed-clock"; 493 clock-frequency = <32000>; 494 #clock-cells = <0>; 495 }; 496 497 xo: xo { 498 compatible = "fixed-clock"; 499 clock-frequency = <19200000>; 500 #clock-cells = <0>; 501 }; 502 }; 503}; 504