1/* 2 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 16 17/ { 18 model = "Qualcomm Technologies, Inc. IPQ8074"; 19 compatible = "qcom,ipq8074"; 20 21 soc: soc { 22 #address-cells = <0x1>; 23 #size-cells = <0x1>; 24 ranges = <0 0 0 0xffffffff>; 25 compatible = "simple-bus"; 26 27 pinctrl@1000000 { 28 compatible = "qcom,ipq8074-pinctrl"; 29 reg = <0x1000000 0x300000>; 30 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 31 gpio-controller; 32 #gpio-cells = <0x2>; 33 interrupt-controller; 34 #interrupt-cells = <0x2>; 35 }; 36 37 intc: interrupt-controller@b000000 { 38 compatible = "qcom,msm-qgic2"; 39 interrupt-controller; 40 #interrupt-cells = <0x3>; 41 reg = <0xb000000 0x1000>, <0xb002000 0x1000>; 42 }; 43 44 timer { 45 compatible = "arm,armv8-timer"; 46 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 50 }; 51 52 timer@b120000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 compatible = "arm,armv7-timer-mem"; 57 reg = <0xb120000 0x1000>; 58 clock-frequency = <19200000>; 59 60 frame@b120000 { 61 frame-number = <0>; 62 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 64 reg = <0xb121000 0x1000>, 65 <0xb122000 0x1000>; 66 }; 67 68 frame@b123000 { 69 frame-number = <1>; 70 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 reg = <0xb123000 0x1000>; 72 status = "disabled"; 73 }; 74 75 frame@b124000 { 76 frame-number = <2>; 77 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 78 reg = <0xb124000 0x1000>; 79 status = "disabled"; 80 }; 81 82 frame@b125000 { 83 frame-number = <3>; 84 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 85 reg = <0xb125000 0x1000>; 86 status = "disabled"; 87 }; 88 89 frame@b126000 { 90 frame-number = <4>; 91 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 92 reg = <0xb126000 0x1000>; 93 status = "disabled"; 94 }; 95 96 frame@b127000 { 97 frame-number = <5>; 98 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 99 reg = <0xb127000 0x1000>; 100 status = "disabled"; 101 }; 102 103 frame@b128000 { 104 frame-number = <6>; 105 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 106 reg = <0xb128000 0x1000>; 107 status = "disabled"; 108 }; 109 }; 110 111 gcc: gcc@1800000 { 112 compatible = "qcom,gcc-ipq8074"; 113 reg = <0x1800000 0x80000>; 114 #clock-cells = <0x1>; 115 #reset-cells = <0x1>; 116 }; 117 118 blsp1_uart5: serial@78b3000 { 119 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 120 reg = <0x78b3000 0x200>; 121 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 123 <&gcc GCC_BLSP1_AHB_CLK>; 124 clock-names = "core", "iface"; 125 status = "disabled"; 126 }; 127 }; 128 129 cpus { 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 133 CPU0: cpu@0 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53", "arm,armv8"; 136 reg = <0x0>; 137 next-level-cache = <&L2_0>; 138 enable-method = "psci"; 139 }; 140 141 CPU1: cpu@1 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53", "arm,armv8"; 144 enable-method = "psci"; 145 reg = <0x1>; 146 next-level-cache = <&L2_0>; 147 }; 148 149 CPU2: cpu@2 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53", "arm,armv8"; 152 enable-method = "psci"; 153 reg = <0x2>; 154 next-level-cache = <&L2_0>; 155 }; 156 157 CPU3: cpu@3 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53", "arm,armv8"; 160 enable-method = "psci"; 161 reg = <0x3>; 162 next-level-cache = <&L2_0>; 163 }; 164 165 L2_0: l2-cache { 166 compatible = "cache"; 167 cache-level = <0x2>; 168 }; 169 }; 170 171 psci { 172 compatible = "arm,psci-1.0"; 173 method = "smc"; 174 }; 175 176 pmu { 177 compatible = "arm,armv8-pmuv3"; 178 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; 179 }; 180 181 clocks { 182 sleep_clk: sleep_clk { 183 compatible = "fixed-clock"; 184 clock-frequency = <32000>; 185 #clock-cells = <0>; 186 }; 187 188 xo: xo { 189 compatible = "fixed-clock"; 190 clock-frequency = <19200000>; 191 #clock-cells = <0>; 192 }; 193 }; 194}; 195